JP2009140979A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate distortion of the shape of a columnar electrode even if a defect in exposure of a plating resist film for columnar electrode formation etc., is caused in a method of manufacturing a semiconductor device called CSP. <P>SOLUTION: On an upper surface of a base metal layer 8 including an upper electrode layer 8, a coating film 25 is formed of a negative type liquid resist first. Then the plating resist film 26 for columnar electrode formation made of a negative type dry film resist is formed on an upper surface of the coating film 25. Then an opening 27 for columnar electrode formation is formed in the plating resist film 26 for columnar electrode formation and the coating film 25 successively. Trailing 28 caused at an inner wall surface bottom of the opening 27 of the coating film 25 owing to a defect in exposure is etched away. Then the columnar electrode is formed in the opening 27 through electrolytic plating. Further, the plating resist film 26 for columnar electrode formation and the coating film 25 are peeled at the same time using resist peeling liquid. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Some conventional semiconductor devices called CSP (chip size package) have columnar electrodes formed on the upper surface of connection pad portions of wiring formed on a semiconductor substrate (see, for example, Patent Document 1).

JP 2004-281615 A

  In the above conventional method of manufacturing a semiconductor device, first, for an upper metal layer for wiring having an opening in a portion corresponding to the upper metal layer forming region for wiring on the upper surface of the base metal layer formed on the entire surface of the semiconductor substrate. A plating resist film is formed. Next, by performing electrolytic plating using the base metal layer as a plating current path, the upper metal layer for wiring is formed on the upper surface of the base metal layer in the opening of the plating resist film for the upper metal layer for wiring.

  Next, while leaving the plating resist film for the upper metal layer for wiring, the plating for forming the columnar electrode having an opening on the connection pad portion of the upper metal layer for wiring, that is, the portion corresponding to the columnar electrode formation region, on the upper surface thereof A resist film is formed. Next, by performing electrolytic plating using the base metal layer as a plating current path, the columnar electrode is formed on the upper surface of the connection pad portion of the upper metal layer for wiring in the opening of the plating resist film for columnar electrode formation. Next, both plating resist films are stripped simultaneously using a resist stripping solution.

  Here, in the state before the plating resist films are peeled off, the plating resist film for the upper metal layer for wiring exists in the gap between the upper metal layers for wiring, so that the columnar electrode is formed in the gap between the upper metal layers for wiring. There is no room for the plating resist film to enter. Thereby, it is possible to reliably prevent the residue of the columnar electrode forming plating resist film on the upper surface of the base metal layer in the gap between the wiring upper metal layers.

  Next, using the upper metal layer for wiring as a mask, the base metal layer in a region other than the region under the upper metal layer for wiring is etched and removed. In this state, a wiring having a two-layer structure is formed by the upper metal layer for wiring and the underlying metal layer remaining therebelow.

  However, in the above-described conventional method of manufacturing a semiconductor device, when the height of the columnar electrode is relatively high, for example, 100 μm, the thickness of the columnar electrode forming plating resist film is relatively large, 100 μm or more. On the other hand, when the opening is formed in the columnar electrode forming plating resist film by photolithography, exposure and development are performed. If the thickness of the columnar electrode forming plating resist film is relatively thick, such as 100 μm or more, the columnar electrode formation is performed. An exposure failure may occur at the bottom of the plating resist film due to a change in the amount of exposure light. When such an exposure failure occurs, there is a problem that the bottom of the inner wall surface of the opening of the plating resist film for forming a columnar electrode is skirted and the shape of the formed columnar electrode is distorted.

  In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing the shape of a conductor such as a columnar electrode from becoming distorted.

The invention according to claim 1 includes a step of forming a base metal layer on the entire surface of the semiconductor substrate, and an upper metal for wiring having an opening in a portion corresponding to the upper metal layer formation region for wiring on the base metal layer. Forming a plating resist film for a layer, and performing electrolytic plating using the base metal layer as a plating current path, thereby providing wiring on the base metal layer in the opening of the plating resist film for the upper metal layer for wiring A step of forming an upper metal layer; a step of removing the plating resist film for the upper metal layer for wiring; and a coating resist film and a plating resist film for forming a conductor on the base metal layer including the upper metal layer for wiring Forming an opening in the conductor forming plating resist film and the coating film in a portion corresponding to a part of the wiring upper metal layer, and forming the conductor forming plating layer. A step of removing tailing generated at the bottom of the inner wall surface of the opening of the coating film when the opening is formed in the strike film and the coating film, and electrolytic plating using the base metal layer as a plating current path Forming a conductor on part of the upper metal layer for wiring in the opening of the coating film and the coating film for forming the conductor, and the plating resist film for forming the conductor and The method includes a step of stripping the coating film using a resist stripping solution and a step of removing the base metal layer in a region other than under the upper metal layer for wiring.
According to a second aspect of the present invention, there is provided a step of forming a base metal layer on the entire surface of a semiconductor substrate, and an upper metal for wiring having an opening in a portion corresponding to the upper metal layer formation region for wiring on the base metal layer. Forming a plating resist film for a layer, and performing electrolytic plating using the base metal layer as a plating current path, thereby providing wiring on the base metal layer in the opening of the plating resist film for the upper metal layer for wiring A step of forming an upper metal layer, a step of forming a coating film and a plating resist film for forming a conductor on the upper metal layer for wiring and the plating resist film for the upper metal layer for wiring, and the upper metal for wiring Forming an opening in the conductor forming plating resist film and the coating film in a portion corresponding to a part of the layer; and forming the opening in the conductor forming plating resist film and the coating film. Forming the conductive film by performing a step of removing tailing generated at the bottom of the inner wall surface of the opening portion of the coating film when the portion is formed, and electrolytic plating using the base metal layer as a plating current path A step of forming a conductor on a part of the upper metal layer for wiring in the opening of the plating resist film and the coating film; the plating resist film for forming the conductor; the coating film; and the upper metal for wiring The method includes a step of stripping the plating resist film for a layer using a resist stripping solution and a step of removing the base metal layer in a region other than under the upper metal layer for wiring.
The invention described in claim 3 is the invention described in claim 1 or 2, characterized in that the skirting is removed by dry etching or wet etching.
According to a fourth aspect of the present invention, in the first or second aspect of the present invention, the upper surface of the coating film is flat.
The invention according to claim 5 is the invention according to claim 1 or 2, wherein the coating film is formed by applying a negative type liquid resist, and the plating resist film for forming a conductor is a negative type dry film It is characterized by being formed by laminating.
The invention according to claim 6 is the invention according to claim 5, wherein the formation of the opening in the conductor forming plating resist film and the coating film is performed by the conductor forming plating resist film and the conductor The coating film is formed by exposure and development.
The invention according to claim 7 is the invention according to claim 1 or 2, wherein the conductor is a columnar electrode.
The invention according to claim 8 is the invention according to claim 7, further comprising a step of forming a sealing film around the columnar electrode.
The invention according to claim 9 is the invention according to claim 8, further comprising a step of forming solder balls on the columnar electrodes.

  According to the present invention, when the opening is formed in the plating resist film for forming a conductor and the coating film, the tailing generated at the bottom of the inner wall surface of the opening of the coating film is removed. It is possible to prevent the shape of the conductor from becoming distorted.

  FIG. 1 is a sectional view showing an example of a semiconductor device manufactured by the manufacturing method of the present invention. This semiconductor device is called a CSP and includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) is provided on the upper surface of the silicon substrate 1, and a plurality of connection pads 2 made of aluminum-based metal or the like are provided on the periphery of the upper surface connected to the integrated circuit.

  An insulating film 3 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 1 excluding the central portion of the connection pad 2, and the central portion of the connection pad 2 is exposed through an opening 4 provided in the insulating film 3. Yes. A protective film 5 made of polyimide resin or the like is provided on the upper surface of the insulating film 3. An opening 6 is provided in the protective film 5 at a portion corresponding to the opening 4 of the insulating film 3.

  A wiring 7 is provided on the upper surface of the protective film 5. The wiring 7 has a two-layer structure of a base metal layer 8 made of copper or the like provided on the upper surface of the protective film 5 and an upper metal layer 9 made of copper provided on the upper surface of the base metal layer 8. One end of the wiring 7 is connected to the connection pad 2 through the openings 4 and 6 of the insulating film 3 and the protective film 5.

  A columnar electrode 10 made of copper is provided on the upper surface of the connection pad portion of the wiring 7. A sealing film 11 made of an epoxy resin or the like is provided on the upper surface of the protective film 5 including the wiring 7 so that the upper surface thereof is flush with the upper surface of the columnar electrode 10. A solder ball 12 is provided on the upper surface of the columnar electrode 10.

(First Embodiment of Manufacturing Method)
Next, a first embodiment of the semiconductor device manufacturing method will be described. First, as shown in FIG. 2, the upper surface of a silicon substrate in a wafer state (hereinafter referred to as a semiconductor wafer 21) is formed of a connection pad 2 made of aluminum metal, an insulating film 3 made of silicon oxide, and a polyimide resin. The protective film 5 is formed, and the connection pad 2 is exposed through the openings 4 and 6 formed in the insulating film 3 and the protective film 5.

  In this case, an integrated circuit (not shown) having a predetermined function is formed in a region where each semiconductor device is formed on the upper surface of the semiconductor wafer 21, and the connection pad 2 is electrically connected to the integrated circuit formed in the corresponding region. Connected. In FIG. 2, an area indicated by reference numeral 22 is an area corresponding to dicing street.

  Next, as shown in FIG. 3, a base metal layer 8 is formed on the entire upper surface of the protective film 5 including the upper surface of the connection pad 2 exposed through the openings 4 and 6 of the insulating film 3 and the protective film 5. . In this case, the base metal layer 8 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

  Next, an upper metal layer plating resist film 23 made of a positive resist is patterned on the upper surface of the base metal layer 8. In this case, an opening 24 is formed in the upper metal layer plating resist film 23 in a portion corresponding to the upper metal layer 9 formation region. Next, the upper metal layer 9 is formed on the upper surface of the base metal layer 8 in the opening 24 of the upper metal layer plating resist film 23 by performing electrolytic plating of copper using the base metal layer 8 as a plating current path. . Next, the plating resist film 22 for the upper metal layer is stripped using a resist stripping solution.

  Next, as shown in FIG. 4, on the upper surface of the base metal layer 8 including the upper metal layer 9, for example, a negative liquid resist made of the same material as a negative dry film resist described later is applied by a spin coating method or the like. Then, the coating film 25 having a flat upper surface is formed. In this case, the upper metal layer 9 is completely covered with the coating film 25 so that the coating film 25 thicker than the thickness of the upper metal layer 9 is formed between the upper metal layers 9.

  Next, a negative dry film resist is laminated on the upper surface of the coating film 25 to form an unexposed columnar electrode forming plating resist film 26. In this case, since the upper surface of the coating film 25 is flat, it is possible to make it difficult for air to remain between the columnar electrode forming plating resist film 26 and the coating film 25. Next, when exposure and development are performed, as shown in FIG. 5, the columnar electrode forming plating resist film 26 and the coating film 25 in the portion corresponding to the connection pad portion (columnar electrode 10 formation region) of the upper metal layer 9. The opening 27 is continuously formed.

  Here, if the thickness of the columnar electrode forming plating resist film 26 is relatively large, such as 100 μm or more, an exposure failure may occur at the bottom of the coating film 25 due to a change in the amount of exposure light. Then, it is assumed that the tailing 28 is generated at the bottom of the inner wall surface of the opening 27 of the coating film 25 due to the occurrence of such exposure failure. Then, when the tailing 28 generated at the bottom of the inner wall surface of the opening 27 of the coating film 25 is removed by dry etching or wet etching, the inner wall surface of the opening 27 is linear as shown in FIG. Thus, the upper surface of the connection pad portion of the upper metal layer 9 is exposed as expected.

  Next, as shown in FIG. 7, when copper is electroplated using the base metal layer 8 as a plating current path, the upper metal layer in the opening 27 of the columnar electrode forming plating resist film 26 and the coating film 25 is obtained. A columnar electrode 10 is formed on the upper surface of the connection pad portion 9. In this case, since the upper surface of the connection pad portion of the upper metal layer 9 is exposed as expected through the opening portion 27 whose inner wall surface is linear, the shape of the columnar electrode 10 is not distorted.

  Next, the columnar electrode forming plating resist film 26 and the coating film 25 are simultaneously stripped using a resist stripping solution as described later. Next, when the base metal layer 8 is removed by etching in a region other than under the upper metal layer 9 using the upper metal layer 9 as a mask, the base metal layer 8 remains only under the upper metal layer 9 as shown in FIG. Is done. In this state, the upper metal layer 9 and the underlying metal layer 8 remaining below the upper metal layer 9 form a two-layer wiring 7.

  Here, peeling of the columnar electrode forming plating resist film 26 and the coating film 25 will be described. In the process shown in FIG. 4, the coating film 25 is formed on the upper surface of the base metal layer 8 including the upper metal layer 9, and the columnar electrode forming plating resist film 26 is formed on the upper surface of the coating film 25. A coating film 25 thicker than the upper metal layer 9 exists between the upper metal layers 9, and there is no room for the columnar electrode forming plating resist film 26 to enter between the upper metal layers 9.

  And the coating film 25 which consists of a negative type liquid resist melt | dissolves and peels with respect to resist stripping solution. On the other hand, the columnar electrode forming plating resist film 26 made of a negative dry film resist is swollen and peeled off from the resist stripping solution. In this case, the columnar electrode forming plating resist film 26 is swollen and peeled off from the surface in contact with the resist stripping solution, and at the same time, the coating film 25 is dissolved and peeled off, thereby Since a cavity is formed under the plating resist film 26, it floats up and is peeled off by a so-called lift-off method.

  Therefore, even when the interval between the wirings 7 is narrow, no resist residue of the columnar electrode forming plating resist film 26 is generated between the wirings 7, and the resist residue of the columnar electrode forming plating resist film 26 is not generated. It is possible to reliably prevent occurrence of a short circuit between the wirings 7 due to the above.

  After the columnar electrode forming plating resist film 26 and the coating film 25 are peeled in this way, next, as shown in FIG. 9, the top surface of the protective film 5 including the wiring 7 and the columnar electrode 10 is spin coated or the like. Thus, the sealing film 11 made of epoxy resin or the like is formed so that its thickness is slightly thicker than the height of the columnar electrode 10. Therefore, in this state, the upper surface of the columnar electrode 10 is covered with the sealing film 11.

  Next, the upper surface side of the sealing film 11 is appropriately polished so that the upper surface of the columnar electrode 10 is exposed and the sealing film 11 including the exposed upper surface of the columnar electrode 10 is formed as shown in FIG. Flatten the top surface. Next, as shown in FIG. 11, solder balls 12 are formed on the upper surface of the columnar electrode 10. Next, as shown in FIG. 12, when the sealing film 11, the protective film 5, the insulating film 3, and the semiconductor wafer 21 are cut along the dicing street 22, a plurality of semiconductor devices shown in FIG. 1 are obtained.

(Second Embodiment of Manufacturing Method)
Next, a second embodiment of the method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, after the step shown in FIG. 3, the upper metal layer forming plating resist film 23 is left on the upper metal layer 9 and the upper metal layer forming plating resist film 23 as shown in FIG. Then, a negative liquid resist is applied by a spin coating method or the like to form a coating film 25 having a flat upper surface.

  Next, a negative dry film resist is laminated on the upper surface of the coating film 25 to form an unexposed columnar electrode forming plating resist film 26. Also in this case, since the upper surface of the coating film 25 is flat, it is possible to make it difficult for air to remain between the columnar electrode forming plating resist film 26 and the coating film 25. Next, when exposure and development are performed, as shown in FIG. 14, the columnar electrode forming plating resist film 26 and the coating film 25 in the portion corresponding to the connection pad portion (columnar electrode 10 formation region) of the upper metal layer 9. The opening 27 is continuously formed.

  Here, also in this case, it is assumed that the bottoming 28 is generated at the bottom of the inner wall surface of the opening 27 of the coating film 25. Then, when the tailing 28 generated at the bottom of the inner wall surface of the opening 27 of the coating film 25 is removed by dry etching or wet etching, the inner wall surface of the opening 27 is linear as shown in FIG. Thus, the upper surface of the connection pad portion of the upper metal layer 9 is exposed as expected.

  Next, as shown in FIG. 16, when electrolytic plating of copper is performed using the base metal layer 8 as a plating current path, the upper metal layer in the opening 27 of the columnar electrode forming plating resist film 26 and the coating film 25 is formed. A columnar electrode 10 is formed on the upper surface of the connection pad portion 9. Also in this case, since the upper surface of the connection pad portion of the upper metal layer 9 is exposed as expected through the opening 27 whose inner wall surface is linear, the shape of the columnar electrode 10 is not distorted.

  Next, the columnar electrode forming plating resist film 26, the coating film 25, and the upper metal layer forming plating resist film 23 are simultaneously stripped using a resist stripping solution as described later. Thereafter, through the same process as described above, a plurality of semiconductor devices shown in FIG. 1 are obtained.

  Here, the plating resist film 23 for forming the upper metal layer in the second embodiment is a positive chemical amplification type, and the novolak resin and the hydroxyl group of polyhydroxystyrene (PHS) are t-butoxycarbonyl (t-BOC). It comprises a protected dissolution inhibitor, a photoacid generator that generates an acid by light, and a solvent for dissolving them.

  Next, the reason will be described. Since the upper metal layer forming plating resist film 23 composed of a positive type non-exposed portion is a chemical amplification type, the unexposed columnar electrode forming plating resist film 26 and the coating film 25 are exposed to ultraviolet rays for exposure. At this time, no gas is generated even when the ultraviolet rays are irradiated, and no bubbles are interposed between the plating resist film 23 for forming the upper metal layer and the coating film 25. It is possible to prevent unnecessary peeling of the covering film 25.

  In contrast, when the upper metal layer forming plating resist film 23 is formed of, for example, a positive resist containing a novolac resin and a photosensitive agent, the unexposed columnar electrode forming plating resist film 26 and the coating film 25 are irradiated with ultraviolet rays. In the exposure, ultraviolet rays are irradiated, nitrogen is released from the photosensitizer by a photosensitive reaction, and the released nitrogen is interposed as bubbles between the upper metal layer forming plating resist film 23 and the coating film 25, It causes unnecessary peeling of the coating film 25 and is not preferable.

  Next, the case where the columnar electrode forming plating resist film 26, the coating film 25, and the upper metal layer forming plating resist film 23 are peeled will be described. First, as an example, the columnar electrode forming plating resist film 26 and the coating film 25 are formed of a resist containing an acrylic resin. The upper metal layer forming plating resist film 23 is formed of a positive chemically amplified resist containing the novolak resin.

  For example, the monoethanolamine-based resist stripping solution is used to form a negative type columnar electrode forming plating resist film 26 containing an acrylic resin, a coating film 25 and a positive type wiring forming plating resist film 22 containing a novolac resin. Both can be peeled off. Therefore, the columnar electrode forming plating resist film 26, the coating film 25, and the upper metal layer forming plating resist film 23 are simultaneously stripped using a monoethanolamine resist stripping solution.

  That is, the upper metal layer forming plating resist film 23 and the coating film 25 are dissolved and peeled off from the resist stripping solution. On the other hand, the columnar electrode forming plating resist film 26 is swollen and peeled off from the resist stripping solution. In this case, the columnar electrode forming plating resist film 26 is swollen and peeled off from the surface in contact with the resist stripping solution, and at the same time, the upper metal layer forming plating resist film 23 and the coating film 25 are dissolved. By peeling off, a cavity is formed under the columnar electrode forming plating resist film 26, so that it floats up and is peeled off by a so-called lift-off method.

  Therefore, in this case as well, even if the interval between the wirings 8 is narrow, the resist residue of the columnar electrode forming plating resist film 26 is not generated between the wirings 8, and the columnar electrode forming plating resist film is formed. The occurrence of a short circuit between the wirings 8 due to the 26 resist residues can be reliably prevented.

  In the above-described embodiment, the case where the columnar electrode 10 is formed on the connection pad portion upper surface of the upper metal layer 9 in the opening 27 of the columnar electrode forming plating resist film 26 and the coating film 25 has been described. It is not limited to. For example, an opening of a plating resist film and a coating film is used as a wiring pattern to form an upper layer wiring, an inductor made of copper or the like, or a conductive material such as a resistor made of a high resistance metal. The present invention can be widely applied when forming a body.

Sectional drawing of an example of the semiconductor device manufactured by the manufacturing method of this invention. Sectional drawing of what was initially prepared in 1st Embodiment of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of a predetermined | prescribed process in 2nd Embodiment of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. FIG. 15 is a sectional view of a step following FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 5 Protective film 7 Wiring 8 Base metal layer 9 Upper metal layer 10 Columnar electrode 11 Sealing film 12 Solder ball 21 Semiconductor wafer 22 Dicing street 23 Upper metal layer plating resist film 24 Opening 25 Coating film 26 Plating resist film for columnar electrode formation 27 Opening

Claims (9)

Forming a base metal layer on the entire surface of the semiconductor substrate;
Forming an upper metal layer plating resist film for wiring having an opening in a portion corresponding to the upper metal layer forming region for wiring on the base metal layer;
Forming an upper metal layer for wiring on the base metal layer in the opening of the plating resist film for the upper metal layer for wiring by performing electrolytic plating using the base metal layer as a plating current path;
Peeling the plating resist film for the upper metal layer for wiring; and
Forming a coating film and a conductor forming plating resist film on the base metal layer including the upper metal layer for wiring; and
Forming an opening in the conductor-forming plating resist film and the coating film in a portion corresponding to a part of the upper metal layer for wiring; and
Removing the tailing generated at the bottom of the inner wall surface of the opening of the coating film when the opening is formed in the conductor-forming plating resist film and the coating film;
By performing electroplating using the base metal layer as a plating current path, a conductor is formed on part of the upper metal layer for wiring within the opening of the plating resist film for forming the conductor and the coating film. Process,
Peeling the plating resist film for conductor formation and the coating film using a resist stripping solution;
Removing the base metal layer in a region other than under the upper metal layer for wiring;
A method for manufacturing a semiconductor device, comprising: Forming a base metal layer on the entire surface of the semiconductor substrate;
Forming an upper metal layer plating resist film for wiring having an opening in a portion corresponding to the upper metal layer forming region for wiring on the base metal layer;
Forming an upper metal layer for wiring on the base metal layer in the opening of the plating resist film for the upper metal layer for wiring by performing electrolytic plating using the base metal layer as a plating current path;
Forming a coating film and a conductor forming plating resist film on the wiring upper metal layer and the wiring upper metal layer plating resist film;
Forming an opening in the conductor-forming plating resist film and the coating film in a portion corresponding to a part of the upper metal layer for wiring; and
Removing the tailing generated at the bottom of the inner wall surface of the opening of the coating film when the opening is formed in the conductor-forming plating resist film and the coating film;
By performing electroplating using the base metal layer as a plating current path, a conductor is formed on part of the upper metal layer for wiring within the opening of the plating resist film for forming the conductor and the coating film. Process,
Stripping the plating resist film for conductor formation, the coating film and the plating resist film for the upper metal layer for wiring using a resist stripping solution;
Removing the base metal layer in a region other than under the upper metal layer for wiring;
A method for manufacturing a semiconductor device, comprising:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the skirting is removed by dry etching or wet etching.   3. The method of manufacturing a semiconductor device according to claim 1, wherein an upper surface of the coating film is flat.   The invention according to claim 1 or 2, wherein the coating film is formed by applying a negative type liquid resist, and the plating resist film for forming a conductor is formed by laminating a negative type dry film redest. A method for manufacturing a semiconductor device.   6. The invention according to claim 5, wherein the opening is formed in the conductor forming plating resist film and the coating film by exposing and developing the conductor forming plating resist film and the coating film. A method for manufacturing a semiconductor device, comprising:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductor is a columnar electrode.   8. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of forming a sealing film around the columnar electrode.   9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of forming a solder ball on the columnar electrode.

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