JP2009140608A5

JP2009140608A5 -

Info

Publication number: JP2009140608A5
Application number: JP2008190500A
Authority: JP
Filing date: 2008-07-24
Publication date: 2011-02-17
Anticipated expiration: 2028-07-24

Claims

A multi-stage shift register,
Each stage of the plurality of stages is
First to third element shift registers each operable as a one-stage shift register;
First to third output terminals for outputting first to third output signals, which are output signals of the first to third element shift registers, respectively;
A first input terminal to which the second output signal at the front stage is input and a second input terminal to which the third output signal at the rear stage is input;
The first element shift register includes:
The first output that is output from the first output terminal in accordance with both the second output signal of the preceding stage input to the first input terminal and the third output signal of the subsequent stage input to the second input terminal. Activate the signal,
The second element shift register is
In response to the second output signal of the previous stage exclusively input to the first input terminal, the second output signal output from the second output terminal is activated,
The third element shift register is
A shift register that activates the third output signal output from the third output terminal exclusively in response to the third output signal of the subsequent stage input to the second input terminal.

The shift register according to claim 1,
In each of the plurality of stages,
At the time of forward shift in which the first output signal is sequentially activated from the front stage to the rear stage, the third element shift register does not activate the third output signal,
2. The shift register according to claim 1, wherein the second element shift register does not activate the second output signal at the time of reverse shift in which the first output signal is activated in order from the rear stage to the front stage.

The shift register according to claim 2, wherein
Each stage of the plurality of stages is
A first reset terminal and a second reset terminal;
In each of the plurality of stages,
The first element shift register includes:
A first clock terminal;
A first transistor for supplying a first clock signal input to the first clock terminal to the first output terminal;
A second transistor having a control electrode connected to the first input terminal and charging a first node to which the control electrode of the first transistor is connected;
A third transistor for discharging the first node in response to a signal input to the first reset terminal;
A fourth transistor having a control electrode connected to the second input terminal and charging the first node;
A fifth transistor for discharging the first node in response to a signal input to the second reset terminal;
The second element shift register is
A second clock terminal;
A sixth transistor for supplying a second clock signal input to the second clock terminal to the second output terminal;
A seventh transistor having a control electrode connected to the first input terminal and charging a second node to which the control electrode of the sixth transistor is connected;
An eighth transistor that discharges the second node in response to a signal input to the first reset terminal;
The third element shift register is
A third clock terminal;
A ninth transistor for supplying a third clock signal input to the third clock terminal to the third output terminal;
A tenth transistor having a control electrode connected to the second input terminal and charging a third node to which the control electrode of the ninth transistor is connected;
An eleventh transistor that discharges the third node in response to a signal input to the second reset terminal;
The shift register according to claim 1, wherein the second and third clock signals are signals in phase with the first clock signal.

A shift register according to claim 3,
In each of the plurality of stages,
The second clock signal is activated during the forward shift, but not activated during the backward shift.
3. The shift register according to claim 1, wherein the third clock signal is activated during the backward shift, but is not activated during the forward shift.

A shift register according to claim 3,
Each stage of the plurality of stages is
A first voltage signal terminal and a second voltage signal terminal supplied with first and second voltage signals complementary to each other;
In each of the plurality of stages,
The seventh transistor is connected between the second node and the first voltage signal terminal;
The tenth transistor is connected between the third node and the second voltage signal terminal.
A shift register characterized by that.

The shift register according to claim 5, wherein
The first to third clock signals are all the same signal
A shift register characterized by that.

A shift register according to any one of claims 3 to 6,
In each of the plurality of stages,
The first element shift register includes:
A twelfth transistor having a control electrode connected to the first clock terminal via a load and discharging the first node;
A thirteenth transistor having a control electrode connected to the first node and discharging a fourth node connected to the control electrode of the twelfth transistor;
A shift register characterized by that.

The shift register according to claim 7, wherein
In each of the plurality of stages,
The first element shift register includes:
A fourteenth transistor having a control electrode connected to the fourth node and discharging the first output terminal;
A shift register characterized by that.

The shift register according to claim 8, wherein
In each of the plurality of stages,
The fourteenth transistor is
One main electrode connected to the first output terminal and the other main electrode to which a signal having a phase different from that of the first clock signal is supplied.
A shift register characterized by that.

A shift register according to any one of claims 7 to 9,
In each of the plurality of stages,
The first element shift register includes:
A fifteenth transistor controlled by a fourth clock signal having a phase different from that of the first clock signal and discharging the first output terminal;
A shift register characterized by that.

A shift register according to any one of claims 7 to 10,
In each of the plurality of stages,
The second element shift register is
A sixteenth transistor controlled by a fifth clock signal having a phase different from that of the first clock signal and discharging the second output terminal;
The third element shift register is
A seventeenth transistor controlled by a sixth clock signal having a phase different from that of the first clock signal and discharging the third output terminal;
A shift register characterized by that.

A shift register according to any one of claims 3 to 11,
In each of the plurality of stages,
The first reset terminal includes
The second output signal in the subsequent stage is input,
The second reset terminal includes
The third output signal in the previous stage is input
A shift register characterized by that.

A shift register according to any one of claims 3 to 11,
In each of the plurality of stages,
Seventh and eighth clock signals having phases different from those of the first clock signal are input to the first and second reset terminals,
The third transistor is connected between the first node and the first input terminal;
The fifth transistor is connected between the first node and the second input terminal;
The eighth transistor is connected between the second node and the first input terminal;
The eleventh transistor is connected between the third node and the second input terminal.
A shift register characterized by that.

A shift register according to any one of claims 3 to 6,
In each of the plurality of stages,
The first element shift register includes:
First and second control terminals to which complementary first and second control signals are respectively input;
Twelfth and thirteenth transistors for discharging the first output terminal;
A drive circuit for alternately driving the twelfth and thirteenth transistors based on the first and second control signals;
A shift register characterized by that.

A shift register according to any one of claims 7 to 10,
In each of the plurality of stages,
The second element shift register is
A sixteenth transistor having a control electrode connected to the second clock terminal via a load and discharging the second node;
A seventeenth transistor having a control electrode connected to the second node and discharging a fifth node connected to the control electrode of the sixteenth transistor;
The third element shift register is
An eighteenth transistor having a control electrode connected to the third clock terminal via a load and discharging the third node;
A nineteenth transistor having a control electrode connected to the third node and discharging a sixth node connected to the control electrode of the eighteenth transistor;
A shift register characterized by that.

The shift register according to claim 15,
In each of the plurality of stages,
The second element shift register is
A 20th transistor having a control electrode connected to the fourth or fifth node and discharging the second output terminal;
The third element shift register is
A 21st transistor having a control electrode connected to the fourth or sixth node and discharging the third output terminal;
A shift register characterized by that.

The shift register according to claim 15 or 16,
In each of the plurality of stages,
The second element shift register is
A second transistor controlled by a fifth clock signal having a phase different from that of the first clock signal and discharging the second output terminal;
The third element shift register is
A 23rd transistor controlled by a 6th clock signal having a phase different from that of the 1st clock signal and discharging the 3rd output terminal is further provided.
A shift register characterized by that.

A shift register according to any one of claims 15 to 17,
In each of the plurality of stages,
The first reset terminal includes
The second output signal in the subsequent stage is input,
The second reset terminal includes
The third output signal in the previous stage is input
A shift register characterized by that.

The shift register according to any one of claims 3 to 18,
A first dummy stage, which is a one-stage shift register that is provided further upstream of the foremost stage of the plurality of stages and outputs a signal to the second reset terminal of the forefront stage;
A second dummy stage, which is provided in a further subsequent stage of the last stage of the plurality of stages and is a one-stage shift register that outputs a signal to the first reset terminal of the last stage,
The first dummy stage is
In response to the third output signal in the forefront stage exclusively, activate the signal to be output to the second reset terminal in the forefront stage,
The second dummy stage is
The signal output to the first reset terminal at the last stage is activated exclusively in response to the second output signal at the last stage.
A shift register characterized by that.