JP2009139417A - Electro-optical device, manufacturing method therefor, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the aperture ratio, while enhancing light shieldability to a TFT for pixel switching in an electro-optical device. <P>SOLUTION: The electro-optical device includes a substrate (10); a scanning line (11); and a data line (6a); a pixel electrode (9a); a channel region (1a); a data line side source drain region (1d); a pixel electrode side source drain region (1e); a semiconductor layer (1a) having a first junction region (1b), and a second junction region (1c); a sidewall (61), which is constituted of an insulating film disposed on a sidewall of a prescribed region, including at least a part of the second junction region in the semiconductor layer; and a gate electrode (3a) which is electrically connected to the scanning line, is arranged so as to face the channel region via a gate insulating film (2) and is disposed so as to cover the prescribed region and the sidewall. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electro-optical device such as a liquid crystal device and a manufacturing method thereof, and a technical field of an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  A liquid crystal device which is an example of this type of electro-optical device is frequently used not only as a direct-view display but also as a light modulation means (light valve) of, for example, a projection display device. In particular, in the case of a projection display device, strong light from a light source is incident on a liquid crystal light valve, and this thin film transistor (TFT: Thin Film Transistor) in the liquid crystal light valve does not cause an increase in leakage current or malfunction. As described above, a light shielding film as a light shielding means for blocking incident light is built in the liquid crystal light valve.

  Regarding such a light shielding means or a light shielding film, for example, Patent Document 1 discloses a gate line disposed on the upper layer side of a semiconductor layer in the vicinity of a side surface of a channel region or LDD (Lightly Doped Drain) region of a semiconductor layer constituting a TFT. A technique for reducing light reaching a channel region or an LDD region of a TFT by providing a contact hole for connecting a light shielding film disposed on a lower layer side of a semiconductor layer is disclosed.

JP 2001-356371 A

  However, as in the technique according to Patent Document 1, when the gate line arranged on the upper layer side of the semiconductor layer constituting the TFT and the light shielding film arranged on the lower layer side of the semiconductor layer are connected through a contact hole, There is a technical problem that it is difficult to widen the opening area in the pixel (that is, the area through which light is transmitted in the pixel). More specifically, when a contact hole is formed in the vicinity of the side surface of the channel region or the LDD region by etching, it is necessary to design with a margin in consideration of the displacement of the resist mask. Therefore, as the margin is secured, the ratio of the non-opening area in the pixel (that is, the area where light is not transmitted, in other words, the area where the light shielding means or the light shielding film is formed) increases. It becomes difficult to improve.

  The present invention has been made in view of, for example, the above-described problems, and can improve the aperture ratio while improving the light shielding property with respect to the pixel switching TFT, and can display a bright and high-quality image. It is another object of the present invention to provide an electronic apparatus including such an electro-optical device.

  In order to solve the above problems, an electro-optical device of the present invention includes a substrate, a data line provided on the substrate, a pixel electrode electrically connected to the data line, a channel region, and the data line. A data line side source / drain region electrically connected, a pixel electrode side source / drain region electrically connected to the pixel electrode, a first junction formed between the channel region and the data line side source / drain region A semiconductor layer having a second junction region formed between the region and the channel region and the pixel electrode side source / drain region, and a gate electrode disposed to face the channel region with a gate insulating film interposed therebetween A sidewall made of an insulating film provided on a sidewall of a predetermined region including at least a part of the second junction region in the semiconductor layer, and the predetermined region and And a light shielding part provided to cover the side wall.

  According to the electro-optical device of the present invention, during the operation, for example, the scanning signal is supplied from the scanning line while the supply of the image signal from the data line to the pixel electrode is controlled, and so-called active matrix image display is possible. It becomes. The image signal is turned on and off according to a scanning signal supplied from the scanning line by a transistor (that is, a pixel switching transistor) which is a switching element electrically connected between the data line and the pixel electrode. The pixel electrode is supplied from the data line through the transistor at a predetermined timing. The pixel electrode is a transparent electrode made of a transparent conductive material such as ITO (Indium Tin Oxide), for example, and a plurality of pixel electrodes are provided in a matrix form in a region to be a display region on the substrate corresponding to the intersection of the data line and the scanning line. It is done.

  The transistor described above includes a semiconductor layer and a gate electrode.

  The semiconductor layer includes a channel region, a data line side source / drain region, a pixel electrode side source / drain region, a first junction region formed between the channel region and the data line side source / drain region, a channel region, and a pixel electrode. And a second junction region formed between the side source / drain regions.

  The channel region has, for example, a channel length along one direction in which the data line or the scanning line extends.

  The first junction region is a region formed at the junction between the channel region and the data line side source / drain region, and the second junction region is formed at the junction between the channel region and the pixel electrode side source / drain region. It is an area to be done. That is, the first and second junction regions are, for example, a PN junction region when the transistor is formed as an NPN type or PNP type transistor (ie, an N channel type or P channel type transistor), or the transistor has an LDD structure. Means an LDD region (that is, an impurity region formed by implanting a smaller amount of impurities than the source / drain regions into the semiconductor layer by implanting impurities such as ion implantation).

  The gate electrode is disposed so as to face the channel region with the gate insulating film interposed therebetween. The gate insulating film electrically insulates the gate electrode and the channel region. The gate insulating film is typically formed in the same planar pattern as the semiconductor layer so as to overlap the semiconductor layer.

  In particular, the present invention includes a sidewall made of an insulating film. The sidewall is provided on a sidewall (or side surface) of a predetermined region including at least a part of the second junction region in the semiconductor layer. The sidewall is formed on the sidewall of a predetermined region in the semiconductor layer so as to extend along the thickness direction of the semiconductor layer. For example, the sidewall is a portion extending with a planar extension so that a portion extending along the thickness direction of the semiconductor layer remains after the insulating film is formed so as to cover the semiconductor layer. (In other words, the portion extending along the substrate surface) is removed by anisotropic etching.

  Further, the light shielding portion is made of a light shielding conductive film, and is provided so as to cover a predetermined region and a sidewall in the semiconductor layer. In other words, the light shielding portion is typically provided on the upper layer side via the gate insulating film and on the side wall side via the sidewall with respect to a predetermined region in the semiconductor layer.

  Therefore, the light incident from the upper layer side and the light incident from the side wall side can be shielded against the predetermined region in the semiconductor layer by the light shielding portion. In other words, the light shielding part can improve the light shielding property with respect to a predetermined region in the semiconductor layer. Therefore, the light leakage current in the semiconductor layer of the transistor can be reduced.

  Here, in particular, the portion of the light shielding portion provided on the side wall of the predetermined region in the semiconductor layer is provided on the side wall provided on the side wall of the semiconductor layer. Therefore, for example, if a light shielding portion is formed in a contact hole or groove formed by performing an etching process on a portion of the insulating film covering the semiconductor layer on the side wall side of the semiconductor layer, for example. A margin considering the positional deviation of the resist mask becomes unnecessary, and the non-opening region in the pixel can be reduced. More specifically, according to the present invention, it is relatively easy to reduce the width of the sidewall within a range in which the light shielding portion and the predetermined region in the semiconductor layer can be electrically insulated, and the non-opening region in the pixel Can be reduced. Thereby, it is possible to relatively widen the opening area and increase the opening ratio. In other words, by forming a part of the light-shielding part so as to cover the side wall, the part is arranged closer to the side of the semiconductor layer than when the contact hole described above is used, for example. It is possible to reduce the non-opening area defined by the light shielding portion. The “opening region” is a region in the pixel through which light is substantially transmitted, and means a region in which light incident on the pixel is not blocked by a wiring, a semiconductor film, a light shielding film, or the like. “Non-opening region” means a region where light contributing to display is not transmitted (in other words, a region excluding the opening region in the pixel), and for example, a non-transparent wiring or electrode is disposed in the pixel. Means an area.

  In addition, in the present invention, in particular, the predetermined region in the semiconductor layer includes at least a part of the second junction region (typically, the entire second junction region). As will be described later, according to the present inventors' research, theoretically, during the operation of the transistor, a light leakage current is relatively generated in the first and second junction regions, particularly in the second junction region. It tends to be easy and has been proven in experiments. According to the present invention, it is possible to improve the light shielding property for the second junction region, which is a region where light leakage current is particularly likely to occur in the semiconductor layer, and as a result, the light leakage current in the semiconductor layer of the transistor is more effectively reduced. It becomes possible to do.

  As described above, according to the electro-optical device of the present invention, it is possible to improve the aperture ratio while improving the light shielding property with respect to the pixel switching transistor. As a result, a bright and high-quality image can be displayed. Here, in particular, when the pixel pitch is miniaturized to meet the demand for further improvement in display performance, it is technically considered to reduce the area of the non-opening region by finely processing the wiring or the electrode. Since it becomes even more difficult, the method of arranging a part of the light-shielding part close to the side of the semiconductor layer by using the side wall has a great effect in terms of increasing the aperture ratio.

  In one aspect of the electro-optical device of the present invention, the scanning line is provided on the substrate, intersects the data line, and is electrically connected to the gate electrode.

  According to this aspect, by supplying a scanning signal to the gate electrode through the scanning line, it is possible to turn on and off the transistor that is a switching element electrically connected between the data line and the pixel electrode. . Note that the scanning line may be formed in a layer different from the gate electrode in the stacked structure on the substrate, or may be formed in the same layer as the gate electrode (or the gate electrode is a part of the scanning line). May be formed).

  In one aspect of the electro-optical device of the present invention, the second junction region is an LDD region.

  According to this aspect, the semiconductor layer has the LDD region, and the transistor is constructed as a transistor having an LDD structure. In addition to the second junction region, the first junction region may also be an LDD region.

  If a light leakage current is generated in the LDD region formed as the second junction region (hereinafter referred to as “pixel electrode side LDD region” as appropriate), the transistor is turned off due to the characteristics of the transistor having the LDD structure. Current flowing in the data line side source / drain region and the pixel electrode side source / drain region increases (ie, off current).

  However, in this embodiment, in particular, light incident on the pixel electrode side LDD region can be effectively shielded by the light shielding portion. Therefore, an increase in off-current as described above can be effectively prevented, and a high-quality image can be displayed.

  In the aspect including the above-described scanning line, the scanning line is formed on the lower layer side of the semiconductor layer via a base insulating film so as to at least partially overlap the predetermined region when viewed in plan on the substrate. The gate electrode is formed on the upper layer side of the semiconductor layer via the gate insulating film, and the light shielding portion is integrally formed from the same film as the gate electrode. And may be configured to be electrically connected to the scanning line.

  In this case, the scanning line is incident on the predetermined region of the semiconductor layer from the lower layer side (in other words, the substrate side) (for example, light due to reflection on the back surface of the substrate, a multi-plate projector, etc. It can function as a light-shielding film that shields light emitted from the electro-optical device and penetrating through the composite optical system. Note that as the light-blocking conductive material included in the scan line, a high-melting-point metal such as titanium or tungsten that can withstand high-temperature treatment of the semiconductor layer and has excellent conductivity is preferably used. Alternatively, in the case where low temperature treatment is sufficient for the semiconductor layer, not only the refractory metal but also aluminum or the like excellent in conductivity may be used.

  Further, the light shielding portion is integrally formed from the same film as the gate electrode, and is electrically connected to the scanning line. In other words, the light shielding portion is formed so as to cover a predetermined region and sidewall in the semiconductor layer and to connect the gate electrode formed on the upper layer side of the semiconductor layer and the scanning line formed on the lower layer side of the semiconductor layer. The Therefore, the gate electrode and the scanning line can be electrically connected by the light shielding portion. Furthermore, the predetermined region in the semiconductor layer can be almost or completely surrounded from the upper layer side, the side wall side, and the lower layer side by the light shielding portion and the scanning line functioning as a light shielding film, and the light shielding property with respect to the predetermined region in the semiconductor layer. Can be further improved. Therefore, the light leakage current in the semiconductor layer of the transistor can be further reduced.

  In addition, in this case, in particular, as described above, the scanning line can function as a light shielding film, and further, since the light shielding portion is integrally formed from the same film as the gate electrode, the device configuration is almost complicated. The light-shielding property can be further improved without making it. Therefore, it is possible to display a higher quality image while preventing an increase in the manufacturing period and an increase in cost.

  The “same film” according to the present invention means films formed on the same occasion in the manufacturing process and are the same kind of film. “Integrally formed” means continuous as a single film. In the present specification, “formed from the same film” does not mean that it is continuous as a single film, but is basically a film separated from each other in the same film. The purpose is sufficient if it is a part.

  In the aspect in which the above-described light-shielding portion is integrally formed from the same film as the gate electrode and is electrically connected to the scanning line, the channel is seen on the substrate in a plane above the semiconductor layer and viewed from above. A portion that is provided in an island shape so as not to overlap the region and at least overlaps the predetermined region, and includes an island-shaped insulating film having a thickness larger than the gate insulating film, and covers the predetermined region of the light shielding portion May be formed on the island-like insulating film.

  In this case, the gate electrode is disposed so as to face the channel region through the gate insulating film, and the portion of the light shielding portion that covers the predetermined region is made of an island-shaped insulating film having a thickness greater than that of the gate insulating film. It arrange | positions so that a predetermined area | region may be interposed. Therefore, the portion of the light shielding portion that is integrally formed from the same film as the gate electrode and covers the predetermined region in the semiconductor layer in the light shielding portion that is electrically connected to the gate electrode is further away from the gate electrode than the gate electrode. Placed in position.

  If the light-shielding portion electrically connected to the gate electrode is brought close to a predetermined region including the second junction region in the semiconductor layer, for example, to the thickness of the gate insulating film, the proximity of the light-shielding portion. This portion functions as an electrode for applying the same potential as the gate voltage to a predetermined region including the second junction region. That is, an unexpected change in carrier density occurs even in a predetermined region in the semiconductor layer. This inherently leads to the occurrence of leakage current, changes in on / off thresholds, and the like in a transistor that is supposed to have a channel formed by applying a gate voltage to the channel region.

  However, in this embodiment, since the island-shaped insulating film is provided, the light-shielding portion electrically connected to the gate electrode and the predetermined region in the semiconductor layer generate leakage current as described above, change in the on / off threshold value, and the like. Will not be in close proximity. Therefore, it is possible to effectively prevent malfunction in the transistor.

  In the aspect including the island-shaped insulating film described above, the island-shaped insulating film may be formed to face the semiconductor layer with a nitride film interposed therebetween.

  In this case, a nitride film such as a silicon nitride film is formed between the semiconductor layer and the island-like insulating film. The nitride film functions as a protective film when, for example, the island-shaped insulating film is patterned by an etching process. Therefore, it is possible to prevent the gate insulating film and the semiconductor layer from being damaged by excessive etching. Therefore, it is possible to prevent the manufacturing process from becoming more sophisticated.

  Furthermore, since the nitride film has a light shielding performance, it is possible to shield light that is about to enter the semiconductor layer. Therefore, it is possible to enhance the effect of preventing the occurrence of light leakage current in the semiconductor layer.

  In addition to the island-like insulating film, the sidewall may be formed so as to face the semiconductor layer via the nitride film.

  In the aspect in which the island-like insulating film is formed so as to face the semiconductor layer via the nitride film, the island-like insulating film and the sidewall have a dielectric constant lower than that of the nitride film. Also good.

  In this case, the island-like insulating film and the sidewall are formed from an insulating film (for example, a silicon oxide film) having a dielectric constant lower than that of the nitride film. Therefore, it is possible to reduce or practically eliminate the electrical adverse effect that the light shielding portion exerts on the predetermined region in the semiconductor layer via the island-shaped insulating film or the sidewall. Therefore, it is possible to prevent an unexpected change in carrier density from occurring in a predetermined region in the semiconductor layer.

  In order to solve the above problems, a method for manufacturing an electro-optical device according to the present invention includes a channel region, a data line side source / drain region, a pixel electrode side source / drain region, the channel region, and the data line side source / drain on a substrate. Forming a semiconductor layer having a first junction region formed between the regions and a second junction region formed between the channel region and the pixel electrode side source / drain region; and planarly on the substrate A step of forming a gate insulating film so as to overlap the semiconductor layer, and a sidewall made of an insulating film on a sidewall of a predetermined region including at least a part of the second junction region in the semiconductor layer. Forming a gate electrode so as to face the channel region with the gate insulating film interposed therebetween, and forming the predetermined region and the size of the gate region. Forming a light shielding portion so as to cover the wall; forming a data line so as to be electrically connected to the data line side source / drain region; and electrically connecting to the pixel electrode side source / drain region. Forming a pixel electrode.

  According to the electro-optical device manufacturing method of the present invention, the above-described electro-optical device of the present invention can be manufactured. Here, in particular, since the light-shielding portion is formed so as to cover the predetermined region and the sidewall in the semiconductor layer, for example, an etching process is performed on a portion on the side wall side of the semiconductor layer in the insulating film covering the semiconductor layer. After forming a contact hole or groove by using this method, when a light shielding part is formed in the contact hole or groove, a margin that takes into account the required resist mask misalignment becomes unnecessary, and the non-opening area in the pixel is reduced. it can.

  In one aspect of the method for manufacturing an electro-optical device according to the present invention, the semiconductor layer and the gate include a step of forming a scanning line so as to intersect the data line before the step of forming the semiconductor layer. The step of forming an insulating film includes a step of forming a first insulating film as a precursor film of a base insulating film serving as a base of the semiconductor layer on the upper side of the scanning line, and on the first insulating film. A step of forming a semiconductor film as a precursor film of the semiconductor layer, the channel region, the data line side source / drain region, the pixel electrode side source / drain region, the first junction region, and the semiconductor film. Forming a second junction region; forming a second insulating film as a precursor film of the gate insulating film on the semiconductor film; and forming a channel region on the second insulating film. No overlap and little A step of forming a third insulating film as a precursor film of an island-shaped insulating film overlapping at least the predetermined region; the first insulating film; the semiconductor film; the second insulating film; and a third insulating film. Is etched using a mask having a pattern corresponding to the semiconductor layer, and the first insulating film, the semiconductor film, the second insulating film, and the third insulating film are patterned at once. The step of forming the sidewall includes a step of forming the base insulating film, the semiconductor layer, and the gate insulating film, and the step of forming the sidewall includes a precursor of the sidewall on the patterned third insulating film. Forming a sidewall, comprising: forming a fourth insulating film as a film; and forming the sidewall by subjecting the fourth insulating film to anisotropic etching. A step of forming an island-like insulating film by performing an etching process on a portion of the patterned third insulating film overlapping the channel region after the step of forming the gate electrode and the light shielding Forming a light-shielding conductive film so as to cover the channel region, the predetermined region, and the sidewall and to be electrically connected to the scanning line, thereby forming the gate electrode and A step of integrally forming the light shielding portion.

  According to this aspect, the above-described electro-optical device of the present invention can be more suitably manufactured, and the aperture ratio can be increased while further improving the light-shielding property with respect to the predetermined region in the semiconductor layer.

  In another aspect of the method for manufacturing an electro-optical device according to the invention, a scan line is formed so as to intersect the data line before the step of forming the semiconductor layer, and the semiconductor layer and the semiconductor layer The step of forming a gate insulating film includes a step of forming a first insulating film as a precursor film of a base insulating film serving as a base of the semiconductor layer on the upper side of the scanning line, and on the first insulating film. Forming a semiconductor film as a precursor film of the semiconductor layer, and forming the channel region, the data line side source / drain region, the pixel electrode side source / drain region, the first junction region, Forming the second junction region, forming a second insulating film as a precursor film of the gate insulating film on the semiconductor film, and forming a first insulating film on the second insulating film. Forming a nitride film; Forming a third insulating film on the first nitride film as a precursor film of an island-shaped insulating film that does not overlap the channel region and at least overlaps the predetermined region; and the first insulating film, Etching is performed on the semiconductor film, the second insulating film, the first nitride film, and the third insulating film using a mask having a pattern corresponding to the semiconductor layer, and the first insulating film Forming the base insulating film, the semiconductor layer, and the gate insulating film by patterning the semiconductor film, the second insulating film, the first nitride film, and the third insulating film at once. And forming the sidewall includes forming a second nitride film so as to cover the patterned third insulating film, and forming the sidewall on the second nitride film. Fourth insulation as a precursor film And a step of forming the sidewall by subjecting the second nitride film and the fourth insulating film to anisotropic etching, and after the step of forming the sidewall Forming the island-like insulating film by performing an etching process on a portion of the patterned third insulating film that overlaps the channel region, and forming the gate electrode and the light shielding portion. The step is to form the light-shielding conductive film so as to cover the channel region, the predetermined region, and the sidewall and to be electrically connected to the scanning line, so that the gate electrode and the light-shielding portion are formed. The process of forming integrally is included.

  According to this aspect, the above-described electro-optical device of the present invention can be more suitably manufactured, and the aperture ratio can be increased while further improving the light-shielding property with respect to the predetermined region in the semiconductor layer. Here, in particular, since the process includes a process of forming a first nitride film and a process of forming a second nitride film, for example, a patterned third insulating film performed after the process of forming a sidewall is performed. In the step of forming the island-like insulating film by performing etching on the portion overlapping the channel region in FIG. 2, the etching is performed on the lower layer side (for example, the gate insulating film, the semiconductor layer, the scanning line, etc.) than the nitride film. Can be prevented.

  In order to solve the above-described problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention.

  According to the electronic apparatus of the present invention, since the electro-optical device of the present invention described above (including various aspects thereof) is provided, a projection display device capable of performing high-quality display, portable Various electronic devices such as a telephone, an electronic notebook, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus according to the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a schematic plan view showing a configuration of a liquid crystal device as seen from the side of a counter substrate, together with each component formed on the TFT array substrate, and FIG. 'Cross section.

  1 and 2, the liquid crystal device according to the present embodiment includes a TFT array substrate 10 and a counter substrate 20 that are arranged to face each other. The TFT array substrate 10 is, for example, a transparent substrate such as a quartz substrate or a glass substrate, or a silicon substrate. The counter substrate 20 is also a substrate made of the same material as the TFT array substrate 10, for example. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are sealed in a seal region positioned around the image display region 10a. The materials 52 are bonded to each other.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. Further, for example, in the sealing material 52, a gap material 56 such as a glass fiber or a glass bead for dispersing the distance (inter-substrate gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed. The liquid crystal device according to this embodiment is small and suitable for performing enlarged display for a light valve of a projector.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  A data line driving circuit 101, a sampling circuit 7, a scanning line driving circuit 104, and an external circuit connection terminal 102 are formed in the peripheral area located around the image display area 10 a on the TFT array substrate 10.

  In the peripheral region on the TFT array substrate 10, the data line driving circuit 101 and the external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 on the outer peripheral side from the seal region. Further, a region located on the inner side of the seal region in the peripheral region on the TFT array substrate 10 is covered with the frame light shielding film 53 along one side of the image display region 10 a along one side of the TFT array substrate 10. A sampling circuit 7 is arranged.

  The scanning line driving circuit 104 is provided along two sides adjacent to one side of the TFT array substrate 10 so as to be covered with the frame light shielding film 53. Further, in order to electrically connect the two scanning line driving circuits 104 provided on both sides of the image display region 10a in this way, the TFT array substrate 10 is covered with the frame light shielding film 53 along the remaining side. A plurality of wirings 105 are provided.

  In the peripheral region on the TFT array substrate 10, vertical conduction terminals 106 are disposed in regions facing the four corners of the counter substrate 20, and vertical conduction is provided between the TFT array substrate 10 and the counter substrate 20. A material is provided corresponding to the vertical conduction terminal 106 and electrically connected to the terminal 106.

  In FIG. 2, on the TFT array substrate 10, a laminated structure is formed in which wirings such as TFTs for pixel switching, scanning lines, and data lines are formed. In the image display area 10a, pixel electrodes 9a are provided in a matrix on the upper layer of wiring such as pixel switching TFTs, scanning lines, and data lines. An alignment film 16 is formed on the pixel electrode 9a.

  On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned, for example, in a lattice shape in the image display region 10a on the counter substrate 20. A counter electrode 21 made of a transparent conductive material such as ITO is formed on the light shielding film 23 (below the light shielding film 23 in FIG. 2) so as to face the plurality of pixel electrodes 9a. An alignment film 22 is formed on 21 (below the counter electrode 21 in FIG. 2).

  The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films. A liquid crystal storage capacitor is formed between the pixel electrode 9 a and the counter electrode 21 by applying a voltage to each of the liquid crystal devices during driving.

  Although not shown here, on the TFT array substrate 10, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, a plurality of data lines are precharged at a predetermined voltage level prior to the image signal. A precharge circuit to be supplied, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during manufacture or at the time of shipment may be formed.

  Next, an electrical configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIG.

  FIG. 3 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms the image display area of the liquid crystal device according to the present embodiment.

  In FIG. 3, each of the plurality of pixels formed in a matrix that forms the image display area 10 a is constructed including the pixel electrode 9 a and an example of the “semiconductor layer” and “gate electrode” according to the present invention. A TFT 30 is formed. The TFT 30 is electrically connected to the pixel electrode 9a, and performs switching control of the pixel electrode 9a during the operation of the liquid crystal device according to the present embodiment. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. Good.

  The scanning line 11 is electrically connected to the gate of the TFT 30, and the liquid crystal device according to this embodiment applies the scanning signals G1, G2,..., Gm to the scanning line 11 in this order at a predetermined timing. It is configured to apply line-sequentially. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the TFT 30 as a switching element for a certain period. It is written at a predetermined timing. A predetermined level of image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a is held for a certain period with the counter electrode formed on the counter substrate.

  The liquid crystal constituting the liquid crystal layer 50 (see FIG. 2) modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The transmittance for light is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added electrically in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode 21 (see FIG. 2). ing. The storage capacitor 70 is a capacitive element that functions as a storage capacitor that temporarily holds the potential of each pixel electrode 9a in response to supply of an image signal. According to the storage capacitor 70, the potential holding characteristic in the pixel electrode 9a is improved, and display characteristics such as contrast improvement and flicker reduction can be improved. A specific configuration of the storage capacitor 70 will be described in detail later.

  Next, a specific configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIGS.

  FIG. 4 is a plan view of the pixel portion of the liquid crystal device according to the first embodiment. FIG. 5 is a plan view showing the configuration of the TFT for pixel switching, focusing on the configuration. FIG. 6 is a cross-sectional view taken along the line A-A ′ of FIG. 4. 7 is a diagram showing a cross-sectional view taken along line BB ′ in FIG. 5 and a cross-sectional view taken along line CC ′ in FIG. 5. FIG. 7A is a cross-sectional view taken along line BB ′ in FIG. FIG. 7B is a cross-sectional view taken along the line CC ′ of FIG.

  In FIGS. 6 and 7, the scales of the layers and members are different from each other in order to make the layers and members recognizable on the drawings. 4 and 6, for convenience of explanation, illustration of a portion located above the pixel electrode 9a is omitted. 4 and 5, some wirings and electrodes such as the scanning lines 11 are transparently illustrated.

  In FIG. 4, a plurality of pixel electrodes 9a are provided in a matrix on the TFT array substrate 10 (see FIG. 2), and are transparent electrodes made of a transparent conductive material such as ITO, for example. Data lines 6a and scanning lines 11 are provided along the vertical and horizontal boundaries of the pixel electrode 9a. In other words, the scanning line 11 extends along the X direction, and the data line 6 a extends along the Y direction so as to intersect the scanning line 11. On the upper layer side of the scanning line 11, a pixel switching TFT 30 as shown in an enlarged view in FIG. 5 is provided for each pixel electrode 9a.

  The scanning line 11, the data line 6a, the TFT 30, and the relay electrode 60 to be described later are viewed on the TFT array substrate 10 in plan view, and the opening area of each pixel corresponding to the pixel electrode 9a (that is, each pixel is actually displayed. Is disposed in a non-opening region surrounding a region where light contributing to the light is transmitted or reflected. That is, the scanning line 11, the data line 6a, the TFT 30, and the relay electrode 60 are arranged not in the opening area of each pixel but in the non-opening area so as not to disturb display.

  During the operation of the liquid crystal device according to the present embodiment, the supply of the image signal from the data line 6a to the pixel electrode 9a is controlled, and the so-called active matrix image display is possible. The image signal is data at a predetermined timing when the TFT 30 which is a switching element electrically connected between the data line 6a and the pixel electrode 9a is turned on / off according to the scanning signal supplied from the scanning line 11. The pixel electrode 9a is supplied from the line 6a through the TFT 30.

  As shown in FIG. 6, on the TFT array substrate 10, various components such as the pixel electrode 9a described above have a laminated structure.

  Hereinafter, the components of the pixel portion shown in FIGS. 4 to 7 will be described in order from the lower layer side.

  In FIG. 6, the scanning line 11 is disposed on the TFT array substrate 10 and is made of a light-shielding conductive material such as a refractory metal material such as tungsten (W), Ti, or TiN. 4 and 5, the scanning line 11 is formed so as to extend along the X direction and include a region facing the channel region 1a ′ of the TFT 30 and the LDD region 1c on the pixel electrode side. Yes. According to such a scanning line 11, the TFT 30 receives the return light such as the back surface reflection on the TFT array substrate 10 or the light emitted from another liquid crystal device by a multi-plate projector or the like and penetrating the composite optical system. The channel region 1a ′ and the pixel electrode side LDD region 1c can be almost shielded from light. That is, the scanning line 11 can also function as a light-shielding film that shields light incident from the TFT array substrate 10 side, in addition to the function as a scanning line that supplies the scanning signal Gi to the TFT 30. Furthermore, according to such a scanning line 11, it is possible to perform a high temperature process after the scanning line 11 is formed. That is, for example, when forming the semiconductor layer 1a constituting a part of the TFT 30 above the scanning line 11, the semiconductor layer 1a is performed in a relatively high temperature environment such as a low pressure CVD (Chemical Vapor Deposition) method. It can be formed by a process.

  6 and 7, the base insulating film 12 is made of, for example, a silicon oxide film. The base insulating film 12 is formed on the TFT array substrate 10 so as to have the same plane pattern as the semiconductor layer 1a. In addition to the function of insulating the semiconductor layer 1a from the scanning line 11, the base insulating film 12 is formed as a base of the semiconductor layer 1a, so that the surface of the TFT array substrate 10 is roughened during polishing or remains after cleaning. It has a function of preventing deterioration of the characteristics of the TFT 30 due to the above.

  4 to 6, the TFT 30 includes the semiconductor layer 1a and the gate electrode 3a.

  The semiconductor layer 1a is made of polysilicon and has a channel region 1a ', a data line side LDD region 1b, a pixel electrode side LDD region 1c, and a data line side source / drain region provided along the X direction shown in FIGS. 1d and the pixel electrode side source / drain region 1e. That is, the TFT 30 has an LDD structure. The data line side LDD region 1b is an example of the “first junction region” according to the present invention, and the pixel electrode side LDD region 1c is an example of the “second junction region” according to the present invention.

  The data line side source / drain region 1d and the pixel electrode side source / drain region 1e are formed substantially in mirror symmetry along the X direction with respect to the channel region 1a '. The data line side LDD region 1b is formed between the channel region 1a 'and the data line side source / drain region 1d. The pixel electrode side LDD region 1c is formed between the channel region 1a 'and the pixel electrode side source / drain region 1e. The data line side LDD region 1b, the pixel electrode side LDD region 1c, the data line side source / drain region 1d, and the pixel electrode side source / drain region 1e are formed by implanting impurities into the semiconductor layer 1a by, for example, ion implantation. This is an impurity region. The data line side LDD region 1b and the pixel electrode side LDD region 1c are formed as low concentration impurity regions with less impurities than the data line side source / drain region 1d and the pixel electrode side source / drain region 1e, respectively. According to such an impurity region, when the TFT 30 is not operating, the off-current flowing between the source region and the drain region can be reduced, and a decrease in the on-current flowing when the TFT 30 is operating can be suppressed. The TFT 30 preferably has an LDD structure. However, the TFT 30 may have an offset structure in which no impurity is implanted into the data line side LDD region 1b and the pixel electrode side LDD region 1c, or the data line side LDD region 1b and the pixel. The data line side source / drain region 1d and the pixel electrode side source / drain region 1e may be formed adjacent to both sides of the channel region 1a 'without forming the electrode side LDD region 1c.

  In FIG. 5, the gate insulating film 2 is made of, for example, a silicon oxide film. The gate insulating film 2 is formed on the TFT array substrate 10 so as to have the same plane pattern as that of the semiconductor layer 1a. The gate insulating film 2 electrically insulates the gate electrode 3a and the channel region 1a '.

  As shown in FIG. 4 to FIG. 7, among the two types of LDD regions in the semiconductor layer 1a (that is, the data line side LDD region 1b and the pixel electrode side LDD region 1c), the island is at least with respect to the pixel electrode side LDD region 1c. An insulating film 31 is provided. As shown in FIG. 5, the island-shaped insulating film 31 does not overlap the channel region 1a ′ and overlaps the pixel electrode side LDD region 1c and the pixel electrode side source / drain region 1e with respect to the pixel electrode side LDD region 1c. It is formed to have a flat island-like pattern. The island-like insulating film 31 is provided for the data line side LDD region 1b as well as the pixel electrode side LDD region 1c side. That is, the island-shaped insulating film 31 is not in the channel region 1a ′ but overlaps the data line side LDD region 1b and the data line side source / drain region 1d with respect to the data line side LDD region 1b. It is formed to have a pattern. As shown in FIGS. 6 and 7, the island-shaped insulating film 31 is formed of, for example, a silicon nitride film or the like so as to have a film thickness thicker than that of the gate insulating film 2. Incidentally, by forming the island-like insulating film 31 from a silicon nitride film, the etching selectivity of the island-like insulating film 31 with respect to the gate insulating film 2 made of a silicon oxide film can be increased. Therefore, in the manufacturing process, when the island-shaped insulating film 31 is patterned by an etching process, the gate insulating film 2 formed from the silicon oxide film can be prevented from being damaged by the etching process.

  As shown in FIGS. 6 and 7, a sidewall 61 is provided on the sidewall of the semiconductor layer 1a. The sidewall 61 is made of an insulating film such as a silicon oxide film, for example, and extends along the thickness direction of the semiconductor layer 1a (that is, along the stacking direction on the TFT array substrate 10) on the sidewall of the semiconductor layer 1a. Is formed. More specifically, the sidewall 61 extends along the stacking direction on the side wall of the stacked body in which the base insulating film 12, the semiconductor layer 1a, the gate insulating film 2, and the island-shaped insulating film 31 are stacked. Is formed. For example, the sidewall 61 is formed after an insulating film such as a silicon oxide film is once formed so as to cover a stacked body in which the base insulating film 12, the semiconductor layer 1a, the gate insulating film 2, and the island-shaped insulating film 31 are stacked. In this insulating film, a portion extending in a planar manner so that a portion extending in the thickness direction of the semiconductor layer 1a remains (in other words, a portion extending along the substrate surface of the TFT array substrate 10). It is formed by removing by an anisotropic etching process.

  4 to 7, the gate electrode 3 a is provided via the gate insulating film 2 so as to overlap the channel region 1 a ′ when viewed in plan on the TFT array substrate 10. Further, the gate electrode 3a extends from the portion overlapping the channel region 1a ′ to the data line side source / drain region 1d side so as to overlap a part of the data line side LDD region 1b, and to the channel region 1a ′. From the overlapping portion, the pixel electrode side source / drain region 1e side is extended so as to overlap all of the pixel electrode side LDD region 1c and part of the pixel electrode side source / drain region 1e. The gate electrode 3a is formed of a light-shielding conductive film having a two-layer structure in which a lower layer is made of conductive polysilicon and an upper layer is a layer containing aluminum. The layer containing aluminum may be formed only from an aluminum film, for example, a titanium (Ti) film, a titanium nitride (TiN) film, an aluminum (Al) film, and a titanium nitride (TiN) film in this order. You may form from the multilayer film laminated | stacked from the lower layer side. In other words, the gate electrode 3a may be formed by laminating a conductive polysilicon film and an aluminum film in this order from the lower layer side. For example, a conductive polysilicon film, a Ti film, a TiN film The Al film and the TiN film may be formed by laminating from the lower layer side in this order. The gate electrode 3a may be formed of a single layer or multiple layers such as a conductive polysilicon film, a metal film, or a metal silicide film.

  5 and 7, in this embodiment, in particular, the gate electrode 3a includes a channel region 1a ', a part of the data line side LDD region 1b, a pixel electrode side LDD region 1c, and a part of the pixel electrode side source / drain region 1e. , And the side wall 61 formed on the side wall of these regions. A portion of the gate electrode 3a formed along the surface of the sidewall 61 is in contact with the scanning line 11, so that the gate electrode 3a and the scanning line 11 are electrically connected. In other words, as well shown in FIG. 7B, the gate electrode 3a is on the upper layer side through the gate insulating film 2 and the island-shaped insulating film 31 with respect to the pixel electrode side LDD region 1c in the semiconductor layer 1a. It has a formed portion and a portion formed on the side wall side through the side wall 61. That is, the gate electrode 3a has a portion formed so as to surround the pixel electrode side LDD region 1c in the semiconductor layer 1a from the upper layer side and the side wall side thereof.

  Thus, the gate electrode 3a can block light incident from the upper layer side and light incident from the side wall side on at least the pixel electrode side LDD region 1c in the semiconductor layer 1a. Therefore, it is possible to improve the light shielding property with respect to the pixel electrode side LDD region 1c, which is a region where the light leakage current is particularly likely to occur in the semiconductor layer 1a. As a result, the light leakage current in the TFT 30 can be effectively reduced.

  As well shown in FIG. 7A, the gate electrode 3a has a portion formed on the upper layer side through the gate insulating film 2 with respect to the channel region 1a ′ in the semiconductor layer 1a. It has a portion formed on the side wall side through the wall 61. That is, the gate electrode 3a also has a portion formed so as to surround the channel region 1a 'in the semiconductor layer 1a from the upper layer side and the side wall side thereof. Therefore, the gate electrode 3a can also block the light incident from the upper layer side and the light incident from the side wall side on the channel region 1a 'in the semiconductor layer 1a.

  Here, in FIG. 7B, in the present embodiment, a portion of the gate electrode 3 a that is provided on the side wall side of the pixel electrode side LDD region 1 c in the semiconductor layer 1 a is provided on the side wall 61. Therefore, the width d1 of the sidewall 61 can be reduced within a range in which the gate electrode 3a and the pixel electrode-side LDD region 1c in the semiconductor layer 1a can be electrically insulated, and the non-opening region in the pixel can be reduced. Thus, it is possible to increase the opening area and increase the opening ratio. In other words, by forming a part of the gate electrode 3a so as to cover the sidewall 61, the gate electrode 3a and the scanning line 11 can be electrically connected without passing through the contact hole, and the gate electrode 3a. Can be disposed closer to the side wall side of the semiconductor layer 1a than when, for example, a contact hole is used, and the non-opening region defined by the gate electrode 3a can be reduced.

  Further, in FIGS. 6 and 7, particularly in the present embodiment, the gate electrode 3a is formed on the gate insulating film 2 in a portion overlapping the channel region 1a ′ (see FIGS. 6 and 7A). The portions overlapping the data line side LDD region 1b and the pixel electrode side LDD region 1c are formed on the island-like insulating film 31 (see FIGS. 6 and 7B). That is, the portion of the gate electrode 3a that overlaps the channel region 1a ′ is disposed so as to face the channel region 1a ′ with the gate insulating film 2 interposed therebetween, and the data line side LDD region 1b and the pixel electrode side of the gate electrode 3a. A portion overlapping the LDD region 1c is disposed so as to face the data line side LDD region 1b and the pixel electrode side LDD region 1c with the island-like insulating film 31 interposed therebetween. Therefore, the gate electrode 3a is not brought close to the data line side LDD region 1b and the pixel electrode side LDD region 1c until they adversely affect the data. Therefore, it is possible to effectively prevent malfunctions in the TFT 30. From this point of view, the island-like insulating film 31 is preferably formed to have a film thickness of, for example, about several tens to several thousand nm (nanometers).

  According to the configuration of the gate electrode 3a as described above, the scanning line 11 that functions as a light-shielding film that shields light incident on the semiconductor layer 1a from the TFT array substrate 10 side, and at least the pixel electrode side in the semiconductor layer 1a. It is possible to reliably improve the light shielding property for the LDD region 1c. Therefore, the light leakage current can be more effectively prevented by blocking the light that enters the pixel electrode side LDD region 1c, which is a region where the light leakage current is particularly likely to occur in the semiconductor layer 1a. . Furthermore, the portion of the gate electrode 3a provided on the side wall side of the pixel electrode side LDD region 1c is provided on the side wall 61, so that it can be disposed close to the pixel electrode side LDD region 1c. Yes, the aperture ratio can be improved.

  In FIG. 6, a data line 6a and a relay electrode 60 are provided on the upper layer side of the semiconductor layer 1a on the TFT array substrate 10 via the gate insulating film 2 and the island-shaped insulating film 31.

  The data line 6a is made of the same film as the gate electrode 3a (and the relay layer 60). That is, like the gate electrode 3a, the data line 6a is formed as a film having a two-layer structure of a layer made of conductive polysilicon in the lower layer and a layer containing aluminum in the upper layer. The data line 6a is formed to extend along the Y direction in FIG. The data line 6a is electrically connected to the data line side source / drain region 1d of the TFT 30 through a contact hole 81 opened through the island-like insulating film 31 and the gate insulating film 2. The electrical connection between the data line 6a and the data line side source / drain region 1d of the TFT 30 is made between the conductive polysilicon layer constituting the data line 6a and the data line side source / drain region 1d made of polysilicon. It is realized by contact, and the electrical connection between the two can be improved.

  The relay electrode 60 is made of the same layer as the gate electrode 3a (and the data line 6a). That is, like the gate electrode 3a, the relay electrode 60 is formed as a film having a two-layer structure of a layer made of conductive polysilicon in the lower layer and a layer containing aluminum in the upper layer. The relay electrode 60 is electrically connected to the pixel electrode side source / drain region 1e of the TFT 30 through the contact hole 83 formed in the island-shaped insulating film 31 and the gate insulating film 2, and is connected to the interlayer insulating film 41 and the capacitor. It is electrically connected to the pixel electrode 9a through a contact hole 85 opened through the insulating film 75. Therefore, the relay electrode 60 relays the electrical connection between the pixel electrode 9a and the pixel electrode side source / drain region 1e of the TFT 30. Therefore, it is possible to avoid a situation in which the interlayer distance between the relay electrode 60 and the pixel electrode side source / drain region 1e is long and it is difficult to connect the two using a single contact hole. Further, the relay electrode 60 makes it possible to reduce the electrical resistance between the pixel electrode 9a and the pixel electrode side source / drain region 1e.

  As shown in FIGS. 4 to 6, the gate electrode 3 a, the data line 6 a, and the relay electrode 60 are formed so as to have a planar shape that is continuous with each other when viewed in plan on the TFT array substrate 10. Instead, each person is formed so as to be divided for patterning. Thus, the gate electrode 3a, the data line 6a, and the relay electrode 60 are electrically insulated from each other by the interlayer insulating film 41. By forming the gate electrode 3a, the data line 6a, and the relay electrode 60 from the same film in this way, the structure of the pixel is simplified and manufactured as compared with the case where they are separately formed from different materials. The number of steps in the process can also be reduced and simplified.

  The interlayer insulating film 41 is made of, for example, NSG (non-silicate glass). As the interlayer insulating film 41, silicate glass such as PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride film, silicon oxide film, or the like can be used.

  In FIG. 6, a capacitor electrode 71 is provided on the upper layer side of the data line 6 a on the TFT array substrate 10 via the interlayer insulating film 41. The capacitor electrode 71 is provided so as to cover both the opening region and the non-opening region except for a portion where the contact hole 85 for electrically connecting the pixel electrode 9a and the relay electrode 60 is provided.

  The capacitor electrode 71 is disposed so as to face the pixel electrode 9 a with the capacitor insulating film 75 therebetween, and forms a storage capacitor 70.

  The capacitive electrode 71 is a fixed potential side capacitive electrode that is electrically connected to a constant potential source through a capacitive line, for example, and maintained at a fixed potential. The capacitor electrode 71 is made of a transparent conductive material such as ITO.

  The capacitor insulating film 75 is, for example, a single layer structure or a multilayer structure formed of a silicon oxide (SiO 2) film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or a silicon nitride (SiN) film. have.

  As described above, by forming the storage capacitor 70, the potential holding characteristic of the pixel electrode 9a is improved, and it is possible to improve display characteristics such as improvement of contrast and reduction of flicker. In addition, since the storage capacitor 70 is formed by the pixel electrode 9a and the capacitor electrode 71, the device configuration is compared with a case where, for example, an upper electrode and a lower electrode are provided in addition to the pixel electrode 9a to form a storage capacitor. Can be simplified.

  Furthermore, since the capacitor electrode 71 is provided on the lower layer side than the pixel electrode 9a, electrical or electromagnetic coupling between the pixel electrode 9a and the lower layer side (for example, the data line 6a) of the capacitor electrode 71 is prevented. It can also function as a shield layer. Therefore, it is possible to reduce the possibility of potential fluctuations or the like in the pixel electrode 9a.

  The configuration of the pixel portion described above is common to each pixel portion as shown in FIG. Such pixel portions are periodically formed in the image display area 10a (see FIG. 1).

  As described above, according to the liquid crystal device according to the present embodiment, it is possible to improve the aperture ratio while improving the light shielding property to the pixel switching TFT 30. As a result, a bright and high-quality image can be displayed. Here, in particular, when the pixel pitch is miniaturized to meet the demand for further improvement in display performance, it is technically considered to reduce the area of the non-opening region by finely processing the wiring or the electrode. Since it becomes more difficult, by using the sidewall 61, a method of arranging a part of the gate electrode 3a functioning as a light-shielding film close to the sidewall side with respect to the semiconductor layer 1a is a viewpoint of increasing the aperture ratio. Has a tremendous effect.

Second Embodiment
Next, a liquid crystal device according to a second embodiment will be described with reference to FIGS.

  FIG. 8 is a sectional view having the same concept as in FIG. 6 in the second embodiment. 9 is a diagram having the same concept as in FIG. 7 in the second embodiment, FIG. 9A is a cross-sectional view having the same concept as FIG. 7A in the second embodiment, and FIG. It is sectional drawing with the same meaning as FIG.7 (b) in 2nd Embodiment. 8 and 9, the same reference numerals are given to the same components as the components according to the first embodiment shown in FIGS. 1 to 7, and the description thereof will be omitted as appropriate.

  8 and 9, the liquid crystal device according to the second embodiment does not include the island-like insulating film 31 in the first embodiment described above, and a gate instead of the gate electrode 3a in the first embodiment described above. Unlike the liquid crystal device according to the first embodiment described above in that the electrode 3b is provided, the other points are substantially the same as those of the liquid crystal device according to the first embodiment described above.

  8 and 9, in the present embodiment, the TFT 30 includes the semiconductor layer 1a and the gate electrode 3b.

  The gate electrode 3b is provided via the gate insulating film 2 so as to overlap the channel region 1a 'when viewed in plan on the TFT array substrate 10. Further, the gate electrode 3b extends from the portion overlapping the channel region 1a ′ to the data line side source / drain region 1d side so as to overlap the data line side LDD region 1b, and from the portion overlapping the channel region 1a ′. The pixel electrode side source / drain region 1e is extended so as to overlap the pixel electrode side LDD region 1c. Here, in this embodiment, the island-shaped insulating film 31 in the first embodiment described above is not provided, and the gate electrode 3b is connected to the channel region 1a ′ and the data line side LDD region 1b via the gate insulating film 2. And the pixel electrode side LDD region 1c. That is, the TFT 30 in this embodiment has a so-called GOLD (Gate OverLapped LDD) structure. Therefore, it is possible to increase the on-current that flows when the TFT 30 operates.

  As shown in FIG. 9, the gate electrode 3b is formed so as to cover the channel region 1a ′, the data line side LDD region 1b, the pixel electrode side LDD region 1c, and the sidewalls 61 formed on the sidewalls of these regions. Has been. In addition, although illustration is abbreviate | omitted here about the part formed so that the data line side LDD area | region 1b and the side wall 61 formed on the side wall among the gate electrodes 3b may be omitted, Of these, the pixel electrode side LDD region 1c and the portion (see FIG. 9B) formed so as to cover the side wall 61 formed on the side wall thereof are formed.

  A portion of the gate electrode 3b formed along the surface of the sidewall 61 is in contact with the scanning line 11, so that the gate electrode 3b and the scanning line 11 are electrically connected. In other words, as well shown in FIG. 9, the gate electrode 3b is connected to the channel region 1a ′, the data line side LDD region 1b, and the pixel electrode side LDD region 1c in the semiconductor layer 1a via the gate insulating film 2. It has a portion formed on the upper layer side and a portion formed on the side wall side through the sidewall 61. That is, the gate electrode 3b is formed so as to surround the channel region 1a ', the data line side LDD region 1b, and the pixel electrode side LDD region 1c in the semiconductor layer 1a from the upper layer side and the side wall side.

  Therefore, the gate electrode 3b blocks the light incident from the upper layer side and the light incident from the side wall side on the channel region 1a ′, the data line side LDD region 1b, and the pixel electrode side LDD region 1c in the semiconductor layer 1a. can do. Accordingly, it is possible to improve the light shielding property for the region including the pixel electrode side LDD region 1c, which is a region where light leakage current is particularly likely to occur in the semiconductor layer 1a. Thereby, the light leakage current in the TFT 30 can be reliably reduced.

<Third Embodiment>
Next, a liquid crystal device according to a third embodiment will be described with reference to FIG.

  FIG. 10 is a diagram having the same concept as in FIG. 7 in the third embodiment, FIG. 10A is a cross-sectional view having the same concept as FIG. 7A in the third embodiment, and FIG. It is sectional drawing with the same meaning as FIG.7 (b) in 3rd Embodiment. In FIG. 10, the same reference numerals are given to the same components as those according to the first embodiment shown in FIGS. 1 to 7, and description thereof will be omitted as appropriate.

  In FIG. 10, the liquid crystal device according to the second embodiment is further provided with a nitride film 110, and the gate electrode 3c is replaced with the gate electrode 3a, the island-like insulating film 31 and the sidewall 61 in the first embodiment described above. The liquid crystal device according to the first embodiment is different from the liquid crystal device according to the first embodiment described above in that the island-shaped insulating film 33 and the sidewall 63 are provided, and the other points are substantially the same as those of the liquid crystal device according to the first embodiment described above. ing.

  In FIG. 10B, the island-like insulating film 33 is formed on the upper side of the pixel electrode side LDD region 1c in the semiconductor layer 1a via the gate insulating film 2 and the nitride film 110. That is, the nitride film 110 is formed between the semiconductor layer 1 a and the island-like insulating film 33 in the stacked structure on the TFT array substrate 10. The island-like insulating film 33 is formed from a silicon oxide film, and the nitride film 110 is formed from a silicon nitride film. Therefore, the nitride film 110 functions as a protective film, for example, when the island-shaped insulating film 33 is patterned by an etching process. Therefore, it is possible to prevent the gate insulating film 2 and the semiconductor layer 1a from being damaged by excessive etching.

  Furthermore, since the nitride film 110 is formed of a silicon nitride film having a light shielding performance, it is possible to shield light that is about to enter the semiconductor layer. Therefore, it is possible to enhance the effect of preventing the occurrence of light leakage current in the semiconductor layer.

  In addition, since the nitride film 110 functions as a protective film as described above, the island-like insulating film 33 can be formed from a material having a low etching selectivity with respect to the gate insulating film 2. Therefore, as in this embodiment, the island-like insulating film 33 can be formed from a silicon oxide film having a relatively low low dielectric constant. That is, in this embodiment, since the island-like insulating film 33 is formed so as to face the semiconductor layer 1a via the nitride film 110, it is possible to reduce the dielectric constant of the island-like insulating film 33. It becomes. Therefore, for example, it is possible to reduce the adverse electrical effect that the portion of the gate electrode 3c that overlaps with the pixel electrode side LDD region 1c exerts on the pixel electrode side LDD region 1c via the island-shaped insulating film 33. Thereby, it is possible to prevent an unexpected change in carrier density from occurring in the semiconductor layer 1a.

  In FIG. 10, the side wall 63 is not provided on the side wall side of the channel region 1a ′ (see FIG. 10A), but is provided on the side wall side of the pixel electrode side LDD region 1c (FIG. 10 ( b)). The side wall 63 is provided not only on the side wall side of the pixel electrode side LDD region 1c but also on each side wall side of the data line side source / drain region 1d, the data line side LDD region 1b, and the pixel electrode side source / drain region 1e. It has been.

  The sidewall 63 is made of a silicon oxide film and has a relatively low dielectric constant. Therefore, for example, the portion of the gate electrode 3c that covers the sidewall 63 formed on the side wall of the pixel electrode side LDD region 1c exerts on the pixel electrode side LDD region 1c via the island-shaped insulating film 33. Adverse effects can be reduced. Thereby, it is possible to prevent an unexpected change in carrier density from occurring in the semiconductor layer 1a.

  Here, the reason why the light leakage current is more likely to occur in the pixel electrode side LDD region 1c than in the data line side LDD region 1b during the operation of the TFT 30 described above will be described with reference to FIGS. This will be described in detail.

  First, a measurement result obtained by measuring the magnitude of the drain current when the test TFT is irradiated with light will be described with reference to FIG. FIG. 11 is a graph showing the relationship between the light irradiation position and the drain current in the test TFT.

  In FIG. 11, data E1 scans a light spot (approximately 2.4 um visible light laser) sequentially from the drain region side to the source region side with respect to a single TFT for test, that is, TEG (Test Element Group). The result of having measured the magnitude | size of the drain current at the time of irradiating is shown. TEG includes a channel region, a source region, and a drain region, a source side junction region formed at a junction between the channel region and the source region, and a drain side junction region formed at a junction between the channel region and the drain region. have.

  The horizontal axis in FIG. 11 indicates the light irradiation position where the light spot is irradiated. The boundary between the channel region and the drain side junction region, the boundary between the channel region and the source side junction region, and the channel region are zeroed. It is said. The vertical axis in FIG. 11 indicates the magnitude of the drain current (however, a relative value normalized by a predetermined value). When the drain current flows from the drain region to the source region, the vertical axis is positive. When the drain current is flowing from the source region to the drain region, a negative value (that is, a negative value) is indicated.

  In FIG. 11, data E1 shows a positive value at any light irradiation position. That is, the drain current flows from the drain region toward the source region. Data E1 shows a larger value in the drain side junction region than in the source side junction region. That is, when the light spot is irradiated into the drain side junction region, the drain current becomes larger than when the light spot is irradiated into the source side junction region. That is, when the light spot is irradiated into the drain side junction region, the light leakage current becomes larger than when the light spot is irradiated into the source side junction region. Note that the drain current includes dark current (or subthreshold leakage, that is, leakage current that flows between the source region and the drain region even when light is not irradiated) and optical leakage current (or photoexcitation current, that is, Current generated by excitation of electrons due to light irradiation).

  Next, with respect to a mechanism in which the light leakage current becomes larger when the light spot is irradiated in the drain side junction region than in the case where the light spot is irradiated in the source side junction region, FIGS. Will be described with reference to FIG. FIG. 12 is a conceptual diagram showing the behavior of carriers when photoexcitation occurs in the drain side junction region. FIG. 13 is a conceptual diagram showing the behavior of carriers when photoexcitation occurs in the source-side junction region. In FIGS. 12 and 13, assuming that the above-described pixel electrode 9 a to which the TFT 30 is electrically connected has intermediate gray scale display, the source potential (that is, the potential of the source region) is 4.5 V, and the gate potential. (That is, the potential of the channel region) is 0 V, and the drain potential (that is, the potential of the drain region) is 9.5 V. The horizontal axis of FIG.12 and FIG.13 has shown each area | region in the semiconductor layer which comprises TEG. The vertical axis in FIGS. 12 and 13 represents the potential of electrons (Fermi level). Since electrons have a negative charge, the higher the potential in each region, the lower the potential of the electrons, and the lower the potential in each region, the higher the potential of the electrons.

  FIG. 12 shows the behavior of carriers when a light spot is irradiated to the drain side junction region formed between the channel region and the drain region, and photoexcitation occurs in the drain side junction region.

  In FIG. 12, it can be estimated that the light leakage current consists of two current components.

  That is, as the first current component, there is a current component due to movement of electrons generated by photoexcitation. More specifically, a current component (this current component) generated when electrons generated by photoexcitation in the drain side junction region (see “e” in the figure) move from the drain side junction region to the drain region having a lower potential. Is from the drain region to the source region).

  As the second current component, there is a current component due to movement of holes generated by photoexcitation (that is, holes, see “h” in the figure). More specifically, the bipolar effect generated by the movement of holes generated by photoexcitation in the drain side junction region from the drain side junction region to the channel region having a lower potential (that is, the electron potential is higher). This is the resulting current component. That is, the positive charge of the holes that have moved to the channel region reduces the potential of the channel region (that is, the so-called base potential) from the potential Lc1 to the potential Lc2, thereby increasing the number of electrons traveling from the source region to the drain region. (This current component flows from the drain region to the source region). Therefore, when photoexcitation occurs in the drain side junction region, the first and second current components are both in the direction of increasing the drain current (in other words, the collector current) (that is, the direction of flowing from the drain region to the source region). appear.

  FIG. 13 shows the behavior of carriers when a light spot is irradiated on the source side junction region formed between the channel region and the source region, and photoexcitation occurs in the source side junction region.

  In FIG. 13, unlike the case where photoexcitation occurs in the drain side junction region described above with reference to FIG. 12, the photoleakage current has a lower potential from the source side junction region (that is, the electron potential is more It can be assumed that the second current component due to the bipolar effect moving to the (high) channel region is dominant. That is, a first current component (this current component is expressed as a result of electrons generated by photoexcitation in the source side junction region (see “e” in the figure) moving from the source side junction region to the source region having a lower potential). , Which flows from the source region to the drain region) can be estimated to be less than the second current component caused by the bipolar effect (this current component flows from the drain region to the source region).

  In FIG. 13, since the base potential is pulled down from the potential Lc1 to the potential Lc3 due to the second current component (that is, the positive charge of the holes moved to the channel region) due to the bipolar effect, the source region moves from the source region to the drain region. The current component due to the effect of increasing electrons flows from the drain region to the source region. On the other hand, the first current component described above flows from the source region to the drain region. That is, the first current component and the second current component flow in opposite directions. Here, in FIG. 11 again, when the light spot is irradiated to the source-side junction region, the drain current (see data E1) shows a positive value. That is, in this case, the drain current flows from the drain region toward the source region. Therefore, it can be said that the first current component only suppresses the current component due to the bipolar effect, which is the dark current and the second current component, and is not large enough to direct the flow of the drain current from the source region to the drain region. .

  Further, since the potential difference between the channel region and the source region is smaller than the potential difference between the channel region and the drain region, the depletion region on the source region side (that is, the source side junction region) is depleted on the drain region side ( That is, it is narrower than the drain side junction region. For this reason, when the light spot is irradiated on the source-side junction region, the absolute amount of photoexcitation is small compared to the case where the light spot is irradiated on the drain-side junction region.

  As described above with reference to FIGS. 12 and 13, when photoexcitation occurs in the drain side junction region, both the first and second current components are generated in the direction of increasing the drain current. On the other hand, when photoexcitation occurs in the source side junction region, the first current component suppresses the second current component. Therefore, when the light spot is irradiated in the drain side junction region, the drain current becomes larger (that is, the light leakage current becomes larger) than when the light spot is irradiated in the source side junction region. .

  Next, when the pixel electrode side source / drain region is set to the drain potential and the light spot is irradiated into the pixel electrode side junction region, the data line side source / drain region is set to the drain potential and the data line side A mechanism in which the light leakage current becomes larger than that in the case where the light spot is irradiated in the junction region will be described with reference to FIGS. FIG. 14 is a conceptual diagram showing the behavior of carriers when photoexcitation occurs in the data line side junction region (in other words, the drain side junction region) when the data line side source / drain region is at the drain potential. is there. FIG. 15 is a conceptual diagram showing the behavior of carriers when photoexcitation occurs in the pixel electrode side junction region (in other words, the drain side junction region) when the pixel electrode side source / drain region is set to the drain potential.

  In the following, a case where charge is held in a pixel portion including a pixel switching TFT and photoexcitation occurs will be considered. The difference from the case of assuming the TEG as described above is that the pixel electrode side of the pixel switching TFT can be in a floating state. A storage capacitor such as a storage capacitor 70 may be connected to the pixel electrode side of the pixel switching TFT. If the capacitance value is sufficiently large, the state is close to a fixed electrode as in the case of using the TEG described above. However, if the capacitance is not sufficiently large, it becomes a floating state or a state close to this. Here, it is assumed that the capacitance value is not sufficiently large.

  14 and 15, the liquid crystal device employs AC driving in order to prevent so-called burn-in. Here, it is assumed that halftone display is assumed, and the pixel electrode holds a negative field charge of 4.5 V and a positive field charge of 9.5 V alternately with 7 V as a reference potential. To do. For this reason, the source and drain of the pixel switching TFT are not fixed and change between the pixel electrode side source / drain region and the data line side source / drain region. That is, as shown in FIG. 14, when a negative field charge is held in the pixel electrode (that is, the potential of the pixel electrode side source / drain region is lower than the potential of the data line side source / drain region), The pixel electrode side source / drain region is a source, whereas, as shown in FIG. 15, when a positive field charge is held in the pixel electrode (that is, the potential of the pixel electrode side source / drain region is the data line side source). When it becomes higher than the potential of the drain region), the pixel electrode side source / drain region becomes the drain.

  In FIG. 14, when a negative field charge is held in the pixel electrode, the pixel electrode side source / drain region becomes the source (or emitter), and the data line side source / drain region becomes the drain (or collector). When photoexcitation occurs in the data line side junction region, which is the drain side junction region, as described above, the first current component due to the movement of electrons generated by photoexcitation and the second current component due to the bipolar effect are generated. . Here, when the second current component due to the bipolar effect occurs (that is, the base potential is pulled down from the potential Lc1 to the potential Lc2, and the source / drain region from the pixel electrode side to the data line side to the source / drain to be the drain) When the electrons move to the region), electrons are extracted from the pixel electrode side source / drain region in a floating state, and the potential of the pixel electrode side source / drain region as an emitter decreases from the potential Ls1 to the potential Ls2 ( The potential rises). That is, when photoexcitation occurs in the data line side junction region which is the drain side junction region, the base potential is lowered and the potential of the pixel electrode side source / drain region as the emitter is also lowered. In other words, when photoexcitation occurs in the data line side junction region, which is the drain side junction region, the emitter potential also increases as the base potential increases. For this reason, the drain current (that is, the collector current) is suppressed.

  On the other hand, in FIG. 15, when a positive field charge is held in the pixel electrode, the data electrode side source / drain region becomes the source (or emitter), and the pixel electrode side source / drain region becomes the drain (or collector). Become. When photoexcitation occurs in the pixel electrode side junction region which is the drain side junction region, as described above, the first current component due to the movement of electrons generated by photoexcitation and the second current component due to the bipolar effect are generated. . Here, since the source / drain region on the data line side serving as the source is connected to the data line, unlike the pixel electrode, it is not in a floating state and the potential does not change. When the second current component due to the bipolar effect is generated (that is, the base potential is lowered from the potential Lc1 to the potential Lc2, and electrons are transferred from the source / drain region on the data line side as the source to the pixel electrode source / drain region as the drain. When the electrons move, electrons flow into the pixel electrode side source / drain region in a floating state, and the potential of the pixel electrode side source / drain region as a collector increases from the potential Ld1 to the potential Ld2 (the potential decreases). ). However, unlike the above-described decrease in the potential of the pixel electrode side source / drain region as the source, the increase in the potential of the pixel electrode side source / drain region as the collector has little function of suppressing the drain current. Since the drain current (ie, collector current) is almost determined by the magnitude of the base potential with respect to the emitter potential, the drain current is hardly suppressed even if the collector potential is lowered. In other words, in the saturation region of the bipolar transistor. It is in the state.

  As described above with reference to FIGS. 14 and 15, when a positive field charge is held in the pixel electrode (that is, when the pixel electrode side source / drain region becomes the drain), the bipolar effect is obtained. The resulting second current component is hardly suppressed, whereas when the negative electrode charge is held in the pixel electrode (that is, when the data-side source / drain region becomes the drain), it is caused by the bipolar effect. The second current component is suppressed due to an increase in potential of the pixel electrode side source / drain region which is in a floating state. That is, when the pixel electrode side source / drain region becomes the drain, the drain current increases due to the light leakage current, compared to when the data side source / drain region becomes the drain.

  Here, FIG. 16 shows the waveform of the pixel electrode potential when relatively strong light is irradiated to the entire pixel switching TFT.

  In FIG. 16, data E2 indicates that the variation Δ1 in the pixel electrode potential when the positive charge is held in the pixel electrode (when the pixel electrode potential is the potential V1) is the negative field charge held in the pixel electrode. This indicates that it is larger than the fluctuation Δ2 of the pixel electrode potential when the pixel electrode potential is set to the potential V2. That is, it is indicated that the positive field charge is less likely to be held than the negative field charge in the pixel electrode (that is, light leakage is likely to occur). This is because when the pixel electrode holds a positive field charge (that is, when the pixel electrode side source / drain region becomes the drain), the pixel electrode holds a negative field charge (that is, This is consistent with the mechanism described above, in which light leakage current is more likely to occur than when the data line side source / drain region becomes the drain.

  As described above in detail with reference to FIGS. 11 to 16, the drain current is likely to increase when photoexcitation occurs in the drain side junction region in the pixel switching TFT. Further, when the pixel electrode side source / drain region becomes the drain, the drain current tends to increase (in other words, when the data line side source / drain region becomes the drain, the current component due to the bipolar effect is suppressed. ing).

  Therefore, as in the liquid crystal devices according to the first to third embodiments described above, the light shielding property with respect to the pixel electrode side LDD region 1c which is the pixel electrode side junction region is set to the data line side LDD region 1b which is the data line side junction region. The light leakage current in the TFT 30 can be extremely effectively reduced while maintaining a high aperture ratio.

<Method of manufacturing electro-optical device>
Next, a manufacturing method for manufacturing the above-described liquid crystal device according to the first embodiment will be described with reference to FIGS.

  FIG. 17 to FIG. 21 are process diagrams showing each process of the manufacturing process of the liquid crystal device according to the first embodiment. 17 to 21 are shown corresponding to the cross-sectional view shown in FIG. Hereinafter, the process of forming the TFT 30 of the liquid crystal device according to the first embodiment will be mainly described.

  First, in the step shown in FIG. 17, the image display region 10a (see FIG. 1) on the TFT array substrate 10 includes at least one of high melting point metals such as Ti, Cr, W, Ta, and Mo. A scanning line 11 having a predetermined pattern is formed by laminating a single metal, an alloy, a metal silicide, a polysilicide, or a laminate thereof. At this time, the scanning line 11 is formed in a stripe shape so as to have a portion overlapping with a TFT 30 to be formed later as a predetermined pattern.

  Subsequently, an insulating film 12 p that is a precursor film of the base insulating film 12 is formed on the entire surface of the TFT array substrate 10. The insulating film 12p is formed by, for example, TEOS (tetraethylorthosilicate) gas, TEB (tetraethylboatate) gas, or TMOP (tetramethyloxyphosphate) gas by atmospheric pressure or low pressure CVD. Etc. are used to form a silicate glass film such as NSG, PSG or BSG, a nitride film, a silicon oxide film, or the like. Note that after the insulating film 12p is formed, the surface thereof may be flattened by performing a flattening process such as a CMP (Chemical Mechanical Polishing) process.

  Subsequently, a semiconductor film 1ap which is a precursor film of the semiconductor layer 1a is formed on the entire surface of the TFT array substrate 10. The semiconductor film 1ap is formed by solid-phase growth of a polysilicon film by forming an amorphous silicon film by, for example, low pressure CVD and performing heat treatment. The semiconductor film 1ap may be formed directly from a polysilicon film by, for example, a low pressure CVD method. Thereafter, a predetermined region in the semiconductor film 1ap is doped with impurity ions at a predetermined concentration, whereby the channel region 1a ′, the data line side LDD region 1b, the pixel electrode side LDD region 1c, and the data line side source / drain region 1d. The pixel electrode side source / drain region 1e is formed.

  Subsequently, an insulating film 2 p that is a precursor film of the gate insulating film 2 is formed on the entire surface of the TFT array substrate 10. The insulating film 2p is formed from a silicon oxide film or the like by, for example, normal pressure or low pressure CVD.

  Subsequently, an insulating film 31p that is a precursor film of the island-shaped insulating film 31 is formed on the entire surface of the TFT array substrate 10. The insulating film 31p is formed of a silicon nitride film or the like so as to have a thickness greater than that of the insulating film 2p, for example, by atmospheric pressure or low pressure CVD. Here, the insulating film 31p is preferably formed from an insulating film having a high etching selectivity with respect to the insulating film 2p. By forming the insulating film 31p from a silicon nitride film, the etching selectivity of the insulating film 31p with respect to the insulating film 2p made of a silicon oxide film or the like can be increased. Therefore, in the subsequent process, when the island-shaped insulating film 31 is formed by patterning the insulating film 31p by an etching process, the etching process prevents the gate insulating film 2 made of a silicon oxide film or the like from being damaged. Can do.

  Subsequently, a resist film 510 having a predetermined pattern corresponding to the planar pattern of the semiconductor layer 1a (see FIG. 4 or FIG. 5) is formed on the insulating film 31p.

  Next, in the process shown in FIG. 18, the insulating film 31p, the insulating film 2p, the semiconductor film 1ap, and the insulating film 12p are etched using the resist film 510 as a mask, so that the insulating film 31p, the insulating film 2p, and the semiconductor are processed. The film 1ap and the insulating film 2p are patterned at once. Thus, the insulating film 2p is patterned to form the base insulating film 2, the semiconductor film 1ap is patterned to form the semiconductor layer 1a, and the insulating film 2p is patterned to form the gate insulating film 2. In addition, the island-shaped insulating film 31 is formed by performing the etching process again on the insulating film 31p patterned by the etching process in a later step.

  Subsequently, the resist film 510 is removed.

  Next, in the step shown in FIG. 19, typically, an insulating film 61p, which is a precursor film of the sidewall 61, is formed on the entire surface of the TFT array substrate 10 so as to cover the semiconductor layer 1a. The insulating film 61p is formed from a silicon oxide film or the like by, for example, normal pressure or low pressure CVD.

  Subsequently, an anisotropic etching process is performed on the insulating film 61p from the upper side of the insulating film 61p, so that the base insulating film 12, the semiconductor layer 1a, the gate insulating film 2, and the insulating film 31p are stacked. A sidewall 61 is formed along the sidewall (see FIG. 20). Here, in the insulating film 61p, the thickness of the portion extending in the vertical direction in the drawing along the side wall of the stacked body in which the base insulating film 12, the semiconductor layer 1a, the gate insulating film 2, and the insulating film 31p are stacked is the insulating film The portion extending along the upper surface of 31p, the portion extending along the upper surface of the scanning line 11, and the portion extending along the upper surface of the TFT array substrate 10 are relatively thick in the vertical direction in the drawing. Therefore, even when the anisotropic etching process is uniformly performed on the insulating film 61p, a portion functioning as the sidewall 61 remains in the insulating film 61p.

  Next, in the step shown in FIG. 20, a resist film 511 is formed so as to cover the TFT array substrate 10 except for the portion of the semiconductor layer 1a where the channel region 1a 'is formed. In other words, the resist film 511 is formed on the entire surface of the TFT array substrate 10 so as to have a window portion 810 opened to correspond to the channel region 1a '. The resist film 511 is formed so that the window portion 810 does not overlap the data line side LDD region 1b and the pixel electrode side LDD region 1c in the semiconductor layer 1a. As shown in FIG. 20A, the resist film 511 may be formed so that the window portion 810 overlaps a part of the sidewall 61 formed on the sidewall of the channel region 1a '.

  Subsequently, the insulating film 31p is etched using the resist film 511 as a mask, and the portion of the insulating film 31p that faces the channel region 1a ′ is removed, whereby the island-shaped insulating film 31 (FIG. 21 and FIG. 21) is removed. (See FIG. 5). At this time, the portion of the sidewall 61 exposed from the window portion 810 is also etched, but the insulating film made of a silicon nitride film or the like on the sidewall 61 made of a silicon oxide film or the like. Since the etching selectivity with respect to 31p is high, the sidewall 61 remains almost or completely in practice.

  Subsequently, the resist film 511 is removed.

  Next, in the step shown in FIG. 21, the gate electrode 3a is formed by using a part of the data line side LDD region 1b, a channel region 1a ', a pixel electrode side LDD region 1c, and a part of the pixel electrode side source / drain region in the semiconductor layer 1a. And the sidewall 61 formed on the sidewalls of these regions. The gate electrode 3a is formed as a light-shielding conductive film having a two-layer structure of a layer made of conductive polysilicon in the lower layer and a layer containing aluminum in the upper layer by, for example, atmospheric pressure or reduced pressure CVD, sputtering, or the like. . At this time, a portion of the gate electrode 3a formed along the surface of the sidewall 61 is formed so as to contact the scanning line 11, and the gate electrode 3a and the scanning line 11 are electrically connected.

  In addition, when forming the gate electrode 3a, the data line 6a and the relay electrode 60 are also formed simultaneously. That is, a light-shielding conductive film having a two-layer structure of a layer made of conductive polysilicon as a lower layer and a layer containing aluminum as an upper layer is formed on the entire surface of the TFT array substrate 10 and then patterned. Thus, the gate electrode 3a, the data line 6a, and the relay electrode 60 are formed.

  Thereafter, an interlayer insulating film 41 is formed on the entire surface of the TFT array substrate 10, and subsequently, a capacitor electrode 71, a capacitor insulating film 75, and a pixel electrode 9a are sequentially formed. Further, an alignment film and a liquid crystal layer are formed on the pixel electrode 9a, and the counter substrate 20 is provided, whereby the liquid crystal device according to the first embodiment described above is manufactured.

  As described above, according to the method for manufacturing a liquid crystal device described above with reference to FIGS. 17 to 21, the liquid crystal device according to the first embodiment described above can be manufactured. In particular, the gate electrode 3a is formed so as to cover at least the pixel electrode side LDD region 1c and the side wall 61 formed on the side wall of the semiconductor layer 1a, so that the light shielding property to the pixel electrode side LDD region 1c is improved. In addition, the gate electrode 3a and the scanning line 11 can be electrically connected without using a contact hole. Furthermore, a part of the gate electrode 3a can be disposed closer to the side of the semiconductor layer 1a than when a contact hole is used, for example, and the non-opening defined by the gate electrode 3a. The area can be reduced.

  In the process shown in FIG. 20, when the insulating film 31p is etched, it is formed so as to cover the TFT array substrate 10 except for the portion where the insulating film 31p is formed, instead of the resist film 511 described above. By using the resist film as a mask to remove all of the insulating film 31p, the liquid crystal device according to the second embodiment described above can be manufactured.

  Next, a manufacturing method for manufacturing the liquid crystal device according to the third embodiment will be described with reference to FIGS.

  FIG. 22 to FIG. 24 are process diagrams showing each process of the manufacturing process of the liquid crystal device according to the third embodiment. 22 to 24 are shown corresponding to the cross-sectional view shown in FIG. In the following, the process of forming the TFT 30 of the liquid crystal device according to the third embodiment will be mainly described. Also, description of the steps similar to those of the liquid crystal device manufacturing method according to the first embodiment described above with reference to FIGS.

  First, in the step shown in FIG. 22, the scanning lines 11 are formed on the TFT array substrate 10 in the same manner as in the method for manufacturing the liquid crystal device according to the first embodiment described above.

  Subsequently, as in the liquid crystal device manufacturing method according to the first embodiment described above with reference to FIG. 17, an insulating film 12 p that is a precursor film of the base insulating film 12 is formed on the entire surface of the TFT array substrate 10. Subsequently, a semiconductor film 1ap which is a precursor film of the semiconductor layer 1a is formed on the entire surface of the TFT array substrate 10. At this time, by doping the semiconductor film 1ap with impurity ions at a predetermined concentration in a predetermined region, the channel region 1a ′, the data line side LDD region 1b, the pixel electrode side LDD region 1c, and the data line side A source / drain region 1d and a pixel electrode side source / drain region 1e are formed. Subsequently, an insulating film 2 p that is a precursor film of the gate insulating film 2 is formed on the entire surface of the TFT array substrate 10.

  Subsequently, a nitride film 110 a is formed on the entire surface of the TFT array substrate 10. The nitride film 110a is formed from a silicon nitride film or the like by, for example, normal pressure or low pressure CVD.

  Subsequently, an insulating film 33p, which is a precursor film of the island-like insulating film 33, is formed on the entire surface of the TFT array substrate 10. The insulating film 33p is formed from a silicon oxide film or the like so as to have a film thickness thicker than that of the insulating film 2p by atmospheric pressure or low pressure CVD. Here, the insulating film 33p is formed of a silicon oxide film or the like, and has a high etching selectivity with respect to the nitride film 110a formed of a silicon nitride film or the like disposed on the lower layer side. Therefore, when the island-shaped insulating film 33 is formed by patterning the insulating film 33p by an etching process in a later process, the nitride film 110a prevents the gate insulating film 2 from being damaged by the etching process. Can do.

  Subsequently, a resist film having a predetermined pattern corresponding to the planar pattern of the semiconductor layer 1a (see FIG. 4 or FIG. 5) is formed on the insulating film 33p formed on the entire surface of the TFT array substrate 10, and this resist film is formed. As a mask, the insulating film 33p, the nitride film 110a, the insulating film 2p, the semiconductor film 1ap, and the insulating film 12p are etched to form the insulating film 33p, the nitride film 110a, the insulating film 2p, the semiconductor film 1ap, and the insulating film 12p. Are collectively patterned. Thereby, the base insulating film 2, the semiconductor film 1a, and the gate insulating film 2 are formed. Note that the insulating film 33p patterned by the etching process here is subjected to an etching process again in a later step, whereby the island-shaped insulating film 33 is formed.

  Subsequently, a nitride film 110b is typically formed on the entire surface of the TFT array substrate 10 so as to cover the semiconductor layer 1a. Similar to the nitride film 110a, the nitride film 110b is formed of a silicon nitride film or the like by, for example, normal pressure or low pressure CVD.

  Subsequently, an insulating film 63p, which is a precursor film of the sidewall 63, is typically formed on the entire surface of the TFT array substrate 10 so as to cover the semiconductor layer 1a. The insulating film 63p is formed from a silicon oxide film or the like by, for example, normal pressure or low pressure CVD.

  Subsequently, anisotropic etching is performed on the insulating film 63p and the nitride film 110b from the upper side of the insulating film 63p, so that the base insulating film 12, the semiconductor layer 1a, the gate insulating film 2, the nitride film 110a, and the insulating film 33p. A side wall 63 is formed along the side wall of the laminate formed by laminating (see FIG. 23). At this time, the sidewall 63 is opposed to the side wall of the stacked body in which the base insulating film 12, the semiconductor layer 1a, the gate insulating film 2, the nitride film 110a, and the insulating film 33p are stacked via the nitride film 110b. become.

  Next, in a step shown in FIG. 23, a resist film 531 is formed so as to cover the TFT array substrate 10 except for a predetermined portion including a portion where the channel region 1a 'is formed in the semiconductor layer 1a. More specifically, the resist film 531 is formed on the entire surface of the TFT array substrate 10 so as to have a window portion 820 opened so as to correspond to the channel region 1a '. Further, the resist film 511 is formed so that the window portion 820 does not overlap the data line side LDD region 1b and the pixel electrode side LDD region 1c in the semiconductor layer 1a. In addition, as shown in FIG. 23A, the resist film 531 is formed so that the window portion 820 overlaps the sidewall 63 formed on the sidewall of the channel region 1a '.

  Subsequently, the insulating film 33p is etched using the resist film 531 as a mask, and the portion of the insulating film 33p that faces the channel region 1a ′ is removed, whereby the island-shaped insulating film 33 (see FIG. 24). ). At this time, the portion of the sidewall 63 exposed from the window portion 820 (in other words, the portion of the sidewall 63 formed on the side wall of the channel region 1a ′) is also subjected to the etching process. Thus, the portion of the sidewall 63 formed on the side wall of the channel region 1a ′ is also removed. Here, since the etching selectivity of the sidewall 63 made of a silicon oxide film or the like to the nitride film 110b made of a silicon nitride film or the like is high, the nitride film 110b has a function of preventing the scanning line 11 from being damaged by the etching process. Also have.

  Subsequently, the resist film 531 is removed.

  Next, in the step shown in FIG. 24, the gate electrode 3c is changed to a part of the data line side LDD region 1b, a channel region 1a ', a pixel electrode side LDD region 1c, and a part of the pixel electrode side source / drain region in the semiconductor layer 1a. In addition, the sidewalls 63 formed on the sidewalls of these regions are formed so as to cover them. At this time, the gate electrode 3c is formed so as to have a portion extending from the portion formed along the surface of the sidewall 63 so as to be in contact with the surface of the scanning line 11, and the gate electrode 3c and the scanning line 11 are formed. Electrically connected.

  Thereafter, the liquid crystal device according to the third embodiment described above is manufactured by forming other constituent elements in the same manner as the method for manufacturing the liquid crystal device according to the first embodiment described above.

  As described above, according to the method for manufacturing the liquid crystal device described above with reference to FIGS. 22 to 24, the liquid crystal device according to the third embodiment described above can be manufactured. In particular, since the nitride films 110a and 110b are formed, for example, an island-shaped insulating film is formed by performing an etching process on a portion of the insulating film 33p that overlaps the channel region 1a ′, which is performed after the sidewall 63 is formed. In the step of forming 33 (see FIG. 23), it is possible to prevent the etching process from being performed on the lower layer side (for example, the gate insulating film 2 and the semiconductor layer 1a) than the nitride film 110a.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  FIG. 25 is a plan view showing a configuration example of the projector. Hereinafter, a projector using the liquid crystal device as a light valve will be described.

  As shown in FIG. 25, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  In addition, since light corresponding to each primary color of R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 25, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic device Examples include a notebook, a calculator, a word processor, a workstation, a videophone, a POS terminal, and a device equipped with a touch panel. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal devices described in the above embodiments, the present invention includes a reflective liquid crystal device (LCOS), a plasma display (PDP), a field emission display (FED, SED), an organic EL display, and a digital micromirror device. (DMD), electrophoresis apparatus and the like are also applicable.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. The manufacturing method and the electronic apparatus provided with the electro-optical device are also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is H-H 'sectional drawing of FIG. 3 is an equivalent circuit diagram of a plurality of pixel units of the liquid crystal device according to the first embodiment. FIG. It is a top view of the pixel part of the liquid crystal device concerning a 1st embodiment. It is a top view which shows the structure paying attention to the structure of TFT for pixel switching. FIG. 5 is a cross-sectional view taken along the line A-A ′ of FIG. 4. FIG. 6 is a diagram showing a cross-sectional view taken along line B-B ′ of FIG. 5 and a cross-sectional view taken along line C-C ′ of FIG. It is sectional drawing with the same meaning as FIG. 6 in 2nd Embodiment. It is a figure of the same meaning as FIG. 7 in 2nd Embodiment. It is a figure of the same meaning as FIG. 7 in 3rd Embodiment. It is a graph which shows the relationship between the light irradiation position and drain current in TFT for a test. It is a conceptual diagram which shows the behavior of a carrier when photoexcitation generate | occur | produces in the drain side junction area | region. It is a conceptual diagram which shows the behavior of the carrier when optical excitation generate | occur | produces in the source side junction area | region. FIG. 6 is a conceptual diagram showing the behavior of carriers when photoexcitation occurs in a data line side junction region (in other words, drain side junction region) when the data line side source / drain region is set to a drain potential. FIG. 5 is a conceptual diagram showing the behavior of carriers when photoexcitation occurs in a pixel electrode side junction region (in other words, drain side junction region) when the pixel electrode side source / drain region is at a drain potential. The waveform of the pixel electrode potential when relatively strong light is irradiated to the entire pixel switching TFT is shown. It is process drawing (the 1) which shows each process of the manufacturing process of the liquid crystal device which concerns on 1st Embodiment. It is process drawing (the 2) which shows each process of the manufacturing process of the liquid crystal device which concerns on 1st Embodiment. It is process drawing (the 3) which shows each process of the manufacturing process of the liquid crystal device which concerns on 1st Embodiment. It is process drawing (the 4) which shows each process of the manufacturing process of the liquid crystal device which concerns on 1st Embodiment. It is process drawing (the 5) which shows each process of the manufacturing process of the liquid crystal device which concerns on 1st Embodiment. It is process drawing (the 1) which shows each process of the manufacturing process of the liquid crystal device which concerns on 3rd Embodiment. It is process drawing (the 2) which shows each process of the manufacturing process of the liquid crystal device which concerns on 3rd Embodiment. It is process drawing (the 3) which shows each process of the manufacturing process of the liquid crystal device which concerns on 3rd Embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 1a '... Channel region, 1b ... Data line side LDD region, 1c ... Pixel electrode side LDD region, 1d ... Data line side source / drain region, 1e ... Pixel electrode side source / drain region, 3a, 3b, 3c DESCRIPTION OF SYMBOLS ... Gate electrode, 6a ... Data line, 9a ... Pixel electrode, 10 ... TFT array substrate, 10a ... Image display area, 11 ... Scanning line, 12 ... Base insulating film, 30 ... TFT, 71 ... Capacitance electrode, 60 ... Relay electrode 61, 63 ... sidewalls, 75 ... capacitive insulating film

Claims (11)

A substrate,
Data lines provided on the substrate;
A pixel electrode electrically connected to the data line;
A channel region, a data line side source / drain region electrically connected to the data line, a pixel electrode side source / drain region electrically connected to the pixel electrode, and between the channel region and the data line side source / drain region. A semiconductor layer having a first junction region formed, and a second junction region formed between the channel region and the pixel electrode side source / drain region;
A gate electrode disposed to face the channel region with a gate insulating film interposed therebetween;
A sidewall made of an insulating film provided on a sidewall of a predetermined region including at least a part of the second bonding region in the semiconductor layer;
An electro-optical device comprising: a light shielding portion provided to cover the predetermined region and the sidewall.   The electro-optical device according to claim 1, further comprising a scanning line provided on the substrate and intersecting the data line and electrically connected to the gate electrode.   The electro-optical device according to claim 1, wherein the second bonding region is an LDD region. The scanning line is formed on the lower layer side of the semiconductor layer through a base insulating film so as to overlap at least partially with the predetermined region when viewed in plan on the substrate, and has a light-shielding conductive material. Comprising
The gate electrode is formed on the upper layer side through the gate insulating film from the semiconductor layer,
4. The electro-optical device according to claim 2, wherein the light-shielding portion is integrally formed from the same film as the gate electrode and is electrically connected to the scanning line. An upper layer side than the semiconductor layer is provided in an island shape so as not to overlap the channel region and at least overlap the predetermined region when viewed in plan on the substrate, and is thicker than the gate insulating film An island-shaped insulating film having
The electro-optical device according to claim 4, wherein a portion of the light shielding portion that covers the predetermined region is formed on the island-shaped insulating film.   6. The electro-optical device according to claim 5, wherein the island-shaped insulating film is formed to face the semiconductor layer via a nitride film.   The electro-optical device according to claim 6, wherein the island-like insulating film and the sidewall have a dielectric constant lower than that of the nitride film. On the substrate, a channel region, a data line side source / drain region, a pixel electrode side source / drain region, a first junction region formed between the channel region and the data line side source / drain region, and the channel region and the pixel Forming a semiconductor layer having a second junction region formed between the electrode-side source / drain regions;
Forming a gate insulating film so as to overlap the semiconductor layer when viewed in plan on the substrate;
Forming a sidewall made of an insulating film on a sidewall of a predetermined region including at least a part of the second bonding region in the semiconductor layer;
Forming a gate electrode so as to face the channel region through the gate insulating film;
Forming a light shielding portion so as to cover the predetermined region and the sidewall;
Forming a data line so as to be electrically connected to the data line side source / drain region;
And a step of forming a pixel electrode so as to be electrically connected to the pixel electrode side source / drain region. Before the step of forming the semiconductor layer, including a step of forming a scan line so as to intersect the data line,
The step of forming the semiconductor layer and the gate insulating film includes:
Forming a first insulating film as a precursor film of a base insulating film serving as a base of the semiconductor layer on the upper side of the scanning line;
Forming a semiconductor film as a precursor film of the semiconductor layer on the first insulating film;
Forming the channel region, the data line side source / drain region, the pixel electrode side source / drain region, the first junction region and the second junction region in the semiconductor film;
Forming a second insulating film as a precursor film of the gate insulating film on the semiconductor film;
Forming a third insulating film on the second insulating film as a precursor film of an island-shaped insulating film that does not overlap the channel region and at least the predetermined region;
Etching is performed on the first insulating film, the semiconductor film, the second insulating film, and the third insulating film using a mask having a pattern corresponding to the semiconductor layer, and the first insulating film is formed. Forming the base insulating film, the semiconductor layer, and the gate insulating film by patterning the film, the semiconductor film, the second insulating film, and the third insulating film at once.
The step of forming the sidewall includes
Forming a fourth insulating film as a precursor film of the sidewall on the patterned third insulating film;
Forming the sidewall by subjecting the fourth insulating film to anisotropic etching,
After the step of forming the sidewall, including the step of forming the island-like insulating film by performing an etching process on a portion of the patterned third insulating film that overlaps the channel region,
The step of forming the gate electrode and the light shielding portion includes:
By forming a light-shielding conductive film so as to cover the channel region, the predetermined region, and the sidewall and to be electrically connected to the scanning line, the gate electrode and the light-shielding portion are integrally formed. The method of manufacturing an electro-optical device according to claim 8, comprising a forming step. Before the step of forming the semiconductor layer, including a step of forming a scan line so as to intersect the data line,
The step of forming the semiconductor layer and the gate insulating film includes:
Forming a first insulating film as a precursor film of a base insulating film serving as a base of the semiconductor layer on the upper side of the scanning line;
Forming a semiconductor film as a precursor film of the semiconductor layer on the first insulating film;
Forming the channel region, the data line side source / drain region, the pixel electrode side source / drain region, the first junction region, and the second junction region in the semiconductor film;
Forming a second insulating film as a precursor film of the gate insulating film on the semiconductor film;
Forming a first nitride film on the second insulating film;
Forming a third insulating film on the first nitride film as a precursor film of an island-shaped insulating film that does not overlap the channel region and at least the predetermined region;
Etching is performed on the first insulating film, the semiconductor film, the second insulating film, the first nitride film, and the third insulating film using a mask having a pattern corresponding to the semiconductor layer. Patterning the first insulating film, the semiconductor film, the second insulating film, the first nitride film, and the third insulating film in a lump so that the base insulating film, the semiconductor layer, and the gate are patterned Forming an insulating film,
The step of forming the sidewall includes
Forming a second nitride film so as to cover the patterned third insulating film;
Forming a fourth insulating film as a precursor film of the sidewall on the second nitride film;
Forming the sidewalls by subjecting the second nitride film and the fourth insulating film to anisotropic etching,
After the step of forming the sidewall, including the step of forming the island-like insulating film by performing an etching process on a portion of the patterned third insulating film that overlaps the channel region,
The step of forming the gate electrode and the light shielding portion includes:
By forming a light-shielding conductive film so as to cover the channel region, the predetermined region, and the sidewall and to be electrically connected to the scanning line, the gate electrode and the light-shielding portion are integrally formed. The method of manufacturing an electro-optical device according to claim 8, comprising a forming step.   An electronic apparatus comprising the electro-optical device according to claim 1.