JP2009136025A - Semi-fixed circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semi-fixed circuit for actualizing circuits of different types as one circuit, even in the circuits having the same function such as scramblers. <P>SOLUTION: The semi-fixed circuit can performs simultaneous processing of a plurality of bits in a plurality of types of CRC (Cycle Redundancy Check) circuits. It includes a plurality of flip-flops, a first exclusive OR circuit for selectively computing exclusive OR in accordance with first input bit signals and output signals from the plurality of flip-flops and outputting output signals equivalent to first-time shift, and a second exclusive OR circuit for selectively computing exclusive OR in accordance with second input bit signals and the output signals equivalent to the first-time shift and outputting output signals equivalent to second-time shift. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a quasi-fixed circuit, and more particularly to a quasi-fixed circuit capable of a plurality of types of circuit operations.

  Conventionally, as data processing required in many communication standards such as mobile communication standard W-CDMA, wireless LAN standards IEEE802.11a and IEEE802.11b, spreaders (scramblers), convolutional encoders (convolutional encoders), A pseudo random code generator using an error detection CRC (Cyclic Redundancy Check) circuit and a linear feedback shift register is used. In addition, a fast Fourier transform (FFT) composed of a Viterbi decoder, a matched filter, and a butterfly operation that performs complex multiplication and addition is used.

  Patent Documents 1 and 2 below describe a pseudo random number generation circuit using a linear feedback shift register. Patent Document 3 below describes a variable CRC generation circuit.

JP-A 63-67628 JP 63-204919 A JP-A-4-292018

  The scrambler, the convolutional encoder, and the like are configured by separate fixed circuits because the processing contents are different. Further, even if the scrambler is the same, scramblers of different standards are constituted by separate fixed circuits. It is inefficient to use hardware resources if they are all configured by separate fixed circuits.

An object of the present invention is to provide a semi-fixed circuit capable of realizing circuits having different functions such as a scrambler and a convolutional encoder with a single circuit.
Another object of the present invention is to provide a quasi-fixed circuit capable of realizing different types of circuits with a single circuit even if the circuit has the same function, such as a scrambler.

According to one aspect of the present invention, a quasi-fixed circuit capable of simultaneous processing of a plurality of bits of a plurality of types of CRC (Cycle Redundancy Check) circuits, including a plurality of flip-flops, a first input bit signal, and a plurality of A first exclusive OR circuit for selectively calculating an exclusive OR based on the output signal of the flip-flop and outputting an output signal corresponding to the first shift, a second input bit signal, and a shift Provided is a semi-fixed circuit having a second exclusive OR circuit for selectively calculating an exclusive OR based on an output signal corresponding to the first time and outputting an output signal corresponding to the second shift. Is done.
According to another aspect of the present invention, there is provided a semi-fixed circuit capable of simultaneously processing a plurality of bits of a plurality of types of scramblers or descramblers, including a plurality of flip-flops, a first input bit signal, and a plurality of flip-flops. A first exclusive OR circuit for selectively calculating an exclusive OR based on the output signal of the group and outputting an output signal corresponding to the first shift, a second input bit signal, and a plurality of There is provided a semi-fixed circuit having a second exclusive OR circuit for selectively calculating an exclusive OR based on the output signal of the flip-flop and outputting an output signal corresponding to the second shift. .
According to yet another aspect of the present invention, a quasi-fixed circuit capable of Viterbi decoding encoded data that has been convolutionally encoded at a plurality of types of coding rates, wherein the encoded data that has been convolutionally encoded is Calculates multiple branch metrics for Viterbi decoding, selects branch metrics according to coding rate and outputs them, and calculates path metrics by selecting necessary branch metrics A quasi-fixed circuit having a pathtric operation circuit is provided.
According to still another aspect of the present invention, a quasi-fixed circuit capable of operating a matched filter and a butterfly operation circuit, for performing a shift register, a plurality of multipliers for performing multiplication, and performing addition And a connection circuit for controlling connection of the shift register, the plurality of multipliers, and the plurality of adders, and the operation of the matched filter and the butterfly operation circuit according to the connection of the connection circuit A quasi-fixed circuit is provided.

  Even with a circuit having the same function, such as a scrambler, a descrambler, or a Viterbi decoder, different types of circuits can be realized by one semi-fixed circuit. In addition, circuits having different functions such as a matched filter and a butterfly operation circuit can be realized by one semi-fixed circuit. Further, simultaneous processing of multiple bits such as multiple types of scramblers, descramblers, or CRC circuits can be realized by one semi-fixed circuit. Thereby, since hardware resources can be shared, the utilization efficiency of hardware resources can be improved. In addition, a plurality of circuits can be realized with one semi-fixed circuit.

FIG. 1A is a diagram showing a configuration example of a transmitter of the wireless LAN standard IEEE 802.11a, and FIG. 1B is a diagram showing a configuration example of a receiver of the wireless LAN standard IEEE 802.11a. 2A is a diagram illustrating a configuration example of a transmitter of the wireless LAN standard IEEE802.11b, and FIG. 2B is a diagram illustrating a configuration example of a receiver of the wireless LAN standard IEEE802.11b. It is a figure which shows the structural example of the scrambler of the wireless LAN specification IEEE802.11a. It is a figure which shows the structural example of the scrambler of the wireless LAN specification IEEE802.11b. 1 is a diagram illustrating a configuration example of a descrambler of a wireless LAN standard IEEE 802.11b. It is a figure which shows the structural example of the semi-fixed circuit by the 1st Embodiment of this invention. It is a figure which shows the structural example of the semi-fixed circuit by the 2nd Embodiment of this invention. It is a figure which shows the structural example of an input EOR circuit. It is a figure which shows the structural example of a middle stage EOR circuit. It is a figure which shows the structural example of a CRC circuit. It is a figure which shows the structural example of the semi-fixed circuit by the 3rd Embodiment of this invention. It is a figure which shows the structural example of a flip-flop circuit. FIG. 2 is a diagram illustrating a configuration example of an IEEE 802.11a coding rate 1/2 convolutional encoder. It is a figure which shows the structural example of the semi-fixed circuit by the 4th Embodiment of this invention. It is a figure which shows the structural example of an input EOR circuit. It is a figure which shows the structural example of the linear feedback shift register (LFSR) of W-CDMA specification. It is a figure which shows the structural example of the semi-fixed circuit by the 5th Embodiment of this invention. It is a figure which shows the structural example of an input EOR circuit. FIGS. 19A and 19B are diagrams illustrating a configuration example of a first type scrambler or descrambler. 20A and 20B are diagrams showing a configuration example of a second type scrambler or descrambler. FIGS. 21A and 21B are diagrams illustrating a configuration example of a third type of scrambler or descrambler. 22A and 22B are diagrams showing a configuration example of the semi-fixed circuit according to the sixth embodiment of the present invention. It is a figure which shows the structural example of the convolutional encoder of coding rate 1/2. It is a figure which shows the structural example of the semi-fixed circuit of the convolutional encoder which can process N bit simultaneously per shift. It is a figure which shows the structural example of the calculator of FIG. It is a figure which shows dividing | segmenting the linear feedback shift register (LFSR) of the W-CDMA specification of FIG. 16 into four calculators. It is a figure which shows the structural example of LFSR which can perform N bit simultaneous batch processing. FIGS. 28A and 28B are diagrams illustrating a configuration example of the first arithmetic unit in FIG. It is a figure which shows the structural example of the circuit containing 32 stages of flip-flops, and an input selector. 30A to 30C are diagrams showing a configuration example of the input selector. It is a figure which shows the internal structural example of a 1st EOR operator. It is a figure which shows the example of an internal structure of a 2nd EOR operator. It is a figure which shows the structural example of the semi-fixed circuit by the 8th Embodiment of this invention. It is a figure which shows the structural example of the 1st calculator of FIG. It is a figure which shows the structural example of the circuit containing 32 stages of flip-flops, and an input selector. FIGS. 36A to 36F are diagrams showing configuration examples of the input selector. It is a figure which shows the internal structural example of a 1st EOR operator. It is a figure which shows the example of an internal structure of a 2nd EOR operator. It is a figure which shows the structural example of the semi-fixed circuit by the 9th Embodiment of this invention. It is a figure which shows the structural example of a branch metric calculating part. It is a figure which shows the structural example of an ACS part. It is a figure which shows the structural example of a selector and ACS. 43A and 43B are diagrams showing a configuration example of the matched filter. It is a figure which shows the structural example of a butterfly calculator. It is a figure which shows the structural example of a fast Fourier transform (FFT) circuit. It is a figure which shows the structural example of the semi-fixed circuit which can selectively implement | achieve a matched filter and a butterfly calculation. It is a figure which shows the structural example of a butterfly calculator. It is a figure which shows the example of an internal structure of the multiplier of FIG. It is a figure which shows the example of whole structure of LSI containing the semi-fixed circuit by the 11th Embodiment of this invention.

(First embodiment)
FIG. 1A shows a configuration example of a transmitter of the wireless LAN standard IEEE802.11a. Input data is wirelessly transmitted as a transmission signal via a scrambler 101, a convolutional encoder 102, an interleave processing circuit 103, a modulation circuit 104, an inverse FFT circuit 105, a D / A conversion circuit 106, and an RF circuit 107 in order. . The scrambler 101 performs a scramble process in order to prevent power from being concentrated on a specific frequency when the same bits are input. The convolutional encoder 102 performs redundant encoding for error correction (Viterbi decoding). The interleave processing circuit 103 rearranges transmission bits in accordance with the rules in advance because Viterbi decoding is weak against burst (continuous) errors during transmission and strong against random errors. The modulation circuit 104 modulates based on input data. The inverse FFT circuit 105 performs inverse fast Fourier transform on the modulated data. The D / A conversion circuit 106 converts a signal from a digital format to an analog format. The RF circuit 107 converts the signal into a radio frequency signal.

  FIG. 1B shows a configuration example of a receiver of the wireless LAN standard IEEE802.11a. The signals received wirelessly are sequentially passed through the RF circuit 111, the A / D conversion circuit 112, the synchronization processing circuit 113, the FFT circuit 114, the demodulation circuit 115, the deinterleave processing circuit 116, the Viterbi decoder 117, and the descrambler 118. Output as data. The RF circuit 111 converts a radio frequency signal into a predetermined frequency signal. The A / D conversion circuit 112 converts a signal from an analog format to a digital format. The synchronization processing circuit 113 includes a matched filter and detects a start (synchronization) point as the head position of the frame. The FFT circuit 114 performs fast Fourier transform. The demodulating circuit 115 demodulates after taking timing synchronization with the modulation signal. The deinterleave processing circuit 116 returns the bit order before interleaving. The Viterbi decoder 117 decodes transmission bits from the convolutionally coded redundant bits. The descrambler 118 restores the scrambled data.

  FIG. 2A shows a configuration example of a transmitter of the wireless LAN standard IEEE802.11b. The input data is sequentially transmitted as a transmission signal wirelessly through the CRC bit addition processing circuit 201, the scrambler 202, the modulation circuit 203, the spreading circuit 204, and the transmission circuit 205 in order. The spreading code generation circuit 206 generates a spreading code and outputs it to the spreading circuit 204. The CRC bit addition processing circuit 201 adds a CRC bit for data error determination. The CRC bit is determined based on the data. Then, the transmitter regards the transmission data as a polynomial, and adds the remainder obtained by dividing the transmission data by a predetermined generator polynomial to the transmission data as a test code. The receiver divides the received data by the generator polynomial, and determines whether there is an error depending on whether it is divisible. The spreading circuit 204 spreads the modulation signal. The transmission circuit 205 includes a D / A conversion circuit and an RF circuit.

  FIG. 2B shows a configuration example of a receiver of the wireless LAN standard IEEE802.11b. The signals received wirelessly are output as data via the reception circuit 211, the despreading circuit 212, the demodulation circuit 213, the CRC processing circuit 214, and the descrambler 215 in this order. The spreading code generation circuit 216 generates a spreading code and outputs it to the despreading circuit 212. The reception circuit 211 includes an RF circuit and an A / D conversion circuit. The despreading circuit 212 multiplies the received signal by the same code as the spreading code, thereby despreading the received signal and restoring the signal before spreading. The CRC processing circuit 214 calculates a CRC bit and checks whether there is an error.

  FIG. 3 shows a configuration example of the scrambler 101 (FIG. 1A) of the wireless LAN standard IEEE802.11a. For example, seven flip-flops FF1 to FF7 are connected in series. An exclusive OR (hereinafter referred to as EOR) circuit 302 performs an EOR operation on the output signals of the flip-flops FF4 and FF7 and outputs the result. The flip-flop FF1 inputs the output signal of the EOR circuit 302. The EOR circuit 301 performs an EOR operation on the input signal INPUT and the output signal of the EOR circuit 302 and outputs it as an output signal OUTPUT. The descrambler 118 in FIG. 1B has the same configuration as the scrambler in FIG. This is because if the initial values are the same and are synchronized, the same code can be output as the output signal OUTPUT. There is no correlation between the internal state of the flip-flop and the input signal INPUT.

  FIG. 4 shows a configuration example of the scrambler 202 (FIG. 2A) of the wireless LAN standard IEEE802.11b. For example, seven flip-flops FF1 to FF7 are connected in series. The EOR circuit 402 performs EOR operation on the output signals of the flip-flops FF4 and FF7 and outputs the result. The EOR circuit 401 performs an EOR operation on the input signal INPUT and the output signal of the EOR circuit 402, and outputs it as an output signal OUTPUT and also outputs it to the flip-flop FF1.

  FIG. 5 shows a configuration example of the descrambler 215 (FIG. 2B) of the wireless LAN standard IEEE802.11b. For example, seven flip-flops FF1 to FF7 are connected in series. The flip-flop FF1 receives the input signal INPUT. The EOR circuit 502 performs EOR operation on the output signals of the flip-flops FF4 and FF7 and outputs the result. The EOR circuit 501 performs an EOR operation on the input signal INPUT and the output signal of the EOR circuit 502 and outputs the result as an output signal OUTPUT.

  In IEEE 802.11b, the configurations of the scrambler in FIG. 4 and the descrambler in FIG. 5 are different. The number of flip-flops is the same for both of them. The scrambler of FIG. 4 outputs a different output signal (sign) OUTPUT if the bit string of the input signal INPUT is different even if the initial values of the flip-flops are the same. There is a correlation between the input signal INPUT and the internal state of the flip-flop. In order to restore the input signal INPUT of the transmitter scrambler by the receiver scrambler, the internal state of the flip-flop of the transmitter scrambler is reproduced by the receiver (descrambler) and then the receiver (desk The EOR of the flip-flop output of the scrambler and the output signal OUTPUT of the transmitter (scrambler) (the descrambler input signal INPUT of FIG. 5) may be taken. This is achieved by the descrambler shown in FIG. In FIG. 5, the input signal INPUT is directly input to the flip-flop FF1, thereby reproducing the internal state of the flip-flop of the scrambler of FIG.

  FIG. 6 shows a configuration example of a semi-fixed circuit according to the first embodiment of the present invention. This semi-fixed circuit includes the scrambler (descrambler) of the wireless LAN standard IEEE802.11a in FIG. 3, the scrambler of the wireless LAN standard IEEE802.11b in FIG. 4, and the descrambler of the wireless LAN standard IEEE802.11b in FIG. Operation is possible.

  J flip-flops FF1 to FFJ are connected in series. A middle stage EOR circuit 602 is connected to a connection line between the flip-flops. As shown in FIG. 9, the middle stage EOR circuit 602 receives the output signal A1 of the flip-flop and the output signal (feedback signal) A3 of the preceding middle stage EOR circuit 602. The EOR circuit 901 performs EOR operation on the signals A1 and A3 and outputs the result as a signal A2. The selector 902 selectively selects the signal A 1, A 2, or A 3 according to the selection signal SELECT and outputs it to the subsequent middle stage EOR circuit 602. For example, in an EOR circuit 602 corresponding to the EOR circuit 302 in FIG. 3, the EOR circuit 402 in FIG. 4, and the EOR circuit 502 in FIG. 5, the selector 902 selects and outputs the signal A2. In the middle stage EOR circuit 602 connected to the final stage flip-flop FF7, the selector 902 selects and outputs the signal A1. In the other middle stage EOR circuit 602, the selector 902 selects and outputs the feedback signal A3.

  An output signal (feedback signal) FB of the middle stage EOR circuit 602 connected between the flip-flops FF1 and FF2 is input to the input EOR circuit 601. As shown in FIG. 8, the input EOR circuit 601 receives the feedback signal FB and the input signal INPUT. The EOR circuit 801 performs an EOR operation on the feedback signal FB and the input signal INPUT and outputs a signal A2. When the feedback signal FB is the signal A1 and the input signal INPUT is the signal A3, the selector 802 alternatively selects the signal A1, A2 or A3 according to the selection signal SELECT and outputs it to the flip-flop FF1. The signal A2 becomes the output signal OUTPUT. In the case of FIG. 3, the selector 802 selects the signal A1. In the case of FIG. 4, the selector 802 selects the signal A2. In the case of FIG. 5, the selector 802 selects the signal A3.

  In FIG. 6, an enable signal ENABLE is a signal for controlling whether or not to enable the flip-flops FF1 to FFJ. For example, only the flip-flops FF1 to FF7 are enabled. The initial value signal LOAD is a signal for setting initial values in the flip-flops FF1 to FFJ. As described above, by controlling the selection state of the input EOR circuit 601 and the middle stage EOR circuit 602 in accordance with the selection signal SELECT, the scrambler and descrambler shown in FIGS. Can be made.

  The fixed circuit scrambler has a hardware structure that depends on parameters such as the shift register length, the tap position input to the EOR circuit, and the number of taps input to the EOR circuit. There was a problem that hardware had to be prepared. According to the quasi-fixed circuit of the present embodiment, by providing the input EOR circuit 601 and the middle-stage EOR circuit 602, various scrambles can be achieved with one quasi-fixed circuit including the three scramblers or descramblers of FIGS. Bra and descrambler operations can be enabled.

(Second Embodiment)
FIG. 7 shows a configuration example of a semi-fixed circuit according to the second embodiment of the present invention. This semi-fixed circuit is obtained by adding a decoder 701 to the semi-fixed circuit of FIG. The decoder 701 outputs a 2L + 2 bit signal based on the L + 1 bit selection signal SELECT, and controls the selection state of the L middle stage EOR circuits 602 and one input EOR circuit 601.

  Originally, in order to control L middle stage EOR circuits 602 and one input EOR circuit 601, a 2L + 2 bit selection signal SELECT is required. Of all patterns, flip-flops and middle stage EOR circuits 602 are used. As a result of subtracting from the total number of patterns the combination patterns of the groups that are not used after being grouped into unused flip-flops and middle-stage EOR circuits 602, the result is (2 (L-1)) × 3 ways Using this pattern, the selection signal SELECT can be made L + 1 bits.

  As described above, the decoder 701 decodes the input signal SELECT with a small number of bits, outputs an output signal with a large number of bits, and selects the middle stage EOR circuit 602 and the input EOR circuit 601. By using the decoder 701, the amount of selection signals can be reduced.

(Third embodiment)
FIG. 10 shows a configuration example of a CRC circuit in the CRC bit addition processing circuit 201 (FIG. 2A) and the CRC processing circuit 214 (FIG. 2B). The EOR circuit 1001 calculates the EOR of the input signal IN and the feedback signal from the last flip-flop FF, and outputs it to the first flip-flop FF. For example, four flip-flops FF are connected in series via the EOR circuit 1002, respectively. Each EOR circuit 1002 calculates EOR of the output signal of the EOR circuit 1001 and the output signal of the preceding flip-flop FF, and outputs it to the subsequent flip-flop FF. The output signals of the flip-flops FF become output signals OUT0, OUT1, OUT2, and OUT3, respectively.

  For the sake of simplicity, the CRC circuit in FIG. 10 has been described with an example in which an EOR circuit is inserted between all flip-flops with 4 taps. However, in the actual CRC circuit configuration, the number of taps is 16, for example, IEEE802.11b. The EOR circuit 1002 is inserted between the flip-flops FF.

  FIG. 11 shows a configuration example of a semi-fixed circuit according to the third embodiment of the present invention. This semi-fixed circuit is a circuit obtained by adding the function of the CRC circuit of FIG. 10 to the semi-fixed circuit (FIG. 6) of the first embodiment. Since the semi-fixed circuit of this embodiment is basically the same as the semi-fixed circuit of the first embodiment, only differences from the first embodiment will be described. The number of taps I corresponding to the number of flip-flop circuits 1101 is basically 16.

  The plurality of flip-flop circuits 1101 has the configuration shown in FIG. 12, unlike FIG. The EOR circuit 1201 calculates EOR of the input data from the input EOR circuit 601 and the output signal A2 of the preceding flip-flop, and outputs a signal A1. The selector 1203 selects the signal A1 or A2 according to the selection signal FF_SELECT and outputs it to the flip-flop 1204. The flip-flop 1204 inputs and outputs the output signal of the selector 1203.

  In order to realize the CRC circuit of FIG. 10, the selector 1203 may select and output the signal A1. In order to realize the circuit of FIG. 6, the selector 1203 may select and output the signal A2.

  In the CRC circuit of FIG. 10, the output signals OUT0 to OUT3 may be output as they are, or the outputs may be inverted and output. Therefore, EOR circuits 1102 and 1103 are added in FIG. When the inversion signal INV_OUT is 1, it is an inverted output, and when it is 0, it is a non-inverted output. The EOR circuit 1103 calculates and outputs EOR of the output signal of the input EOR circuit 601 and the inverted signal INV_OUT. Each of the plurality of EOR circuits 1102 calculates and outputs the EOR of the output signal of each flip-flop 1101 and the inverted signal INV_OUT.

  The CRC circuit or the like of the fixed circuit has a hardware structure depending on parameters, and there is a problem that hardware must be prepared separately when these parameters change. According to this embodiment, a scrambler having an arbitrary configuration and a CRC circuit having an arbitrary configuration can be realized with one semi-fixed circuit.

(Fourth embodiment)
FIG. 13 shows an example of the configuration of the IEEE 802.11a coding rate 1/2 convolutional encoder 102 (FIG. 1A). For example, six flip-flops FF1 to FF6 are connected in series. The input signal INPUT is input to the first flip-flop FF1. The EOR circuit 1301 calculates the EOR of the input signal INPUT and the output signals of the flip-flops FF2, FF3, FF5, and FF6, and outputs an output signal OUTPUT1. The EOR circuit 1302 calculates the EOR of the input signal INPUT and the output signals of the flip-flops FF1, FF2, FF3, and FF6, and outputs an output signal OUTPUT2.

  FIG. 14 shows a configuration example of a semi-fixed circuit according to the fourth embodiment of the present invention. This semi-fixed circuit is a circuit obtained by adding the function of the convolutional encoder of FIG. 13 to the semi-fixed circuit (FIG. 11) of the third embodiment. Since the semi-fixed circuit of this embodiment is basically the same as the semi-fixed circuit of the third embodiment, only differences from the third embodiment will be described.

  In the third embodiment, the middle stage EOR circuit 602 is provided only in the lower stage of the flip-flop 1101. However, in the fourth embodiment, the middle stage EOR circuit 602 is provided in the upper stage as well as the lower stage of the flip-flop 1101. The middle EOR circuit 602 in the upper stage corresponds to the EOR circuit 1301 in FIG. The lower middle EOR circuit 602 corresponds to the EOR circuit 1302 of FIG.

  The input EOR circuit 1401 is provided in place of the input EOR circuit 601 in FIG. 11, and has the configuration in FIG. The input EOR circuit 1401 receives an input signal INPUT, a feedback signal FB1 from the upper middle EOR circuit 602, and a feedback signal FB2 from the lower middle EOR circuit 602. The feedback signal FB1 is input to the selector 1503 as the signal A1, the input signal INPUT is the signal A3, and the feedback signal FB2 is the signal A5.

  The EOR circuit 1501 calculates EOR of the feedback signal FB1 and the input signal INPUT and outputs a signal A2. The signal A2 is output as the output signal OUTPUT1. The EOR circuit 1502 calculates EOR of the feedback signal FB2 and the input signal INPUT, and outputs a signal A4. The signal A4 is output as the output signal OUTPUT2. The decoder 1402 in FIG. 14 decodes the selection signal SELECT and outputs the selection signal, similarly to the decoder 701 in FIG. The selector 1503 selects one of the signals A1 to A5 according to the output signal of the decoder 1402 and outputs it to the flip-flop FF1 at the first stage. In order to realize the convolutional decoder in FIG. 13, the decoder 1503 may select and output the signal A3.

  The fixed circuit convolutional encoder or the like has a hardware structure depending on parameters, and if these parameters change, there is a problem that hardware must be prepared separately. According to this embodiment, a scrambler having an arbitrary configuration, a CRC circuit having an arbitrary configuration, and a convolutional encoder having an arbitrary configuration can be realized with one semi-fixed circuit.

(Fifth embodiment)
FIG. 16 shows a configuration example of a linear feedback shift register (LFSR) of the W-CDMA standard. The linear feedback shift register is used in a spread code generation circuit in the W-CDMA standard. The position of the W-CDMA standard spread code generation circuit is the same as that of the spread code generation circuits 206 and 216 of IEEE802.11b in FIGS. The linear feedback shift register shifts the reproducible bit operation processing based on the value initially set in the flip-flop without taking in the input data.

  The linear feedback shift register (hereinafter referred to as LFSR) includes a first circuit 1611 and a second circuit 1612. First, the first circuit 1611 is described. A plurality of flip-flops FF are connected in series. The EOR circuit 1604 calculates the EOR of the signals of the last stage (left end) flip-flop FF and the other flip-flops FF, and feeds it back to the first stage (right end) flip-flop FF. The EOR circuit 1603 calculates and outputs EOR of the signals of the three flip-flops FF.

  Next, the second circuit 1612 will be described. A plurality of flip-flops FF are connected in series. The EOR circuit 1606 calculates the EOR of the signals of the four flip-flops FF, and feeds it back to the flip-flop FF at the first stage (right end). The EOR circuit 1605 calculates and outputs EOR of the signals of the three flip-flops FF.

  The EOR circuit 1601 calculates EOR of the output signal of the last stage flip-flop FF of the first circuit 1611 and the second circuit 1612, and outputs an output signal OUTPUT1. The EOR circuit 1602 calculates EOR of the output signals of the EOR circuits 1603 and 1605 and outputs an output signal OUTPUT2.

  FIG. 17 shows a configuration example of a semi-fixed circuit according to the fifth embodiment of the present invention. This semi-fixed circuit is a circuit obtained by adding the function of the LFSR of FIG. 16 to the semi-fixed circuit (FIG. 14) of the fourth embodiment. Only the difference between the semi-fixed circuit of the present embodiment and the fourth embodiment will be described.

  The semi-fixed circuit of this embodiment includes a first circuit 1711 and a second circuit 1712. The first circuit 1711 and the second circuit 1712 correspond to the first circuit 1611 and the second circuit 1612 in FIG. 16, respectively, and each correspond to the circuit in FIG.

  The input EOR circuit 1701 is provided instead of the input EOR circuit 1401 of FIG. 14, and has the configuration of FIG. Input signals 1725 and 1726 are signals obtained by selecting the output of the last flip-flop 1101 from the outputs of arbitrary flip-flops 1101 according to the number of stages of the LFSR configured this time. Input signals 1721 and 1722 are output signals of the middle EOR circuit 602 in the upper stage. The input signals INPUT1 and INPUT2 are not used in the LFSR of FIG. 16 and correspond to the input signal INPUT of the fourth embodiment. Input signals 1723 and 1724 are output signals of the lower middle EOR circuit 602.

  The EOR circuit 1801 calculates and outputs EOR of the signals 1721 and 1722 and the input signals INPUT1 and INPUT2. The EOR circuit 1802 calculates and outputs EOR of the signals 1723 and 1724 and the input signals INPUT1 and INPUT2.

  In FIG. 17, a decoder 1702 decodes the selection signal SELECT and outputs a selection signal, and controls the selection states of the input EOR circuit 1701 and the middle EOR circuit 602 of the first circuit 1711. The decoder 1703 decodes the selection signal SELECT and outputs a selection signal, and controls the selection states of the input EOR circuit 1701 and the middle stage EOR circuit 602 of the second circuit 1712.

  In FIG. 18, a selector 1804 selectively selects a signal from signals 1725 and 1726, signals 1721 and 1722, and an output signal of the EOR circuit 1801 in accordance with a selection signal, and outputs output signals 1732 and 1733. To do. The selector 1805 selectively selects a signal from signals 1725 and 1726, signals 1723 and 1724, and an output signal of the EOR circuit 1802 in accordance with the selection signal, and outputs output signals 1734 and 1735. The selector 1803 selectively selects a signal from the signals 1721 and 1722, the output signal of the EOR circuit 1801, the input signals INPUT1 and INPUT2, the output signal of the EOR circuit 1802, and the signals 1723 and 1724 in accordance with the selection signal. The output signal 1731 is output to the first flip-flop FF1.

  In FIG. 17, an EOR circuit 1704 calculates EOR of signals 1732 and 1733 and outputs an output signal OUTPUT1. The EOR circuit 1705 calculates EOR of the signals 1734 and 1735, and outputs an output signal OUTPUT2. The signal 1733 is output as the output signal OUTPUT3, and the signal 1735 is output as the output signal OUTPUT4.

  In order to realize the LFSR of FIG. 16, in the input EOR circuit 1701 of the first circuit 1711, the selector 1804 selects and outputs the input signal 1725, and the selector 1803 selects and outputs the input signal 1721. 1805 selects and outputs the input signal 1723. In the input EOR circuit 1701 of the second circuit 1712, the selector 1804 selects and outputs the input signal 1726, the selector 1803 selects and outputs the input signal 1722, and the selector 1805 selects the input signal 1724. Output.

  The semi-fixed circuit LFSR or the like has a hardware structure depending on parameters, and if these parameters change, there is a problem that hardware must be prepared separately. According to the present embodiment, an arbitrary configuration scrambler, an arbitrary configuration CRC circuit, an arbitrary configuration convolution encoder, and an arbitrary configuration LFSR can be realized by one semi-fixed circuit.

(Sixth embodiment)
FIG. 22A shows a configuration example of a semi-fixed circuit according to the sixth embodiment of the present invention. This quasi-fixed circuit can selectively realize a plurality of types of CRC circuits such as the CRC circuit of FIG. 10 and does not input while shifting one bit at a time as shown in FIG. Input simultaneously and look ahead for several shifts at a time.

  For example, input signals IN [0] to IN [5] are input in parallel by 6 bits. The output signals of the selectors 2201 to 2204 are input to the flip-flops FF1 to FF4, respectively. The output signals OUT0 to OUT3 of the flip-flops FF1 to FF4 have initial setting values corresponding to the 0th shift. Each of the plurality of E circuits 2211 has the configuration illustrated in FIG. 22B and inputs the signal A1 and the signal B1. The EOR circuit 2231 calculates EOR of the signals A1 and B1 and outputs a signal A2. The selector 2232 selects and outputs the signal A1 or A2.

  Data D00, D01, D02, and D03 are output signals corresponding to the first shift. Data D10, D11, D12, and D13 are output signals corresponding to the second shift. Data D20, D21, D22, and D23 are output signals corresponding to the third shift. Data D30, D31, D32, and D33 are output signals corresponding to the fourth shift. Data D40, D41, D42, and D43 are output signals corresponding to the fifth shift. Data D50, D51, D52, and D53 are output signals corresponding to the sixth shift.

  The selector 2201 selectively selects data from the data D00, D10, D20, D30, D40, and D50 and outputs the selected data to the flip-flop FF1. The selector 2202 selectively selects data from the data D01, D11, D21, D31, D41, and D51 and outputs the selected data to the flip-flop FF2. The selector 2203 selectively selects data from the data D02, D12, D22, D32, D42, and D52 and outputs the selected data to the flip-flop FF3. The selector 2204 selectively selects data from the data D03, D13, D23, D33, D43, and D53 and outputs the data to the flip-flop FF4.

  This semi-fixed circuit can select a 1-bit to 6-bit parallel input. For example, when 6-bit parallel input signals IN [0] to IN [5] are input, the selectors 2201 to 2204 select data D50, D51, D52, and D53. When inputting the 5-bit parallel input signals IN [0] to IN [4], the selectors 2201 to 2204 select the data D40, D41, D42, and D43.

  By providing the E circuit 2211, it is possible to realize a CRC circuit in which the EOR circuit 1002 of FIG. In the E circuit 2211, the signal A2 may be selected when the EOR circuit is inserted, and the signal A1 may be selected when the EOR circuit is not inserted.

  Here, the maximum number of look-ahead shifts that can be output at one time is set to 6. At this time, 6 bits are simultaneously input from IN [0] to IN [5]. Then, output signals OUT0 to OUT3 at the time of initial setting of the flip-flops FF1 to FF4 are obtained. At the same time, outputs Dtb with the number of shifts 1 to 6 are obtained. t represents (shift count-1), and b represents the digit position of the bit. At this time, each of the four selectors 2201 to 2204 selects the sixth input from the top. That is, they are D50, D51, D52, D53 in order from the left. If it does so, the output to the number of shifts 7-12 will be obtained by the subsequent 6-bit input. If 5 bits are input at a time, the circuit 2222 is not used, that is, the circuit 2222 is not present, and an operation of fetching 5 bits of input data at a time is performed. In order to do this, the selectors 2201 to 2204 select the fifth input data from the top and input the next 5-bit input signal.

  In this embodiment, in order to deal with the configuration in which the rightmost EOR circuit 1002 in FIG. 10 is not inserted, the signal A1 may be selected by setting all the E circuits 2211 in the circuit 2221 in FIG.

  The configuration of FIG. 22A is obtained from the relationship between the number of shifts t-1 and t obtained from FIG. 10, as shown in the following equation. Here, “x” means EOR.

  {OUT0 [t], OUT1 [t], OUT2 [t], OUT3 [t]} = {OUT3 [t-1] xIN [t-1], OUT3 [t-1] xIN [t-1] xOUT0 [ t-1], OUT3 [t-1] xIN [t-1] xOUT1 [t-1], UT3 [t-1] xIN [t-1] xOUT2 [t-1]}

  The CRC circuit of FIG. 10 is a serial process that outputs 1 bit when 1 bit is input. In this embodiment, instead of repeating 1-bit shift, a plurality of CRC operations can be performed at a time by providing a circuit that performs a plurality of shift processes in advance.

(Seventh embodiment)
FIG. 19A is a configuration example of a first type scrambler (including a descrambler; the same applies hereinafter). The EOR circuit 1901 calculates EOR of the input signal IN and the output signal of the EOR circuit 1902 and outputs an output signal OUT. For example, four flip-flops FF1 to FF4 are connected in series. The output signal of the EOR circuit 1901 is input to the flip-flop FF1. The EOR circuit 1904 calculates EOR of the output signals of the flip-flops FF3 and FF4 and outputs the result. The EOR circuit 1903 calculates EOR of the output signal of the EOR circuit 1904 and the output signal of the flip-flop FF2 and outputs the result. The EOR circuit 1902 calculates EOR of the output signal of the EOR circuit 1903 and the output signal of the flip-flop FF1 and outputs the result to the EOR circuit 1901.

  FIG. 19B shows a configuration example of a scrambler that can simultaneously input a plurality of input bits of the scrambler of FIG. 19A and perform look-ahead processing for several shifts at a time. For example, input signals IN [0] to IN [5] are input in parallel by 6 bits. The EOR circuit 1911 performs EOR operation and outputs the result. Output signals OUT [2] to OUT [5] are fed back to the flip-flops FF1 to FF4, respectively. The output signals OUT [0] to OUT [5] are output signals corresponding to the first to sixth shifts, respectively.

  FIG. 20A is a configuration example of the second type scrambler. The EOR circuit 2001 calculates EOR of the input signal IN and the output signal of the EOR circuit 2002, and outputs an output signal OUT. For example, four flip-flops FF1 to FF4 are connected in series. The output signal of the EOR circuit 2002 is input to the flip-flop FF1. The EOR circuit 2004 calculates EOR of the output signals of the flip-flops FF3 and FF4 and outputs the result. The EOR circuit 2003 calculates and outputs EOR of the output signal of the EOR circuit 2004 and the output signal of the flip-flop FF2. The EOR circuit 2002 calculates EOR of the output signal of the EOR circuit 2003 and the output signal of the flip-flop FF1, and outputs the result to the EOR circuit 2001 and the flip-flop FF1.

  FIG. 20B shows a configuration example of a scrambler that can simultaneously input a plurality of input bits of the scrambler of FIG. 20A and perform look-ahead processing for several shifts at a time. For example, input signals IN [0] to IN [5] are input in parallel by 6 bits. The EOR circuit 2011 performs EOR operation and outputs the result. The EOR circuit 2021 calculates EOR of the input signal IN [5] and the output signal OUT [5] and outputs the result to the flip-flop FF1. The EOR circuit 2022 calculates EOR of the input signal IN [4] and the output signal OUT [4] and outputs the result to the flip-flop FF2. The EOR circuit 2023 calculates EOR of the input signal IN [3] and the output signal OUT [3] and outputs the result to the flip-flop FF3. The EOR circuit 2024 calculates EOR of the input signal IN [2] and the output signal OUT [2] and outputs the result to the flip-flop FF4. The output signals OUT [0] to OUT [5] are output signals corresponding to the first to sixth shifts, respectively.

  FIG. 21A is a configuration example of a third type scrambler. The EOR circuit 2101 calculates EOR of the input signal IN and the output signal of the EOR circuit 2102 and outputs an output signal OUT. For example, four flip-flops FF1 to FF4 are connected in series. The input signal IN is input to the flip-flop FF1. The EOR circuit 2104 calculates EOR of the output signals of the flip-flops FF3 and FF4 and outputs the result. The EOR circuit 2103 calculates and outputs EOR of the output signal of the EOR circuit 2104 and the output signal of the flip-flop FF2. The EOR circuit 2102 calculates EOR of the output signal of the EOR circuit 2103 and the output signal of the flip-flop FF 1 and outputs the result to the EOR circuit 2101.

  FIG. 21B shows a configuration example of a scrambler that can simultaneously input a plurality of input bits of the scrambler of FIG. 21A and perform look-ahead processing for several shifts at a time. For example, input signals IN [0] to IN [5] are input in parallel by 6 bits. The EOR circuit 2111 performs EOR operation and outputs the result. Input signals IN [5] to IN [2] are input to the flip-flops FF1 to FF4, respectively. The output signals OUT [0] to OUT [5] are output signals corresponding to the first to sixth shifts, respectively.

  FIG. 23 shows a configuration example of a convolutional encoder with a coding rate of 1/2. For example, four flip-flops FF1 to FF4 are connected in series. The input signal IN is input to the first stage flip-flop FF1. The EOR circuit 2301 calculates EOR of the input signal INPUT and the output signals of the flip-flops FF1 to FF4, and outputs an output signal OUT1. The EOR circuit 2302 calculates EOR of the input signal INPUT and the output signals of the flip-flops FF1 to FF4, and outputs an output signal OUT2. The operation of this convolutional encoder is to shift in each bit of input data and output 2 bits.

  FIG. 24 shows a configuration example of a semi-fixed circuit of a convolutional encoder that can simultaneously process N bits per shift in the convolutional encoder of FIG. The first convolution calculator 2401 corresponds to the calculator 2311 of FIG. 23, receives an N-bit input signal, and outputs an N-bit output signal OUT1. The arithmetic unit 2311 includes flip-flops FF1 to FF4 and an EOR circuit 2301. The second convolution calculator 2402 corresponds to the calculator 2312 of FIG. 23, and receives an N-bit input signal and outputs an N-bit output signal OUT2. The arithmetic unit 2312 includes flip-flops FF1 to FF4 and an EOR circuit 2302. In addition, the semi-fixed circuit of FIG. 24 can selectively realize the scramblers of FIGS. 19B, 20B, and 21B.

  FIG. 25 shows an example of the same configuration of the arithmetic units 2401 and 2402 of FIG. 24, in which a plurality of bits are simultaneously input and a look-ahead process is performed for several shifts at a time. For example, input signals IN [0] to IN [5] are input in parallel by 6 bits. The output signals of the selectors 2501 to 2504 are input to the flip-flops FF1 to FF4, and signals D0 to D3 are output. The E circuit 2521 has the structure of FIG. The output signals OUT [0] to OUT [5] are output signals corresponding to the first to sixth shifts, respectively. The feedback circuit 2522 outputs signals W0 to W5.

  Selector 2501 selectively selects signals W0, W1, W2, W3, W4, and W5 and outputs them to flip-flop FF1. The selector 2502 selectively selects the signals D0, W0, W1, W2, W3, W4 and outputs them to the flip-flop FF2. The selector 2503 selectively selects the signals D1, D0, W0, W1, W2, and W3 and outputs them to the flip-flop FF3. The selector 2504 selectively selects the signals D2, D1, D0, W0, W1, W2 and outputs them to the flip-flop FF4. Note that the feedback circuit 2522 is not used when the convolutional encoder shown in FIG. 23 is realized, but is used when the scramblers shown in FIGS. 19B, 20B, and 21B are realized.

  In FIG. 23, the value held after the data stored in the flip-flop at the position at a certain time is shifted once is simply the value currently held and output by the previous flip-flop. Further, when shifting is performed more than the number of flip-flops, the data shifted in at the oldest time in the last stage of the flip-flop disappears and replaced with newly input data. Therefore, since the data result that the flip-flop should hold at each time is obtained, the EOR operation, that is, the convolutional encoding is performed according to the arrangement of the EOR circuit at the tap position where the data exists.

  In the case of the convolutional encoder of FIG. 23, the five selectors 2511 to 2515 are set to select the input signals IN [0] to IN [4], respectively. Looking at the relationship between each shift timing and the shift-in and shift-out bits at that timing, when the convolutional coding rate is 1 / M at the first shift, M convolution operators 2401 and 2402 in FIG. N bits of convolutional encoding corresponding to the input signal IN can be simultaneously output by one shift-in. Note that the N = 6 bit input signal IN is composed of IN [0] to IN [5], and is simultaneously encoded and output by the convolutional encoder.

  The presence or absence of the E circuit 2521 is determined by the configuration of the convolution operation to be realized. If an EOR circuit is provided between all flip-flops of a convolutional encoder to be realized, all the E circuits 2521 perform an EOR operation.

  Here, N = 6. When 6 bits are output simultaneously, the four selectors 2501 to 2504 select the sixth input from the top. That is, W5, W4, W3, and W2 are selected in order from the left. Input is performed by setting 6 bits to IN [0] to IN [5] as one set. By setting the selectors 2501 to 2504, simultaneous output of 6 bits or less is possible. Outputs corresponding to inputs IN [0] to IN [5] are OUT [0] to OUT [5], respectively.

  In order to realize the scrambler of FIG. 19B, the selectors 2511 to 2515 select and output the middle signal. In order to realize the scrambler of FIG. 20B, the selectors 2511 to 2515 select and output the right signal. In order to realize the scrambler of FIG. 21B, the selectors 2511 to 2515 select and output the left signal.

  Conventional scramblers and convolutional encoders are serial processes that output 1 bit when 1 bit is input. According to the quasi-fixed circuit of this embodiment, a plurality of scramble processes and a convolutional encoder process can be performed at a time by providing a circuit for performing a shift process for a plurality of times in advance, instead of repeating the 1-bit shift. In addition, the semi-fixed circuit of the present embodiment can constitute a scrambler having an arbitrary configuration that simultaneously processes a plurality of bit inputs and a convolutional encoder having an arbitrary configuration.

(Eighth embodiment)
FIG. 26 is a diagram showing that the W-CDMA standard linear feedback shift register (LFSR) of FIG. 16 is divided into four arithmetic units 2701 to 2704. The first circuit 1611 is divided into computing units 2701 and 2702. The arithmetic unit 2701 includes a plurality of flip-flops FF and an EOR circuit 1603. The arithmetic unit 2702 includes a plurality of flip-flops FF and an EOR circuit 1604. The second circuit 1612 is divided into computing units 2703 and 2704. The arithmetic unit 2703 includes a plurality of flip-flops FF and an EOR circuit 1606. The arithmetic unit 2704 includes a plurality of flip-flops FF and an EOR circuit 1605. The number of flip-flops is 25, for example. After initial setting of the internal state of the flip-flop, a bit series uniquely corresponding to the initial value setting is serially output.

  FIG. 27 is a configuration example of an LFSR that can simultaneously process N bits of the LFSR of FIG. The first circuit 1611 includes a first calculator 2701 and a second calculator 2702. The second circuit 1612 includes a third computing unit 2703 and a fourth computing unit 2704. The first arithmetic unit 2701 and the third arithmetic unit 2703 perform an EOR operation on the internal state of the flip-flop. The second computing unit 2702 and the fourth computing unit 2704 form a feedback loop to update the internal state of the flip-flop. The first to fourth arithmetic units 2701 to 2704 can input and output signals with each other. The first calculator 2701 outputs an N-bit output signal OUTPUT1. The second computing unit 2702 outputs an N-bit output signal OUTPUT2. The first to fourth arithmetic units 2701 to 2704 have the same configuration.

  FIG. 28A shows a configuration example of the first computing unit 2701 in FIG. The circuit 2800 includes a 32-stage flip-flop and its input selector (see FIG. 29), and receives a signal 2850. The signal 2850 includes the signal 2849 and is an 8 × 4 bit signal of the updated value of the flip-flops of the first to fourth arithmetic units. A signal 2849 is an update value signal of the flip-flop of the first arithmetic unit 2701 output from the internal state selector 2828.

  FIG. 29 illustrates a configuration example of the circuit 2800. The signal 2920 is an input signal to the selector relating to the flip-flop FF0, and includes a signal 2849 from the first arithmetic unit, a signal 2912 from the second arithmetic unit, a signal 2913 from the third arithmetic unit, and a fourth The signal 2914 from the arithmetic unit is included. For example, the signal 2849 from the first arithmetic unit is an 8-bit signal indicating the updated value of the flip-flop. The circuit 2901 includes a selector 2907 and selects data for input to the flip-flop FF0 of the first arithmetic unit. A selector 2907 is an update value selector for the flip-flop FF0, and performs selection based on the number of simultaneous parallel processing bits.

  Similar to the circuit 2901 for the first arithmetic unit, the circuit 2902 is a circuit for selecting the input data of the flip-flop FF0 of the second arithmetic unit, and the circuit 2903 is the flip-flop of the third arithmetic unit. This is a circuit for selecting the input data of FF0, and the circuit 2904 is a circuit for selecting the input data of the flip-flop FF0 of the fourth arithmetic unit. Signals 2912 to 2914 are input to the circuits 2902 to 2904, respectively. The selector 2931 alternatively selects the output signals of the circuits 2901 to 2904 and outputs them to the flip-flop FF0. The flip-flop FF0 holds and outputs the signal.

  Similar to the signal 2920, the signal 2921 is an input signal to the selector relating to the flip-flop FF1, and the signal 2922 is an input signal to the selector relating to the flip-flop FF31. Similarly to the circuit 2901, the circuit 2905 is a circuit for selecting the input data of the flip-flop FF1 of the first arithmetic unit, and the circuit 2906 is the input data of the flip-flop FF31 of the first arithmetic unit. This is a circuit for selecting. Input data is alternatively selected and input to the flip-flops FF1 to FF31.

  In the case of 8-bit batch processing, the circuit 2901 selects the FF update value [7] because the update value selector 2907 for the flip-flop FF0 needs to set the eighth bit data in the flip-flop FF0. For 7 bits at a time, the FF update value [6] above is selected, and the FF update value at the top is sequentially selected according to the number of bits to be collectively processed. Note that the initial value of the flip-flop needs to be set separately in the flip-flops FF0 to FF31 before the operation.

  FIG. 30A shows the input selector 2907 for the flip-flop FF1 in the circuit 2905. This selector selects from the output value of the flip-flop FF0 and the 7-bit FF update value [0] to FF update value [6].

  FIG. 30B shows an input selector 2907 for the flip-flop FF2. This selector selects from the output values of the flip-flops FF1 and FF0 and the 6-bit FF update value [0] to FF update value [5].

  FIG. 30C shows the input selector 2907 for the flip-flop FFn. This selector selects from the output values of the flip-flops FF (n−8) to FF (n−1).

  In FIG. 28A, the first EOR operator 2811 includes 32-stage selection EOR circuits 2831a to 2831d and the like as shown in FIG. The selection EOR circuits 2831a to 2831d include an EOR circuit 2891 and a selector 2892 as shown in FIG. The EOR circuit 2891 calculates EOR of the input signals A1 and B1 and outputs a signal A2. The selector 2892 selects and outputs the signal A1 or the signal A2.

  In FIG. 31, the selection EOR circuit 2831a receives the output signal 3100 of the flip-flop FF0 and outputs it to the selection EOR circuit 2831b in the next stage. The signal 3100 is output to the internal state selector 2821 (FIG. 28A) as an intermediate result [0].

  The selection EOR circuit 2831b receives the output signal 3101 of the flip-flop FF1 and the output signal of the selection EOR circuit 2831a, and outputs them to the selection EOR circuit 2831c in the next stage. The signal 3101 is output to the internal state selector 2821 (FIG. 28A) as an intermediate result [1].

  The selection EOR circuit 2831c receives the output signal 3102 of the flip-flop FF2 and the output signal of the selection EOR circuit 2831b, and outputs them to the selection EOR circuit in the next stage. The signal 3102 is output to the internal state selector 2821 (FIG. 28A) as an intermediate result [2].

  The selection EOR circuit 2831d receives the output signal 3103 of the flip-flop FF31 and the output signal of the previous selection EOR circuit, and outputs the signal 3104 as a temporary output [0]. The signal 3104 is output to the internal state selector 2821 (FIG. 28A) as an intermediate result [31].

  In the first EOR operator 2811 (FIG. 28A), the signal 2860 of the temporary output [0] is valid. The signal 2841 of the intermediate results [0] to [31] is not valid. Instead, the signal 2841 of the intermediate results [0] to [31] of the second computing unit 2702 in FIG. 27 is input to the second EOR computing unit 2812 in the next stage.

  In FIG. 28A, the signal 2860 of the temporary output [0] of the first EOR operator 2811 is output as the output signal OUT [0] via the three selection EOR circuits 2831. The selection EOR circuit 2831 receives a signal 2870 of a temporary output [0] of another arithmetic unit.

  The first EOR operator 2811 outputs a 32-bit intermediate result output signal 2841 to the internal state selector 2821. The internal state selector 2821 selects from the 32-bit intermediate result output signals 2841 and 2851 and outputs the selected signal to the second EOR operator 2812. The intermediate result output signal 2851 is an intermediate result output signal of the EOR arithmetic unit from the arithmetic unit set to have a feedback loop.

  The second EOR operator 2812 has the configuration shown in FIG. The selection EOR circuit 2831a inputs the signal 3100 of the intermediate result [0] of the previous stage and outputs it to the selection EOR circuit 2831b of the next stage. The signal 3100 is output as an intermediate result [0].

  The selection EOR circuit 2831b inputs the signal 3101 of the intermediate result [1] of the previous stage and the output signal of the selection EOR circuit 2831a, and outputs them to the selection EOR circuit of the next stage. The signal 3101 is output as an intermediate result [1].

  The selection EOR circuit 2831e receives the signal 3105 of the intermediate result [30] of the previous stage and the output signal of the selection EOR circuit of the previous stage, and outputs them to the selection EOR circuit 2831d of the next stage.

  The selection EOR circuit 2831d receives the signal 3104 of the intermediate result [31] of the previous stage and the output signal of the selection EOR circuit 2831e of the previous stage, and outputs the signal 3201 as the temporary output [1]. The signal 3201 is output as the intermediate result [30], and the signal 3104 is output as the intermediate result [31]. The signal 3201 indicates the location of the intermediate result [31] if the number n of the nth EOR operator is 0, the location of the intermediate result [30] if it is 1, and the location of the intermediate result [24] if it is 7. Enter only one.

  In FIG. 28A, the signal 2861 of the temporary output [1] of the second EOR operator 2812 is output as the output signal OUT [1] through the three selection EOR circuits 2831. The selection EOR circuit 2831 receives the signal 2871 of the temporary output [1] of another arithmetic unit. The second EOR operator 2812 outputs a 32-bit intermediate result signal 2842.

  Similarly, the internal state selector 2827 selects one of the intermediate result output signals 2847 and 2851 and outputs it to the eighth EOR operator 2818. The eighth EOR operator 2818 outputs a temporary output [7] signal 2867 and an intermediate result output signal 2848. The temporary output signal 2867 is output as the output signal OUT [7] via the three selection EOR circuits 2831. The selection EOR circuit 2831 also receives a signal 2877 of a temporary output [7] of another arithmetic unit.

  The internal state selector 2828 selects from the intermediate result output signals 2848 and 2851 and outputs a signal 2849 of the FF update value.

  In the present embodiment, the number of flip-flops is 32 and N = 8 bits. The output signal OUT [n] is an nth shift output of the arithmetic unit. The first to fourth computing units can select each other's internal state signals. In practice, it is only necessary to be able to exchange between the first and second arithmetic units and the third and fourth arithmetic units.

  Finally, EOR of the outputs of the second and fourth arithmetic units is set as an output signal OUTPUT1. For this reason, the EOR is taken inside the second arithmetic unit to obtain an output signal OUTPUT1. Similarly, EOR of the outputs of the first and third arithmetic units is set as an output signal OUTPUT2. For this reason, the EOR is taken inside the first arithmetic unit to obtain an output signal OUTPUT2.

  FIG. 33 shows a configuration example of the semi-fixed circuit according to the present embodiment. This semi-fixed circuit selectively realizes the CRC circuit of FIG. 22, the convolutional encoder of FIG. 25, the scramblers of FIGS. 19B, 20B, and 21B, and the LFSR of FIG. Can do.

  The first computing unit 3301 receives an N-bit input signal IN and outputs an N-bit output signal OUT1. The second computing unit 3302 receives an N-bit input signal IN and outputs an N-bit output signal OUT2. The third arithmetic unit 3303 receives an N-bit input signal IN and outputs an N-bit output signal OUT3. The fourth arithmetic unit 3304 receives an N-bit input signal IN and outputs an N-bit output signal OUT4. The first to fourth arithmetic units 3301 to 3304 can input and output signals with each other. The first to fourth arithmetic units 3301 to 3304 have the same configuration.

  FIG. 34 shows a configuration example of the first computing unit 3301 of FIG. The circuit in FIG. 34 is basically the same as the circuit in FIG. 28A, and therefore, differences from the circuit in FIG. 28A will be described. Although not shown in FIG. 34, the circuit in FIG. 34 is also provided with the signal 2851 and the internal state selectors 2821 to 2828 in FIG. The circuit 3410 corresponds to the circuit 2800 in FIG. 28A, and the EOR calculators 3411 to 418 correspond to the EOR calculators 2811 to 2818 in FIG.

  The circuit 3410 receives the signals 3450 and 3452 and outputs a signal 3481. The signal 3450 is an 8 × 4 bit signal indicating the FF update value from the first to fourth arithmetic units. A signal 3452 is an intermediate result output signal (32 × 8 × 4 bits) of the EOR calculator from the first to fourth calculators. A signal 3481 is an output signal (32 bits) of each flip-flop, inverted by the output inverting circuit 3482, and output as a 32-bit output signal OUT2.

  An 8-bit input signal IN [0] to IN [7] is input. The first EOR operator 3411 receives the signal 3481 and the input signal IN [0], and outputs the signal 3460 of the temporary output 1 [0] and the intermediate result output signal (32 bits) 3441. The signal 3460 outputs the output signal OUT1 [0] through the three selection EOR circuits 2831. The selection EOR circuit 2831 also receives a signal 3470 of the temporary output 1 [0] of another arithmetic unit.

  The second EOR operator 3412 receives the signal 3441 and the input signal IN [1], and outputs a signal 3461 of the temporary output 1 [1] and an intermediate result output signal (32 bits) 3442. The signal 3461 outputs the output signal OUT1 [1] through the three selection EOR circuits 2831. The selection EOR circuit 2831 also receives the signal 3471 of the temporary output 1 [1] of another arithmetic unit.

  The eighth EOR operator 3418 receives the signal 3447 and the input signal IN [7], and outputs a signal 3467 of the temporary output 1 [7] and an intermediate result output signal (32 bits) 3448. The signal 3467 outputs the output signal OUT1 [7] through the three selection EOR circuits 2831. The selection EOR circuit 2831 also receives the signal 3477 of the temporary output 1 [7] of another arithmetic unit.

  The intermediate result output signals 3441 to 3448 are fed back to the circuit 3410 as a signal 3452. The feedback input value selector 3480 receives the 8-bit temporary output signals 3460 to 3467 and the 8-bit input signals IN [0] to IN [7], and outputs a signal 3383 indicating an 8-bit FF update value. The signal 3383 corresponds to W0 to W5 in FIG. 25 and is fed back to the circuit 3410 as a signal 3450.

  FIG. 35 shows a configuration example of the circuit 3410 of FIG. The circuits 3501 to 3506 correspond to the circuits 2901 to 2906 in FIG. 29, the selector 3508 corresponds to the selector 2907 in FIG. 29, and the selector 3531 corresponds to the selector 2931 in FIG.

  A signal 3520 is an input signal to the selector regarding the flip-flop FF0, and includes signals 3511 to 514 of the first to fourth arithmetic units. The first computing unit signal 3511 includes signals 3510 and 3483. The signal 3510 is a signal of the intermediate result [0] of the first to eighth EOR calculators and corresponds to the signal 3452 in FIG. The signal 3383 is a signal indicating the FF update value [0] to the FF update value [7], and corresponds to the signal 3450 in FIG.

  A selector 3507 is an input selector for CRC calculation, and is selected from the signal 3510 and output. A selector 3508 is an arithmetic input selector other than the CRC, and is selected from the signal 3483 and output. The selector 3509 selects and outputs the output signal of the selector 3507 during CRC processing, and selects and outputs the output signal of the selector 3508 during processing other than CRC processing.

  A circuit 3502 is a circuit for input data of the flip-flop FF0 of the second arithmetic unit, and receives a signal 3512 of the second arithmetic unit. A circuit 3503 is a circuit for input data of the flip-flop FF0 of the third arithmetic unit, and receives a signal 3513 of the third arithmetic unit. The circuit 3504 is a circuit for input data of the flip-flop FF0 of the fourth arithmetic unit, and receives the signal 3514 of the fourth arithmetic unit. The selector 3531 selects the output signals of the circuits 3501 to 3504 and outputs them to the flip-flop FF0. The function of the selector 3531 enables LFSR operation.

  A signal 3521 is an input signal to the selector related to the flip-flop FF1, and includes a signal 3511 of the first arithmetic unit. A circuit 3505 is a circuit for selecting data for input to the flip-flop FF1 of the first arithmetic unit, and receives a signal 3511.

  The signal 3522 is an input signal to the selector regarding the flip-flop FF31, and includes the signal 3511 of the first arithmetic unit. A circuit 3506 is a circuit for selecting data for input to the flip-flop FF31 of the first arithmetic unit, and receives a signal 3511.

  The flip-flops FF0 to FF31 hold and output the output signal of the selector 3531.

  FIG. 36A shows a configuration example of the CRC calculation input selector 3507 for the flip-flop FF1 in the circuit 3505 of FIG. The selector 3507 selects and outputs the intermediate result [1] of the first to eighth EOR calculators.

  FIG. 36B shows a configuration example of the CRC calculation input selector 3507 for the flip-flop FF2 of FIG. The selector 3507 selects and outputs the intermediate result [2] of the first to eighth EOR calculators.

  FIG. 36C shows a configuration example of the CRC calculation input selector 3507 for the flip-flop FFn of FIG. The selector 3507 selects and outputs the intermediate result [n] of the first to eighth EOR operators.

  FIG. 36D illustrates a configuration example of the calculation input selector 3508 other than the CRC for the flip-flop FF1 in the circuit 3505 in FIG. The selector 3508 selects and outputs from the output value of the flip-flop FF0, FF update value [0] to FF update value [6].

  FIG. 36E shows a configuration example of an arithmetic input selector 3508 other than the CRC for the flip-flop FF2 in FIG. The selector 3508 selects and outputs from the output values of the flip-flops FF0 and FF1, FF update value [0] to FF update value [5].

  FIG. 36F shows a configuration example of an arithmetic input selector 3508 other than the CRC for the flip-flop FFn in FIG. The selector 3508 selects and outputs from the output values of the flip-flops FF (n-8) to FF (n-1).

  In FIG. 36F, when “#” in the parentheses of “FF (#) output” is negative, “FF (#) output” is replaced with the following signal.

If "-1", FF update value [0]
If it is "-2", FF update value [1]
If "-3", FF update value [2]
If "-4", FF update value [3]
If "-5", FF update value [4]
If "-6", FF update value [5]
If "-7", FF update value [6]
If "-8", FF update value [7]

  FIG. 37 shows a configuration example of the first EOR operator 3411 in FIG. The selection EOR circuits 2831a to 2831d have the configuration shown in FIG. The selector 3701a receives the input signal IN [0] and the temporary output 1 [0] and selectively outputs them. The selection EOR circuit 2831a receives the output signal of the flip-flop FF0 and the output signal of the selector 3701a, and outputs an output signal. The selector 3702a receives the provisional output 1 [0] and the output signal of the flip-flop FF0, and outputs the selected signal as an intermediate result [0].

  The selector 3701b receives and outputs the output signal of the selection EOR circuit 2831a and the temporary output 1 [0]. The selection EOR circuit 2831b receives the output signal of the flip-flop FF1 and the output signal of the selector 3701b, and outputs an output signal. The selector 3702b receives the output signal of the selection EOR circuit 2831a and the output signal of the flip-flop FF1, and outputs the selected signal as an intermediate result [1].

  The selector 3701c receives the output signal of the selection EOR circuit 2831b and the temporary output 1 [0] and selectively outputs them. The selection EOR circuit 2831c receives the output signal of the flip-flop FF2 and the output signal of the selector 3701c, and outputs an output signal. The selector 3702c receives the output signal of the selection EOR circuit 2831b and the output signal of the flip-flop FF2, and outputs the selected signal as an intermediate result [2].

  The selector 3701d receives the input signal IN [0] and the output signal of the selection EOR circuit at the previous stage, and selects and outputs it. The selection EOR circuit 2831d receives the output signal of the flip-flop FF31 and the output signal of the selector 3701d, and outputs a temporary output 1 [0]. The selector 3703 receives the input signal IN [0], the temporary output 1 [0], and the output signal of the flip-flop FF31, and selectively outputs them. The selector 3702d receives the output signal of the previous selection EOR circuit and the output signal of the selector 3703, and outputs the selected signal as an intermediate result [31].

  FIG. 38 shows a configuration example of the second EOR operator 3412 of FIG. The selection EOR circuits 2831a to 2831d have the configuration shown in FIG. The selector 3701a receives the input signal IN [1] and the temporary output 1 [1] and selectively outputs them. The selection EOR circuit 2831a receives the intermediate result [0] of the previous stage and the output signal of the selector 3701a, and outputs an output signal. The selector 3702a receives the provisional output 1 [1] and the intermediate result [0] of the previous stage, and outputs the selected signal as the intermediate result [0].

  The selector 3701b receives and outputs the output signal of the selection EOR circuit 2831a and the temporary output 1 [1]. The selection EOR circuit 2831b receives the intermediate result [1] of the previous stage and the output signal of the selector 3701b, and outputs an output signal. The selector 3702b receives the output signal of the selection EOR circuit 2831a and the intermediate result [1] of the previous stage, and outputs the selected signal as the intermediate result [1].

  The selector 3701c receives and outputs the output signal of the selection EOR circuit in the previous stage and the temporary output 1 [1]. The selection EOR circuit 2831c receives the intermediate result [30] of the previous stage and the output signal of the selector 3701c, and outputs an output signal. The selector 3703 receives the input signal IN [1], the temporary output 1 [1], and the intermediate result [30] of the previous stage and selectively outputs them. The selector 3702c receives the output signal of the selection EOR circuit in the previous stage and the output signal of the selector 3703, and outputs the selected signal as an intermediate result [30].

  The selector 3701d receives the input signal IN [1] and the output signal of the selection EOR circuit 2831c and selectively outputs them. The selection EOR circuit 2831d receives the intermediate result [31] of the previous stage and the output signal of the selector 3701d, and outputs a temporary output 1 [1]. The selector 3702d receives the output signal of the selection EOR circuit 2831c and the intermediate result [31] of the previous stage, and outputs the selected signal as the intermediate result [31].

  If the input signal of the EOR operator is IN [0], the selector 3703 places the intermediate result [31], IN [1] places the intermediate result [30], and IN [7] gives the intermediate result [ 24] Enter only one place.

  In summary, the semi-fixed circuit of FIG. 33 is a circuit in which four circuits of FIG. 34 are arranged. In FIG. 34, output signals OUT1 [0] to [7] are outputs of the scrambler, CRC circuit, convolutional encoder, and LFSR. The output signal OUT2 is a bit inverted output of the CRC circuit. Depending on the specifications of the CRC circuit, it is necessary to invert and output the output, so that the output inversion circuit 3482 can cope with it.

  The effective output range will be described. The scrambler, convolutional encoder, and LFSR are all valid for input. However, in the CRC circuit, the output of all memories at the time when the input of a certain bit string of the length of the generator polynomial is completed is effective. In other words, the output is invalid until a predetermined bit string is input. For example, in the case of a 16-bit CRC circuit, the output when 16-bit input takes 16 clocks and is input to 16 memories becomes valid.

  A conventional linear feedback shift register or the like is a serial process that outputs 1 bit when 1 bit is input. According to the present embodiment, a circuit that performs look-ahead processing up to a plurality of shift points instead of a bit-by-bit shift operation is made one quasi-fixed circuit, and the processing is switched by a selector, whereby a scrambler, a convolutional encoder, CRC circuit and LFSR can be realized.

(Ninth embodiment)
FIG. 39 shows a configuration example of a semi-fixed circuit according to the ninth embodiment of the present invention. This semi-fixed circuit can realize a plurality of types of Viterbi decoders 117 (FIG. 1B). The branch metric calculation unit 3901 receives the input signals A to C and calculates a branch metric (code word hamming distance) in the trellis diagram. The ACS unit 3902 obtains a path metric for each step of the trellis diagram based on the branch metric, and writes the surviving path and its path metric value to the path memory unit 3903. The path memory unit 3903 includes a control unit 3911 and a RAM 3912. The control unit 3911 writes the data input from the ACS unit 3902 to the RAM 3912 and reads the data in the RAM 3912 to the traceback unit 3904. The traceback unit 3904 traces back when the input signal is performed a certain number of times (or when a dummy bit inserted for the end of encoding is input), and obtains the shortest path metric. The path metric is expressed by a connection of branch metrics. Decoding can be performed assuming that the shortest path metric is a signal of a correct codeword.

  Specifically, the branch metric calculation unit 3901 and the ACS unit 3902 will be described by taking a Viterbi decoder corresponding to the coding rate S / T = 1/2, 1/3 as an example. The denominator T corresponds to the number of input signals, and the numerator S corresponds to the number of output signals. If T to be used is 3, the required inputs are three (A, B, C) signals.

  FIG. 40 shows a configuration example of the branch metric calculation unit 3901 corresponding to the coding rates 1/2 and 1/3. The adder 4001 adds the input signals A and B and outputs a signal BM00. The signal BM00 indicates a branch metric value (Hamming distance) between the input signals B and A and the code word “00”. The adder 4002 adds the inverted value of the input signal A and the input signal B, and outputs a signal BM01. The signal BM01 indicates a branch metric value between the input signals B and A and the code word “01”. The adder 4003 adds the inverted values of the input signal A and the input signal B, and outputs a signal BM10. The signal BM10 indicates a branch metric value between the input signals B and A and the code word “10”. The adder 4004 adds the inverted value of the input signal A and the inverted value of the input signal B, and outputs a signal BM11. The signal BM11 indicates a branch metric value between the input signals B and A and the code word “11”. When the coding rate is 1/2, the selectors 4021 to 4024 select four branch metric signals BM00, BM01, BM10, and BM11 and output them as signals BM000, BM001, BM010, and BM011.

  Next, a case where the coding rate is 1/3 will be described. The adder 4011 adds the signal BM00 and the input signal C, and outputs a signal BM000 via the selector 4021. A signal BM000 indicates a branch metric value of the input signals C, B, A and the code word “000”. The adder 4012 adds the signal BM00 and the inverted value of the input signal C, and outputs a signal BM100. The signal BM100 indicates a branch metric value of the input signals C, B, A and the code word “100”.

  The adder 4013 adds the signal BM01 and the input signal C, and outputs a signal BM001 via the selector 4022. A signal BM001 indicates a branch metric value of the input signals C, B, A and the code word “001”. The adder 4014 adds the signal BM01 and the inverted value of the input signal C, and outputs a signal BM101. A signal BM101 indicates a branch metric value of the input signals C, B, A and the code word “101”.

  The adder 4015 adds the signal BM10 and the input signal C, and outputs a signal BM010 via the selector 4023. A signal BM010 indicates a branch metric value of the input signals C, B, A and the code word “010”. The adder 4016 adds the signal BM10 and the inverted value of the input signal C, and outputs a signal BM110. The signal BM110 indicates a branch metric value of the input signals C, B, A and the code word “110”.

  The adder 4017 adds the signal BM11 and the input signal C, and outputs a signal BM011 via the selector 4024. The signal BM011 indicates branch metric values of the input signals C, B, A and the code word “011”. The adder 4018 adds the signal BM11 and the inverted value of the input signal C, and outputs a signal BM111. The signal BM111 indicates a branch metric value of the input signals C, B, A and the code word “111”.

  The selectors 4021 to 4024 select and output in accordance with the coding rate selection signal. The total number of patterns for the branch metric is 2 T power patterns. In the branch metric calculation unit 3901, all branch metrics are calculated in advance so as to correspond to the coding rate, and output to the ACS unit 3902. In FIG. 40, since two coding rates of 1/2 and 1/3 are supported, the output increases. To prevent this, when T is 2, BM00, BM01, BM10, and BM11 are output as BM000, BM001, BM010, and BM011.

  FIG. 41 shows a configuration example of the ACS unit 3902. Eight branch metric signals BM000 to BM111 and 256 path metric signals PM000 to PM255 are input to 256 selectors 4100 to 4102 and the like according to the PM selection signal, the BM selection signal, and the coding rate selection signal. The path metric signals PM_A and PM_B and the branch metric signals BM_A and BM_B are output. 256 ACSs 4110-4112, etc., receive path metric signals PM_A, PM_B and branch metric signals BM_A, BM_B, perform addition, comparison and selection, and survive path metric signals PM000-PM255 and selected paths PATH000-PATH255. Output as path SL.

  FIG. 42 shows a configuration example of the selector 4100 and the ACS 4110. First, the selector 4100 will be described. The selector 4201 selects one of the path metric signals PM000 to PM255 according to the PM selection signal and the coding rate selection signal, and outputs it as a signal PM_A. The selector 4202 also selects one of the path metric signals PM000 to PM255 according to the PM selection signal and the coding rate selection signal, and outputs it as a signal PM_B. The selector 4203 selects one of the branch metric signals BM000 to BM111 according to the BM selection signal and the coding rate selection signal, and outputs it as a signal BM_A. The selector 4204 also selects one of the branch metric signals BM000 to BM111 according to the BM selection signal and the coding rate selection signal, and outputs it as a signal BM_B.

  Next, the ACS 4110 will be described. The adder 4211 adds the signals PM_A and BM_A, and outputs a path metric when the sign is 0. The adder 4221 adds the signals PM_B and BM_B, and outputs a path metric when the sign is 1. The comparator 4222 subtracts the output signal of the adder 4221 from the output signal of the adder 4211 and outputs the sign to the selector 4212 and the flip-flop 4223. The selector 4212 selects the output signal of the adder 4211 or 4221 according to the sign, and outputs it to the flip-flop 4213. That is, a small path metric is selected and output. The flip-flop 4213 stores and outputs the path metric PM000. The flip-flop 4223 stores the code and outputs the selected path PATH000.

  The ACS unit can cope with the maximum number of states 256 (000 to 256). The 256 selectors 000 to 255 in the ACS unit select necessary ones for each state (000 to 255) from the outputs of the branch metric calculation unit 3901 (PM selection, BM selection, coding rate selection). And output to corresponding ACS000-255.

  There are three circuit settings (PM selection, BM selection, coding rate selection) that generate and output encoded data (input signals A, B, and C in FIG. 39) (FIG. 1 (A)). It will be decided uniquely if the making of is decided. To calculate the path metric PM000 of the next step as the output and the selected (survived) path information PATH, when the numerator S = 1 of the coding rate, two sets of path metrics and branch metrics (PM_A, BM_A and 2 sets of PM_B and BM_B). To generalize, the path metric and branch metric of 2 S-groups may be prepared in one ACS.

  Actually, if two sets of coding rates to be used are S1 / T1 = 1/2, S2 / T2 = 1/3, and the number of states is 64,256, the inputs of the selectors 4201, 4202, 4203, 4204 are input. 256 are not necessary. ((2 to the power of S1) + (2 to the power of S2)) × 2 sets = 8 is sufficient. If two sets of coding rates to be used are S1 / T1 = 1/2, S2 / T2 = 1/3, S3 / T3 = 2/3, and the number of states is 64, 256, ((2 raised to the S1 power ) + (2 to the square of S) + (2 to the square of S3)) × 2 sets = 16.

  As described above, in a Viterbi decoder that depends on parameters such as coding rate and number of states, the number of states determined in advance is prepared, and the path metric and branch metric selection (selection) are fixed and wiring is performed. Information is determined and circuitized, but in the quasi-fixed circuit of this embodiment, by changing the setting of a selector (inside the branch metric calculation unit and ACS unit) prepared in advance in the hardware. The degree of freedom can be given, and convolutional codes of any coding rate and number of states can be decoded by one Viterbi decoder.

(Tenth embodiment)
FIG. 43A shows a configuration example of the matched filter 113 in FIG. This matched filter has, for example, 16 taps and 16 delay element registers 4301. Real number component data Dr and imaginary number component data Di are input to 16 registers 4301 (Reg00 to Reg15) as input data. The register Reg00 outputs the real number component data Dr0 and the imaginary number component data Di0 to the complex multiplication circuit 4302. The complex multiplication circuit 4302 has the configuration shown in FIG. 43B, and receives the input data Dr0 and Di0 and the coefficients Wr0 and Wi0 and performs complex multiplication. The coefficient Wr0 is a real number component, and the coefficient Wi0 is an imaginary number component.

  43B, the complex multiplier circuit 4302 includes four multipliers 4311 to 4314 and two adders 4315 and 4316. The multiplier 4311 multiplies the real number component data Dr0 and the real number component coefficient Wr0 and outputs the result. The multiplier 4312 multiplies the imaginary number component data Di0 and the imaginary number component coefficient Wi0 and outputs the result. The multiplier 4313 multiplies the real number component data Dr0 and the imaginary number component coefficient Wi0 and outputs the result. The multiplier 4314 multiplies the imaginary number component data Di0 and the real number component coefficient Wr0 and outputs the result. The adder 4315 gives a positive sign to the output of the multiplier 4311, gives a negative sign to the output of the multiplier 4312, adds both, and outputs the result. The adder 4316 gives a plus sign to the output of the multiplier 4313, gives a plus sign to the output of the multiplier 4314, adds both, and outputs the result.

  In FIG. 43A, the complex multiplication circuit 4303 similarly receives the input data Dr1, Di1 and the coefficients Wr1, Wi1 and performs complex multiplication. The adder group 4304 has two adders, adds corresponding components of the outputs of the two complex multiplier circuits 4302 and 4303, and outputs the result. The adder group 4305 has two adders, adds corresponding components of the outputs of two adjacent adder groups 4304, and outputs the result. The adder group 4306 has two adders, adds the corresponding components of the outputs of the two adjacent adder groups 4305, and outputs the result. The adder group 4307 has two adders, adds corresponding components of the outputs of two adjacent adder groups 4306, and outputs output data (including real number component data and imaginary number component data). To do.

  As described above, this matched filter performs a 16-tap filter operation on the complex number input data Dr and Di, and outputs a complex number. In the complex multiplication circuit 4302 and the like, complex multiplication is performed by four multipliers and two adders. The output is added using the adder group 4304 as one addition unit in order to add the complex components separately, and finally the sum of the complex multiplication results for 16 taps is output. Thus, the resources to be used are 16 registers, 64 multipliers, and 62 adders.

  FIG. 45 illustrates a configuration example of the FFT 114 in FIG. This FFT is an example of a radix-2 time decimation 8-point FFT. The input data a0, a1,..., A7 are complex data. The output data is A0, A1,..., A7. Wφ = exp ((2π / N) × φ)). Here, N is the number of points, for example, 8. Addition is performed at the intersection, and complex multiplication is performed at the point of Wφ. Subtraction is performed where there is a "-" sign.

Each of the first stage 4501, the second stage 4502, and the third stage 4503 performs four butterfly calculations. The butterfly calculation is performed by the butterfly calculator shown in FIG. 44 and performed on two pieces of input data. For example, in the first butterfly computation of the first stage 4501, (a0 + a4) × 1 computation and (a0−a4) × 1 computation are performed. When there is no multiplication of the coefficient W, this is equivalent to multiplication with the coefficient W = 1. In the second butterfly computation of the first stage 4501, (a2 + a6) × W ⁰ computation and (a2-a6) × W ² computation are performed.

  FIG. 44 shows a configuration example of the butterfly calculator 4400. Similarly to FIG. 43A, the register 4401 outputs two pieces of input data D0 (= Dr0 + jDi0) and D1 (= Dr1 + jDi1) to the butterfly calculator 4400. The butterfly calculator 4400 receives a coefficient W (= Wr0 + jWi0) in addition to the two pieces of input data D0 and D1, performs a butterfly calculation, and outputs output data D0_out and D1_out of the following equations. Here, (*) represents a complex conjugate.

D0_out = D0 + W ^(*) × D1
D1_out = D0−W ^(*) × D1

  Multipliers 4411 and 4415 multiply the real number component data Dr1 and the real number component coefficient Wr0 and output the result. Multipliers 4412 and 4416 multiply the imaginary number component data Di1 and the imaginary number component coefficient Wi0 and output the result. Multipliers 4413 and 4417 multiply the imaginary number component data Di1 and the real number component coefficient Wr0 and output the result. Multipliers 4414 and 4418 multiply and output the real number component data Dr1 and the imaginary number component coefficient Wi0.

  The adder 4421 gives a positive sign to the output of the multiplier 4411, gives a negative sign to the output of the multiplier 4412, adds both, and outputs the result. The adder 4422 gives a plus sign to the output of the multiplier 4413, gives a plus sign to the output of the multiplier 4414, adds both, and outputs the result. The adder 4423 gives a negative sign to the output of the multiplier 4415, gives a positive sign to the output of the multiplier 4416, adds both, and outputs the result. The adder 4424 gives a positive sign to the output of the multiplier 4417, gives a positive sign to the output of the multiplier 4418, adds both, and outputs the result.

  The adder 4431 adds a positive sign to the real number component data Dr0, adds a positive sign to the output of the adder 4421, adds both, and outputs the real number component data Dr0_out. The adder 4432 gives a positive sign to the imaginary number component data Di0, adds a positive sign to the output of the adder 4422, adds both, and outputs imaginary number component data Di0_out. The adder 4433 adds a positive sign to the real number component data Dr0, adds a positive sign to the output of the adder 4423, adds both, and outputs real number component data Dr1_out. The adder 4434 gives a positive sign to the imaginary number component data Di0, gives a negative sign to the output of the adder 4424, adds both, and outputs imaginary number component data Di1_out.

  The first output data D0_out and the second output data D1_out are expressed by the following equations.

D0_out = Dr0_out + jDi0_out
= Dr0 + Wr0 × Dr1 + Wi0 × Di1
+ J × (Di0 + Wr0 × Di1-Wi0 × Dr1)
D1_out = Dr1_out + jDi1_out
= Dr0-Wr0 * Dr1-Wi0 * Di1
+ J × (Di0−Wr0 × Di1 + Wi0 × Dr1)

  The butterfly computing unit 4400 includes eight multipliers and eight adders, and can perform a radix-2 butterfly computation once. The matched filter of FIG. 43 and the butterfly calculator of FIG. 44 are the same in that elements such as a register, a multiplier, and an adder are used. The two different parameters are a coefficient used for multiplication, setting of network information between elements, and a sign at the time of addition. By providing a mechanism on the circuit that can reset these parameters, the matched filter operation and the butterfly operation can be handled by the same circuit. At this time, considering that the resources used in the matched filter in FIG. 43 are shared with the butterfly calculator, two adders are added to the resources in FIG. 43 and eight butterfly calculators 4400 are assembled. be able to.

  FIG. 46 shows a configuration example of a semi-fixed circuit that can selectively implement a matched filter and a butterfly operation. As shown in FIG. 44, one butterfly computing unit 4604 has eight multipliers and eight adders. Accordingly, the eight butterfly calculators 4604 have 64 multipliers and 64 adders. On the other hand, as shown in FIG. 43, the matched filter uses 64 multipliers and 62 adders.

  The input memory (register) 4601 receives 16 pieces of input data and output data from the output memory 4605 under the control of the memory control unit 4611, and outputs them to the selector 4602. The selector 4602 selects input data in accordance with the setting of the selector setting unit 4612 and outputs it to the butterfly calculator 4604 in the calculator unit 4603. The calculator unit 4603 includes eight butterfly calculators 4604. The coefficient setting unit 4613 inputs the coefficient W to the butterfly calculator 4604 via the selector 4602 or directly. The sign setting unit 4614 sets a positive / negative sign in the butterfly calculator 4604. The output memory 4605 also functions as a work memory, stores and outputs the calculation result of the butterfly calculator 4604.

  In this embodiment, when there are 64 complex component inputs, that is, 64-point Fourier transform is considered, butterfly computation is required 192 times. However, if an arithmetic unit 4603 having 8 butterfly computation units is used, 192 ÷ It can be processed in 8 = 24 loops. The matched filter can be processed once. Incidentally, in advance by selecting whether to perform processing, the coefficient setting unit 4613 for setting the coefficients, it is reflected in the selector setting unit 4612 and the code setting unit 4614 for setting a wire.

  The amount of resources of the butterfly calculator 4400 of FIG. 44 and the butterfly calculator 4604 of FIG. 46 are the same. In particular, paying attention to the butterfly calculator 4604, its internal configuration is shown in FIG.

  FIG. 47 shows a configuration example of the butterfly calculator 4604. The butterfly calculator 4604 is a circuit that shares the butterfly calculator and the matched filter. The butterfly calculator 4604 includes complex multiplier circuits 4703 and 4704. Complex multiplication circuits 4703 and 4704 correspond to the complex multiplication circuits 4302 and 4303 (FIG. 43B) in FIG.

  The input memory (register) 4702 and the memory control unit 4701 correspond to the input memory 4601 and the memory control unit 4611 in FIG. The input memory 4702 outputs the input data Dr0, Di0, Dr1, Di1 to the butterfly calculator 4604.

  First, the complex multiplication circuit 4703 will be described. The selector 4711 selects and outputs the real number component data Dr1 or Dr0. The selector 4712 selects and outputs the imaginary number component data Di1 or Di0. The multiplier 4311 multiplies the output of the selector 4711 and the coefficient Wr0 and outputs the result. The multiplier 4312 multiplies the output of the selector 4712 and the coefficient Wi0 and outputs the result. The multiplier 4313 multiplies the output of the selector 4711 and the coefficient Wi0 and outputs the result. The multiplier 4314 multiplies the output of the selector 4712 and the coefficient Wr0 and outputs the result.

  The selector 4731 selects and outputs the output signal 4741 of the adder 4315 or the output signal of the selector 4711 in the complex multiplication circuit 4704. The adder 4721 gives a plus sign to the output of the selector 4731, gives a plus sign to the output of the adder 4315, adds both, and outputs the result. The selector 4732 selects and outputs the output signal 4742 of the adder 4316 or the output signal of the selector 4712 in the complex multiplication circuit 4704. The adder 4722 gives a plus sign to the output of the selector 4732, gives a plus sign to the output of the adder 4316, adds both, and outputs the result.

  Next, the complex multiplication circuit 4704 will be described. The selector 4713 selects and outputs the real component coefficient Wr0 or Wr1. The selector 4714 selects and outputs the imaginary component coefficient Wi0 or Wi1. The multiplier 4311 multiplies the output of the selector 4713 and the real number component data Dr1 and outputs the result. The multiplier 4312 multiplies the output of the selector 4714 and the imaginary number component data Di1 and outputs the result. The multiplier 4313 multiplies the output of the selector 4714 and the real number component data Dr1 and outputs the result. The multiplier 4314 multiplies the output of the selector 4713 and the imaginary component data Di1 and outputs the result.

  The selector 4733 selects and outputs the output signal 4743 of the other adder group 4303 or the like of FIG. 43 or the output signal of the selector 4711. The adder 4723 gives a plus sign to the output of the selector 4733, gives a plus sign to the output of the adder 4315, adds both, and outputs the result. The selector 4734 selects and outputs the output signal 4744 of the other adder group 4303 in FIG. 43 or the like or the output signal of the selector 4712. The adder 4724 gives a plus sign to the output of the selector 4734, gives a plus sign to the output of the adder 4316, adds both, and outputs the result.

  The output memory 4705 corresponds to the output memory 4605 of FIG. 46 and stores the output signals of the adders 4721 to 4724. During the butterfly calculation, the signal of the output memory 4705 is fed back to the input memory 4702.

  In the case of matched filter processing, the coefficients Wr0, Wi0 and Wr1, Wi1 are set first. The selectors 4731, 4732, 4733, 4734, 4711, 4712, 4713, and 4714 select the signal 4741, the signal 4742, the signal 4743, the signal 4744, the data Dr0, the data Di0, the coefficient Wr1, and the coefficient Wi1, respectively. The code setting unit 4614 (FIG. 46) sets as shown in FIG. After the calculation in the complex multiplication circuits 4703 and 4704, the complex outputs are added using the remaining adders 4721 to 4724 and the adder of the remaining butterfly calculator 4604 in the calculator unit 4603 of FIG. Only. In the butterfly calculator 4604, the four outputs of the complex multiplier circuits 4703 and 4704 are added using adders 4721 and 4722 (corresponding to the adder group 4304 in FIG. 43). Adders 4723 and 4724 are used for other additions.

  In the case of butterfly calculation processing, every time data enters the input memory 4702, coefficients Wr0 and Wi0 corresponding to the data are set in the coefficient setting. At the same time, the selectors 4731, 4732, 4733, 4734, 4711, 4712, 4713, and 4714 are respectively the output signal of the selector 4711, the output signal of the selector 4712, the output signal of the selector 4711, the output signal of the selector 47212, the data Dr1, and the data Di1. , Coefficient Wr0, coefficient Wi0. The sign setting unit 4614 (FIG. 46) inverts the sign polarity of the two inputs to the adder 4315 in the complex multiplier circuit 4704 and the input signal 4742 of the adder 4724. Under these settings, the butterfly computing unit 4604 performs butterfly computation of complex two-input data and writes it to the output memory 4705. The above is repeated as necessary and loop processing is performed.

  Note that the output signals of the adders 4721 and 4722 are output to the output memory 4705 during the butterfly calculation, but are not actually output to the output memory 4705 during the matched filter operation, and are output to the adder group 4305 and the like (FIG. 43). Is output. At the time of the matched filter, the adders 4723 and 4724 to which input data is not assigned can be assigned to the adder group 4305 and the like, and are output to them.

  Furthermore, as another embodiment, the order of input data to the butterfly calculator 4604 is changed by the memory control 4701, thereby being a part of the CCK (Complementary Code Keying) demodulation process of the wireless LAN standard IEEE802.11b. It can also be applied to complex multiplication (phase rotation) calculations.

  FIG. 48 shows an example of the internal configuration of the multiplier shown in FIG. Here, an input switching selector 4804, a coefficient storage register 4805, and a scheduler (counter) 4806 are newly added.

  First, the coefficient setting unit sets a constant in the coefficient storage register 4805 at the time of initial setting. The selector 4804 can select an external input 2 or a register value in the coefficient storage register 4805 as an input in accordance with an input switching setting signal. The scheduler 4806 includes a counter, and supplies an address to the coefficient storage register 4805 according to the scheduler setting signal. The address is a fixed value or a repeated output of a count that maximizes a certain set number. For example, if 3 is set, 0, 1, 2, 3, 0, 1, 2,. This is because if a constant is first set in the coefficient storage register 4805, the coefficient set for 16 taps of the matched filter can be switched without exchanging signals with the outside. This means that a matched filter operation can be performed. Coefficient storage register 4805 outputs a coefficient to selector 4808 according to the address.

  The sign setting units 4801 and 4803 are set with positive and negative signs according to the sign setting signal. The input 1 is code-set by the code setting unit 4801 and output to the multiplier 4802. The output signal of the selector 4804 is set by the sign setting unit 4803 and output to the multiplier 4802. Multiplier 4802 multiplies the output signals of code setting sections 4801 and 4803 and outputs the result. Note that the present invention is not limited to the multiplier, and the adder may be controlled by the register 4805 and the scheduler 4806.

  As described above, since arithmetic unit resources such as a multiplier and an adder can be shared between the matched filter and the FFT, the circuit scale can be reduced as compared with a case where resources are separately provided.

(Eleventh embodiment)
FIG. 49 shows an overall configuration example of an LSI including a semi-fixed circuit according to the eleventh embodiment of the present invention. The semi-fixed circuit is, for example, the semi-fixed circuit of the first to tenth embodiments. The LSI 4900 includes, for example, a CPU 4901, a semi-fixed circuit 4904, a fixed circuit 4906, and a RISC (DSP) 4908. In addition to the CPU 4901, the setting bus 4902 is connected to a semi-fixed circuit 4904 via a setting unit 4903, a fixed circuit 4906 via a setting unit 4905, and a RISC 4908 via a setting unit 4907. The CPU 4901 can set or reset the setting units 4903, 4905, and 4907.

  The quasi-fixed circuit 4904 does not constitute the whole as an element whose function is fixed like the conventional hardware (fixed circuit) 4906, but by rewriting the setting by software as needed. Switch functions and configure the whole. Of course, if it is not necessary, the function is separated from the whole. For example, a plurality of functions may be switched and used in a time division manner, or may be set and used by a plurality of semi-fixed circuits.

  A CPU (for setting / resetting) 4901 receives an external command corresponding to the upper layer, and passes circuit configuration setting information to LSI component blocks such as the semi-fixed circuit 4904, the fixed circuit 4906, and the RISC 4908. Each element block including the semi-fixed circuit 4904 has a plurality of setting address spaces for setting one or more. Furthermore, the element block performs its own setting / resetting by referring to the circuit configuration setting information read from each setting address space in accordance with an instruction from the CPU 4901.

  As described above, according to the first to eleventh embodiments, different types of circuits can be realized by one quasi-fixed circuit even in a circuit having the same function, such as a scrambler, a descrambler, or a Viterbi decoder. Can do. In addition, circuits having different functions such as a matched filter and a butterfly operation circuit can be realized by one semi-fixed circuit. Further, simultaneous processing of a plurality of bits such as a plurality of types of scramblers, scramblers or CRC circuits can be realized by one semi-fixed circuit. Thereby, since hardware resources can be shared, the utilization efficiency of hardware resources can be improved. In addition, a plurality of circuits can be realized with one semi-fixed circuit.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  The embodiment of the present invention can be applied in various ways as follows, for example.

(Appendix 1)
A semi-fixed circuit capable of operating multiple types of scramblers or scramblers,
A plurality of flip-flops that can be connected in series;
At least one of the exclusive OR signal of the input signal and the first feedback signal, the feedback signal, and the input signal is selected to be one of the plurality of flip-flops. A first selector capable of outputting;
An exclusive OR signal of an output signal of a second flip-flop of at least one of the plurality of flip-flops and a second feedback signal, an output signal of the second flip-flop, and a second feedback signal A quasi-fixed circuit having a second selector that can select any one of the signals and output the first selector to the first selector as the first feedback signal.
(Appendix 2)
The operation of the IEEE 802.11a standard scrambler, the IEEE 802.11b standard scrambler, and the IEEE 802.11b standard scrambler can be operated according to the selection of the first selector and the second selector. Semi-fixed circuit.
(Appendix 3)
The quasi-fixed circuit according to claim 1, further comprising a decoder for decoding the input signal having a small number of bits to output an output signal having a large number of bits and selecting the first selector and the second selector.
(Appendix 4)
Further, an exclusive OR signal between the output signal of the first selector and the output signal of the preceding stage flip-flop, or the output signal of the preceding stage flip-flop, is provided between the plurality of flip-flops to select the succeeding stage A third selector that can output to the flip-flop of
The quasi-fixed circuit according to supplementary note 1, wherein a CRC (Cycle Redundancy Check) circuit is operable in accordance with selection of the first to third selectors.
(Appendix 5)
Further, at least one of the exclusive-OR signal of the output signal of the second flip-flop and the third feedback signal, the output signal of the second flip-flop, and the third feedback signal And a fourth selector capable of outputting a fourth feedback signal.
The first selector can selectively output an exclusive OR signal of the input signal and the fourth feedback signal and a signal including the fourth feedback signal. Yes,
The semi-fixed circuit according to claim 1, wherein the operation of the convolutional encoder is possible in accordance with the selection of the first, second, and fourth selectors.
(Appendix 6)
Two sets of the plurality of flip-flops, the first selector, the second selector, and the fourth selector are provided,
The quasi-fixed circuit according to appendix 5, wherein the linear feedback shift register circuit can operate in accordance with the selection of the first, second, and fourth selectors.
(Appendix 7)
Further, at least one of the exclusive-OR signal of the output signal of the second flip-flop and the third feedback signal, the output signal of the second flip-flop, and the third feedback signal And a fourth selector capable of outputting a fourth feedback signal.
The first selector can selectively output an exclusive OR signal of the input signal and the fourth feedback signal and a signal including the fourth feedback signal. Yes,
The semi-fixed circuit according to appendix 4, wherein the operation of the convolutional encoder is possible according to the selection of the first to fourth selectors.
(Appendix 8)
Two sets of the plurality of flip-flops, the first selector, the second selector, the third selector, and the fourth selector are provided,
The quasi-fixed circuit according to appendix 7, wherein the linear feedback shift register circuit can operate in accordance with the selection of the first to fourth selectors.
(Appendix 9)
The semi-fixed circuit according to appendix 1, wherein the first flip-flop and the second flip-flop are the same or different flip-flops.
(Appendix 10)
There are a plurality of the second selectors, each connected to a connection line between the plurality of flip-flops,
Each of the second selectors excluding both ends inputs the output signal of the second selector adjacent to one as a second feedback signal, and outputs the selected signal to the second selector adjacent to the other Semi-fixed circuit.
(Appendix 11)
A quasi-fixed circuit capable of simultaneous processing of multiple bits of multiple types of CRC (Cycle Redundancy Check) circuits,
Multiple flip-flops,
A first exclusive OR circuit for selectively calculating an exclusive OR based on the first input bit signal and the output signals of the plurality of flip-flops and outputting an output signal corresponding to the first shift When,
A second exclusive OR for selectively calculating an exclusive OR based on the second input bit signal and the output signal corresponding to the first shift and outputting an output signal corresponding to the second shift. A semi-fixed circuit.
(Appendix 12)
Further, an exclusive OR is selectively calculated based on the nth input bit signal and the shift n-1th shift signal, and an nth exclusive logic for outputting an output signal corresponding to the nth shift is output. The quasi-fixed circuit according to appendix 11, which has a sum circuit.
(Appendix 13)
The quasi-fixed circuit according to appendix 12, wherein one flip-flop of the plurality of flip-flops inputs the output signal of the n-th exclusive OR circuit as feedback.
(Appendix 14)
A quasi-fixed circuit capable of simultaneously processing multiple bits of multiple types of scramblers or scramblers,
Multiple flip-flops,
A first exclusive OR circuit for selectively calculating an exclusive OR based on the first input bit signal and the output signals of the plurality of flip-flops and outputting an output signal corresponding to the first shift When,
A second exclusive OR circuit for selectively calculating an exclusive OR based on the second input bit signal and the output signals of the plurality of flip-flops and outputting an output signal corresponding to the second shift And a semi-fixed circuit.
(Appendix 15)
Two sets of the plurality of flip-flops, the first exclusive OR circuit and the second exclusive OR circuit are provided,
15. The quasi-fixed circuit according to appendix 14, wherein the convolutional encoder can operate according to the selection of the first and second exclusive OR circuits.
(Appendix 16)
Four sets of the plurality of flip-flops, the first exclusive OR circuit and the second exclusive OR circuit are provided,
15. The quasi-fixed circuit according to appendix 14, wherein the convolutional encoder and the linear feedback shift register circuit can operate according to the selection of the first and second exclusive OR circuits.
(Appendix 17)
The first exclusive OR circuit selectively calculates an exclusive OR based on the first input bit signal and the output signals of the plurality of flip-flops, and outputs an output signal corresponding to the first shift. And
The second exclusive OR circuit selectively calculates an exclusive OR based on the second input bit signal and the output signal corresponding to the first shift, and outputs the output signal corresponding to the second shift. The quasi-fixed circuit according to appendix 16, wherein a plurality of types of CRC (Cycle Redundancy Check) circuits can be simultaneously processed by outputting a plurality of bits.
(Appendix 18)
A quasi-fixed circuit capable of Viterbi decoding encoded data convolutionally encoded at a plurality of types of coding rates,
A branch metric calculation circuit that calculates a plurality of branch metrics for Viterbi decoding encoded data that has been subjected to convolution encoding, and selects and outputs a branch metric according to a coding rate;
A quasi-fixed circuit having a path trick operation circuit for selecting a necessary one from the plurality of branch metrics and calculating a path metric;
(Appendix 19)
A quasi-fixed circuit capable of operating a matched filter and a butterfly operation circuit,
A shift register;
A plurality of multipliers for performing multiplication;
A plurality of adders for performing addition;
A connection circuit for controlling connection of the shift register, the plurality of multipliers, and the plurality of adders;
A quasi-fixed circuit capable of operating a matched filter and a butterfly operation circuit according to the connection of the connection circuit.
(Appendix 20)
The quasi-fixed circuit according to appendix 19, wherein the matched filter and the fast Fourier transform circuit can operate according to the connection of the connection circuit.
(Appendix 21)
A memory for storing data to be provided as an input to the multiplier or the adder;
The quasi-fixed circuit according to appendix 19, further comprising a schedule circuit that controls the order in which data in the memory is input to the multiplier or the adder.

DESCRIPTION OF SYMBOLS 101 Scrambler 102 Convolutional encoder 103 Interleave processing circuit 104 Modulation circuit 105 Inverse FFT circuit 106 D / A conversion circuit 107 RF circuit 111 RF circuit 112 A / D conversion circuit 113 Synchronization processing circuit 114 FFT circuit 115 Demodulation circuit 116 Deinterleave processing circuit 117 Viterbi decoder 118 Descrambler 201 CRC bit addition processing circuit 202 Scrambler 203 Modulating circuit 204 Spreading circuit 205 Transmitting circuit 206 Spreading code generating circuit 211 Receiving circuit 212 Despreading circuit 213 Demodulating circuit 214 CRC processing circuit 215 Descrambler 216 Spreading code generation Circuits 301, 302, 401, 402, 501, 502 EOR circuit 601 Input EOR circuit 602 Middle stage EOR circuit 701 Decoder 801, 901 EOR circuit 80 , 902 selector

Claims (6)

A quasi-fixed circuit capable of simultaneous processing of multiple bits of multiple types of CRC (Cycle Redundancy Check) circuits,
Multiple flip-flops,
A first exclusive OR circuit for selectively calculating an exclusive OR based on the first input bit signal and the output signals of the plurality of flip-flops and outputting an output signal corresponding to the first shift When,
A second exclusive OR for selectively calculating an exclusive OR based on the second input bit signal and the output signal corresponding to the first shift and outputting an output signal corresponding to the second shift. A semi-fixed circuit. A semi-fixed circuit capable of simultaneous processing of multiple bits of multiple types of scramblers or descramblers,
Multiple flip-flops,
A first exclusive OR circuit for selectively calculating an exclusive OR based on the first input bit signal and the output signals of the plurality of flip-flops and outputting an output signal corresponding to the first shift When,
A second exclusive OR circuit for selectively calculating an exclusive OR based on the second input bit signal and the output signals of the plurality of flip-flops and outputting an output signal corresponding to the second shift And a semi-fixed circuit. Two sets of the plurality of flip-flops, the first exclusive OR circuit and the second exclusive OR circuit are provided,
The quasi-fixed circuit according to claim 2, wherein the convolutional encoder is operable in accordance with selection of the first and second exclusive OR circuits. Four sets of the plurality of flip-flops, the first exclusive OR circuit and the second exclusive OR circuit are provided,
3. The quasi-fixed circuit according to claim 2, wherein the convolutional encoder and the linear feedback shift register circuit are operable in accordance with selection of the first and second exclusive OR circuits. A quasi-fixed circuit capable of Viterbi decoding encoded data convolutionally encoded at a plurality of types of coding rates,
A branch metric calculation circuit that calculates a plurality of branch metrics for Viterbi decoding encoded data that has been subjected to convolution encoding, and selects and outputs a branch metric according to a coding rate;
A quasi-fixed circuit having a path trick operation circuit for selecting a necessary one from the plurality of branch metrics and calculating a path metric; A quasi-fixed circuit capable of operating a matched filter and a butterfly operation circuit,
A shift register;
A plurality of multipliers for performing multiplication;
A plurality of adders for performing addition;
A connection circuit for controlling connection of the shift register, the plurality of multipliers, and the plurality of adders;
A quasi-fixed circuit capable of operating a matched filter and a butterfly operation circuit according to the connection of the connection circuit.

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