JP2009130291A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a micropattern without using a high-resolution exposure system. <P>SOLUTION: In the formation of a micropattern for forming an interconnecting line, a bridging film 6 having a size of (1/2)d is formed on both side faces of a resist film 5 having a size of 2d to form a line pattern having a size of 3d that is composed of the resist film 5 and the bridging film 6 and a space pattern having a minimum size of d. A first opening having the minimum size of d is formed on a second hard mask 4, using the resist film 5 and the bridging film 6 as a mask. The first opening is filled with a backfill material 7. On the second hard mask 4 and the backfill material 7, a bridging film 9 having the size of (1/2)d is formed on both side faces of a resist film 8 having the size of 2d that is shifted by the size 2d relative to the pattern of the resist film 5 to form a line pattern having the size of 3d that is composed of the resist film 8 and the bridging film 9 and a space pattern having the minimum size of d. A second opening having the minimum size of d is formed on the second hard mask 4, using the resist film 8 and the bridging film 9 as a mask. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device for forming a fine pattern.

  In the manufacturing process of a semiconductor integrated circuit, a lithography technique using an exposure apparatus is widely used as a method for forming a fine pattern on a semiconductor substrate. In recent years, with the progress of miniaturization and high integration of semiconductor elements, it is required to form a fine pattern below the physical resolution limit of an exposure apparatus. As a technique for solving this problem, a process for forming a fine pattern by forming a crosslinked film obtained by crosslinking a RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) material on both sides of a resist pattern formed in a lithography process has been proposed. (For example, refer to Patent Document 1).

In the process described in Patent Document 1 or the like, an opening pattern smaller than an opening resist pattern such as a contact hole or a via hole formed in a lithography process can be formed. However, in the RELACS process, the arrangement density of the pattern itself is determined by the resolution of the lithography. Even if miniaturization is possible, the pattern density per unit area cannot be increased.
Japanese Patent Laid-Open No. 10-73927

  The present invention provides a method for manufacturing a semiconductor device capable of forming a fine pattern without using a high-resolution exposure apparatus.

  A method for manufacturing a semiconductor device of one embodiment of the present invention includes a step of forming a hard mask over a workpiece, a step of forming a first resist pattern on the hard mask, and both sides of the first resist pattern. Forming a first cross-linked film on the surface or the periphery, and etching the hard mask using the first cross-linked film and the first resist pattern as a mask to form a first hard mask opening; Forming a backfill material on the first hard mask so that a backfill material is embedded in the first hard mask opening, and exposing the back surface of the hard mask. Flattening until it is completed, forming a second resist pattern on the hard mask and the backfill material so as to cover the backfill material, and the second resist pattern. Forming a second cross-linked film on both sides or around the surface of the pattern, and etching the hard mask using the second cross-linked film and the second resist pattern as a mask to form a second hard mask opening Forming a portion, peeling the backfill material, and etching the workpiece directly under the first and second hard mask openings using the hard mask as a mask. It is characterized by that.

  Furthermore, a method for manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming a hard mask on a workpiece, a step of forming a first resist pattern on the hard mask, and the first resist pattern. Forming a first cross-linked film on both sides or the periphery thereof, and etching the hard mask using the first cross-linked film and the first resist pattern as a mask to form a first hard mask opening. A step of forming an organic film on the hard mask so as to embed the first hard mask opening, a step of forming a silicon-containing film on the organic film, and on the silicon-containing film Forming a second resist pattern so as to cover the first hard mask opening, and forming a second cross-linked film on both sides or around the second resist pattern. Using the second crosslinked film and the second resist pattern as a mask, etching the silicon-containing film and the organic film to form an opening, and forming the hard mask directly under the opening Etching to form a second hard mask opening, peeling the organic film to expose the first hard mask opening, and using the hard mask as a mask, And etching the workpiece directly under the hard mask opening.

  Furthermore, a method for manufacturing a semiconductor device according to another aspect of the present invention is a method for manufacturing a semiconductor device having a first circuit portion and a second circuit portion in which a pattern having a narrower dimension than that of the first circuit portion is provided. A step of forming a hard mask on the workpiece, a step of forming a first resist pattern on the hard mask, and forming a first cross-linking film on both sides or around the first resist pattern. Etching the hard mask using the first cross-linked film and the first resist pattern as a mask to form a wide hard mask opening in the first circuit portion, and the second circuit Forming a first hard mask opening having a narrower dimension than the wide hard mask opening, and filling a backfill material in the wide hard mask opening and the first hard mask opening. The step of forming the backfill material on the hard mask, the step of planarizing the backfill material until the surface of the hard mask is exposed, and the hard mask and the fill of the first circuit portion. Forming a second resist pattern so as to cover the back material and covering the back material on the hard mask and the back material of the second circuit portion; and Forming a second cross-linked film on both sides or around the second resist pattern; and using the second cross-linked film and the second resist pattern of the second circuit portion as a mask, the hard mask Etching to form a second hard mask opening having a narrower dimension than the wide hard mask opening, peeling the backfill material, and using the hard mask as a mask Etching the workpiece directly under the wide hard mask opening of the first circuit portion and the workpiece under the first and second hard mask openings of the second circuit portion; It is characterized by comprising.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can form a fine pattern without using a high-resolution exposure apparatus can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a method for manufacturing a semiconductor device according to Example 1 of the present invention will be described with reference to the drawings. 1 to 13 are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device. Each figure (a) is a plan view, each figure (b) is a sectional view taken along the line AA in the plan view, each figure (c) is a sectional view taken along the line BB in the plan view, Drawing (d) is a sectional view which meets a CC line of a top view, and each figure (e) is a sectional view which meets a DD line of a top view. In this embodiment, a fine pattern of damascene embedded wiring used for a memory device is formed without using a high-resolution exposure apparatus. On the workpiece, two types of hard masks having different processing selection ratios from the workpiece are provided.

  As shown in FIG. 1, in forming a fine pattern of damascene embedded wiring used for a memory device, first, a film to be processed 2, a first hard mask 3, and a second hard mask 4 are formed on a semiconductor base film 1 having semiconductor elements. Then, the resist pattern 21 is formed by patterning the positive resist film 5 on the second hard mask 4 using a known lithography method, for example, with an excimer laser exposure apparatus. In the memory element portion (second circuit portion) that is most required for miniaturization, a line and space pattern having a dimension of the line L of 2d and a dimension of the space S of 2d is formed, and the peripheral circuit portion (first circuit) is formed. Part) is formed with a relatively wide opening. The dimension 2d is a value twice the required minimum dimension d. A fine pattern is formed in the memory element portion (second circuit portion), and a pattern having a relatively wide dimensional width is formed in the peripheral circuit portion (first circuit portion).

  Here, an insulating film such as a TEOS film is used for the film 2 to be processed. For example, a silicon nitride film (SiN film) is used for the first hard mask 3. For example, an amorphous silicon film is used for the second hard mask 4.

  Next, as shown in FIG. 2, a RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) material, which is a water-soluble organic material, is spin-coated on the resist film 5 and the second hard mask 4. After spin coating, a predetermined heat treatment is performed to form a crosslinked film 6. After the heat treatment, development treatment and pure water rinsing treatment are performed to remove the RELACS material in the uncrosslinked portion, and the crosslinked film 6 is formed on the portions in contact with the resist film 5 (side surfaces and upper surface portions of the resist film 5).

  Here, the width of the cross-linked film 6 formed on the side surface of the resist film 5 is approximately (1/2) d. As a result, the line width composed of the resist film 5 and the sidewall cross-linking film 6 becomes 3d, and the space width becomes the minimum dimension d.

  Subsequently, as shown in FIG. 3, the second hard mask 4 is etched by using, for example, RIE (Reactive Ion Etching) method using the resist film 5 and the sidewall cross-linking film 6 as a mask, and the first hard mask 3 The surface is exposed (formation of the first opening of the second hard mask 4). Here, the etching of the second hard mask 4 is preferably performed vertically so as not to cause a dimensional conversion difference. After the etching process, the resist film 5 and the sidewall cross-linking film 6 are removed by, for example, oxygen plasma treatment. As a result, in the memory element portion, a line & space pattern of the second hard mask 4 having a line width of 3d and a space width of the minimum dimension d is formed.

  Then, as shown in FIG. 4, a backfill material 7 is formed on the first hard mask 3 and the second hard mask 4 so as to fill the opening of the second hard mask 4. For the backfilling material 7, it is preferable to use, for example, a coating type insulating film that has a high processing selectivity with respect to the second hard mask 4 and that is excellent in the filling property of the opening.

  Next, as shown in FIG. 5, the backfill material 7 is flatly polished using, for example, a CMP (Chemical Mechanical Polishing) method until the surface of the second hard mask 4 is exposed. As a result, the backfill material 7 is embedded in the opening of the second hard mask 4. Although the CMP method is used here, the backfill material 7 may be flattened by using an etch back method such as RIE.

  Subsequently, as shown in FIG. 6, the positive resist film 8 is patterned using, for example, an excimer laser exposure apparatus using a well-known lithography method, and a resist pattern 22 is formed on the second hard mask 4 and the backfill material 7. Form. In the memory element portion, the resist pattern 22 is formed so that the position thereof is shifted approximately 2d with respect to the resist pattern 21 of FIG. A line & space pattern in which the dimension of the line L is 2d and the dimension of the space S is 2d is formed. The peripheral circuit portion is covered with a resist film 8.

  Then, as shown in FIG. 7, a RELACS material that is a water-soluble organic material is spin-coated on the resist film 8 and the second hard mask 4. After spin coating, a predetermined heat treatment is performed to form a crosslinked film 9. After the heat treatment, development processing is performed to remove the RELACS material in the uncrosslinked portion, and the crosslinked film 6 is formed in the portion in contact with the resist film 8.

  Here, the width of the cross-linked film 9 formed on the side surface of the resist film 8 is approximately (1/2) d. As a result, the line width composed of the resist film 8 and the sidewall cross-linking film 9 is 3d, and the space width is the minimum dimension d.

  Next, as shown in FIG. 8, using the resist film 8 and the sidewall cross-linking film 9 as a mask, the second hard mask 4 is etched using, for example, the RIE method to expose the surface of the first hard mask 3 ( Second opening formation of second hard mask 4). Here, the etching of the second hard mask 4 is preferably performed vertically so as not to cause a dimensional conversion difference.

  Subsequently, as shown in FIG. 9, the resist film 8 and the sidewall cross-linking film 9 are removed by, for example, oxygen plasma treatment. As a result, a line & space pattern having a line width of 3d and a space width of the minimum dimension d is formed in the memory element portion. A backfill material 7 having a minimum dimension d is provided in the center of the pattern having a line width of 3d. That is, the second hard mask 4 having the minimum dimension d is disposed on one side surface, the backfill material 7 having the minimum dimension d is disposed on the center portion, and the second hard mask 4 having the minimum dimension d is disposed on the other side surface.

  Then, as shown in FIG. 10, for example, the backfill material is formed by the RIE method having a condition (high selection ratio) of the etching rate of the backfill material 7 with respect to the second hard mask 4 and the first hard mask 3. 7 is selectively etched. As a result, in the memory element portion, the line & space pattern of the second hard mask 4 having the minimum line width d and the minimum space width d is formed. Although the RIE method is used here, the backfill material 7 may be selectively etched using a wet etching solution.

  Next, as shown in FIG. 11, using the second hard mask 4 as a mask, the first hard mask 3 is etched using, for example, the RIE method to expose the surface of the film 2 to be processed. In the RIE method used here, the second hard mask 4 and the film to be processed 2 are processed in such a way that no dimensional conversion difference occurs under the condition that the etching rate of the first hard mask 3 is large (selectivity is large). It is preferable to use conditions that allow one hard mask 3 to be etched vertically.

  Subsequently, as shown in FIG. 12, the processed film 2 is etched by using, for example, the RIE method using the first hard mask 3 as a mask to expose the surface of the base film 1. In the RIE method used here, the first hard mask 3 is perpendicular to the first hard mask 3 so that a dimensional conversion difference does not occur under the condition that the etching rate of the film 2 to be processed is high (selectivity ratio is large). It is preferable to use conditions that allow etching. Here, the second hard mask 4 is removed by etching by the RIE method.

  Then, as shown in FIG. 13, the first hard mask 3 which is a silicon nitride film (SiN film) is selectively etched away by, for example, hot phosphoric acid treatment. As a result, a line & space pattern of the film to be processed 2 having a minimum line width d and a minimum space width d is formed in the memory element portion. An opening having a relatively large width is formed in the peripheral circuit portion.

  Next, although not shown, a metal to be a wiring is embedded in the openings of the film 2 to be processed in the memory element portion and the peripheral circuit portion by using a known damascene method. After the damascene embedded wiring is formed, an interlayer insulating film and a wiring layer are formed using a well-known technique to complete the memory device.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the processed film 2, the first hard mask 3, and the second hard mask 4 are stacked on the base film 1 having the semiconductor elements, and then the second. A positive resist film 5 is patterned on the hard mask 4. In the memory element portion, a line & space pattern in which the dimension of the line L is 2d and the dimension of the space S is 2d is formed. After the resist pattern 21 is formed, a cross-linking film 6 having a dimension (1/2) d is formed on both sides of the resist film 5 having a dimension 2d in the memory element portion, and a line pattern having a dimension 3d composed of the resist film 5 and the cross-linking film 6 is formed. And a space pattern of the minimum dimension d is formed. The second hard mask 4 is etched using the resist film 5 and the crosslinked film 6 as a mask, and a first opening having a minimum dimension d is formed in the second hard mask 4. After embedding the backfill material 7 in the first opening, the dimension of the line L, which is shifted by 2d with respect to the resist pattern 21 in the memory element portion, is 2d on the second hard mask 4 and the embedding material 7. Then, a resist film 8 having a line & space pattern in which the dimension of the space S is 2d is formed. After the resist pattern 22 is formed, in the memory element portion, a cross-linking film 9 having a dimension (1/2) d is formed on both side surfaces of the resist film 8 having a dimension 2d, and a line pattern having a dimension 3d composed of the resist film 8 and the cross-linking film 9 And a space pattern of the minimum dimension d is formed. The second hard mask 4 is etched using the resist film 8 and the crosslinked film 9 as a mask, and a second opening having a minimum dimension d is formed in the second hard mask 4. The backfill material 7 is peeled off to form a line pattern of the second hard mask 4 having the minimum dimension d and a space pattern of the second hard mask 4 having the minimum dimension d in the memory element portion. The first hard mask 3 is etched using the second hard mask 4 as a mask. The processed film 2 is etched using the first hard mask 3 as a mask. In the memory element portion, a line pattern of the processed film 2 having the minimum dimension d and a space pattern of the processed film 2 having the minimum dimension d are formed.

  For this reason, it is possible to form a damascene embedded wiring line & space pattern having a fine minimum dimension d smaller than the lithography resolution without using a high resolution exposure apparatus with higher accuracy than in the past. Further, since it is possible to realize the processing of the minimum dimension d required without introducing a state-of-the-art exposure apparatus, the manufacturing cost of LSIs that are miniaturized and highly integrated such as memory devices is greatly reduced. be able to.

  In this embodiment, the film to be processed having the required minimum dimension d is formed using a positive resist film and a crosslinked film, but the minimum dimension required using a negative resist film and a crosslinked film. A film to be processed having d may be formed. Moreover, although the line & space pattern which has the minimum dimension d is formed, it is not necessarily limited to this. For example, the line may be the minimum dimension d, and the space may be larger than the minimum dimension d.

  Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. 14 and 15 are a plan view and a cross-sectional view showing the manufacturing process of the semiconductor device. Each figure (a) is a plan view, each figure (b) is a sectional view taken along the line AA in the plan view, each figure (c) is a sectional view taken along the line BB in the plan view, Drawing (d) is a sectional view which meets a CC line of a top view, and each figure (e) is a sectional view which meets a DD line of a top view. In this embodiment, the fine pattern of the wiring of the memory device is formed without using a high-resolution exposure apparatus. Further, using a desired device material directly on the workpiece, for example, a wiring metal film, a gate electrode film, a fin-shaped transistor element region, or a silicon substrate between element isolation regions, as in Example 1, A workpiece is directly processed to form a semiconductor element.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 14, in the fine pattern formation in the present embodiment, a film 2a to be processed, a first hard mask 3 and a second hard mask 4 are formed on the base film 1 and then, for example, an excimer laser exposure apparatus. Thus, the resist film 5 is patterned by using a well-known lithography method, and a resist pattern 21 is formed on the second hard mask 4.

  After the resist pattern 21 is formed, the crosslinked film 6 is selectively formed on the side surface and the upper surface of the resist film 5 as in the first embodiment. As a result, the line width composed of the resist film 5 and the sidewall cross-linking film 6 becomes 3d, and the space width becomes the minimum dimension d.

  Here, for example, an aluminum (AL) film used for wiring is used for the film 2a to be processed. Since the subsequent steps up to the pattern formation including the second hard mask 4 and the first hard mask 3 (FIG. 12) are the same as those in the first embodiment, the description thereof is omitted.

  Next, as shown in FIG. 15, using the second hard mask 4 and the first hard mask 3 as a mask, the film 2a to be processed is etched using, for example, the RIE method. Here, the etching of the film 2a to be processed has a large etching rate for the film 2a made of an aluminum (AL) film with respect to the second hard mask 4, the first hard mask 3, and the base film 1 (selection is possible). For example, it is preferable to perform the etching process vertically using RIE conditions using an etching gas such as chlorine or bromine. After the RIE process, the second hard mask 4 and the first hard mask 3 are removed by etching.

  As a result, a wiring pattern having a minimum line width d and a minimum space width d is formed in the memory element portion. A wiring pattern having a relatively large dimensional width is formed in the peripheral circuit portion.

  As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the film to be processed 2a, the first hard mask 3, and the second hard mask 4 used for wiring are stacked on the base film 1, and then the embodiment is performed. 1, a line pattern of the processed film 2a used for the wiring having the minimum dimension d and a space pattern of the processed film 2a having the minimum dimension d are formed in the memory element portion.

  For this reason, the line & space pattern of the film 2a to be processed used for the wiring having the fine minimum dimension d below the lithography resolution can be formed with higher accuracy than before without using a high resolution exposure apparatus. Further, since it is possible to realize the processing of the minimum dimension d required without introducing a state-of-the-art exposure apparatus, the manufacturing cost of LSIs that are miniaturized and highly integrated such as memory devices is greatly reduced. be able to.

  In this embodiment, the processed film 2a made of an aluminum (AL) film is etched with the required minimum dimension d. However, the processed film made of a single layer or a stacked gate electrode film, The silicon substrate or the like between the element isolation regions may be etched using a hard mask as a mask.

  Next, a method for manufacturing a semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. 16 to 18 are cross-sectional views showing the manufacturing process of the semiconductor device. In this embodiment, a fine pattern of damascene embedded wiring of a memory device is formed without using a high resolution exposure apparatus. On the workpiece, a hard mask layer having a large machining selection ratio with respect to the workpiece is provided.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 16, in the formation of a fine pattern of damascene embedded wiring of a memory device, after the film to be processed 2 and the hard mask 41 are formed on the base film 1, the process up to peeling of the embedded material (FIG. 9) is carried out. The line & space pattern of the hard mask 41 in which the dimension of the line L is the minimum dimension d and the dimension of the space S is the minimum dimension d is formed in the memory element portion. Here, as the hard mask 41, a film capable of obtaining a sufficient processing selection ratio with respect to the film to be processed 2 is used.

  Next, as shown in FIG. 17, using the hard mask 41 as a mask, the film to be processed 2 is etched using, for example, the RIE method to expose the surface of the semiconductor base film 1 having the semiconductor elements.

  Subsequently, as shown in FIG. 18, the hard mask 41 is selectively removed by etching. As a result, a line & space pattern of the film to be processed 2 having a minimum line width d and a minimum space width d is formed in the memory element portion. An opening having a relatively large width is formed in the peripheral circuit portion.

  Although not shown, a wiring metal is embedded in the openings of the film 2 to be processed in the memory element portion and the peripheral circuit portion using a known damascene method. After the damascene embedded wiring is formed, an interlayer insulating film and a wiring layer are formed using a well-known technique to complete the memory device.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the processed film 2 and the hard mask 41 are stacked on the base film 1 and then the minimum dimension d is set in the memory element portion in the same manner as in the first embodiment. A line pattern of the hard mask 41 and a space pattern of the hard mask 41 having the minimum dimension d are formed. The processed film 2 is etched using the hard mask 41 as a mask. In the memory element portion, a line pattern of the processed film 2 having the minimum dimension d and a space pattern of the processed film 2 having the minimum dimension d are formed.

  For this reason, in addition to the same effects as those of the first embodiment, the number of hard masks is reduced, so that the manufacturing process can be reduced as compared with the first embodiment.

  Next, a method for manufacturing a semiconductor device according to Embodiment 4 of the present invention will be described with reference to the drawings. 19 to 23 are cross-sectional views showing the manufacturing process of the semiconductor device. In this embodiment, a fine pattern of damascene embedded wiring of a memory device is formed without using a high resolution exposure apparatus. The fine pattern is formed using a laminated mask structure process.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 19, in the fine pattern formation of the damascene embedded wiring of the memory device, after forming the first opening of the second hard mask (FIG. 3) in the same manner as in Example 1, the organic film 11 and silicon containing A film 12 is laminated and the organic film 11 is embedded in the first opening of the second hard mask 4.

  Here, as the organic film 11, for example, a coating type organic film capable of flattening the film is used. In addition, an organic film may be formed using a CVD method or the like. As the silicon-containing film 12, for example, a coating type oxide film that can flatten the film is used. In addition, a silicon-containing film may be formed using a CVD method or the like. After the organic film 11 and the silicon-containing film 12 are laminated, a positive resist film 13 is applied.

  Next, as shown in FIG. 20, the resist pattern 23 is formed by patterning the positive resist film 13 on the silicon-containing film 12 using, for example, an excimer laser exposure apparatus using a well-known lithography method. Similar to the resist film of the first embodiment, a line and space pattern having a line L dimension of 2d and a space S dimension of 2d is formed in the memory element portion, and the peripheral circuit portion is covered with the resist film 13.

  Subsequently, as shown in FIG. 21, a crosslinked film 14 is selectively formed on the side surface and the upper surface of the resist film 13 in the same manner as in Example 1 (FIG. 7). Here, the width of the cross-linked film 14 formed on the side surface of the resist film 13 is approximately (1/2) d. As a result, the line width composed of the resist film 13 and the sidewall cross-linking film 14 becomes 3d, and the space width becomes the minimum dimension d.

  Then, as shown in FIG. 22, the silicon-containing film 12 is etched using, for example, the RIE method using the resist film 13 and the sidewall cross-linked film 14 as a mask. Further, using the silicon-containing film 12 as a mask, the organic film 11 is etched using, for example, the RIE method to expose the surface of the second hard mask 4.

  Next, as shown in FIG. 23, using the organic film 11 as a mask, the second hard mask 4 is etched using, for example, the RIE method to expose the surface of the first hard mask 3. After the etching of the second hard mask 4, the organic film 11 is peeled off by, for example, oxygen plasma treatment.

  As a result, a line & space pattern of the second hard mask 4 having a minimum line width d and a minimum space width d is formed in the memory element portion. An opening having a relatively large width is formed in the peripheral circuit portion. Since the subsequent steps are the same as those of the first embodiment, illustration and description thereof are omitted.

  As described above, in the method of manufacturing the semiconductor device according to this embodiment, the processed film 2, the first hard mask 3, and the second hard mask 4 are stacked on the base film 1, and then the second hard mask 4. A resist pattern 21 is formed thereon. In the memory element portion, a line & space pattern in which the dimension of the line L is 2d and the dimension of the space S is 2d is formed. After the resist pattern 21 is formed, a cross-linking film 6 having a dimension (1/2) d is formed on both sides of the resist film 5 having a dimension 2d in the memory element portion, and a line pattern having a dimension 3d composed of the resist film 5 and the cross-linking film 6 is formed. And a space pattern of the minimum dimension d is formed. The second hard mask 4 is etched using the resist film 5 and the crosslinked film 6 as a mask, and a first opening having a minimum dimension d is formed in the second hard mask 4. An organic film 11 is formed so as to cover the first opening, and a silicon-containing film 12 is formed on the organic film 11. On the silicon-containing film 12, a resist pattern 23 having a line & space pattern in which the dimension of the line L is 2d and the dimension of the space S is 2d is formed by shifting the position by 2d with respect to the resist pattern 21 in the memory element portion. . After the resist pattern 23 is formed, a cross-linking film 14 having a size (1/2) d is formed on both side surfaces of the resist film 13 having a size 2d in the memory element portion, and a line pattern having a size 3d composed of the resist film 13 and the cross-linking film 14 is formed. And a space pattern of the minimum dimension d is formed. The silicon-containing film 12 and the organic film 11 are etched using the resist film 13 and the cross-linked film 14 as a mask, and the second hard mask 4 is etched using the organic film 11 as a mask. A second opening of dimension d is formed. The organic film 11 is peeled off to form a line pattern of the second hard mask 4 having the minimum dimension d and a space pattern of the second hard mask 4 having the minimum dimension d in the memory element portion.

  For this reason, in addition to the effects of the first embodiment, the backfill material embedding step by etch back, the embedding material etching step, and the like can be omitted, and the surface can be planarized. The manufacturing cost of the highly integrated LSI can be reduced as compared with the first embodiment.

  Next, a semiconductor device manufacturing method according to Embodiment 5 of the present invention will be described with reference to the drawings. 23 to 28 are a plan view and a cross-sectional view showing the manufacturing process of the semiconductor device. In this embodiment, the pattern formation of the fine memory element portion is the same as that of the first embodiment, and the pattern of the peripheral circuit portion is formed by a method different from that of the first embodiment.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 24, in forming a fine pattern of damascene embedded wiring used for a memory device, first, a film to be processed 2, a first hard mask 3, and a second hard mask 4 are formed on a semiconductor base film 1 having semiconductor elements. Then, the resist pattern 21 is formed by patterning the positive resist film 5 on the second hard mask 4 using a known lithography method, for example, with an excimer laser exposure apparatus. The peripheral circuit portion is covered with a positive resist film 5.

  Next, as in Example 1, after forming a fine first opening in the second hard mask 4 of the memory element portion, as shown in FIG. 25, the first hard mask 3 and the second hard mask 3 are formed. A backfill material 7 is formed on the mask 4 so as to fill the opening of the second hard mask 4. A backfill material 7 is formed on the second hard mask 4 in the peripheral circuit portion.

  Subsequently, as in Example 1, after the backfill material 7 is flatly polished, as shown in FIG. 26, the positive resist film 8 is patterned using a known lithography method using, for example, an excimer laser exposure apparatus, A resist pattern 22 is formed on the second hard mask 4 and the backfill material 7 of the memory element portion. At this time, also in the peripheral circuit portion, the positive resist film 8 is patterned on the second hard mask 4 so as to cover the opening, and a resist pattern 22 is formed.

  Then, as shown in FIG. 27, a RELACS material, which is a water-soluble organic material, is spin-coated on the resist film 8 and the second hard mask 4. After spin coating, a predetermined heat treatment is performed to form a crosslinked film 9. After the heat treatment, development is performed to remove the RELACS material in the uncrosslinked portion, and a crosslinked film 9 is formed in a portion in contact with the resist film 8. At this time, the crosslinked film 9 is also formed around the resist pattern 22 in the peripheral circuit portion.

  Next, as shown in FIG. 28, using the resist film 8 and the sidewall cross-linking film 9 as a mask, the second hard mask 4 is etched using, for example, the RIE method to expose the surface of the first hard mask 3 ( Formation of second opening of second hard mask 4 of memory element portion). Similar to the memory element portion, the second hard mask 4 in the peripheral circuit portion is etched using the resist film 8 and the sidewall cross-linking film 9 as a mask. Since the subsequent steps are the same as those in the first embodiment, illustration and description thereof are omitted.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the processed film 2, the first hard mask 3, and the second hard mask 4 are stacked on the base film 1 having the semiconductor elements, and then the second. A positive resist film 5 is patterned on the hard mask 4. The peripheral circuit portion is covered with a positive resist film 5. In the memory element portion, a line & space pattern in which the dimension of the line L is 2d and the dimension of the space S is 2d is formed. After the resist pattern 21 is formed, a cross-linking film 6 having a dimension (1/2) d is formed on both sides of the resist film 5 having a dimension 2d in the memory element portion, and a line pattern having a dimension 3d composed of the resist film 5 and the cross-linking film 6 is formed. And a space pattern of the minimum dimension d is formed. The second hard mask 4 is etched using the resist film 5 and the crosslinked film 6 as a mask, and a first opening having a minimum dimension d is formed in the second hard mask 4. After embedding the backfill material 7 in the first opening, the dimension of the line L, which is shifted by 2d with respect to the resist pattern 21 in the memory element portion, is 2d on the second hard mask 4 and the embedding material 7. Then, a resist film 8 having a line & space pattern in which the dimension of the space S is 2d is formed. After forming the resist pattern 22 in the memory element portion and the peripheral circuit portion, the memory element portion forms a cross-linking film 9 having a dimension (1/2) d on both sides of the resist film 8 having a dimension 2d. A line pattern having a dimension 3d of 9 and a space pattern having a minimum dimension d are formed, and the bridge film 9 is formed around the resist pattern 22 in the peripheral circuit portion. The second hard mask 4 is etched using the resist film 8 and the crosslinked film 9 as a mask, and an opening is formed in the second hard mask 4 in the second opening of the minimum dimension d and in the peripheral circuit portion. For this reason, it has the same effect as Example 1.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, although applied to wiring and gate processing, it can also be applied to processing of an STI element isolation region having a line & space pattern.

Further, configurations as described in the following supplementary notes are conceivable.
(Supplementary Note 1) A step of laminating and forming a first hard mask and a second hard mask on a workpiece, a step of forming a first resist pattern on the second hard mask, and the first Forming a first cross-linked film on both sides or around the resist pattern, and etching the second hard mask using the first cross-linked film and the first resist pattern as a mask Forming a hard mask opening, forming an organic film on the second hard mask so as to embed the first hard mask opening, and forming an insulating film on the organic film A step, a step of forming a second resist pattern on the insulating film, a step of forming a second crosslinked film on both sides or the periphery of the second resist pattern, the second crosslinked film, and the Second review Etching the insulating film and the organic film using a resist pattern as a mask to form an opening, and etching the second hard mask directly below the opening using the organic film as a mask. Forming the second hard mask opening, peeling the organic film to expose the first hard mask opening, and using the second hard mask as a mask, the first and second A method of manufacturing a semiconductor device, comprising: etching the first hard mask immediately below the hard mask opening; and etching the workpiece using the first hard mask as a mask.

(Additional remark 2) The process of forming a hard mask on a workpiece, The process of forming a 1st resist pattern on the said hard mask, A 1st crosslinked film on the both sides | surfaces or circumference | surroundings of the said 1st resist pattern Forming a first hard mask opening by etching the hard mask using the first crosslinked film and the first resist pattern as a mask, and the first hard mask. Forming the backfill material on the hard mask so as to embed the backfill material in the opening, planarizing the backfill material until the surface of the hard mask is exposed, the hard mask and the hard mask Forming a second resist pattern on the backfilling material so as to cover the backfilling material, and a second cross-linking film on both sides or around the second resist pattern Forming a second hard mask opening by etching the hard mask using the second cross-linked film and the second resist pattern as a mask; and peeling the backfill material. Using the hard mask as a mask, and etching the workpiece directly under the first and second hard mask openings, and used for forming the first and second resist patterns. A method of manufacturing a semiconductor device, wherein the line and space dimensions of the workpiece are approximately d when the minimum resolution dimension of the exposure apparatus is 2d.

(Supplementary note 3) The semiconductor device according to any one of Supplementary notes 1 or 2, wherein the workpiece is a silicon substrate between an insulating film for damascene wiring, a wiring metal film, a gate electrode film, a transistor element region, or an element isolation region. Manufacturing method.

1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 1A and 1B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 1 of the invention. 9A and 9B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 2 of the invention. 9A and 9B are a plan view and a cross-sectional view showing a manufacturing process of a semiconductor device according to Example 2 of the invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 3 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 3 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 3 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on Example 4 of this invention. The top view and sectional drawing which show the manufacturing process of the semiconductor device which concerns on Example 5 of this invention. The top view and sectional drawing which show the manufacturing process of the semiconductor device which concerns on Example 5 of this invention. The top view and sectional drawing which show the manufacturing process of the semiconductor device which concerns on Example 5 of this invention. The top view and sectional drawing which show the manufacturing process of the semiconductor device which concerns on Example 5 of this invention. The top view and sectional drawing which show the manufacturing process of the semiconductor device which concerns on Example 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base film 2, 2a Processed film 3 1st hard mask 4 2nd hard mask 5, 8, 13 Resist film 6, 9, 14 Crosslinking film 7 Backfill material 11 Organic film 12 Silicon-containing films 21, 22, 23 resist pattern 41 hard mask d minimum dimension L line S space

Claims (5)

Forming a hard mask on the workpiece; and
Forming a first resist pattern on the hard mask;
Forming a first crosslinked film on both sides or the periphery of the first resist pattern;
Etching the hard mask using the first cross-linked film and the first resist pattern as a mask to form a first hard mask opening;
Forming the backfill material on the first hard mask so as to fill the backfill material in the first hard mask opening;
Planarizing the backfill material until the surface of the hard mask is exposed;
Forming a second resist pattern on the hard mask and the backfill material so as to cover the backfill material;
Forming a second cross-linked film on both sides or around the second resist pattern;
Etching the hard mask using the second crosslinked film and the second resist pattern as a mask to form a second hard mask opening;
Peeling the backfill material;
Etching the workpiece directly under the first and second hard mask openings using the hard mask as a mask;
A method for manufacturing a semiconductor device, comprising: Forming a hard mask on the workpiece; and
Forming a first resist pattern on the hard mask;
Forming a first crosslinked film on both sides or the periphery of the first resist pattern;
Etching the hard mask using the first cross-linked film and the first resist pattern as a mask to form a first hard mask opening;
Forming an organic film on the hard mask so as to embed the first hard mask opening;
Forming a silicon-containing film on the organic film;
Forming a second resist pattern on the silicon-containing film so as to cover the first hard mask opening;
Forming a second cross-linked film on both sides or around the second resist pattern;
Etching the silicon-containing film and the organic film with the second crosslinked film and the second resist pattern as a mask to form an opening;
Etching the hard mask directly under the opening to form a second hard mask opening;
Peeling the organic film to expose the first hard mask opening;
Etching the workpiece directly under the first and second hard mask openings using the hard mask as a mask;
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device having a first circuit portion and a second circuit portion provided with a pattern having a narrower dimension than the first circuit portion,
Forming a hard mask on the workpiece; and
Forming a first resist pattern on the hard mask;
Forming a first crosslinked film on both sides or the periphery of the first resist pattern;
The hard mask is etched using the first cross-linked film and the first resist pattern as a mask to form a wide hard mask opening in the first circuit portion, and the wide circuit portion in the second circuit portion. Forming a first hard mask opening having a narrower dimension than the hard mask opening;
Forming the backfill material on the hard mask so as to embed a backfill material in the wide hard mask opening and the first hard mask opening;
Planarizing the backfill material until the surface of the hard mask is exposed;
A second resist pattern is formed so as to cover the hard mask and the backfill material of the first circuit portion, and to cover the backfill material on the hard mask and the backfill material of the second circuit portion. Forming, and
Forming a second cross-linked film on both sides or around the second resist pattern of the second circuit portion;
A second hard mask opening having a size narrower than that of the wide hard mask opening by etching the hard mask using the second bridging film and the second resist pattern of the second circuit portion as a mask. Forming a step;
Peeling the backfill material;
Using the hard mask as a mask, the workpiece directly under the wide hard mask opening of the first circuit portion and the cover under the first and second hard mask openings of the second circuit portion. Etching the workpiece,
A method for manufacturing a semiconductor device, comprising:   When the line and space dimensions of the first and second resist patterns are 2d, the second resist pattern is formed with a position shifted by approximately 2d with respect to the first resist pattern. The dimension of the first crosslinked film provided on the side surface of the resist pattern and the dimension of the second crosslinked film provided on the side surface of the second resist pattern are substantially (1/2) d. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method. A method of manufacturing a semiconductor device having a first circuit portion and a second circuit portion provided with a pattern having a narrower dimension than the first circuit portion,
Forming a hard mask on the workpiece; and
Forming a first resist pattern on the hard mask;
Forming a first crosslinked film on both sides or the periphery of the first resist pattern;
Etching the hard mask using the first crosslinked film and the first resist pattern as a mask to form a first hard mask opening in the second circuit portion;
Forming the backfill material on the hard mask such that the backfill material is embedded in the first hard mask opening;
Planarizing the backfill material until the surface of the hard mask is exposed;
A second resist pattern is formed so as to have an opening on the hard mask of the first circuit portion and to cover the backfill material on the hardmask and the backfill material of the second circuit portion. Forming, and
Forming a second cross-linking film on both sides or around the second resist pattern of the first and second circuit portions;
Using the second bridge film and the second resist pattern of the first circuit portion as a mask, the hard mask is etched to form a wide hard mask opening wider than the first hard mask opening. The second hard mask opening narrower than the wide hard mask opening by etching the hard mask using the second bridge film and the second resist pattern of the second circuit portion as a mask. Forming a step;
Peeling the backfill material;
Using the hard mask as a mask, the workpiece directly under the wide hard mask opening of the first circuit portion and the cover under the first and second hard mask openings of the second circuit portion. Etching the workpiece,
A method for manufacturing a semiconductor device, comprising:

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