JP2012033839A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which optimizes a depth of a wiring trench between a memory cell array region and a peripheral circuit region.SOLUTION: The method of manufacturing the semiconductor device comprises: a step of processing a core material film using a resist pattern as a mask; a step of forming a side wall film having an etching selection ratio with a film to be processed on the core material film; a step of processing the side wall film by the anisotropic etching process; a step of selectively removing the core material film and the side wall film; and a step of forming an insulting film having a first film thickness on the side wall film and the film to be processed in a first region, and forming an insulating layer having a second film thickness on the film to be processed in a second region. The method further comprises: a step of forming a resist pattern in the second region by the photolithography process; and a step of processing the insulating layer and the film to be processed using the side wall film in the first region and the resist pattern in the second region as masks and then forming a wiring trench in the film to be processed.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Due to demands for miniaturization of semiconductor devices, it is necessary to form wiring patterns that are below the resolution limit of lithography. As a method for realizing this, a so-called sidewall transfer process is known.

  In this method, a hard mask and a resist are formed on a wiring material, and after slimming the resist, the hard mask is etched using the resist as a mask. After removing the resist, a thin film to be a sidewall film is deposited, and the bottom and upper thin films are etched by anisotropic etching or the like, thereby forming a sidewall film on the hard mask sidewall. Then, only the hard mask is removed by anisotropic etching or isotropic etching to leave the sidewall film. Then, the wiring material is processed using this sidewall film as a mask.

  When the pattern to be formed is a damascene process wiring pattern, a wiring groove is formed by etching a wiring interlayer insulating film instead of the above wiring material, and a metal material or the like that becomes wiring is embedded in the groove, and CMP is performed. The wiring is formed by planarization with (Chemical Mechanical Polish) or the like.

  In addition, in a device having a pattern with a difference in wiring width, such as a memory cell array and a peripheral circuit, such as a semiconductor memory device, the wiring pattern below the resolution limit by the sidewall transfer process is the same as the wider wiring pattern. It is necessary to form the wiring layer. In the damascene process in this case, a resist pattern is formed in the peripheral circuit region prior to etching using the sidewall film as a mask. Thereafter, in the memory cell array, the wiring groove is processed using the sidewall film as a mask, and the wiring groove is processed in the peripheral circuit region using the resist pattern as a mask.

  However, when the memory cell array and the peripheral circuit wiring grooves are formed simultaneously in the damascene process, the depth of the wiring grooves is the same in both. Therefore, the requirement in the memory cell array region that a shallow wiring groove is desirable for facilitating embedding of a metal material and the like and the requirement in a peripheral circuit region that a deep wiring groove is desirable for reducing wiring resistance are compatible. It was difficult.

Japanese Patent Application Laid-Open No. 7-263677

  In view of the above-described problems, the present invention has an object to optimize the depth of the wiring trench between the memory cell array region (side wall transfer process portion) and the peripheral circuit region (portion where the side wall transfer process is not performed). To do.

  The method for manufacturing a semiconductor device of one embodiment of the present invention is characterized by the following points. Forming a film to be processed on a semiconductor substrate; forming a core material film on the film to be processed; forming a resist pattern on the core material film in a first region by a photolithography process; It has. Further, a step of processing the core material film using the resist pattern as a mask, a step of forming a sidewall film having an etching selectivity with respect to a film to be processed on the core material film, and an anisotropic etching step of the sidewall film A step of selectively removing the core material film from the side wall film, and an insulating film on the side wall film and the work film in the first region from the surface of the work film. Forming the insulating film on the processed film in a second region different from the first region so as to have a second film thickness from the surface of the processed film; It has. Further, a process of forming a resist pattern by a photolithography process in the second region, and processing the insulating film and the film to be processed using the sidewall film in the first region and the resist pattern in the second region as a mask. And forming a wiring groove in the film to be processed.

1 is an overall view of a NAND flash memory according to an embodiment of the present invention. 1 is a plan view of a NAND flash memory according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a NAND flash memory according to an embodiment of the present invention, (a) a cross-sectional view taken along the line AA in FIG. 2 and viewed in the direction of the arrow; FIG. FIG. 3A is a process cross-sectional view of the NAND flash memory according to the embodiment of the present invention (part 1), (a) a cross-sectional view taken along the line A-A in FIG. 2 and viewed in the direction of the arrow; It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 7 is a process cross-sectional view (part 2) of the NAND flash memory according to the embodiment of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. 2 and viewed in the direction of the arrow; It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 6 is a process cross-sectional view (part 3) of the NAND flash memory according to the embodiment of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 8 is a process cross-sectional view (part 4) of the NAND flash memory according to the embodiment of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 7 is a process cross-sectional view (No. 5) of the NAND flash memory according to the embodiment of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 8 is a process cross-sectional view (No. 6) of the NAND flash memory according to the comparative example of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 8 is a process cross-sectional view (No. 7) of the NAND flash memory according to the embodiment of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 11 is a process cross-sectional view (No. 8) of the NAND flash memory according to the embodiment of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 11 is a process cross-sectional view (No. 9) of the NAND flash memory according to the embodiment of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 7 is a process cross-sectional view (part 1) of the NAND flash memory according to the comparative example of the present invention, (a) a cross-sectional view taken along the line A-A in FIG. 2 and viewed in the direction of the arrow; It is sectional drawing cut | disconnected along BB and looked at the arrow direction. FIG. 7 is a process cross-sectional view (part 2) of the NAND flash memory according to the comparative example of the present invention, (a) a cross-sectional view taken along the line AA in FIG. 2 and viewed in the direction of the arrow; It is sectional drawing cut | disconnected along BB and looked at the arrow direction.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is an overall view of a semiconductor device (for example, a NAND flash memory) according to an embodiment of the present invention. The NAND flash memory 200 according to this embodiment includes a memory cell array region 201 and a peripheral circuit region 202.

  In the memory cell array region 201, an L / S (Line and Space) having a width equal to or smaller than the resolution limit of lithography is formed by using a sidewall transfer process as a mask. In the peripheral circuit region 202, a wiring pattern using a photoresist as a mask is formed.

  FIG. 2 is a plan view of the NAND flash memory according to the embodiment of the present invention. 2A shows a plan view of the memory cell array region 201, and FIG. 2B shows a plan view of the peripheral circuit region 202. FIG. In the memory cell array region shown in FIG. 2A, a metal wiring material 20 (for example, Cu) is formed in an L / S of a narrow groove formed in, for example, a TEOS (Tetraethoxysilane) film 10 that is an interlayer insulating film. ) Is embedded. In the peripheral circuit region shown in FIG. 2B, the metal wiring material 20 is embedded in the groove formed in the interlayer insulating film 10.

  FIG. 3 is a cross-sectional view of the NAND flash memory according to the embodiment of the present invention. 3A is a cross-sectional view taken along the line AA in FIG. 2A and viewed in the direction of the arrow, and FIG. 3B is cut along the line BB in FIG. It is sectional drawing seen in the arrow direction. When the wiring trench is formed by the damascene process, the memory cell array region 201 is shallower than the wiring trench 17 in the peripheral circuit region 202 as described above in order to facilitate the embedding of the metal wiring material into the narrow wiring trench. A wiring groove 16 is formed.

  4 to 9 are process cross-sectional views of the NAND flash memory according to the embodiment of the present invention. 4 (a) to 9 (a) are cross-sectional views taken along the line AA in FIG. 2 (a) and viewed in the direction of the arrows, and FIGS. 4 (b) to 9 (b) are diagrams. Process sectional drawing cut | disconnected along BB of 2 (b) and looked at the arrow direction is represented.

  First, a TEOS film 10 serving as an interlayer insulating film and, for example, a SiN film 11 serving as a core material (hard mask) for a sidewall transfer process are formed on the semiconductor substrate 101. Next, as shown in FIG. 4A, in the memory cell array region, a photoresist pattern having a pitch twice the wiring width (F) of the memory cell array is formed by photolithography. As shown in FIG. 4B, a photoresist pattern is not formed in the peripheral circuit portion. Note that, in this step and the subsequent photolithography steps, a multi-layered photoresist having a multiple-layer resist structure may be used as the photoresist.

  As shown in FIG. 5A, in the memory cell array region, the SiN film 11 is processed by anisotropic etching (for example, RIE (Reactive Ion Etching)) using a photoresist as a mask. Subsequently, a slimming process is performed by isotropic etching, and the width of the SiN film 11 is reduced to F. As shown in FIG. 5B, the SiN film 11 in the peripheral circuit region is removed by RIE.

  Next, as shown in FIG. 6A, for example, an amorphous silicon film 12 serving as a mask for the sidewall transfer process is formed with a film thickness of F on the interlayer insulating film 10 and the SiN film 11. As shown in FIG. 6B, an amorphous silicon film 12 is formed with a film thickness of F in the peripheral circuit region.

  Next, as shown in FIG. 7A, the amorphous silicon film 12 is processed by anisotropic etching to form sidewalls that serve as a mask for subsequent etching. The core SiN film 11 is removed by wet etching such as phosphoric acid. In the memory cell array region, an amorphous silicon film 12 is formed with F line and space. As shown in FIG. 7B, the amorphous silicon film 12 is removed by anisotropic etching in the peripheral circuit region.

  Next, as shown in FIGS. 8A and 8B, a coating film such as an SOG (Spin on Glass) film 13 is formed on the interlayer insulating film 10 and the amorphous silicon film 12. In the memory cell array region, since the walls are formed by the volume of the amorphous silicon film 12 having the sidewall pattern and the amorphous silicon films 12 in the memory cell region, the SOG film 13 is not flown between the amorphous silicon films 12. It stays and is formed thick (film thickness 8A). On the other hand, in the peripheral circuit region, since the amorphous silicon film 12 does not exist, the SOG film 13 flows easily and is formed thinner (film thickness 8B) than the SOG film 13 in the memory cell region.

  Next, as shown in FIG. 9B, in the peripheral circuit region, a photoresist is formed on the SOG film 13, and a photoresist pattern is formed so that the space becomes a wiring pattern of the peripheral circuit by a photolithography process. 15 is formed. At this time, as shown in FIG. 9A, no photoresist pattern is formed in the memory cell array region.

  Next, the SOG film 13 and the interlayer insulating film 10 are etched by the RIE process using the amorphous silicon film 12 as a mask in the memory cell array region and the photoresist pattern 15 as a mask in the peripheral circuit region.

  As shown in FIGS. 10A and 10B, since the SOG film is formed thick in the memory cell region (film thickness 8A) and thin in the peripheral region (film thickness 8B), the SOG film is formed in the memory cell region. While 13 is being etched, the interlayer insulating film 10 is etched in the peripheral circuit region.

  Further, as shown in FIGS. 11A and 11B, even when the interlayer insulating film 10 is etched in the memory cell array region, a groove deeper than the memory cell array region is formed in the interlayer insulating film 10 in the peripheral circuit region. Has been.

  Eventually, as shown in FIGS. 12A and 12B, the depth of the wiring trench 17 formed in the peripheral circuit region is larger than the depth of the wiring trench 16 formed in the memory cell array region. .

  After removing the photoresist 15, the SOG film 13, and the amorphous silicon film 12, respectively, a metal wiring material 20 is formed in the wiring trench and on the surface of the interlayer insulating film, and planarized by CMP, as shown in FIG. And the metal wiring of (b) is formed.

  13 to 14 are process cross-sectional views of a comparative example. 13 (a) to 14 (a) are cross-sectional views taken along the line AA in FIG. 2 (a) and viewed in the direction of the arrows, and FIGS. 13 (b) to 14 (b) are diagrams. Process sectional drawing cut | disconnected along BB of 2 (b) and looked at the arrow direction is shown. Until the amorphous silicon film 12 is formed in the memory cell region with F line and space (corresponding to FIG. 7), it is the same as in the embodiment of the present invention.

  In the comparative example, as shown in FIGS. 13A and 13B, a photoresist is formed on the amorphous silicon film 12 without forming the SOG film 13. Subsequently, a photoresist pattern 15 is formed by a photolithography process so that the space becomes a wiring pattern of the peripheral circuit. At this time, the photoresist pattern 15 is not formed in the memory cell region.

  Next, as shown in FIGS. 14A and 14B, the interlayer insulating film 10 is formed by an RIE process using the amorphous silicon film 12 as a mask in the memory cell array region and the photoresist pattern 15 as a mask in the peripheral circuit region. Etched. Therefore, wiring grooves having the same depth are formed in the memory cell array region and the peripheral circuit region.

  As described above, according to the embodiment of the present invention, since the SOG films 13 having different film thicknesses are formed in the memory cell region and the peripheral circuit region, the depth of the wiring groove in the peripheral circuit region is set to the memory cell region. It is possible to process deeper than the depth of the wiring groove. Thereby, it is possible to reduce the wiring resistance in the peripheral circuit region while ensuring the embedding property of the wiring metal layer in the memory cell region. Moreover, since the embodiment of the present invention only adds an SOG film, an increase in process cost can be suppressed.

100 Semiconductor substrate 10 Interlayer insulation film 11 Core material film (hard mask) of sidewall transfer process
12 Sidewall film 13 in sidewall transfer process 13 Groove depth adjusting film 15 Photoresist 20 Metal material for wiring 200 NAND flash memory 201 Memory cell area 202 Peripheral circuit area

Claims (5)

Forming a film to be processed on a semiconductor substrate;
Forming a core material film on the work film;
Forming a resist pattern by a photolithography process on the core material film in the first region;
Processing the core material film using the resist pattern as a mask;
Forming a sidewall film having an etching selectivity with the film to be processed on the core material film;
Processing the sidewall film by an anisotropic etching process;
Selectively removing the core film from the sidewall film;
An insulating film is formed on the sidewall film and the film to be processed in the first region so as to have a first film thickness from the surface of the film to be processed, and the workpiece in a second region different from the first region Forming the insulating film on the film so as to have a second film thickness from the surface of the film to be processed;
Forming a resist pattern by a photolithography process in the second region;
Processing the insulating film and the film to be processed using the sidewall film in the first region and the resist pattern in the second region as a mask, and forming a wiring groove in the film to be processed;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first film thickness of the insulating film is thicker than the second film thickness.   3. The semiconductor according to claim 1, wherein the depth of the wiring groove from the surface of the film to be processed is such that the depth in the second region is deeper than the depth in the first region. Device manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is an SOG film.   5. The method of manufacturing a semiconductor device according to claim 1, wherein a width of the wiring groove in the first region is smaller than a width of the wiring groove in the second region. 6.

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