JP2009129522A - Memory control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control circuit which prevents an unstable state of a data strobe signal from being propagated to an internal circuit, while using an existing circuit as much as possible. <P>SOLUTION: The memory control circuit has a first delay circuit 220 delaying an input data strobe signal by first delay quantity, a second delay circuit 230 delaying an input data strobe signal by second delay quantity larger than the first delay quantity, an AND circuit 240 in which the first delay signal delayed by the first delay circuit 220 and the second delay signal delayed by the second delay circuit 230 are input and third delay signal DQS 3 including a rise edge being synchronous with a trailing edge of the data strobe signal is generated, a flip-flop 260 taking-in first data D1 input in response to the first delay signal, and a flip-flop 280 taking-in second data D2 input in response to the third delay signal DQS 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a memory control circuit, and more particularly to a memory control circuit that controls reading / writing of data from / to a memory using a data strobe signal.

  In electronic devices such as personal computers and navigation devices, SDRAM (Synchronous Dynamic Random Access Memory) is used as a memory that reads and writes data at high speed and holds a large amount of data. The SDRAM can read or write data in synchronization with a clock signal, and can operate at high speed by increasing the clock frequency. The SDRAM also has a burst mode in which data can be read or written continuously.

  DDR (Double Data Rate) SDRAM is a further increase in the speed of SDRAM. Since DDR SDRAM reads and writes data in response to both the rising and falling edges of the clock signal, its operation is twice that of SDRAM.

  FIG. 4 is a diagram illustrating a connection example of the DDRSDAM 10 and the memory control circuit 20. The DDR SDRAM 10 and the memory control circuit 20 include a data bus 30 that transmits and receives data (DQ), a DQS signal line 32 that transmits and receives a data strobe signal DQS (hereinafter referred to as a DQS signal), a clock signal line 34 that transmits a clock signal, They are connected by an address signal bus 36 for transmitting an address signal. Further, the memory control circuit 20 supplies a command signal for instructing reading (reading) or writing (writing) to the DDR SDRAM 10.

  FIG. 5A is a timing chart when reading data from the memory (reading), and FIG. 5B is a timing chart when writing data into the memory (writing). When reading data, the memory control circuit 20 outputs a read command and an address signal, and in response, the DDR SDRAM 10 outputs the DQS signal and the addressed data to the memory control circuit 10. At this time, since the DQS signal and the data are output in the same phase, the memory control circuit 20 delays the DQS signal and captures the data in a flip-flop or latch in synchronization with the rising edge and falling edge of the DQS signal.

  When writing data, the memory control circuit 20 outputs a write command, an address signal, a DQS signal, and data DQ to the DDR SDRAM 10. At this time, the DQS signal is output after being delayed from the data. The DDR SDRAM 10 writes data to the memory element in synchronization with the rising edge and falling edge of the DQS signal.

  The DQS signal is bi-directionally communicated according to data reading / writing, and is in a high impedance state when there is no access to the memory. In order to guarantee the data read / write operation by the DQS signal, the DQS signal includes a low level period P1 called a preamble at the start of access to the memory and a low level period P2 called a postamble at the end. Patent Document 1 discloses a memory control circuit that controls reading / writing of data to / from such a DDR SDRAM.

JP 2006-40318 A

  As shown in FIG. 6A, the circuit for fetching data of the memory control circuit includes an input buffer 40 for inputting data, a delay circuit 44 for delaying a DQS signal input from the input buffer 42, and a delayed DQS. An inverter 46 that inverts the signal, a flip-flop 48 that captures data in response to the rising edge of the DQS signal delayed by the delay circuit 44, and a flip-flop 50 that captures data in response to the rising edge of the inverted DQS signal. , 52.

  FIG. 6B shows a timing chart of each part. In response to the read command from the memory control circuit, the DDR SDRAM 10 sets the DQS signal to the low level only for the period of the preamble P1, and then outputs the DQS signal and data (DQ) in the same phase. The memory control circuit inputs data and a DQS signal in the input buffers 40 and 42. The input buffer 42 detects the high level and the low level of the DQS signal with a predetermined threshold value, and outputs a waveform-shaped DQS signal. The delay circuit 44 delays the DQS signal from the input buffer 42 by ¼ phase, so that the rising and falling edges of the DQS signal coincide with the center of the data period. The flip-flop 48 captures the data D1 in response to the rising edge of the delayed DQS signal, and the flip-flop 50 is the rising edge of the inverted DQS signal (equal to the timing of the falling edge of the delayed DQS signal). The data D2 is captured in response to.

  By the way, the DQS signal is in a high impedance state when the memory is not accessed, transitions from a high impedance to a low level at the start of access to the memory, and transitions from a low level to a high impedance state at the end of the access. To do. When the DQS signal is in a high impedance state, the DQS signal is pulled up to a value close to the power supply voltage Vdd, but this state is indefinite, and the DQS signal is likely to fluctuate due to overshoot or noise, especially at the transition after postamble. For example, if an undesired overshoot S occurs after the postamble P2, an undesired waveform S1 is generated in the delayed DQS signal, which is input to the flip-flops 48, 50, 52, and erroneous data is captured. There is a problem that it is propagated to the internal circuit.

  In order to solve this problem, Patent Document 1 provides two types of delay circuits that delay the DQS signal, and captures data in a flip-flop in response to the rising edge of the DQS signal output from one of the delay circuits. The DQS signal (enable signal) output from the other delay circuit is connected to the enable terminal of the flip-flop that captures data in response to the falling edge of the DQS signal. However, the solution according to Patent Document 1 requires a flip-flop whose operation is controlled by an enable terminal, and cannot use an existing flip-flop or latch.

  Some DDR SDRAMs output not only single-ended DQS signals but also differential DQS signals, and the memory control circuit is required to cope with such differential DQS signals.

  An object of the present invention is to solve such a conventional problem and to provide a memory control circuit that prevents an indefinite state of a data strobe signal from being propagated to an internal circuit while using an existing circuit as much as possible. And

  The memory control circuit according to the present invention controls writing of data into the memory or reading of data from the memory using the data strobe signal, and delays the input data strobe signal by a first delay amount. A first delay circuit that delays the input data strobe signal by a second delay amount larger than the first delay amount, and a first delay circuit that is delayed by the first delay circuit. A third delay signal having a falling edge or a rising edge synchronized with a rising edge or a falling edge of the input data strobe signal based on the delay signal and the second delay signal delayed by the second delay circuit; A generation circuit for generating, a first circuit for capturing first data input in response to the first delay signal, and the third delay signal In response and a second circuit for taking a second data input.

  Preferably, the generation circuit includes an AND circuit that inputs the first delay signal and the second delay signal. Preferably, the first delay amount has a phase difference of 1/4 with respect to the input data strobe signal, and the second delay amount has a phase difference of 1 with respect to the input data strobe signal. / 4 to 1/2 or less. Preferably, the first circuit captures the first data in response to the rising edge or falling edge of the first delay signal, and the second circuit rises or falls the third delay signal. The second data is captured in response to the edge. Preferably, the memory control circuit further includes a differential circuit that inputs a differential data strobe signal and outputs the input data strobe signal. The first and second circuits are, for example, flip-flops or latches.

  According to the present invention, the data strobe signal is delayed by different delay amounts, and a third delay signal having a rising edge or a falling edge synchronized with the rising edge or the falling edge of the data strobe signal input from both is generated. By taking in the data, even if the data strobe signal becomes indefinite in the high impedance state, it is possible to prevent a malfunction caused by the data strobe signal.

  The best mode for carrying out the present invention will be described below in detail with reference to the drawings. Here, DDR SDRAM is used as an example, and this is referred to as a memory.

  FIG. 1 is a diagram illustrating a circuit configuration of a data capturing unit of a memory control circuit according to an embodiment of the present invention. Memory control circuit 100 includes a DQS circuit region 110 operated by a clock of a DQS signal, and an internal circuit region 120 operated by an internal clock HCLK.

  The DQS circuit area 110 delays the DQS signal received by the input buffer 200 receiving the data from the memory, the input buffer 210 receiving the DQS signal, and the input buffer 210 by a first delay amount when the data is read from the memory. The first delay circuit 220 that outputs the delayed signal DQS1 and the DQS signal received by the input buffer 210 are delayed by a second delay amount that is larger than the first delay amount, and the second delay signal DQS2 is output. The second delay circuit 230, the AND circuit 240 that inputs the first and second delay signals, the inverter 250 that outputs the third delay signal DQS 3 obtained by inverting the output of the AND circuit 240, and the input buffer 200. Flip that captures the received data in response to the rising edge of the first delay signal DQS1 The flip-flop 260, the flip-flop 270 that captures the output of the flip-flop 260 in response to the rising edge of the third delay signal DQS3, and the data received by the input buffer 200 in response to the rising edge of the third delay signal DQS3. And a flip-flop 280 to be captured.

  The internal circuit area 120 includes a flip-flop 300 that captures the output from the flip-flop 270 at the rising edge of the internal clock HCLK, and a flip-flop 310 that captures the output of the flip-flop 280 at the falling edge of the internal clock HCLK.

  Next, the operation of each unit will be described with reference to the timing chart shown in FIG. When reading data from the memory, that is, at the time of reading, the memory control circuit transmits a read command to the memory. In response to this, the memory shifts the DQS signal in the high impedance state at time t1 to the low-level preamble P1, and starts outputting the DQS signal and data from time t2. At this time, the DQS signal and the data are in phase.

  As shown in FIGS. 2A and 2B, the memory control circuit 100 inputs data and a DQS signal to the input buffers 200 and 210. The DQS signal is compared with the threshold voltage in the input buffer 210, and becomes a high level (VIH) or low level (VIL) pulse waveform as shown in FIG.

  Next, the DQS signal is input to the first delay circuit 220, and is delayed by a first delay amount td1 from time t2, that is, from the rising edge of the DQS signal, as shown in FIG. Preferably, the first delay amount td1 is a ¼ phase of the DQS signal. The first delay circuit 220 outputs the first delay signal DSQ1 delayed by the first delay amount to the AND circuit 240 and the flip-flop 260.

  Further, the DQS signal is delayed from the time t2 by the second delay amount td2 as shown in FIG. Preferably, the second delay amount td2 is greater than ¼ phase of the DQS signal and less than or equal to ½ phase. The second delay circuit 230 outputs the second delay signal DQS2 delayed by the second delay amount to the other input of the AND circuit 240.

  The AND circuit 240 inputs the first and second delay signals DQS 1 and DQS 2, and outputs the logical function to the inverter 250. The inverter 250 inverts this and outputs a third delay signal DQS3 as shown in FIG. The falling edge of the third delay signal DQS3 is equal to the rising edge of the second delay signal DQS2, and the rising edge of the third delay signal DQS3 is equal to the falling edge of the first delay signal DQS. Further, the low level period td3 from the falling edge to the rising edge of the third delay signal DQS3 is td3 = td2−td1.

  At time t3, the flip-flop 260 captures the data D1 held in the input buffer 200 in response to the rising edge of the first delay signal DQS1 delayed by the first delay circuit.

  At time t4, the flip-flop 280 takes in the data D2 held in the input buffer 200 in response to the rising edge of the third delay signal DQS3. At the same timing, the flip-flop 270 takes in the data output from the flip-flop 260.

  At time t5, the flip-flop 260 takes in the next transferred data D3 in response to the rising edge of the first delay signal DQS1.

  At time t6, the memory causes the DQS signal to transition to the low-level postamble P2 to end the read operation, and at time t7, the memory causes the DQS signal to transition from the low level to the high impedance state. At this time, if noise or overshoot S occurs in the DQS signal, an undesired pulse waveform S1 is formed in the input buffer 210 (see FIG. 2C). As a result, an undesired pulse waveform S1 is also propagated to the first and second delay signals DQS1 and DQS2 delayed by the first and second delay circuits 220 and 230 (FIGS. 2D and 2E). )). However, the first and second delay signals DQS1, DQS2 are gated by the AND circuit 240, and the unwanted pulse waveform S1 is removed. Therefore, the undesired pulse waveform S1 is not propagated to the third delay signal DQS3, and the flip-flops 270 and 280 are prevented from erroneously capturing data in an indefinite state after the postamble. As a result, the memory control circuit 100 can accurately read data from the memory.

  In the above example, the output of the AND circuit is inverted by the inverter 250 to generate the third delay signal DQS3. However, the output of the AND circuit 240 may be the third delay signal DQS3. In this case, the flip-flops 270 and 280 may capture data in response to the falling edge of the third delay signal DQS. Furthermore, the flip-flops 260, 270, and 280 may take in data in response to either the rising edge or the falling edge, and may use a latch instead of the flip-flop. The delay circuits 220 and 230 can be configured using a DLL or the like.

  Next, a second embodiment of the present invention will be described. FIG. 3 is a diagram showing the configuration of the DQS circuit area of the memory control circuit according to the second embodiment of the present invention. The same components as those in FIG. In the second embodiment, a differential signal is used as the DQS signal that is bidirectionally communicated between the DDR SDRAM and the memory control circuit. The DQS differential signal enables data transfer at a higher speed, and includes a DQS signal and a / DQS signal obtained by inverting the DQS signal.

  As shown in FIG. 3, the DQS circuit area 110 includes a buffer 210 for inputting a DQS signal, an input buffer 212 for inputting a DQS signal obtained by inverting the DQS signal, and a DQS differential signal received by the input buffers 210 and 212. A differential circuit 290 for generating a DQS signal from the DQS signal is included. Note that the input buffers 210 and 212 may include the differential circuit 290. The differential circuit 290 outputs the DQS signal to the first delay circuit 220 and the second delay circuit 230, and the subsequent operation is the rising edge of the delayed DQS signal as in the first embodiment. Data is taken in synchronization with the falling edge. The memory control circuit according to the second embodiment can correspond to a memory that outputs a DQS differential signal.

The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments according to the present invention, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation / change is possible. In the above example,
Although the DDR SDRAM is used as the memory, a synchronous SRAM or flash memory may be used in addition to this.

It is a figure which shows the internal circuit of the data acquisition part of the memory control circuit based on the Example of this invention. FIG. 2 is a diagram showing a timing chart of each part of the memory control circuit shown in FIG. 1. It is a figure which shows the internal circuit of the data taking-in part of the memory control circuit based on 2nd Example of this invention. It is a figure which shows the example of a connection of DDR SDRAM and a memory control circuit. FIGS. 5A and 5B are timing charts for explaining a data read / write operation of a DDR SDRAM. FIG. 5A shows a read time and FIG. 5B shows a write time. FIG. 6A shows a configuration of a conventional memory control circuit, and FIG. 6B is a timing chart thereof.

Explanation of symbols

100: Memory control circuit 110: DQS circuit area 120: Internal clock area 200, 210: Input buffer 220: First delay circuit 230: Second delay circuit 240: AND circuit 250: Inverters 260, 270, 280, 300, 310: Flip-flop 290: Differential circuit

Claims (5)

A memory control circuit that controls writing of data into a memory or reading of data from a memory using a data strobe signal,
A first delay circuit for delaying the input data strobe signal by a first delay amount;
A second delay circuit for delaying the input data strobe signal by a second delay amount larger than the first delay amount;
Falling in synchronization with the rising or falling edge of the input data strobe signal based on the first delay signal delayed by the first delay circuit and the second delay signal delayed by the second delay circuit A generating circuit for generating a third delayed signal having an edge or a rising edge;
A first circuit for capturing first data input in response to the first delay signal;
A memory control circuit including a second circuit for capturing second data input in response to the third delay signal. The memory control circuit according to claim 1, wherein the generation circuit includes an AND circuit that inputs the first delay signal and the second delay signal. The first delay amount has a phase difference of 1/4 with respect to the input data strobe signal, and the second delay amount has a phase difference of 1 / with respect to the input data strobe signal. The memory control circuit according to claim 1, wherein the memory control circuit is greater than 4 and less than or equal to ½. The first circuit captures the first data in response to a rising edge or a falling edge of the first delay signal, and the second circuit receives a rising edge or a falling edge of the third delay signal. 4. The memory control circuit according to claim 1, wherein the second data is fetched in response. 5. The memory control circuit according to claim 1, further comprising a differential circuit that inputs a differential data strobe signal and outputs the input data strobe signal.

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