JP4099470B2 - Memory controller - Google Patents

Description

  The present invention generally relates to a memory controller, and more particularly to a memory controller that controls a DDR SDRAM specification memory.

  DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is a memory that transfers data at a rate twice that of a clock signal among synchronous DRAMs that input and output signals in synchronization with a clock. Specifically, a data transfer rate that is double the clock frequency is realized by inputting and outputting data at both the positive and negative edges of the clock signal.

  A differential clock composed of a clock signal CLK and an inverted clock signal / CLK is supplied from the memory controller to the DDR SDRAM. The command (address and control signal) is supplied from the memory controller to the memory at the positive edge of the clock signal CLK. Data transfer between the memory controller and the memory is executed in synchronization with the bidirectional data strobe signal DQS. The data strobe signal DQS is output by the data transmission side device simultaneously with the data. The memory controller supplies the data strobe signal DQS during the write operation, and the memory transmits the data strobe signal DQS during the read operation. Access to the memory is performed in a burst format, data reading starts from a selected position, and the programmed number of data is read continuously in the programmed order.

  In the prior art, for example, there is a technique in which a DDR signal is divided into parallel signals and latched by a first delayed DS, latched by a second delayed signal, and supplied to an internal circuit in synchronization with CLK ( Patent Document 1).

  FIG. 1 is a timing chart showing the read specifications of the DDR SDRAM. As shown in FIG. 1, first, a read command Read is input from the memory controller to the memory device in synchronization with the rising edge of the clock signal CLK supplied to the memory. Although not shown, the address signal is input to the memory simultaneously with the read command Read.

  In response to the read command Read, a data strobe signal DQS is output from the memory device, and data d0 to d3 are continuously output in synchronization with the data strobe signal DQS. Because of the double data rate specification, the data d0 to d3 are output at the rate of one data in a half cycle of the data strobe signal DQS. FIG. 1 shows the case where the burst length is 4, and the CAS latency (latency from the read command Read input to the first data read) is two cycles.

  FIG. 2 is a circuit diagram showing an example of a conventional configuration of a read data fetch circuit on the memory controller side. The memory controller (MCU) 10 and the memory (DDRDRAM) 11 are connected by a signal line on a printed circuit board, and a data signal Data, a data strobe signal DQS, clock signals CLK and / CLK, and the like are exchanged.

  The clock signal output circuit unit and read data fetch circuit unit of the memory controller 10 include flip-flops 21 to 27, an output buffer 28, input buffers 29 and 30, inverters 31 and 32, a delay circuit 33, and a selector 34. Among them, the flip-flop 21, the inverter 31, and the output buffer 28 constitute a clock signal output circuit unit.

  FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. Hereinafter, the read data capturing operation will be described with reference to FIGS.

  In FIG. 2, the flip-flop 21 takes in the inverted signal of its output by using the rising edge of the system clock sclk as a trigger, thereby generating a clock signal having a cycle twice that of the system clock sclk. Based on this clock signal, the output buffer 28 supplies the clock signal CLK and the inverted clock signal / CLK to the memory 11. The memory 11 reads data from the memory core circuit in synchronization with the clock signal CLK and the inverted clock signal / CLK, and outputs the data signal Data together with the data strobe signal DQS. This state is shown in FIGS. 3A to 3D. The data signal Data is synchronized with the data strobe signal DQS, and four data of d0 to d3 are burst output.

  In FIG. 2, the data strobe signal DQS output from the memory 11 is received by the input buffer 29 of the memory controller 10. The received data strobe signal DQS is supplied as a signal A from the input buffer 29 via the delay circuit 33 to the flip-flop 23, and from the input buffer 29 to the flip-flop 22 via the delay circuit 33 and the inverter 32. Supplied as Signals A and B are shown in FIGS. 3 (e) and 3 (f).

  The data signal Data sent from the memory 11 is received by the input buffer 30 of the memory controller 10. The reception data signal Data is taken into the flip-flop 23 at the rising edge of the signal A and taken into the flip-flop 22 at the rising edge of the signal B. The signal C fetched by the flip-flop 23 is shown in FIG. 3G, and the signal D fetched by the flip-flop 22 is shown in FIG.

  In this way, data capture at a double rate (double speed of the clock signal CLK) is realized. The delay circuit 33 generates an appropriate timing for delaying the reception data strobe signal DQS and capturing the reception data signal because the data strobe signal DQS and the data signal Data are synchronized with the edges aligned. Is to do. The delay circuit 33 has a delay amount delay1.

  The flip-flops 25 and 24 in FIG. 2 take in the signal C and the signal D in synchronization with the rising edge of the system clock sclk, and output them as a signal E and a signal F, respectively. As a result, the captured data can be synchronized with the system clock sclk inside the control circuit 11. Signals E and F synchronized with the system clock sclk are shown in (j) and (k) of FIG.

The selector 34 shown in FIG. 2 receives the clock signal G obtained by frequency-dividing the system clock sclk by the flip-flop 26, and alternately selects the signal E and the signal F in synchronization with the clock signal G and outputs it as the signal I. Specifically, the signal E is selected and output when the signal G is LOW, and the signal F is selected and output when the signal G is HIGH. The flip-flop 27 takes in the signal I in synchronization with the system clock sclk and outputs a data signal H in synchronization with the system clock sclk. The control signal G for the selector is shown in (l) of FIG. 3, and the data signal H is shown in (m) of FIG.
JP 2003-151271 A

  In FIG. 3M, the last read data d3 does not exist in the data signal H synchronized with the system clock sclk. This is due to a malfunction as described below.

  As shown in FIG. 3 (c), the data strobe signal DQS repeats HIGH and LOW in synchronization with the data signals d0 to d3, and then the data signal d3 is terminated and at the same time the HIGH impedance state (“HiZ”: floating). Status). This is a signal change according to the specification of the DDR SDRAM. When the data strobe signal DQS is in a floating state in this way, the output of the input buffer 29 becomes an indefinite state in which HIGH and LOW are irregularly repeated, and the data stored in the flip-flops 22 and 23 until then is lost. That is, as shown in FIG. 3 (h), the output signal D of the flip-flop 22 changes to an indefinite state in response to the timing when the data strobe signal DQS enters the HIGH impedance state and has been stored until then. The second data signal d3 is destroyed.

  The timing at which the data signal d3 is lost is the same as the timing at which the data d2 stored in the flip-flop 23 shown in FIG. As a result, the data signal d2 is maintained for one cycle of the clock signal CLK, but the data signal d3 is maintained for only half the clock signal CLK.

  For this reason, if the data signal is selected by the selector 34 and then fetched in synchronization with the system clock sclk by the flip-flop 27, the signal selection and fetch operation for the data signal d3 fails. As a result, the data signal d3 disappears in the data signal H synchronized with the system clock sclk shown in (m) of FIG.

  The operation shown in FIG. 3 shows the timing when the data signal d3 is unsuccessfully taken in intentionally, and is not an impossible division of the data signal d3. If the delay time of the delay circuit 33 is set appropriately, the timing can be set so that the data signal d3 can be taken in without any problem. However, in this case, since there is no margin in the delay time of the delay circuit 33 and other operation margins, there are problems such as inconvenience with a low degree of freedom in setting operation conditions, and there is a possibility of malfunction when the operation conditions change. There is.

  In view of the above, an object of the present invention is to provide a memory controller having a margin of operation margin without being affected by a signal indefinite state generated due to a high impedance state of a data strobe signal in the DDR SDRAM specification. To do.

A memory controller according to the present invention is coupled to a receiving end of a data strobe signal and outputs a first timing signal obtained by delaying the data strobe signal, and is coupled to an output of the delay circuit and a receiving end of the data signal. A first flip-flop that captures the data signal in response to the first timing signal; and a signal decision that is coupled to the output of the delay circuit and outputs a second timing signal processed by the first timing signal includes a state maintaining circuit, the second flip-flop that takes in response to the data signal is coupled to the said receiving end of the output and the data signal of the signal determined state maintaining circuit to the second timing signal, said 2 is a signal having the same logical value as the logical sum of the logical inversion of the first timing signal and the signal obtained by delaying the first timing signal. , And the said signal determined state maintaining circuit timing signal of the first is a predetermined period of time from when an undefined state and maintains the determined state of the second timing signal.

  According to at least one embodiment of the present invention, the signal determination state maintaining circuit can maintain the signal determination state of the second timing signal, which is the fetch timing signal of the second flip-flop, to a desired length. As a result, the stored data can be held for a desired time after the data signal is taken into the second flip-flop. The length of the signal determination state of the capture timing signal, and thus the length of the data signal held, is determined by the length of time that the signal determination state maintaining circuit maintains the signal determination state. A stable read data fetching operation can be realized without being greatly affected by the operating conditions. In addition, since there is a sufficient margin for the delay amount of the delay circuit and other operating conditions, the degree of freedom in setting the operating conditions is large and the design is simple.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 4 is a block diagram showing the configuration of the memory controller to which the present invention is applied. The memory controller 40 includes a memory control circuit 41, a clock output circuit unit 42, a command / address output circuit unit 43, a read data fetch circuit unit 44, and a write data output circuit unit 45. The memory controller 40 and the memory (DDRSDRAM) 11 are connected by a signal line on the printed circuit board, and the data signal Data, the data strobe signal DQS, the command / address signal CMD / Add, the clock signals CLK and / CLK and the like are exchanged. Is done.

  The memory 11 conforms to the DDR SDRAM specification, and the command signal and the address signal are supplied from the memory controller 40 to the memory 11 at the positive edge of the clock signal CLK. Data transfer between the memory controller 40 and the memory 11 is executed in synchronization with the bidirectional data strobe signal DQS.

  The data strobe signal DQS is output from the data transmission side device simultaneously with the data. The memory controller 40 supplies the data strobe signal DQS during the write operation, and the memory 11 transmits the data strobe signal DQS during the read operation. . Access to the memory 11 is performed in a burst format, data reading starts from a selected position, and a programmed number of data is read continuously in a programmed order. Specifically, the read operation is executed according to the read operation specification of the DDR SDRAM shown in FIG.

  The memory control circuit 41 controls the clock output circuit unit 42, the command / address output circuit unit 43, the read data capture circuit unit 44, and the write data output circuit unit 45, and exchanges signals with the memory 11. Specifically, the command / address output circuit unit 43 supplies the command signal CMD and the address signal Add to the memory 11. A read operation and a write operation are designated by the command signal CMD, and a read address and a write address are designated by the address signal Add.

  The clock output circuit unit 42 generates a clock signal CLK and an inverted clock signal / CLK based on the system clock sclk, and supplies the generated clock signal CLK to the memory 11. The memory 11 performs an internal operation in synchronization with these clock signals CLK and / CLK. In the case of the write operation, the write data output circuit unit 45 outputs the write data signal Data together with the data strobe signal DQS, and the memory 11 writes the write data to the designated address. In the read operation, the memory 11 outputs the read data signal Data together with the data strobe signal DQS, and the read data capture circuit unit 44 captures the read data in synchronization with the data strobe signal DQS. Each circuit portion of the memory controller 40 operates in synchronization with a system clock sclk supplied from the outside.

  FIG. 5 is a circuit diagram showing an embodiment of the clock output circuit section 42 and the read data fetch circuit section 44 of the memory controller 40. In FIG. 5, the same elements as those of FIG. 2 are referred to by the same numerals.

  The clock output circuit unit 42 includes a flip-flop 21, an inverter 31, and an output buffer 28. The read data fetch circuit unit 44 includes flip-flops 22 to 27, input buffers 29 and 30, an inverter 32, a delay circuit 33, a selector 34, and a signal determination state maintaining circuit 50. The signal determination state maintaining circuit 50 includes a delay circuit 51, an inverter 52, and an OR gate 53. As will be described later, the signal determination state maintaining circuit 50 controls the signal so that the signal determination state of the fetch timing signal B of the flip-flop 22 is maintained for a desired time.

  Note that the delay circuit 33 and the delay circuit 51 may be configured by simple delay buffers. Alternatively, the delay circuit 33 and the delay circuit 51 may be configured by a programmable delay circuit or a DLL (Delay Locked Loop) circuit, as will be described in a later embodiment.

  FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. The read data fetching operation according to the present invention will be described below with reference to FIGS.

  In FIG. 5, the flip-flop 21 takes in the inverted signal of its output by using the rising edge of the system clock sclk as a trigger, thereby generating a clock signal having a cycle twice that of the system clock sclk. Based on this clock signal, the output buffer 28 supplies the clock signal CLK and the inverted clock signal / CLK to the memory 11. The memory 11 reads data from the memory core circuit in synchronization with the clock signal CLK and the inverted clock signal / CLK, and outputs the data signal Data together with the data strobe signal DQS. This is shown in FIGS. 6A to 6D. The data signal Data is synchronized with the data strobe signal DQS, and four data of d0 to d3 are burst output.

  In FIG. 5, the data strobe signal DQS output from the memory 11 is received by the input buffer 29 of the memory controller 10. The received data strobe signal DQS is supplied from the input buffer 29 to the flip-flop 23 via the delay circuit 33 as the timing signal A, and from the input buffer 29 to the delay circuit 33, the signal determination state maintaining circuit 50, and the inverter 32 is supplied to the flip-flop 22 through 32 and supplied as a timing signal B. The capture timing signal A and the capture timing signal B are shown in (e) and (h) of FIG.

  The signal determination state maintaining circuit 50 first delays the output of the delay circuit 33 (capture timing signal A) by the delay circuit 51 by a predetermined delay time (delay 2). The delayed signal A ′ is shown in FIG. This signal A ′ is inverted by the inverter 52 to generate a signal B ′ shown in FIG. In these signals A ′ and B ′, as shown in (f) and (g) of FIG. 6, the signal determination state is extended as compared with the signal A by a length equal to the delay time delay2. .

  As a result, also in the capture timing signal B shown in (h) of FIG. 6, the signal determination state is extended as compared with the signal A by a length equal to the delay time delay2. In other words, the signal indeterminate state is masked by a length equal to the delay time delay2. In this way, in the present invention, the signal fixed state of the capture timing signal B can be maintained at a desired length. As a result, as described below, the stored data can be held for a desired time after the reception data signal d3 is taken into the flip-flop 22.

  The data signal Data sent from the memory 11 is received by the input buffer 30 of the memory controller 10. The reception data signal Data is taken into the flip-flop 23 at the rising edge of the signal A and taken into the flip-flop 22 at the rising edge of the signal B. The signal C taken into the flip-flop 23 is shown in (i) of FIG. 6, and the signal D taken into the flip-flop 22 is shown in (j) of FIG.

  In this way, data capture at a double rate (double speed of the clock signal CLK) is realized. In the signal D shown in (j) of FIG. 6, the read data d3 is maintained while the signal determination state of the capture timing signal B continues. Therefore, unlike the operation waveform in the prior art shown in FIG. 3, the read data d3 is not lost simultaneously with the read data d2.

  The flip-flops 25 and 24 in FIG. 5 take in the signal C and the signal D in synchronization with the rising edge of the system clock sclk, and output them as the signal E and the signal F, respectively. As a result, the captured data can be synchronized with the system clock sclk inside the control circuit 11. Signals E and F synchronized with the system clock sclk are shown in (l) and (m) of FIG. In the signal F shown in (m) of FIG. 6, unlike the operation waveform in the case of the prior art shown in (k) of FIG. 3, the read data d3 is not lost simultaneously with the read data d2, and only for a desired time. Data is maintained.

  The selector 34 shown in FIG. 5 receives a clock signal G obtained by frequency-dividing the system clock sclk by the flip-flop 26, and alternately selects the signal E and the signal F in synchronization with the clock signal G and outputs it as the signal I. Specifically, the signal E is selected and output when the signal G is LOW, and the signal F is selected and output when the signal G is HIGH. The flip-flop 27 takes in the signal I in synchronization with the system clock sclk and outputs a data signal H in synchronization with the system clock sclk. The selector control signal G is shown in FIG. 6 (n), and the data signal H is shown in FIG. 6 (o).

  Specifically, the signal E shown in (l) of FIG. 3 is taken in at the timings T1 and T3 by the rising edge of the system clock sclk and becomes d0 and d2 of the data signal H shown in (o) of FIG. Further, the signal F shown in (m) of FIG. 3 is taken in at the timings T2 and T4 by the rising edge of the system clock sclk and becomes d1 and d3 of the data signal H shown in (o) of FIG. At this time, since the read data d3 is maintained for an appropriate time in the signal F, the read data d3 can be taken into the flip-flop 27 at the timing T4.

  As described above, in the data signal H after being synchronized with the system clock sclk, all the read data d0 to d3 exist. Further, since the delay amount delay2 of the delay circuit 51 of the signal determination state maintaining circuit 50 determines the length of the signal determination state of the capture timing signal B, and thus the length of the read data d3 of the signal F, the delay circuit Stable operation can be realized without being affected so much by the delay amount delay 1 of 33 and other operating conditions. In addition, since there is a sufficient margin for the delay amount of the delay circuit 33 and other operating conditions, the degree of freedom in setting the operating conditions is large and the design is simple.

  FIG. 7 is a circuit diagram showing an example of the circuit configuration of the delay circuit 51. A similar circuit configuration may be used for the delay circuit 33. As can be seen from the above description, the delay amount of the delay circuit 51 is an important parameter that determines the success or failure of the read data fetch operation of the memory controller 40 and is preferably set to a desired value.

  The delay circuit 51 of FIG. 7 includes delay buffers 61 to 64 and selectors 65 to 68. The selectors 65 to 68 are controlled in selection operation by the control signals c1 to c3. For example, when the control signal is 0, the input of the upper input terminal is selected, and when the control signal is 1, the input of the lower input terminal is selected. Select. Therefore, for example, when the control signals c1 to c3 are all 0, the input signal in passes through the selectors 65 to 68 without passing through the delay buffers 61 to 64 and becomes the output signal out. In this case, if the delay of the selector is ignored, the amount of delay is zero. When the control signals c1 to c3 are all 1, the input signal in passes through the delay buffers 61 to 64 and becomes the output signal out. In this case, the delay amount is the maximum delay amount that can be set by the delay circuit 51.

  As shown in FIG. 7, each of the delay buffers 61 to 64 has a delay amount of unit length, a delay amount that is twice the unit length, a delay amount that is four times the unit length, and eight times the unit length. Has a delay amount. Therefore, for example, if the values of the control signals c1 to c3 are stored in a 4-bit register, a delay amount proportional to the value is delayed according to the binary value (0 to 15) stored in the register. It can be realized by the circuit 51. For example, the memory controller 40 may calculate the cycle time by a program and set an appropriate delay amount. In this way, a programmable delay circuit can be provided.

  FIG. 8 is a circuit diagram showing another example of the circuit configuration of the delay circuit 51. A similar circuit configuration may be used for the delay circuit 33. The delay amount of the delay circuit 51 in FIG. 7 is a predetermined value set by a register setting value or the like. Even if the operating frequency of the memory controller 40 changes, a fixed delay value is obtained unless the register setting value is changed. It remains. On the other hand, in the configuration shown in FIG. 8, the delay amount can be set dynamically according to the operating frequency.

  The delay circuit 51 of FIG. 8 includes voltage control delay elements 71 to 78, a voltage control signal generator 81, and a phase detector 82. The voltage control delay elements 71 to 78 change in signal delay amount according to the potential level of the voltage control signal VC supplied from the voltage control signal generator 81. The voltage controlled delay elements 71 to 74 are connected in series to form one row of delay element rows, and the voltage controlled delay elements 75 to 78 are connected in series to form another row of delay element rows.

  The delay element array formed by the voltage control delay elements 75 to 78 receives the system clock sclk as an input, delays it, and outputs a delay clock sclk_d. The phase detector 82 detects the phase difference between the system clock sclk and the delay clock sclk_d and supplies a signal corresponding to the detected phase difference to the voltage control signal generator 81.

  The voltage control signal generator 81 controls the delay amount of the voltage control delay elements 75 to 78 by adjusting the potential level of the voltage control signal VC according to the signal from the phase detector 82. At this time, the voltage control signal generator 81 adjusts the potential level of the voltage control signal VC so that the phase difference detected by the phase detector 82 becomes zero. Specifically, when the phase of the delay clock sclk_d is earlier than the phase of the system clock sclk, the voltage control signal VC is changed so that the delay amounts of the voltage control delay elements 75 to 78 are increased. When the phase of the delay clock sclk_d is later than the phase of the system clock sclk, the voltage control signal VC is changed so that the delay amount of the voltage control delay elements 75 to 78 becomes small. As a result, a DLL (delay locked loop) circuit is formed.

  With the above control operation, the delay amounts of the voltage control delay elements 75 to 78 are adjusted so that the phase of the delay clock sclk_d matches the phase of the system clock sclk. That is, the delay of the voltage control delay elements 75 to 78 is the length of one cycle of the system clock sclk. Here, the voltage control delay elements 75 to 78 have the same configuration, and the delay amount of each element is the same. The system clock sclk, the outputs ck1 to ck3 of the voltage control delay elements 75 to 77, and the output sclk_d of the voltage control delay element 78 are shown in (a) to (e) of FIG.

  The voltage control delay elements 71 to 74 have the same configuration as the voltage control delay elements 75 to 78 and are controlled by the same voltage control signal VC. Therefore, the delay amount of the voltage control delay elements 71 to 74 and the delay amount of the voltage control delay elements 75 to 78 are the same. As a result, the output signal out1 is delayed from the input signal in by 1/4 cycle of the system clock sclk, the output signal out2 is delayed from the input signal in by 1/2 cycle of the system clock sclk, and the output signal out3 is delayed from the input signal in to the system. The output signal out4 is delayed by one cycle of the system clock sclk from the input signal in, with a delay of 3/4 cycle of the clock sclk. The input signal in and the output signals out1 to out3 are shown in (f) to (i) of FIG. Of these output signals, a signal having an appropriate delay amount may be selected and used as the output signal of the delay circuit 51.

  FIG. 10 is a circuit diagram showing another embodiment of the clock output circuit section 42 and the read data fetch circuit section 44 of the memory controller 40. In FIG. 10, the same components as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted.

  Compared with the embodiment of FIG. 5, in the embodiment shown in FIG. 10, the DLL circuit 33 </ b> A is used instead of the delay circuit 33, and the DLL circuit 51 </ b> A is used instead of the delay circuit 51.

  As an output signal of the DLL circuit 51A, it is preferable to use a signal delayed by about 4/4 cycle from 3/4 cycle of the system clock sclk. For example, when a signal delayed by 4/4 cycle (1 cycle) is used, the duration of the read data d3 in the signal D after being taken into the flip-flop 22 shown in FIG. Through one cycle of the data strobe signal DQS, the duration is from d2 to d2. In the configuration example shown in FIG. 10, a signal delayed by out3, that is, 3/4 cycle is output as an output signal.

  As an output signal of the DLL circuit 33A, a signal delayed by ½ cycle of the system clock sclk is preferably used. As a result, the data capturing operation can be executed at the timing just in the middle of each data valid period of the data signal Data shown in FIG.

  As described in the operation description of FIG. 8, the delay amount of the DLL circuit is dynamically adjusted according to the cycle length of the system clock sclk. Therefore, in the embodiment shown in FIG. 10, even when the system clock sclk changes, the delay amount is automatically adjusted and the optimum delay time is always provided.

  FIG. 11 is a circuit diagram showing still another embodiment of the clock output circuit section and read data fetch circuit section of the memory controller. 11, the same components as those in FIG. 5 are referred to by the same numerals, and a description thereof will be omitted.

  In the embodiment of FIG. 11, the memory controller 40A includes a signal confirmation state maintaining circuit 50A in place of the signal confirmation state maintaining circuit 50 of FIG. Further, the inverter 32 shown in FIG. 10 is omitted in FIG. The signal determination state maintaining circuit 50A includes a DLL circuit 51A, an inverter 91, and an AND gate 92. This signal determination state maintaining circuit 50A constitutes the same logic as the circuit portion including the signal determination state maintaining circuit 50 and the inverter 32 in FIG. That is, the capture timing signal B input to the flip-flop 22 in FIG. 10 and the capture timing signal B input to the flip-flop 22 in FIG. 11 are logically identical.

  In the embodiment of FIG. 11, the signal determination state maintaining circuit 50A is a circuit that realizes the same logical configuration as that of the embodiment of FIG. 10, but a circuit that realizes another logical configuration may be used. In short, if the indefinite state of the signal obtained by receiving the data strobe signal DQS in the HIGH impedance state by the input buffer 29 does not destroy the data stored in the flip-flop 22 for a predetermined time. Good.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a timing chart which shows the read specification of DDR SDRAM. It is a circuit diagram which shows an example of the conventional structure of the read data taking-in circuit by the side of a memory controller. FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. 2. It is a block diagram which shows the structure of the memory controller to which this invention is applied. FIG. 3 is a circuit diagram illustrating an embodiment of a clock output circuit unit and a read data capturing circuit unit of a memory controller. FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 5. It is a circuit diagram which shows an example of the circuit structure of a delay circuit. It is a circuit diagram which shows another example of the circuit structure of a delay circuit. FIG. 9 is a timing chart for explaining the operation of the circuit of FIG. 8. It is a circuit diagram which shows another Example of the clock output circuit part of a memory controller, and the read data taking-in circuit part. FIG. 10 is a circuit diagram showing still another embodiment of a clock output circuit unit and a read data fetch circuit unit of the memory controller.

Explanation of symbols

11 Memory 40 Memory Controller 41 Memory Control Circuit 42 Clock Output Circuit Unit 43 Command / Address Output Circuit Unit 44 Read Data Capture Circuit Unit 45 Write Data Output Circuit Unit 50 Signal Determination State Maintenance Circuit 51 Delay Circuit 52 Inverter 53 OR Gates 61 to 64 Delay buffers 65 to 68 Selectors 71 to 78 Voltage control delay element 81 Voltage control signal generator 82 Phase detector

Claims (10)

A delay circuit coupled to the receiving end of the data strobe signal and outputting a first timing signal obtained by delaying the data strobe signal;
A first flip-flop coupled to the output of the delay circuit and a receiving end of the data signal for capturing the data signal in response to the first timing signal;
A signal deterministic state maintaining circuit coupled to the output of the delay circuit and outputting a second timing signal processed from the first timing signal;
A second flip-flop coupled to the output of the signal deterministic state maintaining circuit and the receiving end of the data signal for capturing the data signal in response to the second timing signal , the second timing signal comprising: A signal having the same logical value as a logical sum of a logical inversion of the first timing signal and a signal obtained by delaying the first timing signal. A memory controller characterized in that the fixed state of the second timing signal is maintained for a predetermined time after becoming an indefinite state.   2. The memory controller according to claim 1, wherein the indefinite state of the first timing signal corresponds to a HIGH impedance state of the data strobe signal. A third flip-flop coupled to the outputs of the first and second flip-flops to alternately capture the data signal stored by the first and second flip-flops; 2. The memory controller according to claim 1, wherein the length of said three flip-flops is sufficient to capture the data signal stored in said second flip-flop.   2. The memory controller according to claim 1, wherein the signal fixed state maintaining circuit includes a delay buffer having a fixed delay amount, and the predetermined time is set by a delay of the delay buffer.   2. The memory controller according to claim 1, wherein the signal definite state maintaining circuit includes a programmable delay circuit, and the predetermined time is set by a delay of the programmable delay circuit. A delay circuit coupled to the receiving end of the data strobe signal and outputting a first timing signal obtained by delaying the data strobe signal;
A first flip-flop coupled to the output of the delay circuit and a receiving end of the data signal for capturing the data signal in response to the first timing signal;
A signal deterministic state maintaining circuit coupled to the output of the delay circuit and outputting a second timing signal processed from the first timing signal;
A second flip-flop coupled to the output of the signal determination state maintaining circuit and the receiving end of the data signal to capture the data signal in response to the second timing signal;
Including
The signal definite state maintaining circuit maintains the definite state of the second timing signal for a predetermined time after the first timing signal becomes undefined,
The signal definite state maintaining circuit includes a programmable delay circuit, and sets the predetermined time by the delay of the programmable delay circuit,
The programmable delay circuit is:
A plurality of delay elements;
A plurality of selectors, wherein the plurality of delay elements and the plurality of selectors are alternately connected in series, and each of the plurality of selectors is either an output of a preceding delay element or an input to the preceding delay element A memory controller characterized in that it can be selected and output.   2. The memory controller according to claim 1, wherein the signal definite state maintaining circuit includes a DLL circuit, and the predetermined time is set by a delay of the DLL circuit. The DLL circuit
A first delay element array that delays the first clock signal and outputs the second clock signal;
A phase detector that compares the phase of the first clock signal with the phase of the second clock signal;
A control signal generator for generating a control signal for controlling the delay amount of the delay line of the first according to the phase comparison result of the phase detector,
8. The memory controller according to claim 7 , further comprising a second delay element array coupled to the output of the delay circuit and controlled in delay amount by the control signal. A first delay circuit coupled to the receiving end of the data strobe signal and outputting a first timing signal obtained by delaying the data strobe signal;
A first flip-flop coupled to the output of the first delay circuit and a data signal receiving end for capturing the data signal in response to the first timing signal;
A signal processing circuit coupled to the output of the first delay circuit for processing the first timing signal and outputting a second timing signal;
A second flip-flop coupled to the output of the signal processing circuit and the receiving end of the data signal for capturing the data signal in response to the second timing signal , the second timing signal being the second timing signal; 1 having the same logical value as the logical sum of the logical inversion of the timing signal 1 and the signal obtained by delaying the first timing signal, and the signal processing circuit outputs the first timing signal for a predetermined time. A memory controller comprising a second delay circuit for delaying. A third flip-flop coupled to the outputs of the first and second flip-flops to alternately capture the data signal stored by the first and second flip-flops; 10. The memory controller according to claim 9, wherein the length of said three flip-flops is sufficient to capture the data signal stored in said second flip-flop.

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