JP2009118070A - Communication device and demodulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication device and a demodulation method that improve communication quality. <P>SOLUTION: The structure includes: a plurality of signal change detection circuits for detecting a signal change caused by a load modulation concerning load modulation signals which each of the circuits has received; and a demodulation system circuit corresponding to each signal change detection circuit. In this structure, when an output (packet) of the demodulation system circuit is selected, information on a size of an average amplitude level is used in addition to information whether a transmission line code can be detected, thereby enhancing the percentage of correct answers of a selection. For example, when the transmission line code is detected by a plurality of demodulation system circuits, an output of the demodulation system circuit having a highest average amplitude level is selected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a communication device and a demodulation method, and is particularly suitable as a reader / writer device that performs non-contact communication with a non-contact IC card.

JP 2005-318385 A

The non-contact IC card can easily exchange information with a device (reader / writer device) that reads and writes the information by wireless communication, and has a storage capacity compared to a magnetic card. And has many excellent features such as high resistance to unauthorized reading and alteration of stored information. For this reason, in recent years, it has been widely used for applications such as credit cards for financial institutions, storage cards for electronic money, and commuter passes for transportation.
In addition, a device has been developed in which a communication function equivalent to that of a non-contact IC card is built in a device such as a mobile phone or a PDA (Personal Digital Assistant) so that these devices can be used in the same manner as an IC card.

FIG. 17 shows a schematic configuration example of the IC card and the reader / writer device.
In FIG. 17, as an IC card, only an antenna circuit and a load modulation circuit are shown, and a demodulation system and a control system are omitted.
In the IC card, an antenna circuit is formed by a parallel resonant circuit of a coil L10 and a capacitor C10. Further, a load modulation circuit is formed by the switch element Tr1 and the resistor R10.

In the reader / writer device, an antenna circuit 91 is configured by the parallel resonant circuit of the coil L2 and the capacitor C20 and the capacitor C21.
A modulation signal generation circuit 92 is connected in parallel to the antenna circuit 91. The modulation signal generation circuit 92 is shown as a simplified signal source, but this reader / writer device is a circuit unit that generates an ASK (Amplitude Shift Keying) modulation signal to be transmitted to the IC card. For example, it is a circuit that ASK-modulates a carrier signal having a frequency of 13.56 MHz with data to be transmitted.
An ASK demodulation circuit 93 is connected to the antenna circuit 91. The ASK demodulation circuit 93 includes a diode detection circuit 94, a low-pass filter 95, a limiter amplifier 96, a synchronization circuit 97, and a determination unit 98.

Communication between the IC card and the reader / writer device is performed as follows.
The reader / writer device outputs, for example, a modulation signal having a carrier frequency of 13.56 MHz generated by the modulation signal generation circuit 92 from the antenna circuit 91 as a radio wave.
On the IC card side, radio waves transmitted from the reader / writer device are received by the antenna circuit, the ASK modulation signal is demodulated into a digital signal by a demodulation circuit (not shown), and supplied to a control system circuit (not shown).
When transmitting a signal from the IC card to the reader / writer device, the control system circuit of the IC card gives the transmission signal TxD to the switch element Tr1 to turn on / off the switch element Tr1. When the switch element Tr1 is turned on / off, the load resistance value changes, but this is detected on the external reader / writer device side as an ASK modulation signal of the carrier signal, that is, transmission information from the IC card side.
On the reader / writer device side, such an ASK modulation signal is demodulated by the ASK demodulation circuit 93.

By the way, there are the following problems regarding demodulation of a transmission signal by load modulation in an IC card in a reader / writer device.
During load modulation, when the distance between the IC card and the reader / writer device is a specific distance, there is a change in the phase direction but no change in the amplitude direction, so-called null state. In this case, the conventional ASK demodulating circuit 93 cannot demodulate the received signal and cannot communicate.

As a countermeasure against this problem, Patent Document 1 discloses a method of selecting one of the output series of the two circuits using not only an amplitude change detection circuit such as a conventional ASK demodulation circuit but also a phase change detection circuit. is suggesting. That is, as shown in FIG. 18A, an amplitude change detection circuit 101 and a phase change detection circuit 102 are provided. A reception signal obtained by the antenna circuit is supplied to the amplitude change detection circuit 101 and the phase change detection circuit 102, the amplitude change detection circuit 101 detects the amplitude change, and the phase change detection circuit 102 detects the phase change.
The selective demodulation circuit 100 selects one of the amplitude change detection circuit 101 and the phase change detection circuit 102 and outputs reception information RxD.

19A, 19B, and 19C are presented as configuration examples of the selective demodulation circuit 100. FIG.
In the case of the configuration of FIG. 19A, the output of the amplitude change detection circuit 101 is digitized by the A / D converter 111a, and the transmission line code detection unit 112a detects the transmission line code.
Communication between the IC card and the reader / writer device is performed using a packet structure including a preamble, a sync code, data, and CRC (Cyclic Redundancy Check) information as shown in FIG. The detection unit 112a confirms, for example, the detection of a sync code as a transmission line code.
Further, the output of the phase change detection circuit 102 is digitized by the A / D converter 111b, and the transmission path code detection unit 112b detects the transmission path code.
Then, the selector 113 confirms the detection results of the transmission path code detection units 112a and 112b, selects the output of the transmission path code detection units 112a and 112b, which has correctly detected the transmission path code, and performs synchronous detection. Supplied to the unit 114. The synchronization detection unit performs synchronization detection and data reproduction, and the error detection unit 115 performs error detection using CRC information. If there is no error, it is output as correctly demodulated reception information RxD.

  In the case of the configuration of FIG. 19B, the outputs of the amplitude change detection circuit 101 and the phase change detection circuit 102 are digitized by the A / D converters 111a and 111b, and are synchronized with the respective digital signals. The detection units 114a and 114b perform synchronization detection and data reproduction. Then, the selector 113 confirms the synchronization detection processing results from the synchronization detectors 114a and 114b, selects the output from the synchronization detectors 114a and 114b that has correctly detected synchronization and data reproduction, and selects the error detector 115. To supply.

In the case of the configuration of FIG. 19C, the output of the amplitude change detection circuit 101 is digitized by the A / D converter 111a and processed by the synchronization detection unit 114a and the error detection unit 115a. The output of the phase change detection circuit 102 is digitized by the A / D converter 111b and processed by the synchronization detection unit 114b and the error detection unit 115b.
Then, the selector 113 confirms the CRC results of the error detection units 115a and 115b, selects the one with no error, and outputs it as reception information RxD.

  However, these methods still have a problem of causing delays and failing to satisfy the application specifications, or causing a characteristic deterioration due to wrong selection.

For example, in the case of FIGS. 19A and 19B, the processing system (transmission path code detection unit 112a or synchronization detection unit 114a) corresponding to the output of the amplitude change detection circuit 101 and the output of the phase change detection circuit 102 are supported. Of the processing systems (transmission path code detection unit 112b or synchronization detection unit 114b), it is good if only one of the packet data can be correctly detected and processed. I can't choose the best one.
Usually, the communication quality required for detecting a transmission line code and synchronization is not so high. For this reason, for example, even if a transmission line code can be detected, the packet is not always effective.
In Patent Document 1, when a transmission line code is detected in a plurality of processing systems, a method of selecting according to a preset priority is proposed, but valid packet data can be obtained from an amplitude change or a phase change. Since it depends on various factors such as the resonance frequency of antennas and the distance between antennas, it is not an effective means to uniquely increase the priority of either processing system, but rather, the characteristics are significantly degraded. Sometimes it ends up.

  The method as shown in FIG. 19C can select a packet having no error. However, in order to detect a packet error, the packet is collected once until the end and detected by the last CRC of the packet. For this reason, since it takes a lot of time to detect the error detection information, the demodulated data obtained as the reception information RxD is greatly delayed. Many applications typically do not tolerate such delays.

  Therefore, in the present invention, when a received load modulation signal is provided with a plurality of signal change detection circuits for detecting a signal change due to load modulation and one of a plurality of processing systems is selected at the time of demodulation, a large delay is caused. The purpose is to enable selection more accurately.

  Each of the communication devices of the present invention is provided corresponding to each of a plurality of signal change detection circuits for detecting a signal change caused by load modulation for the received load modulation signal, and a plurality of the signal change detection circuits, respectively. Performs a process for data demodulation based on the signal from the corresponding signal change detection circuit, and detects a transmission line code and a mean amplitude level for the signal from the corresponding signal change detection circuit. A demodulation system circuit, a selection circuit that selects one of the outputs of the plurality of demodulation system circuits, and outputs the received information; and the transmission path code and average amplitude level of each of the plurality of demodulation system circuits And a selection control circuit for controlling the selection state of the selection circuit using the detection result.

  The selection control circuit is one of the plurality of demodulation system circuits, and when the transmission line code is detected, causes the selection circuit to select an output of the demodulation system circuit from which the transmission line code is detected. In addition, when the transmission line code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, detection of each average amplitude level in each demodulation system circuit in which the transmission line code is detected Using the result, the selection state of the selection circuit is controlled.

Each of the plurality of demodulation circuits converts the analog signal from the corresponding signal change detection circuit into a digital signal, and detects the average amplitude level of the digital signal.
In particular, in the plurality of demodulation circuits, analog signals from the corresponding signal change detection circuits are converted into digital signals by a 1-bit A / D converter, and digital signals output from the 1-bit A / D converter are output. The average amplitude level is detected by obtaining a moving average value of the two, obtaining a peak value of the moving average value, and adding the peak values.
In this case, when the transmission path code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, the selection control circuit is configured so that each of the demodulation system circuits in which the transmission path code is detected. Among them, control is performed so that the output having the larger value of the detected average amplitude level is selected by the selection circuit.
Alternatively, in the plurality of demodulation circuits, analog signals from the corresponding signal change detection circuits are converted into digital signals by a 1-bit A / D converter, and digital signals output from the 1-bit A / D converter are output. The moving average value is obtained, the value at the zero point timing of the moving average value is obtained, and the average amplitude level is detected from the value at the zero point timing.
In this case, when the transmission path code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, the selection control circuit is configured so that each of the demodulation system circuits in which the transmission path code is detected. Among them, control is performed so that the output having the smaller value of the detected average amplitude level is selected by the selection circuit.
Further, each of the plurality of demodulation circuits performs duty detection for the digital signal, and uses the detected duty information as correction information when detecting the average amplitude level.

The plurality of demodulation circuits detect the average amplitude level of the analog signal from the corresponding signal change detection circuit.
For example, in the plurality of demodulation circuits, the average amplitude level is detected by integrating analog signals from the corresponding signal change detection circuits.
In the case where the transmission path code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, the selection control circuit, among the demodulation system circuits in which the transmission path code is detected, Control is performed so that the output having the larger value of the detected average amplitude level is selected by the selection circuit.
Alternatively, the selection control circuit may detect the transmission path code in two or more demodulation system circuits among the plurality of demodulation system circuits, and each demodulation system circuit in which the transmission path code is detected. When the average amplitude level equal to or higher than a predetermined value is detected, control is performed so that the selection circuit selects the output of the demodulation system circuit set in advance among the demodulation systems in which the transmission line code is detected. To do.

One of the plurality of signal change detection circuits detects an amplitude change caused by the load modulation with respect to the received load modulation signal.
One of the plurality of signal change detection circuits detects a phase change caused by load modulation in the received load modulation signal.

  The demodulation method of the present invention includes a plurality of signal change detection circuits, a plurality of demodulation systems, and a communication circuit including a selection circuit that selects one of the outputs of the plurality of demodulation systems and outputs the received information. As a method of demodulating the apparatus, a transmission path code detection confirmation step for confirming a detection result of the transmission path code of each of the plurality of demodulation circuits, and the transmission path code is detected by one of the plurality of demodulation circuits. A first selection control step for causing the selection circuit to select an output of the demodulation system circuit in which the transmission line code is detected, and two or more demodulation system circuits among the plurality of demodulation system circuits. When the transmission line code is detected in the second selection circuit, a second selection for controlling a selection state of the selection circuit using a detection result of each average amplitude level in each demodulation system circuit in which the transmission line code is detected. A control step.

In the present invention, when selecting the output (packet) of the demodulation system circuit, the correct answer rate is obtained by using the information of the magnitude of the average amplitude level in addition to the information of whether or not the transmission line code has been detected. Improve.
Specifically, when a transmission line code is detected by a plurality of demodulation system circuits, the output of the demodulation system circuit having the largest or smallest average amplitude level is selected.
Alternatively, a threshold is provided for the average amplitude level, and an output is selected from the demodulation system circuits in which the average amplitude level equal to or higher than the threshold is detected.
When detecting the average amplitude level, the duty of the received waveform is also taken into consideration.

In the present invention, it is possible to perform stable and correct selection by using information on the presence / absence of detection of transmission path codes and average amplitude level for selection of outputs of a plurality of demodulation circuits, thereby improving communication quality. Can be made.
In addition, since selection is not performed using the error correction result, a large delay is not caused in the reception information reception.

Hereinafter, embodiments of the present invention will be described by taking a reader / writer device that communicates with a non-contact IC card as an example. The description will be given in the following order.
[1. Basic configuration]
[2. Configuration example A: Analog system amplitude level calculation example]
[3. Configuration example B: Analog system amplitude level calculation example]
[4. Configuration example C: Digital amplitude level calculation example]
[5. Configuration example D: Digital amplitude level calculation example]
[6. Configuration Example E: Digital System Amplitude Level Calculation Example]
[7. Configuration Example F: Digital System Amplitude Level Calculation Example]

[1. Basic configuration]

The basic configuration of the reader / writer device 1 according to the embodiment will be described with reference to FIGS. FIG. 1 shows an example in which the average amplitude level calculation circuit is mounted in the analog domain, and FIG. 2 shows an example in which the average amplitude level calculation circuit is mounted in the digital domain.

First, the configuration of the reader / writer device 1 will be described with reference to FIG.
In the reader / writer device 1, an antenna circuit 2 is constituted by a parallel resonant circuit of a coil L1 and a capacitor C1, and a capacitor C2.
A modulation signal generation circuit 3 is connected in parallel to the antenna circuit 2. Although the modulation signal generation circuit 3 is shown as a simplified signal source, this reader / writer device is a circuit unit that generates an ASK modulation signal to be transmitted to an external IC card. For example, it is a circuit that ASK-modulates a carrier signal having a frequency of 13.56 MHz with data to be transmitted.

As a circuit system for receiving and demodulating a signal from an external IC card, first, signal change detection circuits 10 and 20 are connected to the antenna circuit 2. The signal change detection circuits 10 and 20 are circuits that detect a signal change caused by load modulation for each received load modulation signal.
For example, the signal change detection circuit 10 is an analog ASK detection circuit, and detects an amplitude change for the received signal obtained by the antenna circuit 2.
Further, for example, the signal change detection circuit 20 is an analog phase detection circuit, for example, and detects a phase change of the received signal obtained by the antenna circuit 2.

The outputs of the signal change detection circuits 10 and 20 are supplied to the selective demodulation circuit 4.
In the selective demodulation circuit 4, an A / D converter 31A, a synchronization circuit 32A, a transmission line code detection circuit 33A, and an average amplitude level calculation circuit 34A are provided as demodulation system circuits corresponding to the signal change detection circuit 10. These are referred to as “first demodulation circuit” for the sake of explanation.
As a demodulation system circuit corresponding to the signal change detection circuit 20, an A / D converter 31B, a synchronization circuit 32B, a transmission line code detection circuit 33B, and an average amplitude level calculation circuit 34B are provided. These will be referred to as “second demodulation circuit” for the sake of explanation.
In the selective demodulation circuit 4, a selection circuit 36, an error detection unit 37, and a control circuit 35 are provided.

In this selective demodulation circuit 4, in the first demodulation system circuit, the A / D converter 31A converts the output of the signal change detection circuit 10 into digital data.
The digital data from the A / D converter 31A is supplied to the synchronization circuit 32A, and synchronization detection / data reproduction processing is performed in the synchronization circuit 32A. The signal SA (packet data as reception information) demodulated by the processing of the synchronization circuit 32A is supplied to the selection circuit 36.
Further, the transmission path code detection circuit 33A determines whether or not a sync code, for example, is detected as a transmission path code constituting the demodulated packet, and provides the determination result information to the control circuit 35.
The average amplitude level calculation circuit 34 </ b> A calculates an amplitude level for the output signal of the signal change detection circuit 10 and supplies amplitude level information to the control circuit 35.

Further, as the second demodulation system circuit, the A / D converter 31B converts the output of the signal change detection circuit 20 into digital data.
The digital data from the A / D converter 31B is supplied to the synchronization circuit 32B, and synchronization detection / data reproduction processing is performed in the synchronization circuit 32B. The signal SB demodulated by the processing of the synchronization circuit 32B (packet data as reception information) is supplied to the selection circuit 36.
Further, the transmission path code detection circuit 33B determines whether or not a sync code, for example, is detected as a transmission path code constituting the demodulated packet, and provides the determination result information to the control circuit 35.
The average amplitude level calculation circuit 34B calculates the amplitude level for the output signal of the signal change detection circuit 20 and supplies the amplitude level information to the control circuit 35.

The selection circuit 36 selects one of the signal SA output from the first demodulation system circuit and the signal SB output from the second demodulation system circuit, and outputs the selected signal to the error detection unit 37 at the subsequent stage.
In the control circuit 35, information on the respective transmission line code detection results from the transmission line code detection circuits 33A and 33B in the first and second demodulation circuits and the respective average amplitudes from the average amplitude level calculation circuits 34A and 34B. The selection state of the selection circuit 36 is controlled using the level information.
For example, when a transmission line code is detected on one of the first and second demodulation circuits, the selection circuit 36 selects the output (one of the signals SA and SB) of the demodulation circuit on which the transmission line code is detected. To be controlled.
When a transmission line code is detected in both the first and second demodulation circuits, the selection circuit 36 selects the output (one of the signals SA and SB) of the demodulation circuit having the larger average amplitude level. To control.
Alternatively, a threshold value is provided for the average amplitude level, and one demodulation system circuit is selected from the demodulation system circuits in which the average amplitude level equal to or higher than the threshold value is detected, and the output is selected by the selection circuit 36. Also good.

  The signal selected by the selection circuit 36 is supplied to the error detection unit 37, and error detection processing using CRC information is performed. If there is no error in this processing, the signal is converted into packet data as appropriate reception information RxD and output to a control circuit system in the subsequent stage (not shown).

In the case of the configuration of FIG. 2, the average amplitude level calculation circuits 34A and 34B calculate the average amplitude level for the digital data output from the A / D converters 31A and 31B, respectively. Different.
Also in this case, the control circuit 35 receives information on the respective transmission line code detection results from the transmission line code detection circuits 33A and 33B in the first and second demodulation circuits, and the average amplitude level calculation circuits 34A and 34B. The selection state of the selection circuit 36 is controlled using information on each average amplitude level.

  When implemented in the digital domain, the average amplitude level Aave can be derived, for example, by any one of the following (Equation 1) and (Equation 2).

但し、Ｓは信号、Ｔｓはサンプリング間隔、ｍは伝送路符号が検出されたサンプル数、ａは任意の遅延サンプル数、ｉは平均値を求める際のインデックスである。

However, S is a signal, Ts is a sampling interval, m is the number of samples in which a transmission line code is detected, a is an arbitrary number of delayed samples, and i is an index for obtaining an average value.

  The average amplitude level Aave does not necessarily need to be N samples closest to the timing at which the transmission line code is detected. Moreover, if it is a quantity proportional to said value, it can utilize.

1 and 2, the control circuit 35 preferably avoids erroneous determination of the detection outputs from the transmission line code detection circuits 33A and 33B as follows.
Since the two paths from the signal change detection circuits 10 and 20 are output series of different analog circuits, the data delay amount is naturally different.
For this reason, there is a possibility that the detection status of the other demodulation system circuit is erroneously determined at the timing when the transmission line code is detected by one demodulation system circuit.
For example, the first path and the second path in FIG. 3 indicate transmission path code detection information in the first and second demodulation circuits for the signal change detection circuits 10 and 20, respectively. That is, the signal of the first path is the detection result output of the transmission path code detection circuit 33A, and the signal of the second path is the detection result output of the transmission path code detection circuit 33B.
Here, it is assumed that the control circuit 35 recognizes that the transmission line code is detected in the first demodulation system circuit by the detection output of the transmission line code detection circuit 33A at a certain time t0.
However, at this time t0, depending on the detection output of the transmission line code detection circuit 33B, it is assumed that the result that the transmission line code has been detected has not been obtained due to the influence of an analog signal delay or the like.
For this reason, if the detection status of the other demodulation system circuit is determined at the timing when the transmission line code is detected by one demodulation system circuit, there is a possibility of erroneous determination. Therefore, when a transmission line code is detected in either path, erroneous detection is avoided by reading the detection status of both paths after the time Td has elapsed with the timing as a trigger.
For example, the control circuit 35 can avoid erroneous determination due to analog signal delay by reading the detection result outputs of the transmission line code detection circuits 33A and 33B at the time t1 waiting for the time Td from the time t0.

[2. Configuration example A: Analog system amplitude level calculation example]

Hereinafter, a more specific configuration example will be described. Hereinafter, various configuration examples will be described as the configuration examples A to F. In each configuration example, the same portions as those in FIG. 1 or FIG.

FIG. 4 is a more specific configuration example when the average amplitude level is calculated for the analog signal as shown in FIG.
In this case, an integration circuit 41A is provided as a specific example of the average amplitude level calculation circuit 34A of the first demodulation system circuit corresponding to the signal change detection circuit 10.
Further, as a specific example of the average amplitude level calculation circuit 34B of the second demodulation system circuit corresponding to the signal change detection circuit 20, an integration circuit 41B is provided.
Further, a comparator 42 that compares the outputs of the integration circuits 41A and 41B and outputs comparison result information is provided. Although the comparison result information of the comparator 42 is supplied to the control circuit 35 in the figure, the comparator 42 may be considered as an internal configuration of the control circuit 35.

In this case, the average amplitude level for the output of the signal change detection circuit 10 is obtained as the output of the integration circuit 41A, and the average amplitude level for the output of the signal change detection circuit 20 is obtained as the output of the integration circuit 41B. These are compared by the comparator 42.
The comparator 42 supplies information indicating which average amplitude level is larger to the control circuit 35 as binary comparison result information of “1” and “0”, for example.
As described with reference to FIG. 1, the control circuit 35 is also supplied with detection result information of transmission line codes by the transmission line code detection circuits 33A and 33B.

The control circuit 35 controls the selection circuit 36 by, for example, the process of FIG.
In Step F101, it is confirmed whether or not a transmission line code is detected by any of the transmission line code detection circuits 33A and 33B.
When the detection result information indicating that the transmission line code is detected by one of the transmission line code detection circuits 33A and 33B is obtained, the control circuit 35 proceeds to step F102, waits for time Td, and again detects the transmission line code. The detection result information of the circuits 33A and 33B is confirmed. In other words, in order to avoid erroneous determination as described with reference to FIG. 3, after the passage of time Td from the first recognition of the transmission line code, the transmission line code detection circuits 33A and 33B have detected the transmission line code, respectively. It is to confirm whether or not.

In step F103, the control circuit 35 branches the process depending on whether the transmission line code has been detected by both of the transmission line code detection circuits 33A and 33B or only one of the transmission line codes has been detected.
If the transmission line code can be detected by only one of the transmission line code detection circuits 33A and 33B, the process proceeds to step F104, and the selection circuit 36 is selected so as to select the output of the demodulation system circuit from which the transmission line code is detected. Control.
For example, when the transmission path code can be detected only by the transmission path code detection circuit 33A, the selection circuit 36 selects the output signal SA of the first demodulation system circuit. When the transmission path code can be detected only by the transmission path code detection circuit 33B, the selection circuit 36 selects the output signal SB of the second demodulation system circuit.

When the transmission line code can be detected by both of the transmission line code detection circuits 33A and 33B, the process proceeds to step F105, where the control circuit 35 selects the output of the demodulation system circuit having the larger average amplitude level. 36 is controlled.
That is, the comparison result information from the comparator 42 is confirmed, and if the result that the average amplitude level (output of the integration circuit 41A) obtained by the first demodulation system circuit is larger is obtained, the selection circuit 36 is informed. Causes the output signal SA of the first demodulation system circuit to be selected. If the average amplitude level obtained from the second demodulation system circuit (the output of the integration circuit 41B) is larger, the selection circuit 36 receives the output signal SB of the second demodulation system circuit. Let them choose.

The control circuit 35 controls the selection circuit 36 by such processing, so that information on the presence / absence of detection of the transmission path code and the average amplitude level is selected as the selection of the output signals SA and SB of the first and second demodulation circuits. The correct selection used can be made, thereby improving the communication quality.
The signal (either SA or SB) selected by the selection circuit 36 is supplied to the error detection unit 37 and subjected to error detection processing. If there is no error, the control system in the subsequent stage is used as packet data as appropriate reception information RxD. Supplied to the circuit.
In this configuration, since the error detection result is not used for the selection operation of the selection circuit 36, a large delay is not generated as the output of the reception information RxD of the selection demodulation circuit 4.

[3. Configuration example B: Analog system amplitude level calculation example]

FIG. 6 is also a specific configuration example when the average amplitude level is calculated for the analog signal as shown in FIG.
Also in this case, as a specific example of the average amplitude level calculation circuit 34A of the first demodulation system circuit corresponding to the signal change detection circuit 10, the integration circuit 41A is provided, and the second demodulation corresponding to the signal change detection circuit 20 is provided. As a specific example of the average amplitude level calculation circuit 34B of the system circuit, an integration circuit 41B is provided.
The output voltage of the integration circuit 41A is supplied to the comparator 43A and compared with a predetermined threshold voltage Vth. The comparator 43A supplies the control circuit 35 with comparison result information as to whether or not the output voltage of the integrating circuit 41A is equal to or higher than the threshold voltage Vth.
Similarly, the output voltage of the integration circuit 41B is supplied to the comparator 43B and compared with a predetermined threshold voltage Vth. The comparator 43B supplies the control circuit 35 with comparison result information indicating whether the output voltage of the integrating circuit 41B is equal to or higher than the threshold voltage Vth.
Although the comparison result information of the comparators 43A and 43B is supplied to the control circuit 35 in the figure, the comparators 43A and 43B may be considered as an internal configuration of the control circuit 35.

In this case, information indicating whether or not the average amplitude level for each output of the signal change detection circuits 10 and 20 is equal to or higher than a predetermined value corresponding to the threshold voltage Vth is given to the control circuit 35.
Further, as described with reference to FIG. 1, the control circuit 35 is also supplied with detection result information of transmission line codes by the transmission line code detection circuits 33A and 33B.

The control circuit 35 controls the selection circuit 36 by, for example, the process of FIG.
In step F201, it is confirmed whether or not a transmission line code is detected by any of the transmission line code detection circuits 33A and 33B.
When the detection result information indicating that the transmission line code has been detected by one of the transmission line code detection circuits 33A and 33B is obtained, the control circuit 35 proceeds to step F202 and waits for a time Td to avoid erroneous determination. Again, the detection result information of the transmission line code detection circuits 33A and 33B is confirmed.

In step F203, the control circuit 35 checks whether or not the average amplitude level (integrated value) is equal to or higher than a predetermined level as the threshold voltage Vth in one or both of the demodulation system circuits in which the transmission line codes are detected.
For example, when the transmission line code can be detected only by the transmission line code detection circuit 33A, the comparison result information of the comparator 43A is confirmed, and the threshold value is set as the average amplitude level (output of the integration circuit 41A) of the output signal of the signal change detection circuit 10. It is confirmed whether or not an integral value equal to or higher than Vth is detected.
In this case, if the average amplitude level equal to or higher than the threshold value Vth is detected, the process proceeds to step F204, and if the average amplitude level equal to or higher than the threshold value Vth is not detected, the process returns to step F201.
Further, for example, when the transmission line code can be detected only by the transmission line code detection circuit 33B, the comparison result information of the comparator 43B is confirmed, and the average amplitude level (output of the integration circuit 41B) of the output signal of the signal change detection circuit 20 is confirmed. It is confirmed whether or not an integral value equal to or higher than the threshold value Vth is detected.
In this case, if the average amplitude level equal to or higher than the threshold value Vth is detected, the process proceeds to step F204, and if the average amplitude level equal to or higher than the threshold value Vth is not detected, the process returns to step F201.
When the transmission line code can be detected by both of the transmission line code detection circuits 33A and 33B, the comparison result information of the comparators 43A and 43B is confirmed, and whether or not an integral value of a predetermined level or more is detected in each. Confirm.
In this case, if an average amplitude level equal to or higher than the threshold value Vth is detected on the one hand, the process proceeds to step F204, and if neither average amplitude level equal to or higher than the threshold value Vth is detected, the process returns to step F201.

  When returning to Step F201, the transmission path code can be detected by one or both of the first and second demodulation circuits, but the average amplitude level of the output signal of one or both of the signal change detection circuits 10 and 20 is sufficient. If the signal state is not reliable, the transmission line code is detected again.

If one or both of the first and second demodulation circuits can detect the transmission line code with the average amplitude level being equal to or higher than the threshold value Vth, the process proceeds to step F204. Here, the control circuit 35 The process branches depending on whether the output from which the transmission line code was detected in the state where the level is equal to or higher than the threshold value Vth was either one or both of the signal change detection circuits 10 and 20.
If there is one, the control circuit 35 controls the selection circuit 36 in step F205 so as to select the output of the demodulation system circuit that satisfies the condition.
For example, when the transmission line code can be detected with only the first demodulation system circuit for the output signal of the signal change detection circuit 10 in a state where the average amplitude level is equal to or higher than the threshold value Vth, the selection circuit 36 includes the first demodulation system. The signal SA from the circuit is selected.

  If both the first and second demodulation circuits satisfy the condition, there is no problem even if either is selected. Accordingly, the control circuit 35 proceeds to step F206 and causes the selection circuit 36 to select according to a predetermined priority. For example, when priority is given to the first demodulation system circuit, the signal SA is selected.

As the control circuit 35 controls the selection circuit 36 by such processing, the transmission line code is selected as the selection of the output signals SA and SB of the first and second demodulation circuits as in the case of the configuration example A. The correct selection using the information on the presence / absence of detection and the average amplitude level can be performed without a large delay.

[4. Configuration example C: Digital amplitude level calculation example]

Next, as a configuration example C, a configuration example when the average amplitude level is detected in the digital data stage will be described with reference to FIG.

In the example of FIG. 8, the first demodulation system circuit corresponding to the signal change detection circuit 10 in the selective demodulation circuit 4 includes a 1-bit A / D converter 51A, a moving average filter 52A, a peak value detection circuit 53A, an average amplitude. A level calculation circuit 54A, a synchronization circuit 32A, and a transmission path code detection circuit 33A are provided.
The second demodulation system circuit corresponding to the signal change detection circuit 20 in the selective demodulation circuit 4 includes a 1-bit A / D converter 51B, a moving average filter 52B, a peak value detection circuit 53B, an average amplitude level calculation circuit 54B, A synchronization circuit 32B and a transmission line code detection circuit 33B are provided.
In addition, the selection demodulating circuit 4 includes the control circuit 35, the selection circuit 36, and the error detection unit 37 in the same manner as the above examples.

As a first demodulation system circuit, a 1-bit A / D converter 51A performs 1-bit quantization using a sampling frequency Fs = N × Fbb (Fbb is a data transmission rate) Hz, that is, signal change detection. As oversampling N times the output of the circuit 10, for example, binary output of “1” and “0” is performed as shown in FIG. (○ in Fig. 9 is the sample point)
The moving average filter 52A calculates a moving average value of a predetermined number of samples for the output of the 1-bit A / D converter 51A. The output of the moving average filter 52A is, for example, as shown in FIG.
The peak value detection circuit 53A extracts a sample having a peak value as shown in FIG. 9C from the output value of the moving average filter 52A and supplies the sample to the average amplitude level calculation circuit 34A.
The average amplitude level calculation circuit 34A performs addition (or average value calculation) of absolute values of sample points as peak values, and supplies the result to the control circuit 35 as an average amplitude level value.
The synchronization circuit 32A performs synchronization detection and packet data reproduction as reception information from the output of the moving average filter 52A, and supplies this to the selection circuit 36 as a demodulated signal SA.
The transmission path code detection circuit 33A determines whether or not a sync code, for example, is detected as a transmission path code constituting the demodulated packet, and provides the determination result information to the control circuit 35.

Similar processing is performed in the second demodulation system circuit. That is, the 1-bit A / D converter 51B performs N-times oversampling on the output of the signal change detection circuit 20 at the same sampling frequency Fs, and the moving average filter 52B outputs the output of the 1-bit A / D converter 51B. A moving average value of a predetermined number of samples is calculated. The peak value detection circuit 53B extracts a sample having a peak value from the output value of the moving average filter 52B and supplies the sample to the average amplitude level calculation circuit 34B. The average amplitude level calculation circuit 34B performs addition (or average value calculation) of absolute values of sample points as peak values, and supplies the result to the control circuit 35 as a value of the average amplitude level.
The synchronization circuit 32B performs synchronization detection and packet data reproduction as reception information from the output of the moving average filter 52B, and supplies this to the selection circuit 36 as a demodulated signal SB.
The transmission path code detection circuit 33B determines whether or not a sync code, for example, is detected as a transmission path code constituting the demodulated packet, and provides the determination result information to the control circuit 35.

In this configuration, the control circuit 35 may control the selection circuit 36 by the processing shown in FIG. That is, when a transmission line code is detected by one demodulation system circuit, the output of that demodulation system circuit is selected, and when a transmission line code is detected by both demodulation system circuits, the one with the higher average amplitude level The output of the demodulation system circuit may be selected.
Alternatively, the control circuit 35 may control the selection circuit 36 by the processing of FIG. That is, when a transmission line code is detected in one or both demodulation systems, it is determined whether or not the detected average amplitude level in the demodulation system is equal to or greater than a predetermined threshold value. Then, the selection circuit 36 may be controlled so as to select the signal (SA or SB) of the demodulation system circuit in which the transmission line code is detected and the average amplitude level is equal to or greater than the threshold value.
Also in this configuration, the same effects as those of the configuration examples A and B described above can be obtained.

[5. Configuration example D: Digital amplitude level calculation example]

Next, the configuration of FIG. 10 will be described as a configuration example D. In each demodulation system circuit, the analog signals from the corresponding signal change detection circuits 10 and 20 are converted into digital signals by 1-bit A / D converters 51A and 51B, respectively. The signal is converted into a signal, and moving average values of the digital signals output from the 1-bit A / D converters 51A and 51B are obtained by the moving average filters 52A and 52B. Then, the peak value of the moving average value is obtained, and the average amplitude level is detected by adding the peak values. In particular, as the synchronization circuits 32A and 32B, timing generation circuits 61A and 61B, downsamplers 62A and 62B, This is an example in the case where the determination devices 63A and 63B are configured.

In the first demodulation system circuit, the timing generation circuit 61A generates the timing of the peak value from the output value of the moving average filter 52A.
11A shows the output of the 1-bit A / D converter 51A, and FIG. 11B shows the output of the moving average filter 52A. The timing generation circuit 61A, as shown in FIG. A timing signal indicating the peak timing of the moving average value is generated.
The generation of timing can be derived relatively easily by a technique such as a Costas loop circuit.
The down sampler 62A uses this timing to thin out the output value of the moving average filter 52A to 2Fbb. FIG. 11D shows the output of the down sampler 62A.
The decision unit 63A binarizes the output value of the down sampler 62A and thins the sampling rate to Fbb. Then, the signal SA is supplied to the selection circuit 36.
In the average amplitude level calculation circuit 54A, the output value of the down sampler 62A is added to calculate the average amplitude level, which is supplied to the control circuit 35.
In the transmission line code detection circuit 33A, the presence or absence of transmission line code detection is determined for the signal SA, and the determination result information is given to the control circuit 35.

Similarly, in the second demodulation system circuit, the timing generation circuit 61B generates the timing of the peak value from the output value of the moving average filter 52B, and the downsampler 62B uses this timing to output the output of the moving average filter 52B. Decrease the value to 2Fbb. The determiner 63B binarizes the output value of the downsampler 62B and thins the sampling rate to Fbb. The signal SB is supplied to the selection circuit 36.
In the average amplitude level calculation circuit 54B, the output value of the down sampler 62B is added to calculate an average amplitude level, which is supplied to the control circuit 35.
The transmission line code detection circuit 33B determines whether or not the transmission line code is detected for the signal SB, and provides the determination result information to the control circuit 35.

Even in this configuration, the control circuit 35 may control the selection circuit 36 by the processing of FIG. 5 described above. That is, when a transmission line code is detected by one demodulation system circuit, the output of that demodulation system circuit is selected, and when a transmission line code is detected by both demodulation system circuits, the one with the higher average amplitude level The output of the demodulation system circuit may be selected.
Alternatively, the control circuit 35 may control the selection circuit 36 by the processing of FIG. That is, when a transmission line code is detected in one or both demodulation systems, it is determined whether or not the detected average amplitude level in the demodulation system is equal to or greater than a predetermined threshold value. Then, the selection circuit 36 may be controlled so as to select the signal (SA or SB) of the demodulation system circuit in which the transmission line code is detected and the average amplitude level is equal to or greater than the threshold value.
Also in this configuration, the same effects as those of the configuration examples A and B described above can be obtained.

[6. Configuration Example E: Digital System Amplitude Level Calculation Example]

A configuration example E will be described with reference to FIG. In each demodulating circuit, for the digital signals output from the 1-bit A / D converters 51A and 51B, the moving average values are obtained by the moving average filters 52A and 52B, and the moving average value is zeroed by the synchronization circuits 32A and 32B. In this example, the value at the point timing is obtained, and the average amplitude level is detected from the value at the zero point timing.
The synchronization circuits 32A and 32B are composed of timing generation circuits 61A and 61B, down samplers 62A and 62B, and determiners 63A and 63B.

In the first demodulation system circuit, the timing generation circuit 61A generates the peak value timing and the zero point timing from the output value of the moving average filter 52A.
13A shows the output of the 1-bit A / D converter 51A, and FIG. 13B shows the output of the moving average filter 52A. The timing generation circuit 61A uses the timing TM1 in FIG. 13C as the timing TM1. A timing signal indicating the peak timing of the moving average value is generated, and a timing signal indicating a zero point is generated as the timing TM2 in FIG. Since the zero point timing TM2 is the center of the timing between peak values, it can be easily calculated from the peak value timing TM1.
The down sampler 62A thins out the output value of the moving average filter 52A to 2Fbb using the timing TM1, and supplies the output OTM1 shown in FIG. The determiner 63A binarizes the output OTM1 of the downsampler 62A and thins the sampling rate to Fbb. Then, the signal SA is supplied to the selection circuit 36.
Further, the down sampler 62A thins out the output value of the moving average filter 52A using the timing TM2, and supplies the output OTM2 shown in FIG. 13 (f) to the average amplitude level calculation circuit 54A as the zero point timing value.
In the average amplitude level calculation circuit 54A, the output value of the down sampler 62A is added to calculate the average amplitude level, which is supplied to the control circuit 35.
In the transmission line code detection circuit 33A, the presence or absence of transmission line code detection is determined for the signal SA, and the determination result information is given to the control circuit 35.

Similarly, for the second demodulation system circuit, the timing generation circuit 61B generates the peak value timing and the zero point timings TM1 and TM2 from the output value of the moving average filter 52B, and the downsampler 62B generates the timing at the timing TM1. The output OTM1 is supplied to the determiner 63B, and the output OTM2 at the timing TM2 is supplied to the average amplitude level calculation circuit 34B.
The determiner 63B binarizes the output OTM1 of the downsampler 62B and thins the sampling rate to Fbb. The signal SB is supplied to the selection circuit 36.
In the average amplitude level calculation circuit 54B, the output value of the down sampler 62B is added to calculate an average amplitude level, which is supplied to the control circuit 35.
The transmission line code detection circuit 33B determines whether or not the transmission line code is detected for the signal SB, and provides the determination result information to the control circuit 35.

In the Felica (registered trademark) system used for non-contact wireless communication between an IC card and a reader / writer device, “0” data that is Manchester-encoded is added to the preamble.
For this reason, since the output of the moving average filter regularly shows a zero-crossing point, in this example, this zero point is used. In other words, when the zero point appears regularly, it can be considered as an appropriate signal state.
In the average amplitude level calculation circuits 54A and 54B, the downsampling output at the timing TM2 of the zero point is added. In this case, the smaller the average amplitude level as the added value, the more appropriate the signal.

Therefore, the control circuit 35 controls the selection circuit 36 by a process obtained by modifying Step F105 in FIG.
That is, when a transmission line code is detected by one demodulation system circuit, the output of the demodulation system circuit is selected. If a transmission line code is detected in both demodulation systems, the process proceeds to step F105. In this case, the output of the demodulation system having the smaller average amplitude level may be selected.
Alternatively, the control circuit 35 may control the selection circuit 36 by a process obtained by modifying Step F203 in FIG. That is, when a transmission line code is detected by one or both of the demodulation system circuits, in step F203, it is determined whether or not the average amplitude level in the detected demodulation system circuit is below a predetermined threshold value.
Then, the selection circuit 36 may be controlled so as to select the signal (SA or SB) of the demodulation system circuit in which the transmission line code is detected and the average amplitude level is equal to or less than the threshold value.
Also in this configuration, the same effects as those of the configuration examples A and B described above can be obtained.

[7. Configuration Example F: Digital System Amplitude Level Calculation Example]

In the case of the above configuration examples D, E, and F, the 1st and 2nd demodulating circuits correspond to the signals of different analog demodulating circuits called signal change detecting circuits 10 and 20, respectively. , 51B may have different duty deviations.
When the duty of the output waveforms of the 1-bit A / D converters 51A and 51B is deviated, even if the reception amplitude level is large, the value calculated by the average amplitude level calculation circuits 54A and 54B becomes small, resulting in a selection error. There is a possibility of waking up.

Therefore, as configuration example F, an example is shown in which the duty is detected, and correction is performed when the average amplitude level calculation circuits 54A and 54B are calculated based on the detection result.
FIG. 14 shows an example in which duty detection circuits 56A and 56B are provided in addition to the configuration of FIG.
In the first demodulation system circuit, the output of the 1-bit A / D converter 51A is supplied to the moving average filter 52A and also to the duty detection circuit 56A. The duty detection circuit 56A is also supplied with a timing signal (FIG. 11C) from the timing generation circuit 61A. The duty detection circuit 56A performs duty detection on the output of the 1-bit A / D converter 51A and supplies the detection result to the average amplitude level calculation circuit 54A.
In the second demodulation system circuit, the output of the 1-bit A / D converter 51B is supplied to the moving average filter 52B and also to the duty detection circuit 56B. The timing signal from the timing generation circuit 61B is also supplied to the duty detection circuit 56B. The duty detection circuit 56B performs duty detection on the output of the 1-bit A / D converter 51B and supplies the detection result to the average amplitude level calculation circuit 54B.

The operation in this configuration will be described.
FIGS. 15 (a) and 15 (b) show an example when the duty is shifted from the ideal state. Here, it is assumed that the 1-bit A / D converters 51A and 51B perform 16 times oversampling, and the 16 times oversampling output is indicated by ●. The moving average filters 52A and 52B take a moving average of 8 samples, and the output moving average value is indicated by Δ.

FIG. 15A shows an ideal state in which the duty of the output of the 1-bit A / D converter 51A (51B) is 50%.
Although the value is shown on the vertical axis, in this case, the peak value as the moving average value is “1” and “−1”.
On the other hand, FIG. 15B shows a state in which the duty of the output of the 1-bit A / D converter 51A (51B) is shifted, but the peak value as the moving average value is “1” and “−0.5”. ing.
In the case as shown in FIG. 15B, even if the average amplitude level is calculated by extracting and adding the peak values, the value of the average amplitude level is disadvantageous.

  Therefore, in order to compare both paths equally with SNR (Signal Noise Ratio), the duty detection circuit 56A, 56B calculates the duty ratio for each output waveform of the 1-bit A / D converters 51A, 51B, The value is used to correct the average amplitude level.

In the Felica (registered trademark) packet structure, five bytes of Manchester-encoded data-1, that is, -1,1 data, are added to the head of the packet. When oversampling is performed at 16 times the data transmission rate Fbb, −1 is composed of 8 samples and 1 is composed of 8 samples for one data.
Here, if there is no duty deviation, the moving average value is “0” if the moving average is taken as an integer multiple of 16 samples. In FIG. 15A, the moving average value of 16 samples is indicated by ◯, but the moving average value is “0” as shown in the figure.
However, when the duty is shifted such that “−1” is 6 samples and “1” is 10 samples as shown in FIG. 15B, the moving average is taken as “+0. 25 ".
In this case, since the peak value of the moving average of 8 samples is “−0.5” and “1”, only the minus peak value is an integer multiple of 16 samples and is twice the moving average value, that is, +0.25. × 2 = 0.5
Only correction is necessary.

FIG. 16 shows an example of the duty detection circuits 56A and 56B.
The duty detection circuits 56 </ b> A and 56 </ b> B include a moving average filter 71 and a downsampler 72. The moving average filter 71 obtains a moving average value using a sample number that is equal to the ratio of the data transmission rate Fbb and the sampling rate of the 1-bit A / D converters 51A and 51B and is an integer multiple of the number of samples. For example, when 16-times oversampling is performed with the sampling rate of the 1-bit A / D converters 51A and 51B set to Fbb × 16 as described above, the moving average filter 71 can obtain a moving average value of the number of samples that is an integer multiple of 16. That's fine.
In the down sampler 72, the output of the moving average filter is thinned using the output timing of the timing generation circuit.

The output of the moving average filter 71 is a value indicated by a circle in FIGS. 15A and 15B. That is, the ideal state of the duty is “0”, and the value deviates from 0 according to the amount of deviation of the duty. . Therefore, by down-sampling this output and giving it to the average amplitude level calculation circuits 54A and 54B, the average amplitude level calculation circuits 54A and 54B give the value of the deviation amount of the duty, and correct the average amplitude level. be able to.
The control circuit 35 uses the corrected average amplitude level to control the selection circuit 36 in the process of FIG. 5 or FIG. 7, thereby enabling a more accurate selection operation.

Note that the duty deviation information is not limited to the correction of the average amplitude level but can be used as follows.
For example, it may be used for selection control in the control circuit 35.
For example, in a plurality of demodulation circuits, when a transmission line code is detected and the average amplitude level is the same, it may be possible to select a circuit that is close to the ideal state with a duty of 50%.
It is also possible to compare the duty with a certain threshold value and not select the output of the demodulation system circuit determined to be deteriorated.

  Although the embodiments have been described above, various modifications can be considered as the present invention. For example, in each of the above configuration examples, the case where two demodulation system circuits are provided corresponding to the two signal change detection circuits 10 and 20 has been described. However, three or more signal change detection circuits are provided, and corresponding to each. A configuration in which three or more systems of demodulation system circuits are provided and one of the outputs of each demodulation system circuit is selected by the selection circuit can also be derived from the above embodiments.

It is a block diagram of the basic composition of an embodiment of the invention. It is a block diagram of the basic composition of an embodiment. It is explanatory drawing about the transmission-line code | symbol detection of embodiment. It is a block diagram of composition example A of an embodiment. It is a flowchart of the example of a process of the selection control circuit of embodiment. It is a block diagram of Configuration Example B of the embodiment. It is a flowchart of the example of a process of the selection control circuit of embodiment. It is a block diagram of configuration example C of the embodiment. It is explanatory drawing of operation | movement of the structural example C of embodiment. It is a block diagram of structural example D of an embodiment. It is explanatory drawing of operation | movement of the structural example D of embodiment. It is a block diagram of the structural example E of embodiment. It is explanatory drawing of operation | movement of the structural example E of embodiment. It is a block diagram of composition example F of an embodiment. It is explanatory drawing of operation | movement of the structural example F of embodiment. It is a block diagram of a duty detection circuit of an embodiment. It is a schematic block diagram of an IC card and a reader / writer device. It is explanatory drawing of the structural example and packet structure of the conventional demodulation system. It is a block diagram of the structural example of the conventional demodulation system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Reader / writer apparatus, 2 Antenna circuit, 4 Selection demodulation circuit, 10,20 Signal change detection circuit, 31A, 31B A / D converter, 32A, 32B Synchronous circuit, 33A, 33B Transmission line code detection circuit, 34A, 34B , 54A, 54B Average amplitude level calculation circuit, 35 control circuit, 36 selection circuit, 37 error detection unit, 51A, 51B 1-bit A / D converter, 52A, 52B moving average filter, 53A, 53B peak detection circuit, 56A, 56B duty detection circuit, 61A, 61B timing generation circuit, 62A, 62B downsampler, 63A, 63B

Claims (15)

Each of a plurality of signal change detection circuits for detecting a signal change caused by load modulation for the received load modulation signal;
Each of the plurality of signal change detection circuits is provided in correspondence with each other, and performs processing for data demodulation based on the signal from the corresponding signal change detection circuit, and the signal from the corresponding signal change detection circuit. A plurality of demodulation circuits for detecting a transmission line code and an average amplitude level;
A selection circuit that selects one of the outputs of the plurality of demodulation circuits and outputs the received information;
A selection control circuit for controlling the selection state of the selection circuit using the detection result of the transmission line code and the average amplitude level of each of the plurality of demodulation circuits;
A communication apparatus comprising: The selection control circuit is one of a plurality of demodulation system circuits, and when the transmission line code is detected, causes the selection circuit to select the output of the demodulation system circuit from which the transmission line code is detected. ,
When the transmission line code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, the detection result of each average amplitude level in each demodulation system circuit in which the transmission line code is detected is obtained. The communication device according to claim 1, wherein the selection state of the selection circuit is controlled.   3. The communication according to claim 2, wherein the plurality of demodulation circuits convert analog signals from the corresponding signal change detection circuits into digital signals, and detect the average amplitude level of the digital signals. apparatus.   In the plurality of demodulation system circuits, analog signals from the corresponding signal change detection circuits are converted into digital signals by 1-bit A / D converters, and the digital signals output from the 1-bit A / D converters are moved. The communication apparatus according to claim 3, wherein the average amplitude level is detected by obtaining an average value, obtaining a peak value of the moving average value, and adding the peak values.   In the case where the transmission path code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, the selection control circuit, among the demodulation system circuits in which the transmission path code is detected, 5. The communication apparatus according to claim 4, wherein control is performed so that the output having the larger value of the detected average amplitude level is selected by the selection circuit.   In the plurality of demodulation system circuits, analog signals from the corresponding signal change detection circuits are converted into digital signals by 1-bit A / D converters, and the digital signals output from the 1-bit A / D converters are moved. 4. The communication apparatus according to claim 3, wherein an average value is obtained, a value at the zero point timing of the moving average value is obtained, and the average amplitude level is detected from the value at the zero point timing.   In the case where the transmission path code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, the selection control circuit, among the demodulation system circuits in which the transmission path code is detected, 7. The communication apparatus according to claim 6, wherein control is performed so that the output having the smaller value of the detected average amplitude level is selected by the selection circuit.   4. The communication according to claim 3, wherein each of the plurality of demodulation circuits performs duty detection on the digital signal, and uses the detected duty information as correction information when detecting the average amplitude level. apparatus.   3. The communication apparatus according to claim 2, wherein the plurality of demodulation circuits detect the average amplitude level of the analog signal from the corresponding signal change detection circuit.   The communication device according to claim 9, wherein the plurality of demodulation circuits detect the average amplitude level by integrating analog signals from the corresponding signal change detection circuits.   In the case where the transmission path code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, the selection control circuit, among the demodulation system circuits in which the transmission path code is detected, 10. The communication apparatus according to claim 9, wherein control is performed so that the output having the larger value of the detected average amplitude level is selected by the selection circuit. The selection control circuit has a predetermined value in each of the demodulation system circuits in which the transmission path code is detected by two or more demodulation system circuits of the plurality of demodulation system circuits and the transmission path code is detected. When the above average amplitude level is detected,
10. The communication apparatus according to claim 9, wherein control is performed so as to cause the selection circuit to select an output of a demodulation system circuit that is set in advance among the demodulation circuits in which the transmission path code is detected.   The communication apparatus according to claim 1, wherein one of the plurality of signal change detection circuits detects an amplitude change caused by load modulation in the received load modulation signal.   The communication apparatus according to claim 1, wherein one of the plurality of signal change detection circuits detects a phase change caused by load modulation with respect to the received load modulation signal. Each of a plurality of signal change detection circuits for detecting a signal change caused by load modulation for the received load modulation signal;
Each of the plurality of signal change detection circuits is provided in correspondence with each other, and performs processing for data demodulation based on the signal from the corresponding signal change detection circuit, and the signal from the corresponding signal change detection circuit. A plurality of demodulation circuits for detecting a transmission line code and an average amplitude level;
A selection circuit that selects one of the outputs of the plurality of demodulation circuits and outputs the received information;
As a method for demodulating a communication device equipped with
A transmission line code detection confirmation step for confirming a detection result of the transmission line code of each of the plurality of demodulation systems;
A first selection control step for causing the selection circuit to select an output of the demodulation system circuit in which the transmission path code is detected when the transmission path code is detected by one of the plurality of demodulation system circuits; ,
When the transmission line code is detected by two or more demodulation system circuits among the plurality of demodulation system circuits, the detection result of each average amplitude level in each demodulation system circuit in which the transmission line code is detected is obtained. Using a second selection control step for controlling the selection state of the selection circuit;
A demodulation method characterized by comprising:

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