JP2009118000A - Piezoelectric device - Google Patents

Piezoelectric device Download PDF

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Publication number
JP2009118000A
JP2009118000A JP2007286532A JP2007286532A JP2009118000A JP 2009118000 A JP2009118000 A JP 2009118000A JP 2007286532 A JP2007286532 A JP 2007286532A JP 2007286532 A JP2007286532 A JP 2007286532A JP 2009118000 A JP2009118000 A JP 2009118000A
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piezoelectric device
electrode
electrically connected
semiconductor chip
piezoelectric
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JP2009118000A5 (en
JP5158337B2 (en
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Yuichiro Takasu
雄一郎 高栖
Kazuhiko Shimodaira
和彦 下平
Makoto Komai
誠 駒井
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Miyazaki Epson Corp
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Miyazaki Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a piezoelectric device with a small plain size. <P>SOLUTION: A piezoelectric vibration chip 30 has first and second surfaces 40, 42 which face in opposite directions, and includes a vibration unit 32 which uses a part excluding peripheral parts of the first and second surfaces 40, 42 as front and rear surfaces, and a frame part 34 which uses a part surrounding the vibration unit 32 of the first and second surfaces 40, 42 as front and rear surfaces. First and second wirings 56, 58 are formed on the first and the second surfaces 40, 42 of the frame part 34, and electrically connected to first and second driving electrodes 52, 54. First and second convex parts 44, 46 are formed on the frame part 34 avoiding a region where the first and second wirings 56, 58 of the first and second surfaces 40, 42 are formed. The piezoelectric chip 30 is arranged between first and second semiconductor chips 10, 20, the first and second convex parts 44, 46 of the frame part 34 are respectively joined to the first and second semiconductor chips 10, 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、圧電デバイスに関する。   The present invention relates to a piezoelectric device.

特許文献１には、パッケージ内に圧電振動片及びＩＣチップを気密に封止する圧電発振器が開示され、特許文献２にも、発振回路を構成するＩＣチップと圧電振動片をパッケージ内に配置した構造が開示されている。これらの構造では、ＩＣチップ及び圧電振動片を重ねて配置するので、横に並べて配列するよりも平面サイズを小さくすることができる。しかし、近年、高機能化の要求から、発振回路以外にも付加的な回路（データ書き込み用回路、温度補償回路など）を備えたＩＣチップが使用されるようになってきている。その結果、ＩＣチップの平面サイズが大型化するので、圧電発振器の平面サイズも大型化するという問題があった。
特許第３６２０４５１号公報 特開平１１−３０８０５２号公報 Patent Document 1 discloses a piezoelectric oscillator that hermetically seals a piezoelectric vibrating piece and an IC chip in a package, and Patent Document 2 also arranges an IC chip and a piezoelectric vibrating piece constituting an oscillation circuit in the package. A structure is disclosed. In these structures, since the IC chip and the piezoelectric vibrating piece are arranged so as to overlap each other, the plane size can be made smaller than arranging them side by side. However, in recent years, IC chips equipped with additional circuits (a data writing circuit, a temperature compensation circuit, etc.) in addition to the oscillation circuit have been used due to the demand for higher functionality. As a result, since the planar size of the IC chip is increased, the planar size of the piezoelectric oscillator is also increased.
Japanese Patent No. 3620451 Japanese Patent Laid-Open No. 11-308052

本発明は、平面サイズの小さい圧電デバイスを提供することを目的とする。   An object of the present invention is to provide a piezoelectric device having a small planar size.

本発明は、上述の課題の少なくとも一部を解決するためになされたものであり、以下の形態又は適用例として実現することが可能である。
［適用例１］本適用例に係る圧電デバイスは、
第１の集積回路を内部に有する第１の半導体チップと、
第２の集積回路を内部に有する第２の半導体チップと、
振動部及び前記振動部を囲む枠部を有する圧電振動片と、
前記振動部に形成された励振電極と、
を有し、
前記励振電極は、前記第１及び第２の半導体チップの少なくともいずれか一方と電気的に接続され、
前記圧電振動片は、前記第１及び第２の半導体チップの間に配置され、
前記圧電振動片の前記枠部は、厚み方向において対向する第１および第２の接合面を有し、
前記枠部の前記第１の接合面が前記第１の半導体チップの一方の面に接合され、
前記枠部の前記第２の接合面が前記第２の半導体チップの一方の面に接合されてなる。 SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.
Application Example 1 A piezoelectric device according to this application example is
A first semiconductor chip having a first integrated circuit therein;
A second semiconductor chip having a second integrated circuit therein;
A piezoelectric vibrating piece having a vibrating portion and a frame portion surrounding the vibrating portion;
An excitation electrode formed on the vibrating portion;
Have
The excitation electrode is electrically connected to at least one of the first and second semiconductor chips;
The piezoelectric vibrating piece is disposed between the first and second semiconductor chips,
The frame portion of the piezoelectric vibrating piece has first and second joint surfaces that face each other in the thickness direction;
The first bonding surface of the frame portion is bonded to one surface of the first semiconductor chip;
The second bonding surface of the frame portion is bonded to one surface of the second semiconductor chip.

本適用例によれば、第１及び第２の半導体チップの間に圧電振動片が配置されるので平面サイズの小さい圧電デバイスを提供することができる。
［適用例２］本適用例に係る圧電デバイスにおいて、
前記枠部は、前記厚み方向において対向する第１および第２の面を有し、
前記枠部には前記第１の面に第１の凸部が形成され、前記第１の凸部の前記厚み方向の端面が前記第１の接合面とされ、
前記枠部には前記第２の面に第２の凸部が形成され、前記第１の凸部の前記厚み方向の端面が前記第２の接合面とされてなる。
［適用例３］本適用例に係る圧電デバイスにおいて、
前記第１の半導体チップは、前記第１の集積回路に電気的に接続された第１の電極を有し、
前記第２の半導体チップは、前記第２の集積回路に電気的に接続された第２の電極を有し、
前記励振電極は、第１及び第２の励振電極からなり、
前記枠部の前記第１の面上に形成され、前記第１の励振電極と電気的に接続され、前記第１及び第２の電極の少なくともいずれか一方の電極に電気的に接続されている第１の接続部を有する第１の配線と、
前記枠部の前記第２の面上に形成され、前記第２の励振電極と電気的に接続され、前記第１及び第２の電極の少なくともいずれか一方の電極に電気的に接続されている第２の接続部を有する第２の配線と、
を有する。
［適用例４］本適用例に係る圧電デバイスにおいて、
前記第１の凸部は、第１の切り欠きを有して前記振動部を囲む形状をなし、前記第１の切り欠きの位置を前記第１の配線が通り、
前記第２の凸部は、第２の切り欠きを有して前記振動部を囲む形状をなし、前記第２の切り欠きの位置を前記第２の配線が通る。
［適用例５］本適用例に係る圧電デバイスにおいて、
前記第１の凸部は、前記第１の接続部と前記振動部の間に形成され、
前記第２の凸部は、前記第２の接続部と前記振動部の間に形成されている。
［適用例６］本適用例に係る圧電デバイスにおいて、
前記圧電振動片は水晶からなり、
前記第１及び第２の半導体チップはそれぞれシリコン酸化膜を表面に有し、
前記第１及び第２の凸部は、直接接合によって、前記シリコン酸化膜に接合されている。
［適用例７］本適用例に係る圧電デバイスにおいて、
前記圧電振動片は、前記第１の面を、前記第１の半導体チップの前記第１の電極が形成された面に対向させて配置されている。
［適用例８］本適用例に係る圧電デバイスにおいて、
前記圧電振動片は、前記第１の接続部が前記第１の電極に対向するように配置されている。
［適用例９］本適用例に係る圧電デバイスにおいて、
前記圧電振動片は、前記第２の面を、前記第２の半導体チップの前記第２の電極が形成された面に対向させて配置されている。
［適用例１０］本適用例に係る圧電デバイスにおいて、
前記圧電振動片は、前記第２の接続部が前記第２の電極に対向するように配置されている。
［適用例１１］本適用例に係る圧電デバイスにおいて、
前記第１の半導体チップは、前記第１の電極が形成された面とは反対面に前記第１の集積回路と電気的に接続された第１の接続端子をさらに有し、
前記第２の半導体チップは、前記第２の電極が形成された面に前記第２の集積回路と電気的に接続された第２の接続端子をさらに有し、
前記第１及び第２の接続端子が導電体によって電気的に接続されている。
［適用例１２］本適用例に係る圧電デバイスにおいて、
前記第１の半導体チップは、前記第１の電極が形成された面に前記第１の集積回路と電気的に接続された第１の接続端子をさらに有し、
前記第２の半導体チップは、前記第２の電極が形成された面に前記第２の集積回路と電気的に接続された第２の接続端子をさらに有し、
前記第１及び第２の接続端子は、前記枠部を貫通する貫通孔に配置された部分を有する導電体によって電気的に接続されている。
［適用例１３］本適用例に係る圧電デバイスにおいて、
前記第１の半導体チップは、前記第１の電極が形成された面に前記第１の集積回路と電気的に接続された第１の接続端子をさらに有し、
前記第２の半導体チップは、前記第２の電極が形成された面に前記第２の集積回路と電気的に接続された第２の接続端子をさらに有し、
前記第１及び第２の接続端子は、前記圧電振動片の前記周縁部の側面上に配置された部分を有する導電体によって電気的に接続されている。
［適用例１４］本適用例に係る圧電デバイスにおいて、
前記第２の半導体チップは、前記第２の電極が形成された面とは反対面に、前記第２の集積回路と電気的に接続された外部端子を有する。 According to this application example, since the piezoelectric vibrating piece is disposed between the first and second semiconductor chips, a piezoelectric device having a small planar size can be provided.
[Application Example 2] In the piezoelectric device according to this application example,
The frame portion has first and second surfaces opposed in the thickness direction,
The frame portion is formed with a first convex portion on the first surface, and the end surface in the thickness direction of the first convex portion is the first joint surface,
In the frame portion, a second convex portion is formed on the second surface, and an end surface in the thickness direction of the first convex portion serves as the second joint surface.
Application Example 3 In the piezoelectric device according to this application example,
The first semiconductor chip has a first electrode electrically connected to the first integrated circuit,
The second semiconductor chip has a second electrode electrically connected to the second integrated circuit;
The excitation electrode includes first and second excitation electrodes,
Formed on the first surface of the frame portion, electrically connected to the first excitation electrode, and electrically connected to at least one of the first and second electrodes. A first wiring having a first connection portion;
Formed on the second surface of the frame, electrically connected to the second excitation electrode, and electrically connected to at least one of the first and second electrodes A second wiring having a second connection portion;
Have
Application Example 4 In the piezoelectric device according to this application example,
The first convex portion has a first notch and surrounds the vibrating portion, and the first wiring passes through the position of the first notch,
The second convex portion has a second notch and surrounds the vibrating portion, and the second wiring passes through the position of the second notch.
Application Example 5 In the piezoelectric device according to this application example,
The first convex portion is formed between the first connecting portion and the vibrating portion,
The second convex portion is formed between the second connection portion and the vibration portion.
Application Example 6 In the piezoelectric device according to this application example,
The piezoelectric vibrating piece is made of quartz,
Each of the first and second semiconductor chips has a silicon oxide film on the surface,
The first and second protrusions are bonded to the silicon oxide film by direct bonding.
Application Example 7 In the piezoelectric device according to this application example,
The piezoelectric vibrating piece is disposed with the first surface facing the surface of the first semiconductor chip on which the first electrode is formed.
Application Example 8 In the piezoelectric device according to the application example,
The piezoelectric vibrating piece is disposed so that the first connection portion faces the first electrode.
Application Example 9 In the piezoelectric device according to this application example,
The piezoelectric vibrating reed is disposed with the second surface facing the surface on which the second electrode of the second semiconductor chip is formed.
Application Example 10 In the piezoelectric device according to the application example,
The piezoelectric vibrating piece is disposed so that the second connection portion faces the second electrode.
Application Example 11 In the piezoelectric device according to the application example,
The first semiconductor chip further includes a first connection terminal electrically connected to the first integrated circuit on a surface opposite to the surface on which the first electrode is formed,
The second semiconductor chip further includes a second connection terminal electrically connected to the second integrated circuit on a surface on which the second electrode is formed,
The first and second connection terminals are electrically connected by a conductor.
Application Example 12 In the piezoelectric device according to the application example,
The first semiconductor chip further includes a first connection terminal electrically connected to the first integrated circuit on a surface on which the first electrode is formed,
The second semiconductor chip further includes a second connection terminal electrically connected to the second integrated circuit on a surface on which the second electrode is formed,
The first and second connection terminals are electrically connected by a conductor having a portion disposed in a through hole that penetrates the frame portion.
[Application Example 13] In the piezoelectric device according to this application example,
The first semiconductor chip further includes a first connection terminal electrically connected to the first integrated circuit on a surface on which the first electrode is formed,
The second semiconductor chip further includes a second connection terminal electrically connected to the second integrated circuit on a surface on which the second electrode is formed,
The first and second connection terminals are electrically connected by a conductor having a portion disposed on a side surface of the peripheral portion of the piezoelectric vibrating piece.
[Application Example 14] In the piezoelectric device according to this application example,
The second semiconductor chip has an external terminal electrically connected to the second integrated circuit on a surface opposite to the surface on which the second electrode is formed.

（第１の実施の形態）
図１は、本発明の第１の実施の形態に係る圧電デバイスの平面図である。図２は、図１に示す圧電デバイスの正面図である。図３は、図１に示す圧電デバイスのIII−III線断面図である。図４は、図１に示す圧電デバイスの左側面図である。図５は、図１に示す圧電デバイスのＶ−Ｖ線断面図である。図６は、図１に示す圧電デバイスの底面図である。 (First embodiment)
FIG. 1 is a plan view of the piezoelectric device according to the first embodiment of the present invention. FIG. 2 is a front view of the piezoelectric device shown in FIG. FIG. 3 is a cross-sectional view of the piezoelectric device shown in FIG. 1 taken along the line III-III. FIG. 4 is a left side view of the piezoelectric device shown in FIG. FIG. 5 is a cross-sectional view of the piezoelectric device shown in FIG. FIG. 6 is a bottom view of the piezoelectric device shown in FIG.

圧電デバイスは第１の半導体チップ１０を有する。第１の半導体チップ１０は、第１の集積回路１２を内部（表層部）に有し、第１の集積回路１２に電気的に接続された第１の電極１４を有する。第１の電極１４は、第１の集積回路１２が形成された表層部の表面に形成されている。第１の半導体チップ１０は、第１の電極１４が形成された面とは反対面に第１の集積回路１２と電気的に接続された第１の接続端子１６をさらに有する。第１の電極１４と第１の接続端子１６は、図示しない貫通電極によって電気的に接続されていてもよい。第１の半導体チップ１０は、シリコン酸化膜１８を表面（少なくとも第１の電極１４が形成された面）に有する。   The piezoelectric device has a first semiconductor chip 10. The first semiconductor chip 10 has a first integrated circuit 12 inside (surface layer portion) and has a first electrode 14 electrically connected to the first integrated circuit 12. The first electrode 14 is formed on the surface of the surface layer portion where the first integrated circuit 12 is formed. The first semiconductor chip 10 further includes a first connection terminal 16 that is electrically connected to the first integrated circuit 12 on the surface opposite to the surface on which the first electrode 14 is formed. The first electrode 14 and the first connection terminal 16 may be electrically connected by a through electrode (not shown). The first semiconductor chip 10 has a silicon oxide film 18 on the surface (at least the surface on which the first electrode 14 is formed).

圧電デバイスは第２の半導体チップ２０を有する。第２の半導体チップ２０は、第２の集積回路２２を内部（表層部）に有し、第２の集積回路２２に電気的に接続された第２の電極２４を有する。第２の電極２４は、第２の集積回路２２が形成された表層部の表面に形成されている。第２の半導体チップ２０は、第２の電極２４が形成された面に第２の集積回路２２と電気的に接続された第２の接続端子２６をさらに有する。第２の半導体チップ２０は、第２の電極２４が形成された面とは反対面に、第２の集積回路２２と電気的に接続された外部端子２８を有する。外部端子２８には、図示しないハンダボールを設けてもよい。第２の電極２４と外部端子２８は、図示しない貫通電極によって電気的に接続されていてもよい。第２の半導体チップ２０は、シリコン酸化膜１８を表面（少なくとも第２の電極２４が形成された面）に有する。本実施の形態では、第２の半導体チップ２０の第２の電極２４が形成された面は、第１の半導体チップ１０の第１の電極１４が形成された面よりも大きい。   The piezoelectric device has a second semiconductor chip 20. The second semiconductor chip 20 has a second integrated circuit 22 inside (surface layer portion), and has a second electrode 24 electrically connected to the second integrated circuit 22. The second electrode 24 is formed on the surface of the surface layer portion where the second integrated circuit 22 is formed. The second semiconductor chip 20 further has a second connection terminal 26 electrically connected to the second integrated circuit 22 on the surface on which the second electrode 24 is formed. The second semiconductor chip 20 has an external terminal 28 electrically connected to the second integrated circuit 22 on the surface opposite to the surface on which the second electrode 24 is formed. The external terminal 28 may be provided with a solder ball (not shown). The second electrode 24 and the external terminal 28 may be electrically connected by a through electrode (not shown). The second semiconductor chip 20 has the silicon oxide film 18 on the surface (the surface on which at least the second electrode 24 is formed). In the present embodiment, the surface of the second semiconductor chip 20 on which the second electrode 24 is formed is larger than the surface of the first semiconductor chip 10 on which the first electrode 14 is formed.

図７（Ａ）は、第１の実施の形態に係る圧電デバイスの圧電振動片の平面図である。図７（Ｂ）は、図７（Ａ）に示す圧電振動片のＢ−Ｂ線断面図である。図７（Ｃ）は、図７（Ａ）に示す圧電振動片のＣ−Ｃ線断面図である。図７（Ｄ）は、図７（Ａ）に示す圧電振動片の底面図である。   FIG. 7A is a plan view of the piezoelectric vibrating piece of the piezoelectric device according to the first embodiment. FIG. 7B is a cross-sectional view of the piezoelectric vibrating piece shown in FIG. FIG. 7C is a cross-sectional view of the piezoelectric vibrating piece shown in FIG. FIG. 7D is a bottom view of the piezoelectric vibrating piece shown in FIG.

圧電デバイスは、圧電振動片３０を有する。圧電振動片３０は水晶からなる。圧電振動片３０は、相互に反対を向く第１及び第２の面４０，４２を有する。圧電振動片３０は、第１及び第２の面４０，４２の周縁部を除く部分（例えば中央部）を表裏面とする振動部３２と、第１及び第２の面４０，４２の振動部３２を囲む部分（例えば周縁部）を表裏面とする枠部３４と、を含む。圧電振動片３０は、振動部３２と枠部３４を接続する少なくとも１つ（図７（Ａ）では２つ）の連結部３６を有する。詳しくは、振動部３２から相互に反対方向に一対の連結部３６が形成されている。振動部３２と枠部３４は、連結部３６にて連結される部分を除いて、スリット３８にて分離されている。   The piezoelectric device has a piezoelectric vibrating piece 30. The piezoelectric vibrating piece 30 is made of quartz. The piezoelectric vibrating piece 30 has first and second surfaces 40 and 42 facing opposite to each other. The piezoelectric vibrating piece 30 includes a vibrating portion 32 having front and rear surfaces of the first and second surfaces 40 and 42 excluding the peripheral portions (for example, the central portion), and the vibrating portions of the first and second surfaces 40 and 42. And a frame portion 34 having front and rear surfaces of a portion (for example, a peripheral portion) surrounding 32. The piezoelectric vibrating piece 30 has at least one (two in FIG. 7A) connecting portion 36 that connects the vibrating portion 32 and the frame portion 34. Specifically, a pair of connecting portions 36 are formed in the opposite directions from the vibrating portion 32. The vibrating part 32 and the frame part 34 are separated by a slit 38 except for the part connected by the connecting part 36.

振動部３２の第１の面４０上には第１の励振電極５２が形成されている。振動部３２の第２の面４２上には第２の励振電極５４が形成されている。第１及び第２の励振電極５２，５４によって振動部３２が挟まれており、印加される電圧によって振動部３２が振動する。   A first excitation electrode 52 is formed on the first surface 40 of the vibration part 32. A second excitation electrode 54 is formed on the second surface 42 of the vibration part 32. The vibration part 32 is sandwiched between the first and second excitation electrodes 52 and 54, and the vibration part 32 vibrates by an applied voltage.

枠部３４の第１の面４０上には、第１の配線５６が形成されている。第１の配線５６は、第１の電極１４に電気的に接続するための第１の接続部６０を有する。第１の配線５６は、第１の励振電極５２と電気的に接続されている。電気的接続のため、第１の配線５６は、連結部３６上に形成される部分を有する。枠部３４の第２の面４２上には、第２の配線５８が形成されている。第２の配線５８は、第２の電極２４に電気的に接続するための第２の接続部６２を有する。第２の配線５８は、第２の励振電極５４と電気的に接続されている。電気的接続のため、第２の配線５８は、連結部３６上に形成される部分を有する。相互に反対方向に延びる一対の連結部３６の一方に第１の配線５６の一部が形成され、他方に第２の配線５８の一部が形成されている。したがって、第１及び第２の配線５６，５８は、オーバーラップしないようになっている。   A first wiring 56 is formed on the first surface 40 of the frame portion 34. The first wiring 56 has a first connection portion 60 for electrically connecting to the first electrode 14. The first wiring 56 is electrically connected to the first excitation electrode 52. For electrical connection, the first wiring 56 has a portion formed on the coupling portion 36. A second wiring 58 is formed on the second surface 42 of the frame portion 34. The second wiring 58 has a second connection portion 62 for electrically connecting to the second electrode 24. The second wiring 58 is electrically connected to the second excitation electrode 54. For electrical connection, the second wiring 58 has a portion formed on the coupling portion 36. A part of the first wiring 56 is formed on one of the pair of connecting portions 36 extending in opposite directions, and a part of the second wiring 58 is formed on the other. Therefore, the first and second wirings 56 and 58 are not overlapped.

枠部３４には、第１の面４０に第１の凸部４４が形成されている。第１の凸部４４は、第１の配線５６が形成された領域を避けて形成されている。第１の凸部４４は、第１の接続部６０と振動部３２の間に形成されている。第１の凸部４４は、１箇所のみの第１の切り欠き４８を有して振動部３２を囲む形状をなしている。第１の凸部４４は、スリット３８に隣接して形成されている。第１の切り欠き４８の位置を第１の配線５６が通る。枠部３４には、第２の面４２に第２の凸部４６が形成されている。第２の凸部４６は、第２の配線５８が形成された領域を避けて形成されている。第２の凸部４６は、第２の接続部６２と振動部３２の間に形成されている。第２の凸部４６は、１箇所のみの第２の切り欠き５０を有して振動部３２を囲む形状をなしている。第２の凸部４６は、スリット３８に隣接して形成されている。第２の切り欠き５０の位置を第２の配線５８が通る。第１及び第２の凸部４４，４６は、それぞれ、第１及び第２の配線５６，５８の厚みよりも高くなるように形成されている。   A first convex portion 44 is formed on the first surface 40 of the frame portion 34. The first convex portion 44 is formed so as to avoid the region where the first wiring 56 is formed. The first convex portion 44 is formed between the first connection portion 60 and the vibration portion 32. The first convex portion 44 has a shape that surrounds the vibrating portion 32 by having the first notch 48 at only one location. The first convex portion 44 is formed adjacent to the slit 38. The first wiring 56 passes through the position of the first notch 48. A second convex portion 46 is formed on the second surface 42 of the frame portion 34. The second convex portion 46 is formed to avoid the region where the second wiring 58 is formed. The second convex portion 46 is formed between the second connecting portion 62 and the vibrating portion 32. The second convex portion 46 has a shape that surrounds the vibrating portion 32 by having the second notch 50 at only one location. The second convex portion 46 is formed adjacent to the slit 38. The second wiring 58 passes through the position of the second notch 50. The first and second convex portions 44 and 46 are formed to be higher than the thickness of the first and second wirings 56 and 58, respectively.

圧電振動片３０は、第１及び第２の半導体チップ１０，２０の間に配置されている。枠部３４の第１及び第２の凸部４４，４６の厚み方向の端面がそれぞれ第１及び第２の半導体チップ１０，２０に接合されている。第１及び第２の凸部４４，４６の厚み方向の端面は、枠部３４の第１及び第２の接合面である。第１及び第２の凸部４４，４６は、直接接合によって、第１及び第２の半導体チップ１０，２０のシリコン酸化膜１８（その平坦な表面）に接合されている。直接接合を適用するために、第１及び第２の凸部４４，４６の表面は圧電振動片３０を構成している水晶が露出している。直接接合の代わりに陽極接合を適用してもよい。   The piezoelectric vibrating piece 30 is disposed between the first and second semiconductor chips 10 and 20. End faces in the thickness direction of the first and second convex portions 44 and 46 of the frame portion 34 are joined to the first and second semiconductor chips 10 and 20, respectively. The end surfaces in the thickness direction of the first and second convex portions 44 and 46 are the first and second joint surfaces of the frame portion 34. The first and second convex portions 44 and 46 are bonded to the silicon oxide film 18 (the flat surface thereof) of the first and second semiconductor chips 10 and 20 by direct bonding. In order to apply direct bonding, the crystal forming the piezoelectric vibrating piece 30 is exposed on the surfaces of the first and second convex portions 44 and 46. Anodic bonding may be applied instead of direct bonding.

第１及び第２の凸部４４，４６と第１及び第２の半導体チップ１０，２０は、気密に接合している。また、図２及び図３に示すように、第２の切り欠き５０には封止材７０が設けられ、同様に、第１の切り欠き４８にも封止材（図示せず）が設けられている。封止材７０は、電気的な導通が問題にならなければハンダ等の導電材料であってもよいし、電気的な絶縁を図る必要があればガラスであってもよい。ハンダ又はガラスは溶融して第１及び第２の切り欠き４８，５０に設ける。封止材７０によって、第１及び第２の切り欠き４８，５０が気密に塞がれている。したがって、第１及び第２の凸部４４，４６並びに封止材７０によって囲まれたスペースは気密に封止されており、このスペースは真空になっていてもよいし、空気以外のガス（窒素等）が充填されていてもよい。   The first and second convex portions 44 and 46 and the first and second semiconductor chips 10 and 20 are airtightly joined. As shown in FIGS. 2 and 3, the second cutout 50 is provided with a sealing material 70, and similarly, the first cutout 48 is provided with a sealing material (not shown). ing. The sealing material 70 may be a conductive material such as solder if electrical continuity is not a problem, and may be glass if electrical insulation is required. Solder or glass is melted and provided in the first and second cutouts 48 and 50. The first and second cutouts 48 and 50 are hermetically closed by the sealing material 70. Therefore, the space surrounded by the first and second convex portions 44 and 46 and the sealing material 70 is hermetically sealed, and this space may be in a vacuum, or a gas other than air (nitrogen) Etc.) may be filled.

図８は、第１の半導体チップと圧電振動片の取り付けの詳細を説明する分解図である。図９は、第２の半導体チップと圧電振動片の取り付けの詳細を説明する分解図である。圧電振動片３０は、第１の面４０を、第１の半導体チップ１０の第１の電極１４が形成された面に対向させて配置されている。圧電振動片３０は、第１の接続部６０が第１の電極１４に対向するように配置されている。第１の接続部６０と第１の電極１４の間には、導電部材６６（例えばハンダ）が設けられて両者を電気的に接続している。圧電振動片３０は、第２の面４２を、第２の半導体チップ２０の第２の電極２４が形成された面に対向させて配置されている。圧電振動片３０は、第２の接続部６２が第２の電極２４に対向するように配置されている。第２の接続部６２と第２の電極２４の間には、導電部材６６（例えばハンダ）が設けられて両者を電気的に接続している。   FIG. 8 is an exploded view illustrating details of attachment of the first semiconductor chip and the piezoelectric vibrating piece. FIG. 9 is an exploded view illustrating details of attachment of the second semiconductor chip and the piezoelectric vibrating piece. The piezoelectric vibrating piece 30 is arranged with the first surface 40 facing the surface on which the first electrode 14 of the first semiconductor chip 10 is formed. The piezoelectric vibrating piece 30 is disposed so that the first connection portion 60 faces the first electrode 14. A conductive member 66 (for example, solder) is provided between the first connection portion 60 and the first electrode 14 to electrically connect them. The piezoelectric vibrating piece 30 is disposed with the second surface 42 facing the surface on which the second electrode 24 of the second semiconductor chip 20 is formed. The piezoelectric vibrating piece 30 is disposed so that the second connection portion 62 faces the second electrode 24. A conductive member 66 (for example, solder) is provided between the second connection portion 62 and the second electrode 24 to electrically connect them.

図１に示すように、第１の半導体チップ１０の第１の接続端子１６と第２の半導体チップ２０の第２の接続端子２６が導電体６４（例えばワイヤ）によって電気的に接続されている。また、導電体６４を封止する樹脂６８を設けてもよい。樹脂６８は、第１及び第２の接続端子１６，２６をさらに覆ってもよい。樹脂６８は、第１の半導体チップ１０をさらに覆ってもよいし、圧電振動片３０を覆ってもよい。樹脂６８は、第２の半導体チップ２０の第２の接続端子２６が形成された面を覆ってもよい。   As shown in FIG. 1, the first connection terminal 16 of the first semiconductor chip 10 and the second connection terminal 26 of the second semiconductor chip 20 are electrically connected by a conductor 64 (for example, a wire). . Further, a resin 68 for sealing the conductor 64 may be provided. The resin 68 may further cover the first and second connection terminals 16 and 26. The resin 68 may further cover the first semiconductor chip 10 or the piezoelectric vibrating piece 30. The resin 68 may cover the surface of the second semiconductor chip 20 on which the second connection terminals 26 are formed.

圧電デバイスの機能は次の通りである。第１の集積回路１２は、温度センサを含む。温度センサは温度変化によって出力信号が変化する。第１の集積回路１２は、温度補償電圧生成回路を含む。温度補償電圧生成回路は、温度センサからの出力信号に基づいて温度補償電圧を出力する。第２の集積回路２２の少なくとも一部と圧電振動片３０によって電圧制御型発振回路が構成されており、温度補償電圧に応じた周波数の発振信号を発振回路は出力する。すなわち、温度が変化すると圧電振動片３０の振動周波数が変動するが、振動周波数の変動を修正するようになっている。   The function of the piezoelectric device is as follows. The first integrated circuit 12 includes a temperature sensor. The output signal of the temperature sensor changes depending on the temperature change. The first integrated circuit 12 includes a temperature compensation voltage generation circuit. The temperature compensation voltage generation circuit outputs a temperature compensation voltage based on an output signal from the temperature sensor. At least a part of the second integrated circuit 22 and the piezoelectric vibrating piece 30 constitute a voltage-controlled oscillation circuit, and the oscillation circuit outputs an oscillation signal having a frequency corresponding to the temperature compensation voltage. That is, when the temperature changes, the vibration frequency of the piezoelectric vibrating piece 30 varies, but the variation of the vibration frequency is corrected.

本実施の形態によれば、第１及び第２の半導体チップ１０，２０の間に圧電振動片３０が配置されるので平面サイズの小さい圧電デバイスを提供することができる。また、第１及び第２の配線５６，５８を避けた第１及び第２の凸部４４，４６が、第１及び第２の半導体チップ１０，２０に接合されるので、第１及び第２の配線５６，５８と第１及び第２の半導体チップ１０，２０の好ましくない電気的接続を避けることができる。本実施の形態に係る電子デバイスの製造方法は、上述した電子デバイスの構成から自明な方法を含む。   According to the present embodiment, since the piezoelectric vibrating piece 30 is disposed between the first and second semiconductor chips 10 and 20, a piezoelectric device having a small planar size can be provided. In addition, the first and second protrusions 44 and 46 that avoid the first and second wirings 56 and 58 are joined to the first and second semiconductor chips 10 and 20. Undesirable electrical connection between the wirings 56 and 58 and the first and second semiconductor chips 10 and 20 can be avoided. The method for manufacturing an electronic device according to the present embodiment includes a method that is obvious from the configuration of the electronic device described above.

（第２の実施の形態）
図１０及び図１１は、それぞれ、本発明の第２の実施の形態に係る圧電デバイスの断面図である。図１２は、第２の実施の形態に係る圧電デバイスの圧電振動片を示す平面図である。なお、図１０に示す圧電振動片の断面は、図１２に示すＸ−Ｘ線断面に対応し、図１１に示す圧電振動片の断面は、図１２に示すXI−XI線断面に対応する。 (Second Embodiment)
10 and 11 are cross-sectional views of the piezoelectric device according to the second embodiment of the present invention, respectively. FIG. 12 is a plan view showing the piezoelectric vibrating piece of the piezoelectric device according to the second embodiment. The cross section of the piezoelectric vibrating piece shown in FIG. 10 corresponds to the XX line cross section shown in FIG. 12, and the cross section of the piezoelectric vibrating piece shown in FIG. 11 corresponds to the XI-XI line cross section shown in FIG.

本実施の形態では、第１の集積回路１１２が形成された第１の半導体チップ１１０は、第１の接続端子１１６が第１の電極１１４が形成された面に形成されている点で、第１の実施の形態に係る第１の半導体チップ１０とは異なる。すなわち、第１の半導体チップ１１０の同一面に、少なくとも１つの第１の電極１１４と、少なくとも１つの第１の接続端子１１６が形成されている。第１の電極１１４及び第１の接続端子１１６は同じ平面形状であってもよく、複数の第１の接続端子１１６と少なくとも１つの第１の電極１１４が一列に並んでいてもよい。その列において、第１の電極１１４は、一対の第１の接続端子１１６の間に位置していてもよい。第２の半導体チップ１２０は、第２の電極１２４が形成された面に第２の集積回路１２２と電気的に接続された第２の接続端子１２６を有する。   In the present embodiment, the first semiconductor chip 110 on which the first integrated circuit 112 is formed has the first connection terminal 116 formed on the surface on which the first electrode 114 is formed. This is different from the first semiconductor chip 10 according to the first embodiment. That is, at least one first electrode 114 and at least one first connection terminal 116 are formed on the same surface of the first semiconductor chip 110. The first electrode 114 and the first connection terminal 116 may have the same planar shape, and the plurality of first connection terminals 116 and at least one first electrode 114 may be arranged in a line. In the column, the first electrode 114 may be located between the pair of first connection terminals 116. The second semiconductor chip 120 has a second connection terminal 126 that is electrically connected to the second integrated circuit 122 on the surface on which the second electrode 124 is formed.

第１及び第２の接続端子１１６，１２６は、対向するように配置されている。第１及び第２の半導体チップ１１０，１２０は、平面形状が同じ（同じ大きさ）になっている。第１及び第２の半導体チップ１１０，１２０のそれ以外の構成については、第１の実施の形態で説明した第１及び第２の半導体チップ１０，２０の内容が該当する。   The first and second connection terminals 116 and 126 are arranged to face each other. The first and second semiconductor chips 110 and 120 have the same planar shape (the same size). The other configurations of the first and second semiconductor chips 110 and 120 correspond to the contents of the first and second semiconductor chips 10 and 20 described in the first embodiment.

第１及び第２の半導体チップ１１０，１２０の間には圧電振動片１３０が配置されている。圧電振動片１３０は、振動部１３２及び枠部１３４を有する。枠部１３４には、第１及び第２の凸部１４４，１４６を避けて、第１及び第２の面１４０，１４２を貫通するように１つ又は複数の貫通孔１７２が形成されている。貫通孔１７２は、対向する第１及び第２の接続端子１１６，１２６の間に位置している。第１及び第２の接続端子１１６，１２６は、貫通孔１７２に配置された部分を有する導電体１６４によって電気的に接続されている。詳しくは、導電体１６４は、貫通孔１７２内の部分と、貫通孔１７２とオーバーラップするように第１及び第２の面１４０，１４２に形成された部分と、第１及び第２の接続端子１１６，１２６と接合される部分（例えばハンダ）と、を含む。圧電振動片１３０のそれ以外の構成については、第１の実施の形態で説明した圧電振動片３０の内容が該当する。例えば、第１及び第２の凸部１４４，１４６には、切り欠き１５０が形成され、切り欠き１５０の位置を第１及び第２の配線１５６，１５８が通る。また、切り欠き１５０には封止材１７０が設けられている。   A piezoelectric vibrating piece 130 is disposed between the first and second semiconductor chips 110 and 120. The piezoelectric vibrating piece 130 includes a vibrating part 132 and a frame part 134. One or more through holes 172 are formed in the frame portion 134 so as to penetrate the first and second surfaces 140 and 142, avoiding the first and second convex portions 144 and 146. The through hole 172 is located between the first and second connection terminals 116 and 126 facing each other. The first and second connection terminals 116 and 126 are electrically connected by a conductor 164 having a portion disposed in the through hole 172. Specifically, the conductor 164 includes a portion in the through hole 172, a portion formed on the first and second surfaces 140 and 142 so as to overlap the through hole 172, and the first and second connection terminals. 116 and 126 (for example, solder). The other configuration of the piezoelectric vibrating piece 130 corresponds to the content of the piezoelectric vibrating piece 30 described in the first embodiment. For example, a cutout 150 is formed in the first and second convex portions 144 and 146, and the first and second wirings 156 and 158 pass through the position of the cutout 150. The notch 150 is provided with a sealing material 170.

図１１に示すように、枠部１３４には、第１の配線１５６の第１の接続部１６０とオーバーラップする位置には貫通孔１７２が形成されておらず、第２の配線１５８の第２の接続部１６２とオーバーラップする位置にも貫通孔１７２が形成されていない。ただし、第１の半導体チップ１１０の第１の電極１１４とオーバーラップする位置には、第２の半導体チップ１２０に第２の接続端子１２６を形成し、第２の半導体チップ１２０の第２の電極１２４とオーバーラップする位置には、第１の半導体チップ１１０に第１の接続端子１１６を形成してもよい。この場合の第１及び第２の接続端子１１６，１２６は、第１及び第２の電極１２４に電気的に接続されないのでダミー端子であるため、第１及び第２の集積回路１１２，１２２と電気的に接続されていなくてもよいし、電気的に接続されていてもよい。変形例として、この位置にも貫通孔を形成し、貫通孔に配置された部分を有する導電体によって、第１の配線１５６の第１の接続部１６０と第２の接続端子１２６（又は第２の配線１５８の第２の接続部１６２と第１の接続端子１１６）を電気的に接続してもよい。   As shown in FIG. 11, in the frame portion 134, the through hole 172 is not formed at a position overlapping the first connection portion 160 of the first wiring 156, and the second wiring 158 has a second shape. The through hole 172 is not formed at a position overlapping the connecting portion 162. However, the second connection terminal 126 is formed on the second semiconductor chip 120 at a position overlapping the first electrode 114 of the first semiconductor chip 110, and the second electrode of the second semiconductor chip 120 is formed. The first connection terminal 116 may be formed on the first semiconductor chip 110 at a position overlapping with the first semiconductor chip 110. In this case, the first and second connection terminals 116 and 126 are dummy terminals because they are not electrically connected to the first and second electrodes 124, and thus are electrically connected to the first and second integrated circuits 112 and 122. May not be electrically connected, or may be electrically connected. As a modified example, a through hole is also formed at this position, and the first connecting portion 160 and the second connecting terminal 126 (or the second connecting terminal 126) of the first wiring 156 are formed by a conductor having a portion disposed in the through hole. The second connection portion 162 of the wiring 158 and the first connection terminal 116) may be electrically connected.

本実施の形態でも、第１の実施の形態で説明した効果を達成することができ、同じ大きさの第１及び第２の半導体チップ１１０，１２０を使用することで圧電デバイスの平面サイズをさらに小型化することができる。なお、第１及び第２の凸部１４４，１４６の外側であって、枠部１３４と第１及び第２の半導体チップ１１０，１２０の間のスペースは樹脂等によって封止してもよい。   Also in this embodiment, the effect described in the first embodiment can be achieved, and the planar size of the piezoelectric device can be further increased by using the first and second semiconductor chips 110 and 120 having the same size. It can be downsized. The space between the frame portion 134 and the first and second semiconductor chips 110 and 120 outside the first and second convex portions 144 and 146 may be sealed with resin or the like.

（第３の実施の形態）
図１３及び図１４は、それぞれ、本発明の第３の実施の形態に係る圧電デバイスの断面図である。図１５は、第３の実施の形態に係る圧電デバイスの圧電振動片を示す平面図である。なお、図１３に示す圧電振動片の断面は、図１５に示すXIII−XIII線断面に対応し、図１４に示す圧電振動片の断面は、図１５に示すXIV−XIV線断面に対応する。 (Third embodiment)
13 and 14 are cross-sectional views of the piezoelectric device according to the third embodiment of the present invention, respectively. FIG. 15 is a plan view showing the piezoelectric vibrating piece of the piezoelectric device according to the third embodiment. 13 corresponds to the XIII-XIII line cross section shown in FIG. 15, and the cross section of the piezoelectric vibration piece shown in FIG. 14 corresponds to the XIV-XIV line cross section shown in FIG.

本実施の形態では、圧電振動片２３０の枠部２３４に貫通孔を形成せずに、導電体２６４が圧電振動片２３０（枠部２３４）の周縁部の側面上に配置された部分を有する点で第２の実施の形態と異なる。導電体２６４は、圧電振動片２３０（枠部２３４）の第１及び第２の面２４０，２４２に配置された部分も有する。なお、枠部２３４の周縁部には切り欠き２６６が形成され、切り欠き２６６に導電体２６４が形成されている。   In the present embodiment, the conductor 264 has a portion disposed on the side surface of the peripheral portion of the piezoelectric vibrating piece 230 (frame portion 234) without forming a through hole in the frame portion 234 of the piezoelectric vibrating piece 230. This is different from the second embodiment. The conductor 264 also includes portions disposed on the first and second surfaces 240 and 242 of the piezoelectric vibrating piece 230 (frame portion 234). Note that a notch 266 is formed in the peripheral portion of the frame portion 234, and a conductor 264 is formed in the notch 266.

第１の半導体チップ２１０は、第１の電極２１４が形成された面に第１の集積回路２１２と電気的に接続された第１の接続端子２１６をさらに有する。第２の半導体チップ２２０は、第２の電極２２４が形成された面に第２の集積回路２２２と電気的に接続された第２の接続端子２２６をさらに有する。第１及び第２の接続端子２１６，２２６は、導電体２６４によって電気的に接続されている。   The first semiconductor chip 210 further has a first connection terminal 216 that is electrically connected to the first integrated circuit 212 on the surface on which the first electrode 214 is formed. The second semiconductor chip 220 further includes a second connection terminal 226 electrically connected to the second integrated circuit 222 on the surface on which the second electrode 224 is formed. The first and second connection terminals 216 and 226 are electrically connected by a conductor 264.

図１４に示すように、第１の半導体チップ２１０の第１の電極２１４とオーバーラップする位置には、第２の半導体チップ２２０に第２の接続端子が形成されておらず、第２の半導体チップ２２０の第２の電極２２４とオーバーラップする位置には、第１の半導体チップ２１０に第１の接続端子が形成されていない。しかし、第１の接続部２６０が、圧電振動片２３０（枠部２３４）の周縁部の側面上に延長し、さらに、第２の面２４２に至るように形成されている。同様に、第２の接続部２６２が、圧電振動片２３０（枠部２３４）の周縁部の側面上に延長し、さらに、第１の面２４０に至るように形成されている。変形例として、図１４には示されていない第１及び第２の接続端子を、第２及び第１の接続部２６２，２６０と対向するように形成してもよい。そして、対向する第１の接続部２６０と図示しない第２の接続端子（又は対向する第２の接続部２６２と図示しない第１の接続端子）を電気的に接続してもよい。なお、第１及び第２の集積回路２１２，２２２に電気的に接続される第１及び第２の接続端子２１６，２２６の代わりに、第１及び第２の集積回路２１２，２２２に電気的に接続されないダミー端子を設けてもよい。   As shown in FIG. 14, the second connection terminal is not formed on the second semiconductor chip 220 at the position overlapping the first electrode 214 of the first semiconductor chip 210, and the second semiconductor chip The first connection terminal is not formed on the first semiconductor chip 210 at a position overlapping the second electrode 224 of the chip 220. However, the first connection portion 260 is formed so as to extend on the side surface of the peripheral portion of the piezoelectric vibrating piece 230 (frame portion 234) and further reach the second surface 242. Similarly, the second connection portion 262 is formed so as to extend on the side surface of the peripheral portion of the piezoelectric vibrating piece 230 (frame portion 234) and further reach the first surface 240. As a modification, the first and second connection terminals not shown in FIG. 14 may be formed to face the second and first connection portions 262 and 260. Then, the opposing first connection portion 260 and a second connection terminal (not shown) (or the opposing second connection portion 262 and a first connection terminal (not shown)) may be electrically connected. In addition, instead of the first and second connection terminals 216 and 226 electrically connected to the first and second integrated circuits 212 and 222, the first and second integrated circuits 212 and 222 are electrically connected. A dummy terminal that is not connected may be provided.

第１及び第２の半導体チップ２１０，２２０並びに圧電振動片２３０のその他の構成については、第１及び第２の実施の形態で説明した内容を適用することができる。例えば、第１及び第２の凸部２４４，２４６には、切り欠き２５０が形成され、切り欠き２５０の位置を第１及び第２の配線２５６，２５８が通る。また、切り欠き２５０には封止材２７０が設けられている。本実施の形態でも、第１及び第２の実施の形態で説明した効果を達成することができる。   The contents described in the first and second embodiments can be applied to the other configurations of the first and second semiconductor chips 210 and 220 and the piezoelectric vibrating piece 230. For example, a cutout 250 is formed in the first and second convex portions 244 and 246, and the first and second wirings 256 and 258 pass through the position of the cutout 250. The notch 250 is provided with a sealing material 270. Also in the present embodiment, the effects described in the first and second embodiments can be achieved.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１は、本発明の第１の実施の形態に係る圧電デバイスの平面図である。FIG. 1 is a plan view of the piezoelectric device according to the first embodiment of the present invention. 図２は、図１に示す圧電デバイスの正面図である。FIG. 2 is a front view of the piezoelectric device shown in FIG. 図３は、図１に示す圧電デバイスのIII−III線断面図である。FIG. 3 is a cross-sectional view of the piezoelectric device shown in FIG. 1 taken along the line III-III. 図４は、図１に示す圧電デバイスの左側面図である。FIG. 4 is a left side view of the piezoelectric device shown in FIG. 図５は、図１に示す圧電デバイスのＶ−Ｖ線断面図である。FIG. 5 is a cross-sectional view of the piezoelectric device shown in FIG. 図６は、図１に示す圧電デバイスの底面図である。FIG. 6 is a bottom view of the piezoelectric device shown in FIG. 図７（Ａ）は、第１の実施の形態に係る圧電デバイスの圧電振動片の平面図であり、図７（Ｂ）は、図７（Ａ）に示す圧電振動片のＢ−Ｂ線断面図であり、図７（Ｃ）は、図７（Ａ）に示す圧電振動片のＣ−Ｃ線断面図であり、図７（Ｄ）は、図７（Ａ）に示す圧電振動片の底面図である。FIG. 7A is a plan view of the piezoelectric vibrating piece of the piezoelectric device according to the first embodiment, and FIG. 7B is a cross-sectional view taken along line BB of the piezoelectric vibrating piece shown in FIG. 7C is a cross-sectional view taken along line CC of the piezoelectric vibrating piece shown in FIG. 7A, and FIG. 7D is a bottom view of the piezoelectric vibrating piece shown in FIG. 7A. FIG. 図８は、第１の半導体チップと圧電振動片の取り付けの詳細を説明する分解図である。FIG. 8 is an exploded view illustrating details of attachment of the first semiconductor chip and the piezoelectric vibrating piece. 図９は、第２の半導体チップと圧電振動片の取り付けの詳細を説明する分解図である。FIG. 9 is an exploded view illustrating details of attachment of the second semiconductor chip and the piezoelectric vibrating piece. 図１０は、本発明の第２の実施の形態に係る圧電デバイスの断面図である。FIG. 10 is a cross-sectional view of a piezoelectric device according to the second embodiment of the present invention. 図１１は、本発明の第２の実施の形態に係る圧電デバイスの断面図である。FIG. 11 is a cross-sectional view of a piezoelectric device according to the second embodiment of the present invention. 図１２は、第２の実施の形態に係る圧電デバイスの圧電振動片を示す平面図である。FIG. 12 is a plan view showing the piezoelectric vibrating piece of the piezoelectric device according to the second embodiment. 図１３は、本発明の第３の実施の形態に係る圧電デバイスの断面図である。FIG. 13 is a cross-sectional view of a piezoelectric device according to the third embodiment of the present invention. 図１４は、本発明の第３の実施の形態に係る圧電デバイスの断面図である。FIG. 14 is a cross-sectional view of a piezoelectric device according to the third embodiment of the present invention. 図１５は、第３の実施の形態に係る圧電デバイスの圧電振動片を示す平面図である。FIG. 15 is a plan view showing the piezoelectric vibrating piece of the piezoelectric device according to the third embodiment.

符号の説明Explanation of symbols

１０…第１の半導体チップ、１２…第１の集積回路、１４…第１の電極、１６…第１の接続端子、１８…シリコン酸化膜、２０…第２の半導体チップ、２２…第２の集積回路、２４…第２の電極、２６…第２の接続端子、２８…外部端子、３０…圧電振動片、３２…振動部、３４…枠部、３６…連結部、３８…スリット、４０…第１の面、４２…第２の面、４４…第１の凸部、４６…第２の凸部、４８…第１の切り欠き、５０…第２の切り欠き、５２…第１の励振電極、５４…第２の励振電極、５６…第１の配線、５８…第２の配線、６０…第１の接続部、６２…第２の接続部、６４…導電体、６６…導電部材、６８…樹脂、７０…封止材、１１０…第１の半導体チップ、１１２…第１の集積回路、１１４…第１の電極、１１６…第１の接続端子、１２０…第２の半導体チップ、１２２…第２の集積回路、１２４…第２の電極、１２６…第２の接続端子、１３０…圧電振動片、１３２…振動部、１３４…枠部、１４０…第１の面、１４２…第２の面、１４４…第１の凸部、１４６…第２の凸部、１５６…第１の配線、１５８…第２の配線、１６０…第１の接続部、１６２…第２の接続部、１６４…導電体、１７２…貫通孔、２１０…第１の半導体チップ、２１２…第１の集積回路、２１４…第１の電極、２１６…第１の接続端子、２２０…第２の半導体チップ、２２２…第２の集積回路、２２４…第２の電極、２２６…第２の接続端子、２３０…圧電振動片、２４０…第１の面、２４２…第２の面、２３４…枠部、２６０…第１の接続部、２６２…第２の接続部、２６４…導電体、２６６…切り欠き DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor chip, 12 ... 1st integrated circuit, 14 ... 1st electrode, 16 ... 1st connection terminal, 18 ... Silicon oxide film, 20 ... 2nd semiconductor chip, 22 ... 2nd Integrated circuit 24 ... second electrode 26 ... second connection terminal 28 ... external terminal 30 ... piezoelectric vibrating piece 32 ... vibrating part 34 ... frame part 36 ... connecting part 38 ... slit 40 ... 1st surface, 42 ... 2nd surface, 44 ... 1st convex part, 46 ... 2nd convex part, 48 ... 1st notch, 50 ... 2nd notch, 52 ... 1st excitation Electrode, 54 ... second excitation electrode, 56 ... first wiring, 58 ... second wiring, 60 ... first connection portion, 62 ... second connection portion, 64 ... conductor, 66 ... conductive member, 68 ... Resin, 70 ... Sealing material, 110 ... First semiconductor chip, 112 ... First integrated circuit, 114 ... First electrode, 116 ... First connection 120 ... second semiconductor chip 122 ... second integrated circuit 124 ... second electrode 126 ... second connection terminal 130 ... piezoelectric vibrating piece 132 ... vibrating part 134 ... frame part 140 ... 1st surface, 142 ... 2nd surface, 144 ... 1st convex part, 146 ... 2nd convex part, 156 ... 1st wiring, 158 ... 2nd wiring, 160 ... 1st connection part 162 ... 2nd connection part, 164 ... conductor, 172 ... through hole, 210 ... 1st semiconductor chip, 212 ... 1st integrated circuit, 214 ... 1st electrode, 216 ... 1st connection terminal, 220 ... second semiconductor chip, 222 ... second integrated circuit, 224 ... second electrode, 226 ... second connection terminal, 230 ... piezoelectric vibrating piece, 240 ... first surface, 242 ... second surface 234 ... frame portion, 260 ... first connection portion, 262 ... second connection portion, 264 ... conductor, 66 ... notch

Claims (14)

第１の集積回路を内部に有する第１の半導体チップと、
第２の集積回路を内部に有する第２の半導体チップと、
振動部及び前記振動部を囲む枠部を有する圧電振動片と、
前記振動部に形成された励振電極と、
を有し、
前記励振電極は、前記第１及び第２の半導体チップの少なくともいずれか一方と電気的に接続され、
前記圧電振動片は、前記第１及び第２の半導体チップの間に配置され、
前記圧電振動片の前記枠部は、厚み方向において対向する第１および第２の接合面を有し、
前記枠部の前記第１の接合面が前記第１の半導体チップの一方の面に接合され、
前記枠部の前記第２の接合面が前記第２の半導体チップの一方の面に接合されてなる圧電デバイス。 A first semiconductor chip having a first integrated circuit therein;
A second semiconductor chip having a second integrated circuit therein;
A piezoelectric vibrating piece having a vibrating portion and a frame portion surrounding the vibrating portion;
An excitation electrode formed on the vibrating portion;
Have
The excitation electrode is electrically connected to at least one of the first and second semiconductor chips;
The piezoelectric vibrating piece is disposed between the first and second semiconductor chips,
The frame portion of the piezoelectric vibrating piece has first and second joint surfaces that face each other in the thickness direction;
The first bonding surface of the frame portion is bonded to one surface of the first semiconductor chip;
A piezoelectric device in which the second bonding surface of the frame portion is bonded to one surface of the second semiconductor chip. 請求項１に記載された圧電デバイスにおいて、
前記枠部は、前記厚み方向において対向する第１および第２の面を有し、
前記枠部には前記第１の面に第１の凸部が形成され、前記第１の凸部の前記厚み方向の端面が前記第１の接合面とされ、
前記枠部には前記第２の面に第２の凸部が形成され、前記第１の凸部の前記厚み方向の端面が前記第２の接合面とされてなる圧電デバイス。 The piezoelectric device according to claim 1,
The frame portion has first and second surfaces opposed in the thickness direction,
The frame portion is formed with a first convex portion on the first surface, and the end surface in the thickness direction of the first convex portion is the first joint surface,
A piezoelectric device in which a second convex portion is formed on the second surface of the frame portion, and an end surface in the thickness direction of the first convex portion serves as the second bonding surface. 請求項２に記載された圧電デバイスにおいて、
前記第１の半導体チップは、前記第１の集積回路に電気的に接続された第１の電極を有し、
前記第２の半導体チップは、前記第２の集積回路に電気的に接続された第２の電極を有し、
前記励振電極は、第１及び第２の励振電極からなり、
前記枠部の前記第１の面上に形成され、前記第１の励振電極と電気的に接続され、前記第１及び第２の電極の少なくともいずれか一方の電極に電気的に接続されている第１の接続部を有する第１の配線と、
前記枠部の前記第２の面上に形成され、前記第２の励振電極と電気的に接続され、前記第１及び第２の電極の少なくともいずれか一方の電極に電気的に接続されている第２の接続部を有する第２の配線と、
を有する圧電デバイス。 The piezoelectric device according to claim 2,
The first semiconductor chip has a first electrode electrically connected to the first integrated circuit,
The second semiconductor chip has a second electrode electrically connected to the second integrated circuit;
The excitation electrode includes first and second excitation electrodes,
Formed on the first surface of the frame portion, electrically connected to the first excitation electrode, and electrically connected to at least one of the first and second electrodes. A first wiring having a first connection portion;
Formed on the second surface of the frame, electrically connected to the second excitation electrode, and electrically connected to at least one of the first and second electrodes A second wiring having a second connection portion;
A piezoelectric device having: 請求項３に記載された圧電デバイスにおいて、
前記第１の凸部は、第１の切り欠きを有して前記振動部を囲む形状をなし、前記第１の切り欠きの位置を前記第１の配線が通り、
前記第２の凸部は、第２の切り欠きを有して前記振動部を囲む形状をなし、前記第２の切り欠きの位置を前記第２の配線が通る圧電デバイス。 The piezoelectric device according to claim 3, wherein
The first convex part has a first notch and surrounds the vibrating part, and the first wiring passes through the position of the first notch,
The second convex portion has a second notch and has a shape surrounding the vibrating portion, and the second wiring passes through the position of the second notch. 請求項１から４のいずれか１項に記載された圧電デバイスにおいて、
前記第１の凸部は、前記第１の接続部と前記振動部の間に形成され、
前記第２の凸部は、前記第２の接続部と前記振動部の間に形成されている圧電デバイス。 The piezoelectric device according to any one of claims 1 to 4, wherein
The first convex portion is formed between the first connecting portion and the vibrating portion,
The second convex portion is a piezoelectric device formed between the second connection portion and the vibration portion. 請求項１から５のいずれか１項に記載された圧電デバイスにおいて、
前記圧電振動片は水晶からなり、
前記第１及び第２の半導体チップはそれぞれシリコン酸化膜を表面に有し、
前記第１及び第２の凸部は、直接接合によって、前記シリコン酸化膜に接合されている圧電デバイス。 The piezoelectric device according to any one of claims 1 to 5,
The piezoelectric vibrating piece is made of quartz,
Each of the first and second semiconductor chips has a silicon oxide film on the surface,
The piezoelectric device in which the first and second protrusions are bonded to the silicon oxide film by direct bonding. 請求項１から６のいずれか１項に記載された圧電デバイスにおいて、
前記圧電振動片は、前記第１の面を、前記第１の半導体チップの前記第１の電極が形成された面に対向させて配置されている圧電デバイス。 The piezoelectric device according to any one of claims 1 to 6,
The piezoelectric vibrating piece is a piezoelectric device in which the first surface is disposed to face the surface of the first semiconductor chip on which the first electrode is formed. 請求項７に記載された圧電デバイスにおいて、
前記圧電振動片は、前記第１の接続部が前記第１の電極に対向するように配置されている圧電デバイス。 The piezoelectric device according to claim 7, wherein
The piezoelectric vibrating piece is a piezoelectric device in which the first connecting portion is disposed so as to face the first electrode. 請求項７又は８に記載された圧電デバイスにおいて、
前記圧電振動片は、前記第２の面を、前記第２の半導体チップの前記第２の電極が形成された面に対向させて配置されている圧電デバイス。 The piezoelectric device according to claim 7 or 8,
The piezoelectric vibrating piece is a piezoelectric device in which the second surface is disposed to face the surface of the second semiconductor chip on which the second electrode is formed. 請求項９に記載された圧電デバイスにおいて、
前記圧電振動片は、前記第２の接続部が前記第２の電極に対向するように配置されている圧電デバイス。 The piezoelectric device according to claim 9, wherein
The piezoelectric vibrating piece is a piezoelectric device in which the second connecting portion is disposed so as to face the second electrode. 請求項９又は１０に記載された圧電デバイスにおいて、
前記第１の半導体チップは、前記第１の電極が形成された面とは反対面に前記第１の集積回路と電気的に接続された第１の接続端子をさらに有し、
前記第２の半導体チップは、前記第２の電極が形成された面に前記第２の集積回路と電気的に接続された第２の接続端子をさらに有し、
前記第１及び第２の接続端子が導電体によって電気的に接続されている圧電デバイス。 The piezoelectric device according to claim 9 or 10,
The first semiconductor chip further includes a first connection terminal electrically connected to the first integrated circuit on a surface opposite to the surface on which the first electrode is formed,
The second semiconductor chip further includes a second connection terminal electrically connected to the second integrated circuit on a surface on which the second electrode is formed,
A piezoelectric device in which the first and second connection terminals are electrically connected by a conductor. 請求項９又は１０に記載された圧電デバイスにおいて、
前記第１の半導体チップは、前記第１の電極が形成された面に前記第１の集積回路と電気的に接続された第１の接続端子をさらに有し、
前記第２の半導体チップは、前記第２の電極が形成された面に前記第２の集積回路と電気的に接続された第２の接続端子をさらに有し、
前記第１及び第２の接続端子は、前記枠部を貫通する貫通孔に配置された部分を有する導電体によって電気的に接続されている圧電デバイス。 The piezoelectric device according to claim 9 or 10,
The first semiconductor chip further includes a first connection terminal electrically connected to the first integrated circuit on a surface on which the first electrode is formed,
The second semiconductor chip further includes a second connection terminal electrically connected to the second integrated circuit on a surface on which the second electrode is formed,
The piezoelectric device in which the first and second connection terminals are electrically connected by a conductor having a portion disposed in a through hole penetrating the frame portion. 請求項９又は１０に記載された圧電デバイスにおいて、
前記第１の半導体チップは、前記第１の電極が形成された面に前記第１の集積回路と電気的に接続された第１の接続端子をさらに有し、
前記第２の半導体チップは、前記第２の電極が形成された面に前記第２の集積回路と電気的に接続された第２の接続端子をさらに有し、
前記第１及び第２の接続端子は、前記圧電振動片の前記周縁部の側面上に配置された部分を有する導電体によって電気的に接続されている圧電デバイス。 The piezoelectric device according to claim 9 or 10,
The first semiconductor chip further includes a first connection terminal electrically connected to the first integrated circuit on a surface on which the first electrode is formed,
The second semiconductor chip further includes a second connection terminal electrically connected to the second integrated circuit on a surface on which the second electrode is formed,
The first and second connection terminals are electrically connected by a conductor having a portion disposed on a side surface of the peripheral edge of the piezoelectric vibrating piece. 請求項１から１３のいずれか１項に記載された圧電デバイスにおいて、
前記第２の半導体チップは、前記第２の電極が形成された面とは反対面に、前記第２の集積回路と電気的に接続された外部端子を有する圧電デバイス。 The piezoelectric device according to any one of claims 1 to 13,
The second semiconductor chip is a piezoelectric device having an external terminal electrically connected to the second integrated circuit on a surface opposite to a surface on which the second electrode is formed.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11031908B2 (en) 2019-08-29 2021-06-08 Seiko Epson Corporation Vibration device, electronic apparatus, and vehicle

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001119264A (en) * 1999-10-15 2001-04-27 Nippon Dempa Kogyo Co Ltd Crystal oscillator
JP2002198739A (en) * 2000-12-26 2002-07-12 Toyo Commun Equip Co Ltd Surface mount piezoelectric oscillator
JP2004015444A (en) * 2002-06-06 2004-01-15 Nippon Dempa Kogyo Co Ltd Pll-controlled oscillator
WO2007091417A1 (en) * 2006-02-10 2007-08-16 Murata Manufacturing Co., Ltd. Vibrator module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001119264A (en) * 1999-10-15 2001-04-27 Nippon Dempa Kogyo Co Ltd Crystal oscillator
JP2002198739A (en) * 2000-12-26 2002-07-12 Toyo Commun Equip Co Ltd Surface mount piezoelectric oscillator
JP2004015444A (en) * 2002-06-06 2004-01-15 Nippon Dempa Kogyo Co Ltd Pll-controlled oscillator
WO2007091417A1 (en) * 2006-02-10 2007-08-16 Murata Manufacturing Co., Ltd. Vibrator module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11031908B2 (en) 2019-08-29 2021-06-08 Seiko Epson Corporation Vibration device, electronic apparatus, and vehicle

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