JP2009117507A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2009117507A
JP2009117507A JP2007287016A JP2007287016A JP2009117507A JP 2009117507 A JP2009117507 A JP 2009117507A JP 2007287016 A JP2007287016 A JP 2007287016A JP 2007287016 A JP2007287016 A JP 2007287016A JP 2009117507 A JP2009117507 A JP 2009117507A
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Prior art keywords
terminal
loop antenna
insulating layer
semiconductor device
semiconductor chip
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Withdrawn
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JP2007287016A
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Japanese (ja)
Inventor
Tomonaga Kobayashi
知永 小林
Norio Hama
範夫 浜
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where an antenna is arranged on a semiconductor chip. <P>SOLUTION: The semiconductor device includes a loop antenna 30 and a second insulating layer 15; the loop antenna 30 includes a semiconductor chip 100, including a power circuit section 120 and a transmission/reception circuit section 110, a first insulating layer 10 formed on the semiconductor chip 100, loop-like wiring of which one end is connected to a first terminal T1 and the other end is connected to a second terminal T2, and a capacitor C1 connected between the first terminal T1 and the second terminal T2; the second insulating layer 15 is formed in a shape including a region occupied by the loop antenna between the first insulating layer 10 and the loop antenna 30; and in the semiconductor device 1, the first terminal T1 and the second terminal T2 are connected to the power circuit section 120 and the transmission/reception circuit section 110. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、電磁誘導により電源電圧の供給及びデータを送受信する半導体装置に関する。   The present invention relates to a power supply voltage supply and data transmission / reception by electromagnetic induction.

各種データなどの記録・保存が可能な記憶装置として、たとえば各種のメモリカードが知られている。そして、この種の記憶装置には、CPUを内蔵した接触型のマイコンカード、および電波により情報の送受を行う非接触型の無線カードなどがあり、また、これらの両ICカードなどは、それぞれ実用性における特徴、もしくは優位性があるので、前記特徴、優位性に対応した形で広く実用に供されている。非接触型の無線カードの場合、半導体チップとアンテナをカード内に設置し、電力とデータの両方の供給を受ける必要がある。   For example, various memory cards are known as storage devices capable of recording / saving various data. This type of storage device includes a contact type microcomputer card with a built-in CPU and a non-contact type wireless card that transmits and receives information by radio waves. Therefore, it is widely used in a form corresponding to the above characteristics and advantages. In the case of a contactless wireless card, it is necessary to install a semiconductor chip and an antenna in the card and receive both power and data.

例えば特許文献1〜3には、半導体チップとアンテナを別体で構成する方法が記載されている。しかしながら、これら従来の方法では、アンテナと半導体チップを接続するための配線層を設けなければならず、部品点数が多くなるため組み立て工数が増加し、コストが割高となる。   For example, Patent Documents 1 to 3 describe a method of configuring a semiconductor chip and an antenna separately. However, in these conventional methods, it is necessary to provide a wiring layer for connecting the antenna and the semiconductor chip, which increases the number of parts, increases the number of assembly steps, and increases the cost.

この問題を解決するために、例えば特許文献4には、半導体チップ上に絶縁層を介してアンテナを配置する方法が記載されている。   In order to solve this problem, for example, Patent Document 4 describes a method of disposing an antenna on a semiconductor chip via an insulating layer.

特開平7−176646号公報JP-A-7-176646 特許第3549104号公報Japanese Patent No. 3549104 特許第3800884号公報Japanese Patent No. 3800884 特許第3377786号公報Japanese Patent No. 3377786

しかしながら、従来の方法では、アンテナコイルが多重に巻かれているため、半導体チップとの間にコンデンサ容量が多く付いてしまうため伝送効率が悪いという課題がある。   However, in the conventional method, since the antenna coil is wound in multiple layers, there is a problem in that transmission efficiency is poor because a large amount of capacitor capacity is attached to the semiconductor chip.

本発明は、上述の課題の少なくとも一部を解決するためになされたものであり、以下の形態または適用例として実現することが可能である。   SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[適用例1]
電源回路部と送受信回路部とを含む半導体チップと、前記半導体チップ上に形成された第1の絶縁層と、一端が第1端子に接続され他端が第2端子に接続されたループ状の配線と、前記第1端子と前記第2端子との間に接続されたコンデンサと、を含むループアンテナと、前記第1の絶縁層と前記ループアンテナとの間に前記ループアンテナが占有する領域を含む形状に形成された第2の絶縁層と、を含み、前記第1端子及び前記第2端子は前記電源回路部及び前記送受信回路部に接続されている、ことを特徴とする半導体装置。
[Application Example 1]
A semiconductor chip including a power supply circuit portion and a transmission / reception circuit portion, a first insulating layer formed on the semiconductor chip, and a loop shape having one end connected to the first terminal and the other end connected to the second terminal A loop antenna including wiring, a capacitor connected between the first terminal and the second terminal, and a region occupied by the loop antenna between the first insulating layer and the loop antenna. A semiconductor device, wherein the first terminal and the second terminal are connected to the power supply circuit portion and the transmission / reception circuit portion.

この構成によれば、1つの半導体装置でループアンテナにより電力の供給と送受信を行えるので、組み立て工数の削減とコストの削減ができる。また、第2の絶縁層により半導体チップとループアンテナの距離を離すことができるのでコンデンサ容量を減らすことができ、送受信効率を上げることができる。さらに、第2の絶縁層がループアンテナの下の必要最小限の領域に形成されているので、半導体チップの全面に2層の絶縁層を塗布した場合に比べ、半導体チップの反り返りを防止することができる。   According to this configuration, since power can be supplied and transmitted / received by a loop antenna with one semiconductor device, the number of assembling steps and the cost can be reduced. In addition, since the distance between the semiconductor chip and the loop antenna can be increased by the second insulating layer, the capacitance of the capacitor can be reduced and transmission / reception efficiency can be increased. Furthermore, since the second insulating layer is formed in the minimum necessary area under the loop antenna, the semiconductor chip is prevented from warping compared to the case where two insulating layers are applied to the entire surface of the semiconductor chip. Can do.

以下、半導体装置の実施形態について図面に従って説明する。   Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings.

(第1実施形態)
<半導体装置の構成>
まず、第1実施形態に係る半導体装置の構成について、図1を参照して説明する。図1(A)は、第1実施形態に係る半導体装置の構成を示す斜視図、図1(B)は、半導体装置の構成を示すA−A’線の断面図である。
(First embodiment)
<Configuration of semiconductor device>
First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1A is a perspective view showing the configuration of the semiconductor device according to the first embodiment, and FIG. 1B is a cross-sectional view taken along the line AA ′ showing the configuration of the semiconductor device.

図1(A)、(B)に示すように、半導体装置1は、電源回路部120と送受信回路部110を含む半導体チップ100上に応力緩和樹脂などの第1の絶縁層10が塗布され、一端が第1端子T1に接続され他端が第2端子T2に接続されたループ状の配線と、第1端子T1と第2端子T2とのコンデンサC1と、から構成されたループアンテナ30と、第1の絶縁層10とループアンテナ30との間にループアンテナ30が占有する領域を含む形状に形成された第2の絶縁層15と、第1の絶縁層10、第2の絶縁層15、ループアンテナ30上に保護用樹脂20が塗布されている。   As shown in FIGS. 1A and 1B, in the semiconductor device 1, a first insulating layer 10 such as a stress relaxation resin is applied on a semiconductor chip 100 including a power supply circuit unit 120 and a transmission / reception circuit unit 110. A loop antenna 30 composed of a loop-shaped wiring having one end connected to the first terminal T1 and the other end connected to the second terminal T2, and a capacitor C1 of the first terminal T1 and the second terminal T2, A second insulating layer 15 formed in a shape including a region occupied by the loop antenna 30 between the first insulating layer 10 and the loop antenna 30; a first insulating layer 10; a second insulating layer 15; A protective resin 20 is applied on the loop antenna 30.

ループアンテナ30とコンデンサC1は、第1端子T1と第2端子T2とに並列に接続されたLC並列発振回路として動作する。   The loop antenna 30 and the capacitor C1 operate as an LC parallel oscillation circuit connected in parallel to the first terminal T1 and the second terminal T2.

図2は、半導体装置の回路図である。図2に示すように、ループアンテナ30の第1端子T1と第2端子T2は、電源回路部120を構成する増幅器121に接続され、ループアンテナ30で受信した電力を増幅し電源回路122に出力する。   FIG. 2 is a circuit diagram of the semiconductor device. As shown in FIG. 2, the first terminal T <b> 1 and the second terminal T <b> 2 of the loop antenna 30 are connected to the amplifier 121 that constitutes the power supply circuit unit 120, amplifies the power received by the loop antenna 30, and outputs it to the power supply circuit 122. To do.

また、ループアンテナ30の第1端子T1と第2端子T2は、送受信回路部110を構成する増幅器111にも接続され、ループアンテナ30で受信したデータを増幅し送受信回路112に出力する。   The first terminal T1 and the second terminal T2 of the loop antenna 30 are also connected to the amplifier 111 constituting the transmission / reception circuit unit 110, and amplify the data received by the loop antenna 30 and output the amplified data to the transmission / reception circuit 112.

以上に述べた本実施形態によれば、以下の効果が得られる。   According to the present embodiment described above, the following effects can be obtained.

本実施形態では、1つの半導体装置1でループアンテナにより電力の供給とデータの送受信を行えるので、組み立て工数の削減とコストの削減ができる。また、第2の絶縁層により半導体チップとループアンテナの距離を離すことができるのでコンデンサ容量を減らすことができ、送受信効率を上げることができる。さらに、第2の絶縁層がループアンテナの下の必要最小限の領域に形成されているので、半導体チップの全面に2層の絶縁層を塗布した場合に比べ、半導体チップの反り返りを防止することができる。   In the present embodiment, since power can be supplied and data can be transmitted and received by the loop antenna in one semiconductor device 1, assembly man-hours and costs can be reduced. In addition, since the distance between the semiconductor chip and the loop antenna can be increased by the second insulating layer, the capacitance of the capacitor can be reduced and transmission / reception efficiency can be increased. Furthermore, since the second insulating layer is formed in the minimum necessary area under the loop antenna, the semiconductor chip is prevented from warping compared to the case where two insulating layers are applied to the entire surface of the semiconductor chip. Can do.

以上、半導体装置の実施形態を説明したが、こうした実施の形態に何ら限定されるものではなく、趣旨を逸脱しない範囲内において様々な形態で実施し得ることができる。以下、変形例を挙げて説明する。   As mentioned above, although embodiment of the semiconductor device was described, it is not limited to such embodiment at all, It can implement in various forms within the range which does not deviate from the meaning. Hereinafter, a modification will be described.

(変形例1)半導体装置の変形例1について説明する。前記第1実施形態では、ループアンテナ30をチップ形状に合わせ四角い形状で説明したが、円形状や楕円形状にしてもよい。   (Modification 1) Modification 1 of the semiconductor device will be described. In the first embodiment, the loop antenna 30 has been described as a square shape in accordance with the chip shape, but it may be circular or elliptical.

(A)第1実施形態に係る半導体装置の構成を示す斜視図、(B)半導体装置の構成を示す断面図。1A is a perspective view illustrating a configuration of a semiconductor device according to a first embodiment, and FIG. 3B is a cross-sectional view illustrating a configuration of the semiconductor device. 半導体装置の回路図。1 is a circuit diagram of a semiconductor device.

符号の説明Explanation of symbols

1…半導体装置、10…第1の絶縁層、15…第2の絶縁層、20…保護用樹脂、30…ループアンテナ、100…半導体チップ、110…送受信回路部、111…増幅器、112…送受信回路、120…電源回路部、121…増幅器、122…電源回路。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... 1st insulating layer, 15 ... 2nd insulating layer, 20 ... Protection resin, 30 ... Loop antenna, 100 ... Semiconductor chip, 110 ... Transmission / reception circuit part, 111 ... Amplifier, 112 ... Transmission / reception Reference numeral 120 denotes a power supply circuit unit, 121 denotes an amplifier, and 122 denotes a power supply circuit.

Claims (1)

電源回路部と送受信回路部とを含む半導体チップと、
前記半導体チップ上に形成された第1の絶縁層と、
一端が第1端子に接続され他端が第2端子に接続されたループ状の配線と、前記第1端子と前記第2端子との間に接続されたコンデンサと、を含むループアンテナと、
前記第1の絶縁層と前記ループアンテナとの間に前記ループアンテナが占有する領域を含む形状に形成された第2の絶縁層と、
を含み、
前記第1端子及び前記第2端子は前記電源回路部及び前記送受信回路部に接続されている、
ことを特徴とする半導体装置。
A semiconductor chip including a power supply circuit section and a transmission / reception circuit section;
A first insulating layer formed on the semiconductor chip;
A loop antenna including a loop-shaped wiring having one end connected to the first terminal and the other end connected to the second terminal; and a capacitor connected between the first terminal and the second terminal;
A second insulating layer formed in a shape including a region occupied by the loop antenna between the first insulating layer and the loop antenna;
Including
The first terminal and the second terminal are connected to the power supply circuit unit and the transmission / reception circuit unit,
A semiconductor device.
JP2007287016A 2007-11-05 2007-11-05 Semiconductor device Withdrawn JP2009117507A (en)

Priority Applications (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011227755A (en) * 2010-04-21 2011-11-10 Fukui Genshiryoku Kogyo Co Ltd Method for detecting object existence area, object detection system and device for assembling transmission/reception of radio wave

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011227755A (en) * 2010-04-21 2011-11-10 Fukui Genshiryoku Kogyo Co Ltd Method for detecting object existence area, object detection system and device for assembling transmission/reception of radio wave

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Effective date: 20110201