JP2009116164A - Liquid crystal display device and manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device, capable of preventing interference fringes or moire while improving aperture ratio, and also efficiently obtaining a fringe capacity from its specific structure. <P>SOLUTION: In the field driving liquid crystal display device 100 adapted to apply a drive voltage to a signal line 106 through a pixel electrode 111 connected to a liquid crystal cell corresponding to each pixel to thereby display an image by the liquid crystal cells, and to connect a storage capacity Cs for replenishing a retention capacity and a liquid crystal capacity C<SB>LC</SB>in parallel to the liquid crystals for enhancing the liquid crystal applied voltage retention rate of the pixel part to thereby drive the liquid crystals, the storage capacity Cs line LCs is set to have a key-shaped, comb-shaped, ladder-shaped, or hole-shaped structure or the like to acquire a further large fringe capacity, and branch lines and hole-shaped structure parts of the Cs line LCs are disposed at random intervals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix liquid crystal display device such as a liquid crystal display, which includes a thin film transistor (TFT) as a switching element, and a manufacturing method thereof.

  FIG. 1 is an equivalent circuit diagram of a general active matrix display device having a storage capacitor.

The gate line LGT laterally in the display device, Cs lines LCs, longitudinally has a signal line LSG, parallel storage capacitor Cs and the pixel capacitance _{C LC} is the region surrounded by the gate line LGT and the signal line LSG It is installed.
The storage capacitor Cs is repeatedly charged and discharged through the TFT 1 serving as a switching element. The storage capacitor Cs can hold the voltage applied to the pixel capacitor _CLC for a certain period of time using the charged charge.
This storage capacity is determined by the area of the Cs line, the thinness of the insulating film sandwiched between the electrodes, and the material of the insulating film.

However, if the area of the Cs line LCs is increased, the storage capacity Cs increases, but a decrease in the aperture ratio is inevitable.
According to the thin insulating film sandwiched between the electrodes and the method using the material of the insulating film, the insulating property is deteriorated and a leak current is likely to occur, and the charge charged in the storage capacitor may be reduced. In particular, the thinning of the insulating film can be obtained efficiently in the storage capacity, but the dispersion of the storage capacity for each pixel increases.

Therefore, various techniques for solving these problems have been proposed (for example, Patent Documents 1 to 4).
JP-A-4-367828 JP 2000-39626 A JP-A-9-153882 JP 2002-303876 A

In the technique described in Patent Document 1, as shown in FIG. 2, a comb-shaped groove 3 is formed in an insulating substrate 2, and a storage capacitor Cs is formed in a region where the groove 3 is formed.
By forming the storage capacitor Cs on the insulating substrate 2, not only the bottom surface of the groove 3 but also the inner peripheral surface can be used as a capacity generation unit, so that the occupation ratio of the storage capacitor Cs to the surface area of the insulating substrate 2 is increased. In addition, the storage capacity can be improved.

In the technique disclosed in Patent Document 2, as shown in FIG. 3, the storage capacitor is increased by forming the concave groove 5 in the substrate 4 and forming the storage capacitor Cs in the region of the groove 5. .
Further, as shown in FIG. 4, the storage capacitor Cs is improved by embedding a high dielectric constant insulating film 7 in the substrate 6.

  However, these methods have problems such as reduction in mass productivity and reliability, such as the need to create grooves in the insulating substrate without damaging the substrate or to adopt a new process.

  Further, as shown in FIG. 5, the technique disclosed in Patent Document 3 includes an insulating film sandwiched between two transparent electrode films 8 and 9 that serve as a storage capacitor while satisfying a required storage capacitor. The aperture ratio of the pixel is improved.

  In this method, the entire pixel part can be covered with a transparent electrode, so it is possible to improve the aperture ratio and the storage capacity. However, by using two transparent electrodes in the pixel part, the transmittance is reduced. Is concerned. Moreover, the increase in the man-hour of the process which adds a transparent electrode, and the increase in a film thickness become a problem.

  In the technique disclosed in Patent Document 4, as shown in FIGS. 6A to 6C, in order to increase the storage capacitor Cs, it is necessary to adopt a structure that increases the boundary length of the shape of the Cs line electrode 10. is suggesting.

In this method, the storage capacity can be obtained with high efficiency. However, because the Cs line has periodicity in this structure, interference fringes due to interference at a specific wavelength and moire due to repeated geometric patterns occur. There is a concern that the display characteristics will be significantly reduced.
In particular, when the wiring period of the Cs line becomes approximately the same as that in the visible light region, it is considered that the display characteristics are further remarkably deteriorated.

  The present invention provides a liquid crystal display device capable of improving the aperture ratio, preventing generation of interference fringes and moire, and efficiently obtaining a fringe capacitance from its unique structure, and a method for manufacturing the same. There is.

  According to a first aspect of the present invention, a driving voltage to a signal line is applied through a pixel electrode connected to a liquid crystal cell corresponding to each pixel, and a storage capacitor for supplementing a storage capacitor is connected in parallel with the liquid crystal capacitor. In addition, in the electric field drive type liquid crystal display device, the storage capacitor lines are formed to have irregular patterns with different intervals.

  Preferably, the storage capacitor wiring includes a main line portion and a plurality of branch portions formed so as to branch from the main line portion, and the plurality of branch portions have no periodicity.

  Preferably, the storage capacitor wiring has a plurality of holes formed at different intervals in the wiring.

  Preferably, the storage capacitor wiring has a plurality of transmission holes randomly formed in the wiring.

  Preferably, the pattern of the storage capacitor wiring is different between pixels.

  Preferably, in the storage capacitor wiring, the irregular pattern is formed as a pattern capable of suppressing interference of a specific wavelength with respect to transmitted light.

  Preferably, in the storage capacitor wiring, the irregular pattern is formed as a pattern having no wavelength dependency with respect to transmitted light.

  According to a second aspect of the present invention, a driving voltage to a signal line is applied through a pixel electrode connected to a liquid crystal cell corresponding to each pixel, and a storage capacitor for supplementing a storage capacitor is connected in parallel with the liquid crystal capacitor. In the manufacturing method of the liquid crystal display device of electric field driving type, the storage capacitor wiring is formed so as to have an irregular pattern with different intervals.

  According to the present invention, the liquid crystal is driven from the liquid crystal capacitor and the storage capacitor serving as the potential supply source when the liquid crystal capacitor is insufficient. Here, the generation of interference fringes and moire is prevented by dividing a part of the storage capacitor wiring into a random cycle, and the fringe capacitor can be efficiently obtained from the unique structure.

  According to the present invention, the aperture ratio can be improved, the generation of interference fringes and moire can be prevented, and the fringe capacity can be efficiently obtained from the unique structure.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 7 is a diagram illustrating an arrangement example in the array substrate (liquid crystal panel unit) of the active matrix liquid crystal display device according to the present embodiment.

As shown in FIG. 7, the liquid crystal display device 100 includes a pixel display region 101 in which pixels are arranged in an array, a horizontal transfer circuit 102, vertical transfer circuits 103-1, 103-2, a precharge circuit 104, and a level converter. The circuit 105 is formed.
In the pixel display region 101, a plurality of signal lines 106 and a plurality of scanning lines (gate wirings) 107 are arranged in a grid pattern. One end of each signal line 106 is connected to the horizontal transfer circuit 102, and the other end is precharged. Connected to the circuit 104, the end of each gate wiring 107 is connected to the vertical transfer circuits 103-1, 103-2.

A plurality of pixels PX that are formed in a matrix that constitutes the pixel display region 101 of the liquid crystal display element 100 are provided with a pixel switching transistor (TFT) 108 that controls switching, a liquid crystal 109, and a storage capacitor (Cs) 110. Yes.
A signal line 106 to which a pixel signal is supplied is electrically connected to the source of the transistor 108 and supplies a pixel signal to be written. Further, a gate wiring (scanning line) 107 is electrically connected to the gate of the transistor 108, and a scanning signal is applied to the gate wiring 107 in a pulse manner at a predetermined timing.
In one pixel region surrounded by the gate wiring 107 and the signal line 106, a pixel capacitor _CLC and a storage capacitor Cs are provided in parallel. A gate electrode and a source electrode of a transistor (TFT) 108 are connected to the gate wiring 107 and the signal line 106, respectively.
The pixel electrode 111 is electrically connected to the drain of the transistor 108. By turning on the transistor 108, which is a switching element, for a certain period, the pixel signal supplied from the signal line 106 is transmitted at a predetermined timing. Write pixel signal.

A pixel signal of a predetermined level written to the liquid crystal 109 via the pixel electrode 111 is held for a certain period with the counter electrode formed on the counter substrate. The liquid crystal 109 modulates light and enables gradation display by changing the orientation and order of the molecular assembly according to the applied voltage level.
In the case of normally white display, incident light can pass through the liquid crystal portion according to the applied voltage, and light having a contrast corresponding to the pixel signal is emitted from the liquid crystal display element as a whole.
Here, in order to prevent the held pixel signal from leaking, a storage capacitor (Cs) 110 is added in parallel with the liquid crystal capacitor _CLC formed between the pixel electrode and the counter electrode. Thereby, the retention characteristics are further improved, and a liquid crystal display element with a high contrast ratio can be realized.
Further, in order to form such a storage capacitor 110, a resistance common wire 112 is provided.

FIG. 8 is a diagram illustrating a pattern example of a basic pixel structure.
9A is a cross-sectional view taken along line ab in FIG. 8, and FIG. 9B is a cross-sectional view taken along line bc in FIG.

In the pixel PX, a gate electrode 203 covered with a gate insulating film 202 is formed on a transparent insulating substrate (for example, a glass substrate) 201. The gate electrode 203 is connected to a gate wiring (scanning line) 107, a scanning signal is input from the gate wiring 107, and the transistor (TFT) 108 is turned on / off in response to the scanning signal. The gate electrode is formed, for example, by depositing a metal or alloy such as molybdenum (Mo) or tantalum (Ta) by a method such as sputtering.
A semiconductor film (channel formation region) 204 on the gate insulating film 202, and a pair of n ⁻ diffusion layers (LDD regions) 205 and 206, n ⁺ diffusion layers 207 and 208 (source region (electrode), sandwiching the semiconductor film 204, A drain region (electrode)) is formed.
Further, a transparent electrode 209 made of ITO is connected to the source electrode. The gate insulating film 202, the semiconductor layer (channel formation region) 204, the n ⁻ diffusion layers (LDD regions) 205 and 206, the n ⁺ diffusion layers 207 and 208 (source and drain regions), and the transparent electrode 209 are covered. An insulating film 210 is formed.
A counter electrode 213 is formed on the counter substrate 212 with the liquid crystal layer 211 interposed therebetween.

In this structure, the transparent electrode 209 and the signal line 106 are directly connected. Charge and discharge are performed through a transistor (TFT) 108 serving as a switching element. The storage capacitor Cs is formed by coupling the Cs line 112 and the transparent electrode 209 in the drawing. If it is possible to generate a sufficiently storage capacitor Cs, the voltage can be maintained for a predetermined time to be applied to the pixel capacitor C _LC.

Next, a method for manufacturing the liquid crystal display device shown in FIGS. 8 and 9 will be described with reference to FIGS.
10 to 15, the left Tr (transistor) portion and the right Cs capacitance forming portion in the drawings are the pixel transistor portion sectional view of FIG. 9A and the Cs capacitance forming portion of FIG. 9B, respectively. FIG.

First, as shown in FIG. 10A, a glass substrate 301 is used as a transparent insulating substrate, and a metal film (for example, Al (aluminum), Al alloy, Mo, MoN (molybdenum nitride) is directly formed on the glass substrate 301. )) Is formed on the entire surface by sputtering.
Next, as shown in FIG. 10B, after a resist layer 303 is formed on the entire surface, exposure is performed using a first photomask 304 to form resist masks 305 and 306.
Subsequently, as shown in FIG. 10C, the gate wiring 308 and the storage capacitor forming portion 309 are formed by etching (as shown by reference numeral 307 in the drawing).

Subsequently, as shown in FIG. 11D, for example, SiN (silicon nitride film) 310 is laminated on the entire surface of the substrate by plasma CVD, and an interlayer insulating film is formed for the gate insulating film and the storage capacitor forming portion.
Next, an a-Si (amorphous silicon) layer 311 is formed as a semiconductor layer on the entire substrate by plasma CVD.
For example, if the semiconductor layer is to be made of Poly-Si (polysilicon), as shown in FIG. 11E, a-Si 311 is irradiated with laser, and a-Si is melt-recrystallized to form Poly-Si. To.
Further, as shown in FIG. 11F, as the channel protective film (etching stopper film) 312, for example, SiN is formed on the entire surface of the substrate by plasma CVD.

As shown in FIG. 12G, a photoresist 313 is formed on the entire surface by spin coating, and back exposure is performed using the gate wiring portion and the storage capacitor forming portion as a mask. Since the exposed resist layer is melted, a resist pattern remains on the gate wiring and the storage capacitor forming portion.
As shown in FIG. 12H, by exposing the resist pattern using the second mask 314, the resist pattern remains only in the channel protection film formation region.
Thereafter, as shown in FIG. 13I, an etching process is performed to form a channel protective film 315.
Subsequently, as shown in FIG. 13J, a mask pattern 316 for ion implantation is formed, a resist is coated, and exposure is performed.

Further, as shown in FIGS. 14K and 14L, when the substrate is coated with a resist 317 and exposed with a stepper using a pattern mask, Si not covered with the resist is etched.
Next, as shown in FIGS. 14 (M) and 15 (N), a metal (Al (aluminum), Al alloy, Cr (chromium), etc.) to be the electrodes is used to form the source electrode 318 and the drain electrode 319. After sputtering, the resist layer is patterned using a third mask, and etching is performed using the patterned resist layer as an etching mask to form drain / source electrodes.
During this etching, the channel protective film 315 functions as an etching stopper, and the silicon layer remains without being etched.

  Next, as shown in FIG. 15 (O), ITO 320 is sputtered, the resist layer is patterned with a fourth mask, and etching is performed using the patterned resist layer as an etching mask. As shown in FIG. 15 (P), A drain / source electrode is formed. Finally, as shown in FIG. 15Q, an organic film is stacked over the entire surface. When the above steps are completed, the fabrication of the pixel transistor and the storage capacitor forming portion is completed.

The manufacturing method of the present liquid crystal display device 100 has been described above.
The characteristic Cs line structure of this embodiment will be described below. This Cs line structure can be formed by the manufacturing method described above.

FIG. 16 is a diagram illustrating a first configuration example of the Cs line of the pixel according to the present embodiment.
17 is a cross-sectional view taken along line ab in FIG.

The storage capacitor wiring (Cs line) LCs has a main line portion ML and a plurality of branch portions BL formed on both sides in the longitudinal direction of the main line portion ML. The plurality of branch portions BL are formed as patterns having no regularity, for example, patterns having randomly different intervals and shapes (thicknesses).
It can be seen that the Cs line LCs has a so-called key structure. By adopting the configuration of the Cs line, a larger storage capacity can be obtained with the same area as the Cs line that is generally formed only by the main line.
In particular, by arranging the wiring width and inter-wiring width of the branch part BL of the key type structure at random intervals, it is possible to prevent the transmitted light of the branch part from having wavelength dependency.

The principle of efficient storage capacity acquisition using this configuration will be described below.
FIG. 18 is a diagram for explaining the principle that the storage capacitor wiring (Cs line) LCs according to the present embodiment can efficiently acquire the storage capacitor.

The capacitance between the two conductors CDCB1 and CDCB2 is not only a parallel plate capacitance generated between the facing surfaces but also a fringe capacitance that wraps around between the conductors as shown in FIG.
By adopting the Cs line structure of the key type structure, the wraparound capacitance component (fringe capacitance component) becomes larger than the rectangular Cs line structure.
For this reason, more storage capacity can be obtained with the Cs line having the key structure while having the same area.

FIG. 19 is a diagram illustrating a result of calculating the storage capacity in the key Cs line structure according to the present embodiment and the storage capacity in the rectangular Cs line structure with the same area by electric field simulation.
In FIG. 19, the horizontal axis represents the number of key-shaped convex portions, and the vertical axis represents the capacitance value (au).
From FIG. 19, it can be seen that a storage capacity larger by about 30% can be obtained with the key-type Cs structure.

  FIG. 20 is a diagram illustrating a second configuration example of the Cs line of the pixel according to the present embodiment.

The pseudo comb-shaped Cs line structure shown in FIG. 20 in which the Cs wiring LCs is bent like a broken line and the bending interval and thickness are random is also compared with a general rectangular Cs line structure. A larger storage capacity can be obtained.
Also in the pseudo comb structure, the transmitted light does not exhibit wavelength dependency by randomly arranging the wiring width and the inter-wiring width.

FIG. 21 is a diagram illustrating a third configuration example of the Cs line of the pixel according to the present embodiment.
FIG. 22 is a diagram illustrating a fourth configuration example of the Cs line of the pixel according to the present embodiment.

As shown in FIGS. 21 and 22, even with a structure in which holes are provided at random sizes and intervals in the Cs wiring, it is possible to efficiently acquire the storage capacity.
In the example of FIG. 21, a plurality of holes 1121 having different intervals are formed in the wiring. That is, it is formed in a ladder shape.
In the example of FIG. 22, a plurality of transmission holes are randomly formed in the Cs line LCs.

  In addition, for the Cs wiring of adjacent pixels, by introducing a Cs wiring structure of various shapes for each pixel, for example, by providing a key shape, a comb shape, or a hole shape, a shape that does not repeat the geometric pattern is provided. Further, it is possible to efficiently generate the storage capacity without preventing the generation of interference fringes and moire and without deteriorating the visual characteristics.

By adopting the Cs structure according to the present embodiment, it is possible to efficiently increase the storage capacity while maintaining a high aperture ratio without increasing the number of man-hours or examining new processes that have been problematic until now. .
With this method, it is possible to secure a large storage capacity Cs that should be required in a small area compared to the conventional storage capacity occupation region without deteriorating visual characteristics.

FIG. 23 is a diagram illustrating another pixel structure.
24A is a cross-sectional view taken along line ab in FIG. 23, and FIG. 24B is a cross-sectional view taken along line bc in FIG.

  23 and 24, the same parts as those in FIGS. 8 and 9 are denoted by the same reference numerals for easy understanding.

In this pixel PX, a transparent electrode 209a is formed on the liquid crystal layer 211 side, contacts CNT1S and CNT1D are formed on the interlayer insulating film 210, and a source electrode 207A and a drain electrode 208A formed on the interlayer insulating film 210 are contacts CNT1S, The source region 207 and the drain electrode 208 are connected via the CNT1D.
Then, an interlayer insulating film 214 is formed on the interlayer insulating film 210, the source electrode 207A, and the drain electrode 208A, and a contact CNT2 is formed on the interlayer insulating film 214, and on the source electrode 207A and the interlayer insulating film 214 via the contact CNT2. The transparent electrode 209a is connected.

  In this pixel structure, the storage capacitor Cs is dominated by the two-layer Cs wiring, not between the Cs wiring LCs and the transparent electrode 209a. If the insulating film between the two layers is made thin, a larger storage capacity can be obtained.

FIG. 25 is a diagram illustrating a fifth configuration example of the Cs line of the pixel according to the present embodiment.
FIG. 26 is a diagram illustrating a sixth configuration example of the Cs line of the pixel according to the present embodiment.
27 is a cross-sectional view taken along line ab in FIG.

As shown in FIGS. 25 and 26, the upper and lower layers of the two-layer Cs wirings LCs1 and LCs2 are key-shaped and comb-shaped, so that a larger storage capacity can be obtained with the same area as the rectangular Cs-line structure.
As can be seen from the cross-sectional view of the Cs wiring portion of FIG. 25 shown in FIG. 27, it is possible to efficiently obtain the storage capacity even with the hole-type or comb-shaped (ladder-type) Cs wiring structure described above.

FIG. 28 is a diagram showing another pixel structure.
29A is a cross-sectional view taken along line ab in FIG. 28, and FIG. 29B is a cross-sectional view taken along line bc in FIG.

  28 and 29, the same parts as those in FIGS. 23 and 24 are denoted by the same reference numerals for easy understanding.

28 and 29 show a top gate type liquid crystal display device 100A.
The Cs wiring structure according to the present embodiment can be developed not only for the bottom gate type liquid crystal display device as described above but also for the top gate structure as shown in FIGS.
Also in the Cs wiring of the top gate, the storage capacitor can be efficiently formed by the Cs wiring structure of the key type, comb type, ladder type, and hole type.

Further, if the present invention is used, it can be used not only for the pixel portion but also for the capacitor forming portion of the drive circuit. In other words, the present invention can be applied to all circuits that need to acquire a larger capacity in a small area. By reducing the conventional wiring structure to a key shape and a comb shape, a reduction in layout area can be expected, and a narrow frame can be expected.
In addition, it is possible to form the storage capacitor wiring pattern differently between pixels, and in this case, it is also possible to prevent the occurrence of interference fringes due to interference at a specific wavelength and moire due to repeated geometric patterns. is there.

As described above, according to the present embodiment, the drive voltage to the signal line 106 is applied via the pixel electrode 111 connected to the liquid crystal cell corresponding to each pixel, and an image is displayed by these liquid crystal cells. In addition, in order to increase the liquid crystal applied voltage holding ratio of the pixel portion, the storage capacitor Cs for supplementing the holding capacitor is connected in parallel with the liquid crystal capacitor _CLC and the liquid crystal to drive the liquid crystal. In order to supply electric charge to the storage capacitor Cs with high efficiency and low power consumption, the structure of the Cs line LCs is a key type, comb type, ladder type, hole type, etc. In addition, since the branch wiring of the Cs wiring LCs and the hole-shaped structure portion are arranged at random periods, the generation of interference fringes due to interference of a specific wavelength with respect to transmitted light and moire caused by repeated geometric patterns is prevented. Possible it is.
In addition, with respect to the Cs wiring of adjacent pixels, various shapes of Cs wiring structures are introduced for each pixel, for example, a key shape, a comb shape, a hole shape, etc. Thus, the storage capacity can be efficiently generated without deteriorating visual characteristics.

  And according to this embodiment, without causing a change in the number of steps, device fabrication process, and display characteristics, it is possible to increase the transmittance by reducing the area of the Cs line and to reduce the power consumption by efficiently obtaining the fringe capacitance. Narrow frame due to downsizing, module downsizing due to downsizing of area of Cs line, downsizing of module due to downsizing of area of area, high definition by reduction of pixel part, downsizing of area of Cs line, reduction of capacity forming part of peripheral circuit part There is an advantage that it is possible to obtain an effect such as the conversion.

It is an equivalent circuit diagram of a general active matrix display device having a storage capacitor. It is a figure which shows a 1st prior art example. It is a figure which shows the 2nd prior art example. It is a figure which shows the 3rd prior art example. It is a figure which shows the 4th prior art example. It is a figure which shows the 5th prior art example. It is a figure which shows the example of arrangement | positioning in the array substrate (liquid crystal panel part) of the active matrix type liquid crystal display device which concerns on this embodiment. It is a figure which shows the example of a pattern of a basic pixel structure. It is sectional drawing in the ab line and bc line of FIG. FIG. 10 is a first view for explaining a method of manufacturing the liquid crystal display device shown in FIGS. 8 and 9. FIG. 10 is a second view for explaining the method of manufacturing the liquid crystal display device shown in FIGS. 8 and 9. FIG. 10 is a third view for explaining the method of manufacturing the liquid crystal display device shown in FIGS. 8 and 9. FIG. 10 is a fourth view for explaining the method of manufacturing the liquid crystal display device shown in FIGS. 8 and 9. FIG. 10 is a fifth view for explaining the method of manufacturing the liquid crystal display device shown in FIGS. 8 and 9. FIG. 10 is a sixth view for explaining the method of manufacturing the liquid crystal display device shown in FIGS. 8 and 9. It is a figure which shows the 1st structural example of the Cs line of the pixel which concerns on this embodiment. It is sectional drawing in the ab line | wire of FIG. It is a figure for demonstrating the principle in which the storage capacity wiring (Cs line) LCs which concerns on this embodiment can acquire a storage capacity efficiently. It is a figure which shows the result of having calculated the storage capacity in the key type Cs line structure based on this embodiment in the same area, and the storage capacity in a rectangular Cs line structure by electric field simulation. It is a figure which shows the 2nd structural example of Cs line | wire of the pixel which concerns on this embodiment. It is a figure which shows the 3rd structural example of the Cs line of the pixel which concerns on this embodiment. It is a figure which shows the 4th structural example of the Cs line of the pixel which concerns on this embodiment. It is a figure which shows another pixel structure. It is sectional drawing in the ab line and bc line of FIG. It is a figure which shows the 5th structural example of the Cs line of the pixel which concerns on this embodiment. It is a figure which shows the 6th structural example of the Cs line of the pixel which concerns on this embodiment. It is sectional drawing in the ab line | wire of FIG. It is a figure which shows another pixel structure. It is sectional drawing in the ab line | wire and bc of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100,100A ... Liquid crystal display device, 101 ... Pixel display area, 102 ... Horizontal transfer circuit, 103-1, 103-2 ... Vertical transfer circuit, 106 ... Signal line, 107 ... Gate wiring (scanning line), 108 ... transistor (TFT), 109 ... liquid crystal liquid crystal, 110 ... storage capacitor (Cs), 111 ... pixel electrode, LCs ... storage capacitor wiring (Cs) Line), PX ... pixel, 201 ... transparent insulating substrate (glass substrate), 202 ... gate insulating film, 203 ... gate electrode, 204 ... semiconductor film (channel formation region) 207, 208 ... n ⁺ diffusion layer (source region (electrode), drain region (electrode)), 207A ... source electrode, 208A ... drain electrode, 209, 209a ... transparent electrode, 211 ... liquid crystal layer 213 ... Counter electrode.

Claims (8)

An electric field drive type liquid crystal display device in which a drive voltage to a signal line is applied via a pixel electrode connected to a liquid crystal cell corresponding to each pixel, and a storage capacitor for supplementing a storage capacitor is in parallel with the liquid crystal capacitor. There,
A liquid crystal display device in which the storage capacitor wiring has an irregular pattern with different intervals. Storage capacitor wiring
The main line section;
A plurality of branch portions formed so as to branch from the main line portion,
The liquid crystal display device according to claim 1, wherein the plurality of branch portions have no periodicity. The storage capacitor wiring is
The liquid crystal display device according to claim 1, wherein a plurality of holes having different intervals are formed in the wiring. The storage capacitor wiring is
The liquid crystal display device according to claim 1, wherein a plurality of transmission holes are randomly formed in the wiring. The liquid crystal display device according to claim 1, wherein a pattern of the storage capacitor wiring is different between pixels. The storage capacitor wiring is
The liquid crystal display device according to claim 1, wherein the irregular pattern is formed as a pattern capable of suppressing interference at a specific wavelength with respect to transmitted light. The storage capacitor wiring is
The liquid crystal display device according to claim 1, wherein the irregular pattern is formed as a pattern having no wavelength dependency with respect to transmitted light. A drive voltage to the signal line is applied through a pixel electrode connected to a liquid crystal cell corresponding to each pixel, and an electric field drive type liquid crystal display device in which a storage capacitor for supplementing a storage capacitor is in parallel with the liquid crystal capacitor A manufacturing method comprising:
A method of manufacturing a liquid crystal display device, wherein storage capacitor wiring is formed to have irregular patterns with different intervals.

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