JP2009111202A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of a leakage current in a semiconductor device having a silicide film at the upper part of a heavily doped layer. <P>SOLUTION: A first MOS transistor has a first heavily doped layer 306a formed below the outer side part of a first sidewall spacer 305a in an active region 300x and a first silicide film 311a formed at the upper part of the first heavily doped layer 306a. A second MOS transistor has a second heavily doped layer 306b formed below the outer side part of a second sidewall spacer 305b in the active region 300x and a second silicide film 311b formed at the upper part of the second heavily doped layer 306b. The crystal grain diameter of crystal grains constituting the first silicide film 311a and the second silicide film 311b is equal to or less than an interval between the first sidewall spacer 305a and the second sidewall spacer 305b. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a silicide film on a high concentration diffusion layer and a manufacturing method thereof.

  An LDD (Lightly Doped Drain) structure is adopted to improve resistance to hot carriers in order to cope with miniaturization and high speed of MOS (Metal Oxide Semiconductor) transistors, and low resistance of gate electrodes and high-concentration diffusion layers. For the purpose of achieving this, a salicide technique is employed in which the upper portions of the gate electrode and the high-concentration diffusion layer are silicided (see, for example, Patent Document 1).

  In the past, a titanium silicide film was used as the silicide film, but the silicide film is usually polycrystalline and has a thermal expansion coefficient significantly different from that of silicon. As a result, the silicide film is disconnected and the gate electrode has a high resistance.

  Therefore, a technique using a nickel silicide film as a silicide film has been proposed for the purpose of suppressing disconnection of the silicide film (see, for example, Non-Patent Document 2 and Patent Document 3). Furthermore, since the junction depth of the high-concentration diffusion layer has become shallower with the miniaturization of semiconductor devices, a nickel silicide film with a low silicon content has been studied (for example, see Non-Patent Document 4).

  Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to FIGS. 10 (a) to 10 (c). 10 (a) to 10 (c) are cross-sectional views of main steps showing a conventional method of manufacturing a semiconductor device in the order of steps.

  First, as shown in FIG. 10A, an element isolation region 601 in which an insulating film is buried in a trench is selectively formed on a semiconductor substrate 600 made of silicon by an STI (Shallow Trench Isolation) method. . As a result, an active region 600x composed of the semiconductor substrate 600 surrounded by the element isolation region 601 is formed.

  Next, a first gate electrode 603a made of a polysilicon film having a thickness of 160 nm is formed on the active region 600x through a first gate insulating film 602a made of a silicon oxide film having a thickness of 5 nm. A second gate electrode 603b made of a polysilicon film having a thickness of 160 nm is formed on the active region 600x through a second gate insulating film 602b made of a silicon oxide film having a thickness of 5 nm. Thereafter, a first low-concentration diffusion layer 604a is formed below the first gate electrode 603a in the active region 600x, and a second lower side of the second gate electrode 603b in the active region 600x. A low concentration diffusion layer 604b is formed.

  Next, a first sidewall spacer 605a is formed on the side surface of the first gate electrode 603a, and a second sidewall spacer 605b is formed on the side surface of the second gate electrode 603b. Thereafter, a first high-concentration diffusion layer 606a is formed on the outer side of the first sidewall spacer 605a in the active region 600x, and at the same time on the outer side of the second sidewall spacer 605b in the active region 600x. 2 high-concentration diffusion layers 606b are formed.

  Next, as shown in FIG. 10B, a metal film 607 made of a Ni film having a thickness of 20 nm is formed on the entire surface of the semiconductor substrate 600 under the conditions of a pressure of 0.27 Pa and a DC power of 100 W. At this time, the film thickness of the metal film 607 is set according to the junction depth (see FIG. 10C: D) of the high concentration diffusion layers 606a and 606b. As a result, in the next step shown in FIG. 10C, the first and second silicide films (FIG. 10C: 609a, 609a formed on the first and second high-concentration diffusion layers 606a and 606b are formed. 609b) is formed thick to prevent the first and second high-concentration diffusion layers 606a and 606b from penetrating.

  Next, as shown in FIG. 10 (c), the first heat treatment is performed at 330 ° C. for 60 seconds using the RTA apparatus, and the first and second gate electrodes 603a, 603b and the first and second gates are then performed. Si of the high concentration diffusion layers 606a and 606b is reacted with Ni of the metal film 607. Thereafter, an unreacted metal film remaining on the semiconductor substrate 600 using an acidic chemical solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide solution are mixed, or an alkaline chemical solution in which ammonium hydroxide and hydrogen peroxide solution are mixed. 607 is removed. Thereafter, a second heat treatment is performed at 450 ° C. for 60 seconds. In this manner, the first on-gate silicide film 608a made of NiSi film is formed on the first gate electrode 603a, and the first silicide made of NiSi film is formed on the first high-concentration diffusion layer 606a. A film 609a is formed. On the other hand, a second on-gate silicide film 608b made of NiSi film is formed on the second gate electrode 603b, and a second silicide film 609b made of NiSi film is formed on the second high-concentration diffusion layer 606b. Form.

As described above, in the conventional method for manufacturing a semiconductor device, as a method for forming a silicide film, the metal film 607 having a film thickness corresponding to the junction depth D of the high-concentration diffusion layers 606a and 606b is formed on the entire surface of the semiconductor substrate 600. The method of heat-treating in the state formed is adopted.
Japanese Patent Laid-Open No. 8-46189 Proc. IEEE VMIC Conf. 267 (1992) JP 2007-88255 A IEDM Technical. Digest, p. 45-48, 2000.

  At present, the shallow junction of the high-concentration diffusion layer is further advanced. Therefore, the conventional method for manufacturing a semiconductor device has the following problems.

  The silicide films 609a and 609b formed on the upper portions of the high-concentration diffusion layers 606a and 606b are formed in a state where unevenness is generated at the NiSi-Si interface as shown in FIG. Therefore, as the shallow junction of the high-concentration diffusion layer further progresses, a silicide film (particularly, a convex portion) is formed through the high-concentration diffusion layer (or close to the junction of the high-concentration diffusion layer). There is a problem that leakage current occurs. As described above, in the conventional method for manufacturing a semiconductor device, leakage current is generated only by setting the thickness of the metal film 607 to a predetermined thickness according to the junction depth D of the high-concentration diffusion layers 606a and 606b. Cannot be reliably prevented.

  In view of the above, an object of the present invention is to accurately form a silicide film on the upper portion of the high-concentration diffusion layer (specifically, by forming a silicide film without generating irregularities at the interface with Si), This is to prevent the occurrence of leakage current.

  In order to achieve the above object, a first semiconductor device manufacturing method according to the present invention includes: a first transistor having a first gate electrode on an active region surrounded by an element isolation region in a semiconductor substrate; In a method for manufacturing a semiconductor device including a second transistor having a second gate electrode, a first gate electrode is formed on the active region via a first gate insulating film, and the first gate electrode is formed on the active region. A step (a) of forming a second gate electrode through two gate insulating films, a first sidewall spacer is formed on a side surface of the first gate electrode, and a side surface of the second gate electrode is formed. Forming a second sidewall spacer on the first region, forming a first high-concentration diffusion layer outside the first sidewall spacer in the active region, and forming a second sidewall spacer in the active region. A step (c) of forming a second high-concentration diffusion layer on the outer side of the wall spacer, and a natural oxide film formed on the surfaces of the first high-concentration diffusion layer and the second high-concentration diffusion layer. Included in the metal layer is a step (d) for removing, a step (e) for forming a metal layer in which a single film made of metal and a film containing gas and containing metal are sequentially laminated on a semiconductor substrate And a metal contained in the first high-concentration diffusion layer is reacted to form a first silicide film on the first high-concentration diffusion layer, and the metal contained in the metal layer and the second And (f) forming a second silicide film on the second high concentration diffusion layer by reacting with silicon contained in the high concentration diffusion layer. In the step (f), the first silicide The film and the second silicide film have a crystal grain size of the first support. Characterized in that it is formed to be equal to or less than the spacing between the de-wall spacer and the second sidewall spacer.

  According to the first method for manufacturing a semiconductor device of the present invention, the metal layer in which the single layer film and the containing film are sequentially stacked is subjected to heat treatment in a state in which the metal layer is formed on the semiconductor substrate. Since the Si of the first and second high-concentration diffusion layers can be reacted slowly and intermittently, a relatively small crystal grain size (that is, between the first sidewall spacer and the second sidewall spacer) The first and second silicide films having a crystal grain size equal to or smaller than the interval and having a relatively small variation in crystal grain size can be formed. For this reason, the first and second silicide films have no irregularities at the interface with Si, can prevent the occurrence of junction leakage current due to the abnormal growth portion extending in the depth direction, and abnormal growth extending in the lateral direction. Generation of leakage current between the source and drain due to the portion can be prevented.

  In order to achieve the above object, a second method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a transistor having a gate electrode on an active region surrounded by an element isolation region in a semiconductor substrate. , A step (a) of forming a gate electrode on the active region through a gate insulating film, a step (b) of forming a sidewall spacer on the side surface of the gate electrode, and an outer side of the sidewall spacer in the active region. A step (c) of forming a high-concentration diffusion layer below, a step (d) of removing a natural oxide film formed on the surface of the high-concentration diffusion layer, a single film made of metal on a semiconductor substrate, A step (e) for forming a metal layer in which a gas-containing metal-containing film is sequentially laminated, and a metal contained in the metal layer and a silicon contained in the high-concentration diffusion layer are reacted to produce a high concentration A step (f) of forming a silicide film on the upper part of the diffusion layer, and in the step (f), the silicide film has a crystal grain size of not more than a width in the gate width direction of the active region. It is formed.

  According to the second method for manufacturing a semiconductor device of the present invention, the metal layer in which the single layer film and the containing film are sequentially stacked is heat-treated in a state in which the single layer film and the containing film are formed on the semiconductor substrate. Since it can react with Si in the concentration diffusion layer gently and intermittently, it has a relatively small crystal grain size (that is, a crystal grain size equal to or smaller than the width of the active region in the gate width direction) and the crystal grain A silicide film with relatively small diameter variation can be formed. For this reason, the silicide film has no unevenness at the interface with Si, and in particular, it is possible to prevent the occurrence of junction leakage current due to the abnormally grown portion extending in the depth direction.

  In the first or second method for manufacturing a semiconductor device according to the present invention, the step (e) is a step (e1) of forming a single film on the semiconductor substrate by a first sputtering method using argon gas plasma. And a step (e2) of forming a containing film on the single film by a second sputtering method using argon gas plasma and gas plasma.

  In the first or second method for manufacturing a semiconductor device according to the present invention, the gas is preferably nitrogen gas or oxygen gas.

  In the first or second method for manufacturing a semiconductor device according to the present invention, the metal is preferably made of titanium, cobalt, nickel, platinum, hafnium, or palladium.

In the first or second method for manufacturing a semiconductor device according to the present invention, the step (d) is preferably performed by a chemical dry etching method. Specifically, for example, NF ₃ gas plasma and H ₂ gas It is preferably performed by a chemical dry etching method using plasma.

  In order to achieve the above object, a first semiconductor device according to the present invention includes a first transistor having a first gate electrode in an active region surrounded by an element isolation region in a semiconductor substrate, and a second gate. In a semiconductor device including a second transistor having an electrode, the first transistor includes a first gate insulating film formed over the active region and a first gate insulating film formed over the first gate insulating film. A gate electrode, a first sidewall spacer formed on a side surface of the first gate electrode, a first high-concentration diffusion layer formed on the outside of the first sidewall spacer in the active region, A first silicide film formed on the first high-concentration diffusion layer, and the second transistor includes a second gate insulating film formed on the active region and a second gate insulating film Formed in the second A gate electrode, a second side wall spacer formed on the side surface of the second gate electrode, a second high-concentration diffusion layer formed outside the second side wall spacer in the active region, And a second silicide film formed on the second high-concentration diffusion layer, and the crystal grain size of the crystal grains constituting the first silicide film and the second silicide film is the first sidewall. The distance between the spacer and the second sidewall spacer is equal to or smaller than the distance.

  According to the first semiconductor device of the present invention, the crystal grains of the first and second silicide films have a crystal grain size between the first sidewall spacer and the second sidewall spacer (that is, the leakage current). Therefore, the occurrence of leakage current can be prevented.

  In the first semiconductor device according to the present invention, the conductivity types of the first transistor and the second transistor are p-type, and the crystal grain sizes of the crystal grains constituting the first silicide film and the second silicide film Is preferably 10 nm or more and 130 nm or less.

  In the first semiconductor device according to the present invention, the conductivity type of the first transistor and the second transistor is n-type, and the crystal grain size of the crystal grains constituting the first silicide film and the second silicide film Is preferably 10 nm or more and 70 nm or less.

  In the first semiconductor device according to the present invention, the first silicide film and the second silicide film are made of a titanium silicide film, a cobalt silicide film, a nickel silicide film, a platinum silicide film, a hafnium silicide film, or a palladium silicide film. It is preferable.

  In order to achieve the above object, a second semiconductor device according to the present invention is a semiconductor device including a transistor having a gate electrode on an active region surrounded by an element isolation region in a semiconductor substrate. A gate insulating film formed on the region; a gate electrode formed on the gate insulating film; a sidewall spacer formed on a side surface of the gate electrode; and an outer side of the sidewall spacer in the active region. A high-concentration diffusion layer and a silicide film formed on the high-concentration diffusion layer, and the crystal grain size of the crystal grains constituting the silicide film is less than the width of the active region in the gate width direction. Features.

  According to the second semiconductor device of the present invention, since the crystal grain size of the crystal grains constituting the silicide film is equal to or smaller than the width of the active region in the gate width direction, it is possible to particularly prevent the occurrence of junction leakage current.

  In the second semiconductor device according to the present invention, the conductivity type of the transistor is p-type, and the crystal grain size of the crystal grains constituting the silicide film is preferably 10 nm or more and 130 nm or less.

  In the second semiconductor device according to the present invention, the conductivity type of the transistor is n-type, and the crystal grain size of the crystal grains constituting the silicide film is preferably 10 nm or more and 70 nm or less.

  In the second semiconductor device according to the present invention, the silicide film is preferably made of a titanium silicide film, a cobalt silicide film, a nickel silicide film, a platinum silicide film, a hafnium silicide film, or a palladium silicide film.

  According to the semiconductor device and the method for manufacturing the same according to the present invention, the metal layer in which the single layer film and the containing film are sequentially stacked is heat-treated in a state where the metal layer is formed on the semiconductor substrate. Since the layer Si can be allowed to react slowly and intermittently, a relatively small crystal grain size (for example, a crystal grain size equal to or smaller than the interval between the first sidewall spacer and the second sidewall spacer, or A silicide film having a crystal grain size equal to or smaller than the width of the active region in the gate width direction and having a relatively small variation in crystal grain size can be formed. Therefore, the silicide film has no unevenness at the interface with Si, and leakage current due to the convexly formed portion of the silicide film can be prevented.

  Embodiments of the present invention will be described below with reference to the drawings.

  Here, as a result of the cumulative distribution of leak current (see FIGS. 6A and 6B described later), the result of the distribution of the crystal grain size of the silicide film (see FIGS. 3A and 3B described later), etc. As a result of extensive studies by the present inventors based on the above, the mechanism by which irregularities occur at the NiSi-Si interface in the conventional silicide film is presumed as follows. This mechanism will be described with reference to FIGS. 11 (a) to 11 (e). 11 (a) to 11 (e) are diagrams showing a mechanism in which unevenness is generated at the NiSi-Si interface in the conventional silicide film. In order to simplify the explanation of this mechanism, a conventional method for forming a silicide film on a p-type (or n-type) diffusion layer formed on a semiconductor substrate made of silicon is used. A case where a silicide film is formed will be described as a specific example. For the sake of simplicity, the “seed” shown in FIG. 11B is shown in a circle, and the “crystal grains” shown in FIGS. 11C to 11D are shown in an ellipse. These are all shown and may be different from the actual shape.

  As shown in FIG. 11A, a p-type (or n-type) diffusion layer is implanted into a semiconductor substrate 700 by implanting p-type impurities (or n-type impurities) into the semiconductor substrate 700 made of silicon by ion implantation. Form. Thereafter, a cleaning process using a HF chemical solution is performed to remove a natural oxide film (not shown) formed on the surface of the diffusion layer, and then a metal film 701 made of a Ni film is formed on the semiconductor substrate 700. Form.

  Next, as shown in FIG. 11B, when the first heat treatment is started, Ni silicide seeds 702 are diffused and formed on the upper part of the diffusion layer. Thus, since the Ni of the metal film 701 is rapidly diffused into the diffusion layer with the start of the first heat treatment, the seed 702 is formed unevenly on the diffusion layer. In particular, when the clean state of the Ni / Si interface is non-uniform, the seed 702 is formed more non-uniformly on the upper part of the diffusion layer.

  Next, as shown in FIG. 11 (c), as the first heat treatment proceeds, Ni in the metal film 701 is diffused toward the seed 702, the seed 702 grows, and Ni silicide crystal grains 703 are formed. As it is formed, a diffusion path 704 is locally generated in the gap between the crystal grains 703.

  Next, as shown in FIG. 11D, as the first heat treatment further proceeds, Ni in the metal film 701 is diffused through the locally generated diffusion path 704. Thereby, Ni diffusion in the depth direction becomes dominant, and Ni silicide crystal grains 705 are formed so as to block the diffusion path 704.

  Finally, as shown in FIG. 11E, after the unreacted metal film 701 remaining on the semiconductor substrate 700 is removed, a silicide film 706 made of a NiSi film is formed on the diffusion layer by the second heat treatment. It is formed. Note that a dotted line illustrated in the silicide film 706 indicates a crystal grain boundary.

  In this way, a silicide film 706 having a relatively large crystal grain size, unevenness at the NiSi / Si interface, an abnormally grown portion 707 extending in the depth direction, and an abnormally growing portion 708 extending in the lateral direction. Is presumed to be formed.

  Here, in the silicide film 706, the inventors infer that the abnormal growth portion 707 extending in the depth direction and the abnormal growth portion 708 extending in the lateral direction are formed as follows.

  First, the inventors of the present invention infer the cause of the abnormal growth portion 707 extending in the depth direction as follows. In the conventional method for forming a silicide film, with the start of the first heat treatment, Ni in the metal film 701 is rapidly diffused in the diffusion layer, and the seed 702 is formed unevenly (see FIG. 11B). . Therefore, the crystal grains 703 are formed unevenly, the diffusion path 704 is locally generated (see FIG. 11C), and Ni in the metal film 701 is diffused through the locally generated diffusion path 704. Crystal grains 705 that are continuously diffused in the layer and extend in the depth direction are formed (see FIG. 11D). For this reason, as shown in FIG. 11E, it is presumed that an abnormally grown portion 707 extending in the depth direction is formed in the silicide film 706.

  Next, the present inventors infer the cause of the formation of the abnormally growing portion 708 extending in the lateral direction as follows. In the conventional method of forming a silicide film, Ni in the metal film 701 is rapidly diffused in the diffusion layer with the start of the first heat treatment, and the metal film 701 is diffused into the diffusion layer during the first heat treatment. Ni diffusion continues continuously without being interrupted (see FIGS. 11B to 11D). For this reason, the crystal grain size continuously grows without being interrupted, and it is assumed that an abnormally grown portion 708 extending in the lateral direction is formed in the silicide film 706 as shown in FIG. 11 (e). .

  Therefore, in the conventional semiconductor device, the abnormally grown portion extending in the depth direction of the silicide film (see FIG. 11E: 707) is close to the junction of the high concentration diffusion layer or the high concentration diffusion layer is formed. Since it penetrates, it is considered that junction leakage current occurs. Further, the abnormally grown portion (see FIG. 11 (e): 708) extending in the lateral direction in the silicide film extends below the side wall spacer, so that it is considered that a source-drain leakage current is generated.

  As described above, in the conventional method of manufacturing a semiconductor device, Ni of a metal film set to a predetermined film thickness according to the junction depth of the high concentration diffusion layer and Si are reacted rapidly and continuously. Therefore, since the nonuniformly formed crystal grains continuously grow, a silicide film having a relatively large crystal grain size is formed, and in the silicide film, an abnormally grown portion extending in the depth direction and extending in the lateral direction. It is considered that an abnormally grown portion is formed, that is, irregularities are generated at the interface with Si.

  Therefore, as a result of further intensive studies based on the above consideration, the present inventors have a relatively small crystal grain size in order to prevent irregularities from occurring at the interface with Si in the silicide film. It was found that it is important to form a silicide film, and furthermore, by uniformly and intermittently reacting a metal (for example, Ni) and Si, the uniformly formed crystal grains are grown intermittently. The inventors have found that a silicide film having a relatively small crystal grain size is formed.

(First embodiment)
Hereinafter, a method for forming a silicide film according to the first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (c). FIGS. 1A to 1C are principal part process cross-sectional views illustrating the silicide film forming method according to the first embodiment of the present invention in the order of processes.

As shown in FIG. 1A, a p-type impurity (or n-type impurity) is implanted into a semiconductor substrate 100 made of silicon by an ion implantation method, and a p-type (or n-type) diffusion layer is formed in the semiconductor substrate 100. To do. Thereafter, a natural oxide film (not shown) formed on the surface of the diffusion layer is removed by in-situ pretreatment. Here, the in-situ pre-processing is as follows. Under a microwave power source of 1 kW, a gas flow rate of N ₂ / H ₂ / NF ₃ = 850/100/200 cc / min, and a pressure of 400 Pa, hydrogen gas is irradiated with microwaves to generate hydrogen radicals, and NF ₃ gas Is activated to generate NH _x F _y gas (etchant gas). This etchant gas is supplied onto the semiconductor substrate 100 by a remote plasma method, and the etchant gas reacts with the natural oxide film on the surface of the diffusion layer to remove the natural oxide film (that is, by chemical dry etching). , Remove the natural oxide film). Thereafter, the by-product generated during the reaction between the etchant gas and the natural oxide film is sublimated and removed by annealing at 180 ° C. for 100 seconds. In this way, a diffusion layer having a uniform surface clean state is obtained.

Next, as shown in FIG. 1B, a metal layer 103 in which a single film made of a Ni film and a containing film containing nitrogen and a Ni film are sequentially laminated is formed by sputtering. Specifically, as shown in FIG. 1B, the metal layer 103 is a layer in which the single film 101a, the containing film 102a, the single film 101b, the containing film 102b, and the single film 101c are sequentially stacked. Here, as the single films 101a, 101b, and 101c, for example, film formation is performed for 10 seconds under a gas flow rate of Ar = 80 cc / min, a pressure of 0.4 Pa, a DC power of 3 kW, and a film thickness of 5 nm. A single film is formed. Further, as the containing films 102a and 102b, for example, the film thickness is 20 seconds under the condition that the gas flow rate is Ar / N ₂ = 40/60 cc / min, the pressure is 0.05 Pa, the DC power is 3 kW. A 5.5 nm-containing film is formed.

  Next, as shown in FIG. 1C, the first heat treatment is performed at 330 ° C. for 60 seconds, for example, to react Ni of the metal layer 103 with Si of the diffusion layer. Thereafter, an unreacted metal layer remaining on the semiconductor substrate 100 using an acidic chemical solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide solution are mixed, or an alkaline chemical solution in which ammonium hydroxide and hydrogen peroxide solution are mixed. 103 is removed. Thereafter, a second heat treatment is performed at 450 ° C. for 60 seconds, for example. In this way, the silicide film 104 made of the NiSi film is formed on the diffusion layer. A dotted line shown in the silicide film 104 indicates a crystal grain boundary.

  As described above, the silicide film according to this embodiment can be formed.

  According to the present embodiment, instead of adopting a metal film consisting only of a Ni film as in the prior art, as shown in FIG. 1 (b), a single film consisting only of a Ni film and a Ni film containing nitrogen are used. A metal layer 103 in which contained films are sequentially stacked is used. This allows Ni in the metal layer 103 and Si in the diffusion layer to react slowly and intermittently, so that the crystal grains uniformly formed on the upper portion of the diffusion layer are intermittently grown, The silicide film 104 having a small crystal grain size (specifically, for example, a crystal grain size equal to or smaller than the interval between the sidewall spacers or a crystal grain diameter equal to or smaller than the width of the active region in the gate width direction) can be formed. Therefore, it is possible to prevent unevenness from occurring at the NiSi / Si interface in the silicide film 104.

  In other words, conventionally, in a metal film composed only of a Ni film, the film thickness is set considering only the junction depth of the high-concentration diffusion layer. In the metal layers sequentially stacked, the scale of the region where the silicide film is formed by adding the film thickness of the single film, the film thickness of the contained film, and the nitrogen content of the contained film to the junction depth of the high concentration diffusion layer Set in consideration of. Specifically, for example, in addition to the junction depth of the high-concentration diffusion layer, the narrowest region (specifically, for example, a high-concentration diffusion layer sandwiched between sidewall spacers, Alternatively, it is set in consideration of a high concentration diffusion layer sandwiched between element isolation regions orthogonal to the gate electrode. Accordingly, it is possible to realize Ni diffusion controlled in multiple stages, not disordered Ni diffusion as in the prior art, and it is possible to prevent unevenness from occurring at the interface with Si in the silicide film.

  In recent years, for the purpose of suppressing rapid diffusion of Ni, there has been proposed a method of performing a heat treatment in a state where a suppression film is interposed between a semiconductor substrate and a metal film made of only a Ni film. In the method, even if the suppression effect by the suppression film is obtained in the initial stage of the silicide reaction, as soon as the suppression film is broken, Ni is dominantly diffused in the depth direction through the breakdown, and abnormal growth occurs. There is a problem that a silicide film having a portion is formed. On the other hand, in this embodiment, since a heat treatment method is adopted in which a metal layer in which a single film and a containing film are sequentially laminated is formed on a semiconductor substrate, rapid Ni diffusion is effectively prevented. Can be suppressed.

  Here, as a result of the cumulative distribution of leak current (see FIGS. 6A and 6B described later), the result of the distribution of the crystal grain size of the silicide film (see FIGS. 3A and 3B described later), etc. Based on the above, the present inventors infer the mechanism of the formation of the silicide film of the present invention as follows. This mechanism will be described with reference to FIGS. 2 (a) to (f). 2 (a) to 2 (f) are diagrams showing the mechanism by which the silicide film of the present invention is formed. 2 (a) corresponds to FIG. 1 (b), and FIG. 2 (f) corresponds to FIG. 1 (c). In order to simplify the explanation of this mechanism, the “seed” shown in FIG. 2 (b) and the “crystal grains” shown in FIGS. 2 (c) to 2 (e) are both circular. It may be different from the actual shape.

  With the start of the first heat treatment, mainly Ni in the single film 101a is uniformly diffused in the diffusion layer. As a result, as shown in FIG. 2B, the Ni silicide seed 200 is uniformly formed on the diffusion layer. Thus, in this embodiment, the diffusion source of Ni diffused in the diffusion layer is mainly the single film 101a, and the single film 101a is formed to be relatively thin, and the surface of the diffusion layer is Since the clean state is uniform, the seed 200 is uniformly formed on the diffusion layer.

  As the first heat treatment proceeds, Ni in the single-layer film 101a having a relatively thin film thickness is gradually diffused toward the seed 200, and the seed 200 grows slowly, and Ni silicide crystal grains (FIG. 2 (c) : 201) is formed.

  When Ni in the single film 101a is consumed, the containing film 102a covers the semiconductor substrate 100 as shown in FIG. Thereby, Ni diffusion from the single film 101b formed on the containing film 102a is suppressed.

  At the same time, Ni in the containing film 102a containing nitrogen is gradually diffused through the uniform diffusion path (see FIG. 2C: arrow) generated in the gap between the crystal grains 201, and the crystal It diffuses gently toward the grains 201. This prevents Ni from being diffused abruptly to generate a non-uniform diffusion path, and prevents the crystal grains 201 from growing abruptly and causing the crystal grain diameter to increase suddenly. In this manner, new Ni silicide seeds are uniformly formed in the diffusion layer by uniform grain boundary diffusion, and the seeds are gradually grown to form new Ni silicide crystal grains uniformly. In this way, crystal grains having a small crystal grain size are formed in layers.

  Note that the Ni diffusion rate from the single film is estimated to be faster than the Ni diffusion rate from the contained film. This is believed to be due to differences based on the presence or absence of nitrogen. Further, it is estimated that the amount of Ni diffused through the uniform diffusion path is larger than the amount of Ni diffused toward the crystal grains. This is because Ni diffused toward the crystal grains is supplied to the crystal grains (that is, Ni silicide), whereas Ni diffused through the uniform diffusion path is supplied to Si in the diffusion layer. I believe that.

  When Ni in the containing film 102a is consumed, the single film 101b covers the semiconductor substrate 100. Then, Ni in the single film 101b is gently diffused through the uniform Ni diffusion path to uniformly form Ni silicide crystal grains (see FIG. 2 (d): 202) and toward the crystal grains. Slowly diffused and crystal grains grow slowly, and Ni silicide crystal grains (see FIG. 2 (d): 203) are formed.

  When Ni in the single film 101b is consumed, the containing film 102b covers the semiconductor substrate 100 as shown in FIG. Thereby, Ni diffusion from the single film 101c formed on the containing film 102b is suppressed. At the same time, Ni in the contained film 102b is gradually diffused through the uniform diffusion path (see FIG. 2D: arrow) generated in the gap between the crystal grains 203 and directed toward the crystal grains 203. And diffuse slowly.

  When the Ni in the containing film 102b is consumed, the single film 101c covers the semiconductor substrate 100 as shown in FIG. Then, Ni in the single film 101c is gently diffused through a uniform Ni diffusion path (see FIG. 2 (e): arrow) so that the crystal grains 202 grow slowly, and Ni silicide crystal grains 204 are formed. At the same time, the crystal grains 203 are gradually diffused toward the crystal grains 203 to grow slowly, and Ni silicide crystal grains 205 are formed.

  Thereafter, the unreacted metal layer 103 remaining on the semiconductor substrate 100 is removed, and then a second heat treatment is performed. In this way, as shown in FIG. 2 (f), it is presumed that a silicide film 104 having a relatively small crystal grain size and having no unevenness is formed at the NiSi / Si interface.

  In order to effectively explain the effects of the present invention, the silicide film of the present invention formed by the silicide film forming method according to the first embodiment and the conventional method of forming the conventional silicide film are described below. This will be described in comparison with the silicide film.

  The inventors of the present invention compared the crystal grain size (grain size) between the silicide film of the present invention and the conventional silicide film, and found that the following is shown. The results of the crystal grain size will be described with reference to FIGS. 3 (a) and 3 (b). FIGS. 3A and 3B are graphs showing the distribution of the crystal grain size of the silicide film. Specifically, FIG. 3 (a) is a graph showing the distribution of the crystal grain size of the silicide film formed on the p-type diffusion layer. Specifically, the solid line shows the silicide film of the present invention. A broken line shows a conventional silicide film. On the other hand, FIG. 3B is a graph showing the distribution of the crystal grain size of the silicide film formed on the upper part of the n-type diffusion layer. Specifically, the solid line shows the silicide film of the present invention, and the broken line shows the conventional one. The silicide film is shown.

  Here, the evaluation method of the crystal grain size is as follows.

  The average crystal grain size was determined for each of the conventional silicide film and the SEM (scanning photomicrograph) image or TEM (transmission photomicrograph) image of the silicide film of the present invention using the line intercept method. In addition, about the SEM image (or TEM image), the SEM image (or TEM image) area | region which has an area about 10 times with respect to the area of a crystal grain was made into object.

  First, when the conventional silicide film formed on the p-type diffusion layer and the silicide film of the present invention formed on the p-type diffusion layer were compared, the following was found.

  In the case of the conventional silicide film, as shown by the broken line in FIG. 3A, the crystal grain size with the highest frequency is 120 nm to 130 nm, and the range of the crystal grain size is a few tens to 200 nm. From this, 1) the most frequent crystal grain size is very large as 120 nm to 130 nm, and 2) the range of crystal grain size is from several tens of nm to over 200 nm, and the variation in crystal grain size is large. found.

  On the other hand, in the case of the silicide film of the present invention, as shown by the solid line in FIG. 3A, the most frequent crystal grain size is 60 nm, and the crystal grain size range is 10 nm to 130 nm. From this, 1) The most frequent crystal grain size is reduced to about one-half that of the prior art, and 2) The variation in crystal grain size is smaller than the conventional one. ,There was found.

  Next, when the conventional silicide film formed on the n-type diffusion layer and the silicide film of the present invention formed on the n-type diffusion layer were compared, the following was found.

  In the case of a conventional silicide film, as shown by the broken line in FIG. 3 (b), the crystal grain size with the highest frequency is 160 nm to 180 nm, and the range of crystal grain size is less than 100 nm to less than 300 nm. From this, it was found that 1) the crystal grain size with the highest frequency is as very large as 160 nm to 180 nm, and 2) the range of the crystal grain size is from less than 100 nm to less than 300 nm, and the variation is large.

  On the other hand, in the case of the silicide film of the present invention, as shown by the solid line in FIG. 3B, the most frequent crystal grain size is 30 nm, and the crystal grain size range is 10 nm to 70 nm. From this, 1) the most frequent crystal grain size is reduced to about one-sixth of the conventional one, and 2) the variation in crystal grain size is extremely small compared to the conventional one. It has been found.

  From these facts, it can be seen that it is important to reduce the crystal grain size and the variation in order to realize a silicide film having no unevenness at the interface with Si.

  The reason why reducing the crystal grain size of the silicide film is effective in preventing the occurrence of leakage current will be described below with reference to FIGS. 4 (a) and 4 (b). FIG. 4A is a diagram showing a case where the silicide film of the present invention is formed on the high concentration diffusion layer, and FIG. 4B is a diagram showing a conventional silicide film formed on the high concentration diffusion layer. FIG. In this description, as shown in FIGS. 4A and 4B, the sidewall spacer width Wa is 40 nm, the interval Wb between adjacent sidewall spacers is 60 nm, and the interval Wc between adjacent gate electrodes is 140 nm. The semiconductor device will be described as a specific example.

  For example, in the case of a conventional silicide film formed on a p-type diffusion layer, the most frequent crystal grain size is 120 nm to 130 nm (see FIG. 3 (a)), as shown in FIG. 4 (b). Assuming that the crystal grain size of the crystal grain P of the silicide film formed on the p-type high concentration diffusion layer is 120 nm to 130 nm and the shape of the crystal grain P is circular, the crystal grain P is a sidewall. It can be seen that the leakage current between the source and the drain is generated because it also exists under the sidewall spacer beyond the region between the spacers. In the case of the conventional silicide film formed on the upper part of the n-type diffusion layer, the most frequent crystal grain size is 160 nm to 180 nm (see FIG. 3B), as shown in FIG. 4B. Assuming that the crystal grain size of the crystal grain N of the silicide film formed on the upper part of the n-type high-concentration diffusion layer is 160 nm to 180 nm and the shape of the crystal grain N is circular, the crystal grain N It can be seen that it exists under the sidewall spacer beyond the region between the spacers, and a source-drain leakage current is generated.

  In FIG. 4B, the case where the center of the crystal grain P and the crystal grain N is located at the center between the side wall spacers is described as a specific example. However, the center of the crystal grain P and the crystal grain N is Needless to say, in any case between the sidewall spacers, when the crystal grain size exceeds 60 nm, which is the interval Wb between the sidewall spacers, a source-drain leakage current is generated.

  In contrast, in the case of the silicide film of the present invention formed on the p-type diffusion layer, the most frequent crystal grain size is 60 nm (see FIG. 3 (a)), as shown in FIG. 4 (a). Further, assuming that the crystal grain size P of the silicide film formed on the upper part of the p-type high concentration diffusion layer is 60 nm and the shape of the crystal grain P is circular, the crystal grain P is a sidewall spacer. The leakage current between the source and the drain does not occur. However, when the center of the crystal grain P is not located at the center between the side wall spacers as shown in FIG. 4A, but located outside the center between the side wall spacers, the crystal grain P is below the side wall spacer. However, the silicide film of the present invention can effectively prevent the occurrence of leakage current between the source and the drain as compared with the conventional silicide film. In the case of the silicide film of the present invention formed on the upper part of the n-type diffusion layer, the most frequent crystal grain size is 30 nm (see FIG. 3B), and as shown in FIG. Assuming that the crystal grain size N of the silicide film formed on the upper part of the n-type high concentration diffusion layer is 30 nm and the shape of the crystal grain N is circular, the crystal grain N is between the sidewall spacers. It exists in the region and no source-drain leakage current occurs. In addition, even when the center of the crystal grain N is not located at the center between the side wall spacers as shown in FIG. The possibility of being present under the wall spacer is low, and it can be seen that the silicide film of the present invention can very effectively prevent the occurrence of leakage current between the source and the drain as compared with the conventional silicide film.

  In the first embodiment, the case where the Ni film containing nitrogen is used as the containing films 102a and 102b has been described as a specific example. However, the present invention is not limited to this, and for example, oxygen Even in the case of using the Ni film containing Ni, an effect similar to that of the first embodiment can be obtained.

  In the first embodiment, the case where nickel is used as the metal contained in the metal layer 103 has been described as a specific example. However, the present invention is not limited to this, and for example, titanium, cobalt, Platinum, hafnium, or palladium may be used. In that case, a titanium silicide film, a cobalt silicide film, a platinum silicide film, a hafnium silicide film, or a palladium silicide film is formed as the silicide film 104.

  In the first embodiment, as the metal layer 103, a case where a metal layer in which five films of the single film 101a, the containing film 102a, the single film 101b, the containing film 102b, and the single film 101c are sequentially stacked is used. Although described by way of example, the present invention is not limited to this.

  First, for example, a metal layer in which two films of a single film and a containing film are sequentially stacked may be used. In this case, it is preferable that the single film is thin and the containing film is thick. Thereby, the metal contained in the metal layer can be diffused slowly and intermittently in the diffusion layer.

  Second, for example, a metal layer in which three films of a single film, a containing film, and a single film are sequentially stacked may be used. In this case, similarly to the above case, it is preferable that the single film is formed thin and the containing film is formed thick. In addition, when the structure of a metal layer is three or more films | membranes, you may form the film thickness of a single film | membrane and the film thickness of a containing film | membrane identically.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 5 (a) to 5 (c). FIGS. 5A to 5C are cross-sectional views of relevant steps showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. Note that the semiconductor device according to the second embodiment is a semiconductor device having a silicide film formed using the silicide film forming method according to the first embodiment above the high-concentration diffusion layer.

  As shown in FIG. 5A, an element isolation region 301 in which an insulating film is buried in a trench is selectively formed on a semiconductor substrate 300 made of silicon by an STI (Shallow Trench Isolation) method. As a result, an active region 300 x composed of the semiconductor substrate 300 surrounded by the element isolation region 301 is formed.

  Next, a first gate electrode 303a made of, for example, a 120 nm-thickness polysilicon film is formed on the active region 300x via a first gate insulating film 302a made of, for example, a 2 nm-thickness silicon oxide film. At the same time, a second gate electrode 303b made of, for example, a 120 nm-thickness polysilicon film is formed on the active region 300x via a second gate insulating film 302b made of, for example, a 2 nm-thickness silicon oxide film. To do. Thereafter, a p-type impurity (or n-type impurity) is implanted into the active region 300x by ion implantation using the first and second gate electrodes 303a and 303b as a mask, thereby forming a first gate in the active region 300x. A p-type (or n-type) first low-concentration diffusion layer 304a having a relatively shallow junction depth is formed below the side of the electrode 303a, and below the side of the second gate electrode 303b in the active region 300x. Then, the p-type (or n-type) second low-concentration diffusion layer 304b having a relatively shallow junction depth is formed.

  Next, a first sidewall spacer 305a is formed on the side surface of the first gate electrode 303a, and a second sidewall spacer 305b is formed on the side surface of the second gate electrode 303b. Thereafter, p-type impurities (or n-type impurities) are applied to the active region 300x by ion implantation using the first and second gate electrodes 303a and 303b and the first and second sidewall spacers 305a and 305b as a mask. By implanting, a p-type (or n-type) first high-concentration diffusion layer 306a is formed outside the first sidewall spacer 305a in the active region 300x, and the second side in the active region 300x. A p-type (or n-type) second high-concentration diffusion layer 306b is formed on the outer side of the wall spacer 305b.

  Next, under the same conditions as the in-situ pretreatment conditions in the first embodiment, the surfaces of the first and second high-concentration diffusion layers 306a and 306b, and the first and second gate electrodes 303a, A natural oxide film (not shown) formed on the surface of 303b is removed.

  Next, as shown in FIG. 5B, on the semiconductor substrate 300 under the same conditions as those for forming the metal layer (see FIG. 1A: 108) in the first embodiment, the single film 307a, A metal layer 309 in which the containing film 308a, the single film 307b, the containing film 308b, and the single film 307c are sequentially stacked is formed.

  Next, as shown in FIG. 5 (c), the first heat treatment is performed, for example, at 330 ° C. for 60 seconds using the RTA apparatus, and the first and second gate electrodes 303a, 303b and the first, second The Si of the high concentration diffusion layers 306a and 306b and the Ni of the metal layer 309 are reacted. Thereafter, unreacted metal remaining on the semiconductor substrate 300 using, for example, an acidic chemical solution in which sulfuric acid or hydrochloric acid and hydrogen peroxide water are mixed, or an alkaline chemical solution in which ammonium hydroxide and hydrogen peroxide water are mixed. Layer 309 is removed. Thereafter, a second heat treatment is performed at 450 ° C. for 60 seconds, for example. In this way, the first on-gate silicide film 310a made of NiSi film is formed on the first gate electrode 303a, and the silicide film 311a made of NiSi film is formed on the first high-concentration diffusion layer 306a. Form. On the other hand, a second on-gate silicide film 310b made of NiSi film is formed on the second gate electrode 303b, and a silicide film 311b made of NiSi film is formed on the second high-concentration diffusion layer 306b.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  According to the present embodiment, the heat treatment is performed in a state where the metal layer 309 in which the single film made of the Ni film and the containing film made of nitrogen and containing the Ni film are sequentially stacked is formed on the entire surface of the semiconductor substrate 300. Thus, Ni in the metal layer 309 and Si in the high-concentration diffusion layers 306a and 306b can be reacted slowly and intermittently, so that a relatively small crystal grain size (that is, the first sidewall spacer 305a and the first Silicide films 311a and 311b having a crystal grain size equal to or smaller than the interval between the two side wall spacers 305b and having relatively small variations in crystal grain size can be formed. For this reason, in the silicide films 311a and 311b, there is no unevenness at the NiSi / Si interface, and it is possible to prevent the occurrence of junction leakage current due to abnormally grown portions extending in the depth direction (see FIG. 11 (e): 707). In addition, it is possible to prevent the leakage current between the source and the drain due to the abnormally growing portion extending in the lateral direction (see FIG. 11E: 708).

  Hereinafter, in order to effectively explain the effects of the present invention, the semiconductor device of the present invention manufactured by the method of manufacturing a semiconductor device according to the second embodiment and the conventional method manufactured by the conventional method of manufacturing a semiconductor device are described. This will be described in comparison with the semiconductor device.

The inventors of the present invention compared the leakage current between the semiconductor device of the present invention and a conventional semiconductor device, and found that the following is shown. The result of the leakage current will be described with reference to FIGS. 6 (a) and 6 (b). 6A and 6B are graphs showing the cumulative distribution of leakage current. Specifically, FIG. 6 (a) is a graph showing a cumulative distribution of junction leakage current in a p-type MOS transistor. Specifically, ◯ indicates the semiconductor device of the present invention, and Δ indicates a conventional semiconductor device. Show about. On the other hand, FIG. 6B is a graph showing a cumulative distribution of source-drain leakage current in an n-type MOS transistor. Specifically, ◯ shows a semiconductor device of the present invention, and △ shows a conventional semiconductor device. Show. The horizontal axis in FIG. 6 (a) indicates the junction leakage current, and the horizontal axis in FIG. 6 (b) indicates the source-drain leakage current. E-02 means 1 × 10 ⁻² .

  First, the junction leakage current in the p-type MOS transistor was compared between the prior art and the present invention, and the following was found.

  As shown in FIG. 6 (a), in the conventional case, about half of the shots are out of the main distribution. From this, it can be seen that the junction leakage current is degraded in about half of the shots. On the other hand, in the case of the present invention, no deterioration of the junction leakage current is observed in any shot.

  Next, the source-drain leakage current in an n-type MOS transistor was compared between the prior art and the present invention, and the following was found.

  As shown in FIG. 6B, in the conventional case, about half of the shots are out of the main distribution, and it can be seen from this that the leakage current between the source and drain is deteriorated in about half of the shots. On the other hand, in the case of the present invention, no deterioration of the source-drain leakage current is observed in any shot.

  As described above, in the semiconductor device of the present invention, it is possible to effectively prevent the occurrence of junction leakage current in the p-type MOS transistor as compared with the conventional semiconductor device, and the source-drain leakage current in the n-type MOS transistor. It turns out that generation | occurrence | production can be prevented effectively.

  In the above description, the junction leakage current that occurs more frequently than the source-drain leakage current among the leakage currents generated in the p-type MOS transistor has been considered as a specific example. On the other hand, among the leak currents generated in the n-type MOS transistor, the leak current between the source and drain, which is more frequently generated than the junction leak current, was examined as a specific example.

  In addition, in order to analyze the structure of the semiconductor device of the present invention and the structure of the conventional semiconductor device, the inventors of the present invention use a TEM image to show a cross section of each semiconductor device (specifically, a p-type MOS transistor). (Cross section) was analyzed. When the cross-sectional TEM image of the p-type MOS transistor was compared between the present invention and the conventional one, the following was found. A cross-sectional TEM image of the p-type MOS transistor will be described with reference to FIGS. FIG. 7 is a cross-sectional TEM image of a p-type MOS transistor constituting the semiconductor device of the present invention. On the other hand, FIG. 8 is a cross-sectional TEM image of a p-type MOS transistor constituting a conventional semiconductor device.

  As shown in FIG. 8, in the conventional case, the silicide film 404 </ b> B formed on the high concentration diffusion layer sandwiched between the sidewall spacers 402 has a remarkable unevenness at the NiSi-Si interface. found. Further, it has been found that the silicide film 404B is formed so as to enter under the side wall spacers 402.

  In contrast, in the case of the present invention, the silicide film 404A formed on the high concentration diffusion layer sandwiched between the sidewall spacers 402 has no unevenness at the NiSi-Si interface, and the interface is very Turned out to be smooth. Further, it has been found that the silicide film 404A is not formed under the sidewall spacer 402.

  As described above, the silicide film 404A according to the present invention is not formed with the abnormal growth portion 408 in the depth direction and the abnormal growth portion 409 in the lateral direction unlike the conventional silicide film 404B. It can be seen that the occurrence of junction leakage current due to the abnormal growth portion in the vertical direction can be prevented, and the occurrence of leakage current between the source and drain due to the abnormal growth portion in the lateral direction can be prevented.

  The configuration of the semiconductor device used for the examination of the cross-sectional TEM image is as follows.

  This semiconductor device includes a semiconductor substrate 400 made of silicon, a gate insulating film formed on the semiconductor substrate 400, a gate electrode 401 formed on the gate insulating film, and a cross section formed on the side surface of the gate electrode 401. Side wall spacer 402 having an L-shape, a low concentration diffusion layer formed on the lower side of gate electrode 401 in the active region, and a high concentration diffusion formed on the outer side of sidewall spacer 402 in the active region Layer, a silicide film 403 on the gate formed on the gate electrode 401, a silicide film (FIG. 7: 404A, FIG. 8: 404B) formed on the high concentration diffusion layer, and the gate electrode 401. Liner film 405 (see FIG. 8 in particular), interlayer insulating film 406 formed on liner film 405, liner film 405 and interlayer Formed in Enmaku 406, silicide films (Figure 7: 404A, Figure 8: 404B) and a contact plug 407 for electrically connecting the high-concentration diffusion layer via the.

  In the second embodiment, a semiconductor device having two or more MOS transistors on an active region surrounded by an element isolation region is sandwiched between sidewall spacers that are expected to have the highest frequency of leakage current. Paying attention to the high-concentration diffusion layer (that is, the narrowest region among the regions where the silicide film is formed), the crystal grain size of the crystal grains constituting the silicide film should be less than the interval between the sidewall spacers However, the present invention is not limited to this example.

  Other modifications will be described with reference to FIGS. 9 (a) and 9 (b). FIGS. 9A and 9B are cross-sectional views showing the structure of a semiconductor device according to another modification of the present invention. Specifically, FIG. 9 (a) is a cross-sectional view in the gate length direction, while FIG. 9 (b) is a cross-sectional view in the gate width direction, and more specifically, IXb shown in FIG. 9 (a). It is sectional drawing in the -IXb line.

  The semiconductor device shown in FIG. 9A is formed on an active region 500x composed of a semiconductor substrate 500 surrounded by an element isolation region 501, a gate insulating film 502 formed on the active region 500x, and a gate insulating film 502. Gate electrode 503, sidewall spacer 505 formed on the side surface of gate electrode 503, low-concentration diffusion layer 504 formed on the side of gate electrode 503 in active region 500x, and side in active region 500x A high concentration diffusion layer 506 formed on the outer side of the wall spacer 505, an on-gate silicide film 510 formed on the gate electrode 503, and a silicide film 511 formed on the high concentration diffusion layer 506. I have.

  As shown in FIG. 9A, in the semiconductor device having a MOS transistor on the active region 500x surrounded by the element isolation region 501, the width in the gate width direction of the active region 500x (see FIG. 9B: W) Is very narrow, the silicide film is very likely to be formed extending in the depth direction in the high-concentration diffusion layer 506 sandwiched between the element isolation regions 501 orthogonal to the gate electrode 503, and the junction leakage current Is very likely to occur.

  Therefore, paying attention to the high-concentration diffusion layer 506 sandwiched between the element isolation regions 501 that is expected to generate the highest leakage current, the crystal grain size of the silicide film 511 is changed to the active region 500x. By making the width in the gate width direction (that is, the interval between the element isolation regions 501 orthogonal to the gate electrode 503) W or less, generation of leakage current can be prevented.

  The formation of such a silicide film 511 is performed by performing heat treatment in a state where a metal layer in which a single film and a containing film are sequentially stacked is formed on the entire surface of the semiconductor substrate 500, as in the second embodiment. It can be carried out. As a result, a silicide film 511 having a relatively small crystal grain size and relatively small variation in crystal grain size, that is, a silicide film 511 having no unevenness at the interface with Si can be formed. In order to set the crystal grain size of the crystal grains constituting the silicide film 511 to be equal to or less than the width W in the gate width direction of the active region 500x, the film thickness of the single film, the film thickness of the contained film, and the gas content of the contained film It can be realized by appropriately setting the amount.

  As described above, paying attention to the narrowest region among the regions where the silicide film is formed in the semiconductor device, that is, the region where the leakage current is expected to occur most frequently, the crystal grains constituting the silicide film By setting the particle size, the occurrence of leakage current can be prevented.

  In the second embodiment, the case where the Ni film containing nitrogen is used as the containing films 308a and 308b has been described as a specific example. However, the present invention is not limited to this, and for example, oxygen Even in the case of using the Ni film containing, the same effects as in the second embodiment can be obtained.

  In the second embodiment, the case where nickel is used as the metal contained in the metal layer 309 has been described as a specific example. However, the present invention is not limited to this, and for example, titanium, cobalt, Platinum, hafnium, or palladium may be used. In that case, a titanium silicide film, a cobalt silicide film, a platinum silicide film, a hafnium silicide film, or a palladium silicide film is formed as the silicide films 311a and 311b.

  In the second embodiment, the metal layer 309 is exemplified by a case where a metal layer in which the single film 307a, the containing film 308a, the single film 307b, the containing film 308b, and the single film 307c are sequentially stacked is used. Although described, the present invention is not limited to this.

  As described above, the present invention is useful for a semiconductor device having a silicide film on a high concentration diffusion layer and a manufacturing method thereof.

(a)-(c) is principal part process sectional drawing which shows the formation method of the silicide film | membrane concerning the 1st Embodiment of this invention in order of a process. (a)-(f) is a figure shown about the mechanism in which the silicide film | membrane of this invention is formed. (a) is a graph showing the distribution of the crystal grain size of the silicide film formed on the p-type diffusion layer, and (b) is the distribution of the crystal grain size of the silicide film formed on the n-type diffusion layer. It is a graph which shows. (a) is a diagram showing the case where the silicide film of the present invention is formed on the high concentration diffusion layer, and (b) is a diagram showing the case where the conventional silicide film is formed on the high concentration diffusion layer. It is. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (a) is a graph showing a cumulative distribution of junction leakage current in a p-type MOS transistor, and (b) is a graph showing a cumulative distribution of source-drain leakage current in an n-type MOS transistor. It is a cross-sectional TEM image of the p-type MOS transistor which comprises the semiconductor device of this invention. It is a cross-sectional TEM image of the p-type MOS transistor which comprises the conventional semiconductor device. (a) And (b) is sectional drawing shown about the structure of the semiconductor device which concerns on the other modification of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the conventional semiconductor device in order of a process. (a)-(e) is a figure which shows about the mechanism in which an unevenness | corrugation generate | occur | produces in the NiSi / Si interface in the conventional silicide film | membrane.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 101a, 101b, 101c Single-piece | unit film | membrane 102a, 102b Containing film 103 Metal layer 104 Silicide film 200 Seed 201 Crystal grain 202 Crystal grain 203 Crystal grain 204 Crystal grain 205 Crystal grain Wa Side wall spacer width Wb Space | interval between sidewall spacers Wc Interval between gate electrodes 300 Semiconductor substrate 300x Active region 301 Element isolation region 302a First gate insulating film 302b Second gate insulating film 303a First gate electrode 303b Second gate electrode 304a First low-concentration diffusion layer 304b Second low concentration diffusion layer 305a First side wall spacer 305b Second side wall spacer 306a First high concentration diffusion layer 306b Second high concentration diffusion layer 307a, 307b, 307c Single film 308a, 308 Containing film 309 Metal layer 310a First silicide film on gate 310b Second silicide film on gate 311a First silicide film 311b Second silicide film 400 Semiconductor substrate 401 Gate electrode 402 Side wall spacer 403 Silicide film on gate 404A Silicide Film 404B Silicide film 405 Liner film 406 Interlayer insulating film 407 Contact plug 500 Semiconductor substrate 500x Active region 501 Element isolation region 502 Gate insulating film 503 Gate electrode 504 Low concentration diffusion layer 505 Side wall spacer 506 High concentration diffusion layer 510 On-gate silicide film 511 Silicide film W Active region width in the gate width direction

Claims (15)

In a method for manufacturing a semiconductor device, comprising: a first transistor having a first gate electrode; and a second transistor having a second gate electrode on an active region surrounded by an element isolation region in a semiconductor substrate.
Forming the first gate electrode on the active region via a first gate insulating film and forming the second gate electrode on the active region via a second gate insulating film; a) and
Forming a first sidewall spacer on the side surface of the first gate electrode and forming a second sidewall spacer on the side surface of the second gate electrode;
A first high-concentration diffusion layer is formed outside the first sidewall spacer in the active region, and a second high-concentration diffusion layer is formed outside the second sidewall spacer in the active region. Forming a layer (c);
A step (d) of removing a natural oxide film formed on the surfaces of the first high concentration diffusion layer and the second high concentration diffusion layer;
A step (e) of forming a metal layer in which a single film made of metal and a film containing gas and containing the metal are sequentially laminated on the semiconductor substrate;
The metal contained in the metal layer and the silicon contained in the first high-concentration diffusion layer are reacted to form a first silicide film on the first high-concentration diffusion layer, and the metal (F) forming a second silicide film on the second high concentration diffusion layer by reacting the metal contained in the layer with silicon contained in the second high concentration diffusion layer. Prepared,
In the step (f), the first silicide film and the second silicide film have a crystal grain size equal to or less than an interval between the first sidewall spacer and the second sidewall spacer. A method for manufacturing a semiconductor device, characterized in that: In a method for manufacturing a semiconductor device including a transistor having a gate electrode on an active region surrounded by an element isolation region in a semiconductor substrate,
Forming the gate electrode on the active region through a gate insulating film;
Forming a sidewall spacer on a side surface of the gate electrode;
Forming a high-concentration diffusion layer below the sidewall spacer in the active region (c);
A step (d) of removing a natural oxide film formed on the surface of the high concentration diffusion layer;
A step (e) of forming a metal layer in which a single film made of metal and a film containing gas and containing the metal are sequentially laminated on the semiconductor substrate;
A step (f) of reacting the metal contained in the metal layer with silicon contained in the high concentration diffusion layer to form a silicide film on the high concentration diffusion layer;
In the step (f), the silicide film is formed so that the crystal grain size of the silicide film is equal to or less than the width of the active region in the gate width direction. In the manufacturing method of the semiconductor device according to claim 1 or 2,
In the step (e), a step (e1) of forming the single film on the semiconductor substrate by a first sputtering method using argon gas plasma, and argon gas plasma and gas plasma are used. And a step (e2) of forming the containing film on the single film by a second sputtering method. In the manufacturing method of the semiconductor device according to claim 3,
The method for manufacturing a semiconductor device, wherein the gas is nitrogen gas or oxygen gas. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the metal is made of titanium, cobalt, nickel, platinum, hafnium, or palladium. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the step (d) is performed by a chemical dry etching method. In the manufacturing method of the semiconductor device according to claim 6,
The method of manufacturing a semiconductor device, wherein the step (d) is performed by chemical dry etching using NF ₃ gas plasma and H ₂ gas plasma. In a semiconductor device including an active region surrounded by an element isolation region in a semiconductor substrate, a first transistor having a first gate electrode, and a second transistor having a second gate electrode.
The first transistor includes:
A first gate insulating film formed on the active region;
The first gate electrode formed on the first gate insulating film;
A first sidewall spacer formed on a side surface of the first gate electrode;
A first high-concentration diffusion layer formed outside the first sidewall spacer in the active region;
A first silicide film formed on the first high-concentration diffusion layer,
The second transistor is
A second gate insulating film formed on the active region;
The second gate electrode formed on the second gate insulating film;
A second sidewall spacer formed on a side surface of the second gate electrode;
A second high-concentration diffusion layer formed outside the second sidewall spacer in the active region;
A second silicide film formed on the second high-concentration diffusion layer,
A crystal grain size of crystal grains constituting the first silicide film and the second silicide film is equal to or less than an interval between the first sidewall spacer and the second sidewall spacer. Semiconductor device. The semiconductor device according to claim 8,
The conductivity type of the first transistor and the second transistor is p-type,
A semiconductor device, wherein crystal grains of crystal grains constituting the first silicide film and the second silicide film are 10 nm or more and 130 nm or less. The semiconductor device according to claim 8,
The conductivity type of the first transistor and the second transistor is n-type,
A semiconductor device, wherein a crystal grain size of crystal grains constituting the first silicide film and the second silicide film is 10 nm or more and 70 nm or less. The semiconductor device according to claim 8,
The semiconductor device according to claim 1, wherein the first silicide film and the second silicide film are made of a titanium silicide film, a cobalt silicide film, a nickel silicide film, a platinum silicide film, a hafnium silicide film, or a palladium silicide film. In a semiconductor device including a transistor having a gate electrode on an active region surrounded by an element isolation region in a semiconductor substrate,
The transistor is
A gate insulating film formed on the active region;
The gate electrode formed on the gate insulating film;
A sidewall spacer formed on a side surface of the gate electrode;
A high-concentration diffusion layer formed outside the sidewall spacer in the active region;
A silicide film formed on the high concentration diffusion layer,
2. A semiconductor device according to claim 1, wherein a crystal grain size of a crystal grain constituting the silicide film is not more than a width in a gate width direction of the active region. The semiconductor device according to claim 12,
The conductivity type of the transistor is p-type,
A semiconductor device characterized in that a crystal grain size of a crystal grain constituting the silicide film is 10 nm or more and 130 nm or less. The semiconductor device according to claim 12,
The conductivity type of the transistor is n-type,
A semiconductor device characterized in that a crystal grain size of a crystal grain constituting the silicide film is 10 nm or more and 70 nm or less. The semiconductor device according to claim 12,
The semiconductor device is characterized in that the silicide film is made of a titanium silicide film, a cobalt silicide film, a nickel silicide film, a platinum silicide film, a hafnium silicide film, or a palladium silicide film.