JP2009111001A - Method for manufacturing thin-film transistor, thin-film transistor, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin-film transistor that can be manufactured inexpensively through a simple process and that has high performance; a thin-film transistor; and a display device. <P>SOLUTION: A method for manufacturing a thin-film transistor, a thin-film transistor and a display device are provided, the method including stacking together a first base formed with an opening and formed with a source electrode and a drain electrode via the opening and a second base formed with a gate electrode and a gate insulating film, so that it can manufacture an inexpensive, high-performance thin-film transistor through a simple process without damaging an organic semiconductor layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film transistor, a thin film transistor, and a display device, and more particularly, a thin film transistor in which a first substrate on which a source electrode and a drain electrode are formed and a second substrate on which a gate electrode and a gate insulating film are formed are stacked. The present invention relates to a method, a thin film transistor, and a display device.

  In recent years, TFTs using organic semiconductors (hereinafter referred to as organic TFTs) have been studied as an alternative to thin film transistors (hereinafter referred to as TFTs) using amorphous silicon (a-Si). The organic TFT has a feature that it can be manufactured at a low cost because it can be manufactured using a printing process instead of a conventional semiconductor manufacturing process. Moreover, since the manufacturing process temperature is as low as 200 ° C. or lower, a film substrate can be used, and application to a flexible display is expected.

Although the performance of organic TFTs has improved year by year, it is still not sufficient for use in flat panel displays (hereinafter referred to as FPD) such as liquid crystal displays. In particular, the mobility is one of the indicators of performance has become the order of 0.001~0.1cm ² / V · s, and 1 order of magnitude lower value as compared with 1cm ² / V · s of the a-Si .

  As a method for improving the mobility, in addition to the improvement of the organic semiconductor material, improvement of the manufacturing process of the organic TFT has been attempted. For example, since the current flow of an organic semiconductor is determined according to the crystal state, it is important to crystallize it satisfactorily.

  Therefore, in Patent Document 1, in the bottom contact type TFT, attention is paid to the fact that the step of the source and drain electrodes hinders the crystallization of the organic semiconductor. A method for improving the performance of a TFT is described.

Patent Document 2 describes a method for forming source and drain electrodes using a plating method in which a plating seed layer is formed using an electrophotographic method, and a metal plating layer is formed using the plating seed layer as a nucleus. Yes.
JP 2006-41219 A JP 2006-5041 A

  However, in the method described in Patent Document 1, since many vacuum deposition processes are used during the manufacturing process, the process is complicated, the manufacturing takes time, and the manufacturing apparatus is expensive, so that the manufacturing is performed at a low cost. The advantage of organic TFT that it can be lost. For example, in Example 1 of Patent Document 1, a vacuum deposition method such as sputtering is used in at least four steps. Furthermore, a chemical mechanical polishing (CMP) method is used to planarize the gate insulating portion and the source and drain electrodes, which is also a factor in increasing the cost.

  In the method described in Patent Document 2, in the case of a bottom gate type TFT, the source and drain electrodes are formed on the organic semiconductor layer by plating, so that the organic semiconductor layer is damaged by the plating solution. Causes deterioration. The top gate type TFT can prevent deterioration of the organic semiconductor layer due to the plating solution, but it can be applied by dissolving the organic semiconductor layer, particularly in a solvent, in the process of forming a gate insulating film on the organic semiconductor layer. Since remarkable characteristic deterioration occurs in the case of an organic semiconductor, a top gate type cannot be adopted for an organic TFT.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a thin film transistor, a thin film transistor, and a display device that can be manufactured at low cost with a simple process.

  The object of the present invention can be achieved by the following constitution.

1. An opening forming step of forming an opening in the first substrate;
A source / drain electrode forming step of forming a source electrode and a drain electrode by conducting both surfaces of the first substrate through the opening;
Forming a gate electrode on the second substrate; and
Forming a gate insulating film including the gate electrode on the second substrate; and
A laminating step of laminating the first substrate on the gate insulating film of the second substrate;
A method of manufacturing a thin film transistor, comprising: a semiconductor layer forming step of forming a semiconductor layer between the source electrode and the drain electrode.

2. An opening forming step of forming an opening in the first substrate;
A source / drain electrode forming step of forming a source electrode and a drain electrode by conducting both surfaces of the first substrate through the opening;
Forming a gate electrode on the second substrate; and
Forming a gate insulating film including the gate electrode on the second substrate; and
A semiconductor layer forming step of forming a semiconductor layer on the gate insulating film;
And a laminating step of laminating the first substrate on the gate insulating film of the second substrate.

  3. 3. The method of manufacturing a thin film transistor according to 1 or 2, wherein the source / drain electrode forming step is a step using a plating method.

  4). 4. The method of manufacturing a thin film transistor according to 3, wherein the plating is performed by autocatalytic plating and displacement plating.

  5). 5. The method of manufacturing a thin film transistor according to 4, wherein the displacement plating deposits gold (Au).

  6. A thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of items 6.1 to 5.

  A display device comprising a plurality of thin film transistors according to 7.6 arranged in a two-dimensional matrix.

  According to the present invention, an opening is formed, and a first substrate on which a source electrode and a drain electrode are formed via the opening and a second substrate on which a gate electrode and a gate insulating film are formed are stacked. Thus, it is possible to provide a thin film transistor manufacturing method, a thin film transistor, and a display device that can manufacture a high performance thin film transistor at a low cost with a simple process without damaging the organic semiconductor layer.

  Hereinafter, the present invention will be described based on the illustrated embodiment, but the present invention is not limited to the embodiment. In the drawings, the same or equivalent parts are denoted by the same reference numerals, and redundant description is omitted.

  First, a display device using a TFT according to the present invention will be described with reference to FIG. 1. FIG. 1 is a schematic diagram showing an example of a configuration of a display device using a TFT according to the present invention.

  In FIG. 1, the display device 1 includes a TFT sheet 10, a horizontal driving circuit 20, a vertical driving circuit 30, and the like. In the TFT sheet 10, a plurality of pixels each including a TFT 11, a storage capacitor 13, and an output element 15 are arranged in a two-dimensional matrix.

  A gate bus line 21 output from the horizontal drive circuit 20 for each horizontal line of the TFT sheet 10 is connected to the gate of each TFT 11. A source bus line 31 output from the vertical drive circuit 30 for each vertical column of the TFT sheet 10 is connected to the source of each TFT 11.

  An output element 15 is connected to the drain of each TFT 11 for each pixel. The output element 15 is, for example, a liquid crystal or an electrophoretic element. In the example of FIG. 1, a liquid crystal is shown as an output element 15 in an equivalent circuit composed of a resistor and a capacitor.

  Next, an example of the structure of a TFT manufactured by the TFT manufacturing method of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view showing an example of the structure of a TFT manufactured by the manufacturing method of the present invention.

  In FIG. 2, the TFT 11 includes a first substrate BP1, a second substrate BP2, a gate electrode GE, a gate insulating film GIL, an organic semiconductor layer OS, a source electrode SE, a drain electrode DE, a protective layer PT, and the like.

  The gate electrode GE is provided on the second substrate BP2, and the gate insulating film GIL is provided on the second substrate BP2 so as to include the gate electrode GE.

  The source electrode SE and the drain electrode DE are provided across the both surfaces of the first substrate BP1 via the inner wall of the opening HL at positions facing each other across the opening HL provided in the first substrate BP1.

  The second substrate BP2 on which the gate electrode GE and the gate insulating film GIL are formed and the first substrate BP1 on which the opening HL, the source electrode SE, and the drain electrode DE are formed are stacked and pressure-bonded.

  The organic semiconductor layer OS is provided at the bottom of the opening HL on the gate insulating film GIL, and is protected from the outside air by a protective layer PT provided so as to close the opening HL.

  In this example, the source electrode SE and the drain electrode DE are provided across both surfaces of the first substrate BP1 via the inner wall of the opening HL. However, the present invention is not limited to this. For example, only the inner wall portion of the opening HL or only the side of the first substrate BP1 facing the second substrate BP2 may be used as long as the contact can be satisfactorily taken.

(First embodiment)
Next, a first embodiment of a TFT manufacturing method according to the present invention will be described with reference to FIGS. FIG. 3 is a main process diagram showing a first embodiment of a TFT manufacturing method according to the present invention.

  In FIG. 3, the opening HL is opened in the first substrate BP1 in the opening forming step S100. Details will be described with reference to FIG. In the source / drain electrode formation step S200, the source electrode SE and the drain electrode are formed across the both surfaces of the first substrate BP1 through the opening HL at positions facing each other across the opening HL of the first substrate BP1 by plating. DE is formed. Details will be described with reference to FIGS.

  In the gate electrode formation step S300, the gate electrode GE is formed on the second substrate BP2. Details will be described with reference to FIGS. In the gate insulating film forming step S400, the gate insulating film GIL is formed on the second substrate BP2 so as to include the gate electrode GE. Details will be described with reference to FIG.

  In the stacking step S500, the second substrate BP2 on which the gate electrode GE and the gate insulating film GIL are formed and the first substrate BP1 on which the opening HL, the source electrode SE, and the drain electrode DE are formed are stacked and pressure-bonded. Is done. Details will be described with reference to FIGS. In the semiconductor layer forming step S600, the organic semiconductor layer OS is formed at the bottom of the opening HL. Details will be described with reference to FIG. In the protective layer forming step S700, the protective layer PT is formed so as to close the opening HL, and the organic semiconductor layer OS is protected from the outside air. Details will be described with reference to FIG.

  Next, the detail of each process mentioned above is demonstrated. In the following description, the TFT1 element will be described except for FIG. 12, but the same applies when a plurality of TFTs are formed.

  4A and 4B are schematic diagrams for explaining a sub-process of the opening forming step S100. FIG. 4A is a sub-process diagram of the opening forming step S100, and FIG. 4B is a first view in which the opening HL is formed. FIG. 4C is a cross-sectional view of the substrate BP1, and FIG. 4C is a top view of the first substrate BP1 in which the opening HL is formed.

  4A, in the opening step S101, an opening HL penetrating the first substrate BP1 is opened using, for example, laser light or the like, as shown in FIGS. 4B and 4C. In the cleaning / drying step S103, the first substrate BP1 after opening is cleaned and dried, and the process returns to the opening forming step S100 in FIG.

  As the first substrate BP1, a glass plate or various plastic plates or films can be used, and is not particularly limited. The same applies to a second substrate BP2 described later.

  The glass plate is advantageous for positional accuracy of the opening HL and alignment when laminated with another substrate in that the dimensional change due to a disturbance such as heat is smaller than that of a plastic plate or film. As a material of the glass plate, soda lime glass, white plate glass, quartz glass, or the like can be used.

  On the other hand, plastic plates and films are advantageous in that they can be easily processed. Further, if a plastic film is used, a so-called flexible display can be realized.

  As a method of forming the opening HL, a method of mechanically forming using a drill, an optical processing method using a third harmonic of a carbon dioxide laser or a YAG laser, an etching method using dry etching or wet etching, or the like may be used. There is no particular limitation. In particular, the opening of a plastic plate or film can be easily formed by these methods.

  5 to 7 are schematic diagrams for explaining a sub-process of the source / drain electrode formation step S200. FIG. 5 is a sub-process diagram of the source / drain electrode formation step S200. FIGS. It is sectional drawing or a top view which shows the formation state of the source / drain electrode in each sub process.

  In FIG. 5, the resist coating step S201 to the development step S205 are so-called photolithography patterning steps. In the resist coating step S201, as shown in FIG. 6A, a positive resist RG is applied by spin coating or the like on both surfaces of the first substrate BP1 in which the openings HL are formed.

  In the exposure step S203 of FIG. 5, as shown in FIG. 6B, exposure is performed with light L such as ultraviolet rays through a photomask PM that is opened only at portions where source and drain electrodes are formed. Development is performed in the development step S205 of FIG. 5, and the resist RG in the portion where the source and drain electrodes exposed in the exposure step S203 are formed is removed, and as shown in FIGS. 6C and 6D, Only the resist RG that has not been exposed remains.

  In the AgPd film forming step S207 of FIG. 5, the first substrate BP1 on which the resist RG is formed is immersed in a solution in which AgPd fine particles are dispersed, and the first substrate BP1 is exposed as shown in FIG. 7A. An AgPd thin film is formed on the inner wall of the opening and the opening HL.

  In the catalyst film forming step S209 of FIG. 5, the first substrate BP1 on which the AgPd thin film is formed is immersed in, for example, a solution in which the catalyst CT is dispersed, and the AgPd thin film is formed as shown in FIG. 7B. The catalyst CT is attached to the part. The catalyst CT is a metal such as Pd, Pt, or Au, and the solution containing the catalyst CT is a metal in which metal nanoparticles such as Pd nanoparticles, Pt nanoparticles, or Au nanoparticles are dispersed in a solvent. Nano ink can be used.

  In the opening enlargement step S211 of FIG. 5, as shown in FIGS. 7C and 7D, the portion where the catalyst CT is adhered is formed, for example, by using laser light, and the portion where the source electrode is formed and the drain electrode are formed. The opening HL is enlarged so as to be separated from the portion to be formed.

  In the metal film forming step S213 in FIG. 5, as shown in FIG. 7E, a metal ME such as Ni is deposited on the surface of the catalyst CT by electroless plating. If a reducing agent is selected such that the metal ME to be deposited is catalytically active with respect to the oxidation reaction, the deposited metal ME can grow in an autocatalytic manner and have an arbitrary film thickness. Since the growth rate of the metal ME can be managed by the concentration or temperature of the plating solution, the metal ME can be grown to an accurate thickness by controlling the plating process time. For example, when Ni is precipitated, for example, sodium phosphinate, dimethylamine borane, hydrazine, potassium tetrahydroborate and the like can be used as the reducing agent.

  In the Au film deposition step S215 of FIG. 5, as shown in FIG. 7F, the upper surface of the metal ME is subjected to substitution plating to deposit the Au film Au. Au is chemically very stable and can be in good contact with the organic semiconductor layer OS described later. Instead of Au, platinum group metals such as Pd, Pt, Ru, and Rh can also be used because they have good contact with the organic semiconductor layer OS described later.

  In the resist removal step S217 of FIG. 5, the resist RG is removed, and the source electrode SE and the drain electrode DE having the Au film Au on the surface are formed on the first substrate BP1, and the source / drain electrode formation step of FIG. Return to S200. FIG. 7G shows a cross-sectional view of the first substrate BP1 on which the source electrode SE and the drain electrode DE are formed, and FIG. 7H shows a top view. Wiring for connecting the source electrode SE and the drain electrode DE to the external circuit may be formed simultaneously in the source / drain electrode forming step S200.

  Although an example using a positive resist is shown here, a negative resist may be used. In this case, in the exposure step S203 of FIG. 5, the photomask PM in which only the portion where the source and drain electrodes are formed is shielded from light is used.

  8 and 9 are schematic diagrams for explaining a sub-process of the gate electrode forming step S300, FIG. 8 is a sub-process diagram of the gate electrode forming step S300, and FIG. 9 is a gate electrode in each sub-process of FIG. It is sectional drawing which shows the formation state of.

  In FIG. 8, in the gate electrode film forming step S301, as shown in FIG. 9A, an electrode film GL that becomes the gate electrode GE at the end of the step is formed on the second substrate BP2. As the material of the electrode film GL, metals such as Cr, Al, Ag, Au, Ti, and Cu, alloys of these metals with other metals, nanoparticles of various metals, ITO (indium tin oxide), IZO ( A metal oxide film such as indium zinc oxide) or an organic conductive film such as PEDOT (polyethylenedioxythiophene) / PSS (polystyrene sulfonic acid) can be used, but is not particularly limited.

  The electrode film GL can be formed by a PVD (physical vapor deposition method) method such as sputtering or vacuum deposition, a spin coating method, a plating method, or the like, but is not particularly limited. Using an ink in which nanoparticles are dispersed or a dispersion in which a conductive polymer is dispersed, an ink-jet coating method (hereinafter referred to as IJ method) or various printing methods can be used to form a film and patterning described below. Can be performed simultaneously, and the process can be simplified.

  The resist coating process S303 to the resist stripping process S311 in FIG. 8 are so-called photolithography patterning processes. In the resist coating step S303 of FIG. 8, as shown in FIG. 9B, a positive resist RG2 is applied on the electrode film GL by spin coating or the like.

  In the exposure step S305 of FIG. 8, as shown in FIG. 9C, exposure is performed with light L such as ultraviolet rays through a photomask PM in which only the portion where the gate electrode GE is formed is shielded. Development is performed in the development step S307 of FIG. 8, the resist RG2 in the portion exposed in the exposure step S305 is removed, and only the unexposed resist RG2 is left as shown in FIG. 9D.

  In the etching step S309 of FIG. 8, the electrode film GL is etched using the resist RG2 left in the developing step S307 using a wet etching method, a dry etching method, etc., as shown in FIG. Only the electrode film GL masked with the resist RG2 is left. In the resist stripping step S311 of FIG. 8, the remaining resist RG2 is stripped to form the gate electrode GE on the second substrate BP2, and the process returns to the gate electrode forming step S300 of FIG. A wiring for connecting the gate electrode GE and the external circuit may be formed simultaneously in the gate electrode formation step S300.

  Although an example using a positive resist is shown here, a negative resist may be used. In this case, in the exposure step S305, the photomask PM having an opening only in a portion where the gate electrode GE is formed is used.

  FIG. 10 is a schematic diagram for explaining a sub-process of the gate insulating film forming step S400. FIG. 4A is a sub-process diagram of the gate insulating film forming process S400, and FIG. It is sectional drawing of 2nd board | substrate BP2 formed.

10A and 10B, in the gate insulating film forming step S401, for example, SiO ₂ or SiN is formed using a sputtering method or a CVD method to form the gate insulating film GIL, and the gate shown in FIG. It returns to electrode formation process S400.

As another example of the gate insulating film forming step S401, a silane compound, an organic insulating film material, or the like can be formed by a spin coat method or various printing methods. This method has an advantage that the process is simple as compared with the case where SiO ₂ or SiN is formed by sputtering or CVD.

  FIG. 11 is a schematic diagram for explaining the sub-process of the stacking step S500. FIG. 11 (a) is a sub-process diagram of the stacking step S500, and FIGS. 11 (b) and 11 (c) are diagrams of FIG. 11 (a). It is sectional drawing which shows the lamination | stacking state in a sub process. FIG. 12 is a schematic view showing an example of a pressure bonding method used in the stacking step S500.

  In FIG. 11A, in the alignment step S501, as shown in FIG. 11B, the first substrate BP1 and the second substrate BP2 are each provided with an alignment marker AM. In a state where the first substrate BP1 and the second substrate BP2 are brought close to each other, the alignment marker AM of each substrate is simultaneously monitored with an alignment video camera or the like, and the substrate holding unit (not shown) is moved to perform alignment. Is called.

  In a state where alignment is performed in the crimping step S503 of FIG. 11A, as shown in FIG. 11C, the first substrate BP1 in which the opening HL, the source electrode SE, and the drain electrode DE are formed; The gate electrode GE and the second substrate BP2 on which the gate insulating film GIL is formed are stacked and pressure bonded.

  An example of a method of pressing the substrate will be described with reference to FIG. In FIG. 12A, the surface of the first substrate BP1 in which the opening HL, the source electrode SE, and the drain electrode DE are formed, and the second substrate BP2 in which the gate electrode GE and the gate insulating film GIL are formed have a surface. The two pressure rollers PR1 and PR2 covered with silicon rubber or the like are sandwiched and pressed. By providing a heater in both or one of the pressure rollers PR1 and PR2, and performing heating and pressure at the same time, it is possible to perform pressure bonding with better adhesion.

  In FIG. 12B, the second substrate BP2 on which the gate electrode GE and the gate insulating film GIL are formed is placed on the crimping plate PP1, and the aligned opening HL, source electrode SE, and drain electrode DE are formed thereon. The first substrate BP1 on which is formed is laminated, pressed by the pressure roller PR1, and pressed.

  In FIG. 12C, the first substrate BP1 in which the opening HL, the source electrode SE, and the drain electrode DE are formed and the second substrate BP2 in which the gate electrode GE and the gate insulating film GIL are formed are aligned. In this state, it is sandwiched between two pressure-bonding flat plates PP1 and PP2 and pressurized and pressure-bonded. The example shown here is an example and can be crimped using various other methods.

  FIG. 13 is a schematic diagram for explaining a sub-process of the semiconductor layer forming step S600. FIG. 13A is a sub-process diagram of the semiconductor layer forming step S600, and FIGS. 13B and 13C are FIGS. It is sectional drawing which shows the formation state of the organic-semiconductor layer in each sub process of a).

  In FIG. 13A, in the organic semiconductor film coating step S601, using various printing methods such as IJ method, screen printing, μ contact printing, etc., as shown in FIG. A solution OSL containing a semiconductor OS is applied. In the solvent drying step S603 of FIG. 13A, the solvent of the solution OSL is dried to form the organic semiconductor layer OS as shown in FIG. 13C, and the process returns to the semiconductor layer forming step S600 of FIG. . The organic semiconductor layer OS is a channel portion of the TFT 11.

  As the organic semiconductor OS, for example, as a coating type organic semiconductor material, thiophene compounds such as P3HT (poly-3-hexylthiophene) and F8T2 (polyfluorene-thiophene copolymer), phthalocyanines, silylethynylpentacenes, and others A precursor solution can be used, but is not particularly limited thereto.

  14A and 14B are schematic diagrams for explaining a sub-process of the protective layer forming step S700. FIG. 14A is a sub-process diagram of the protective layer forming step S700, and FIGS. 14B and 14C are FIGS. It is sectional drawing which shows the formation state of the protective layer in each sub process of a).

  14A, in the protective layer solution coating step S701, using various printing methods such as IJ method, screen printing, μ contact printing, etc., as shown in FIG. A protective layer solution PTL for forming a protective layer PT for protecting the organic semiconductor layer OS from the outside air is applied on the semiconductor layer OS.

  In the solvent drying step S703 of FIG. 14A, the solvent of the protective layer solution PTL is dried to form the protective layer PT on the organic semiconductor layer OS as shown in FIG. The process returns to the layer forming step S700.

  The protective layer PT is not essential depending on the type of the organic semiconductor layer OS. Further, the protective layer PT may be formed by forming a protective film such as SiO2 by sputtering, for example, other than the method of dropping the protective layer solution PTL described above.

  According to the first embodiment of the TFT manufacturing method of the present invention described above, the first substrate in which the opening is formed and the source electrode and the drain electrode are formed through the opening, the gate electrode, and the gate insulation By laminating and pressure-bonding with a second substrate on which a film is formed and forming an organic semiconductor layer in the opening, the organic semiconductor layer is not damaged, and a high-performance thin film transistor with a simple process and low cost A thin film transistor manufacturing method, a thin film transistor, and a display device can be provided.

(Second Embodiment)
Next, a second embodiment of the TFT manufacturing method according to the present invention will be described with reference to FIGS. FIG. 15 is a main process diagram showing a second embodiment of a TFT manufacturing method according to the present invention. The second embodiment is different from the first embodiment in a semiconductor layer forming step S800 and a stacking step S900.

  In FIG. 15, the process from the opening forming step S100 to the gate insulating film forming step S400 is the same as that of the first embodiment shown in FIG. Subsequent to the gate insulating film forming step S400, in the semiconductor layer forming step S800, the organic semiconductor layer OS is formed on the gate insulating film GIL. Details will be described with reference to FIG.

  In the stacking step S900, the second substrate BP2 on which the gate electrode GE, the gate insulating film GIL, and the semiconductor layer OS are formed, and the first substrate BP1 on which the opening HL, the source electrode SE, and the drain electrode DE are formed, Laminated and crimped. Details will be described with reference to FIG. The protective layer forming step S700 is the same as that of the first embodiment described in FIG.

  Next, details of the semiconductor layer forming step S800 and the stacking step S900 described above will be described. In the following description, the TFT 1 element will be described, but the same applies when a plurality of TFTs are formed.

  FIG. 16 is a schematic diagram for explaining a sub-process of the semiconductor layer forming step S800 in the second embodiment. FIG. 16A is a sub-process diagram of the semiconductor layer forming step S800, and FIG. And (c) is a cross-sectional view showing the formation state of the organic semiconductor layer in each sub-process of FIG.

  In FIG. 16A, in the organic semiconductor film coating step S801, by using various printing methods such as IJ method, screen printing, μ contact printing, etc., as shown in FIG. 16B, the second substrate BP2 A solution OSL containing an organic semiconductor OS is applied on the gate insulating film GIL formed above at a position to be a channel portion of the TFT 11. In the solvent drying step S803 of FIG. 16A, the solvent of the solution OSL is dried to form the organic semiconductor layer OS as shown in FIG. 16C, and the process returns to the semiconductor layer forming step S800 of FIG. .

  As the organic semiconductor OS, as in the first embodiment, for example, as a coating type organic semiconductor material, a thiophene compound such as P3HT (poly-3-hexylthiophene) or F8T2 (polyfluorene-thiophene copolymer), or , Phthalocyanines, silylethynylpentacenes, and other precursor solutions may be used, but are not particularly limited thereto.

  FIG. 17 is a schematic diagram for explaining a sub-process of the stacking step S900 in the second embodiment. FIG. 17 (a) is a sub-process diagram of the stacking step S900, and FIGS. 17 (b) and (c). These are sectional drawings which show the lamination | stacking state in each sub process of Fig.17 (a).

  In FIG. 17A, in the alignment step S901, as shown in FIG. 17B, alignment markers AM are provided on the first substrate BP1 and the second substrate BP2, respectively. In a state where the first substrate BP1 and the second substrate BP2 are brought close to each other, the alignment marker AM of each substrate is simultaneously monitored with an alignment video camera or the like, and the substrate holding unit (not shown) is moved to perform alignment. Is called.

  In a state where alignment is performed in the pressure bonding step S903 of FIG. 17A, as shown in FIG. 17C, the first substrate BP1 in which the opening HL, the source electrode SE, and the drain electrode DE are formed; The gate electrode GE, the gate insulating film GIL, and the second substrate BP2 on which the organic semiconductor layer OS is formed are stacked and pressure bonded. The substrate pressing method may be the same as that of the first embodiment shown in FIG.

  According to the second embodiment of the TFT manufacturing method of the present invention described above, the first substrate in which the opening is formed and the source electrode and the drain electrode are formed through the opening, the gate electrode, and the gate insulation A thin film transistor manufacturing method capable of manufacturing a high performance thin film transistor at a low cost in a simple process without damaging the organic semiconductor layer by laminating and pressing the film and the second substrate on which the organic semiconductor layer is formed. A thin film transistor and a display device can be provided.

  Hereinafter, although the TFT based on this invention is concretely demonstrated by the Example based on each embodiment of this invention, this invention is not limited to this.

(Example 1)
Example 1 is according to the first embodiment described above. As the first substrate BP1, an epoxy resin film substrate having a thickness of 60 μm was used. The opening HL in the first substrate BP1 was formed using a wavelength of 355 nm, which is the third harmonic of the YAG laser. After forming the opening HL, it was washed with a neutral detergent and dried (see FIG. 4).

  Subsequently, after masking the portions other than the portions where the source and drain electrodes are formed with a resist RG using photolithography (see FIG. 6), the first substrate BP1 is immersed in a solution in which AgPd fine particles are dispersed, An AgPd thin film was formed on the exposed portion of the substrate BP1 and the inner surface of the opening HL (see FIG. 7A). Further, the first substrate BP1 on which the AgPd thin film was formed was immersed in a solution in which Pd as the catalyst CT was dispersed, and Pd was adhered only to the portion where the AgPd layer was exposed (see FIG. 7B). ).

  Next, two portions of the opening HL were spread using a laser to separate the source electrode and the drain electrode (see FIGS. 7C and 7D). Next, electroless plating was performed by immersing the first substrate BP1 in a Ni plating solution to form a Ni layer on a Pd thin film as a catalyst (see FIG. 7E). Further, the surface of the Ni plating layer was replaced with Au using an Au plating solution (see FIG. 7F), and the resist RG was removed to form source and drain electrodes whose surfaces were covered with Au (FIG. 7). (See (g) and (h)).

  On the other hand, a glass substrate was used as the second substrate BP2. A Cr film having a thickness of 120 nm is formed as a gate electrode film GL by sputtering on the surface of the second substrate BP2 (see FIG. 9A), and patterning is performed by photolithography (FIGS. 9B to 9E). The gate electrode GE was formed (see FIG. 9F). Subsequently, a thermoplastic urethane material was applied to a thickness of 1 μm on the second substrate BP2 on which the gate electrode GE was formed, thereby forming a gate insulating film GIL.

  Next, the first substrate BP1 and the second substrate BP2 were stacked. With the second substrate BP2 adsorbed and fixed on the pressure-bonded flat plate PP1 heated to 60 ° C., the first substrate BP1 is held by a holding jig, and one end of the second substrate BP2 is stacked on the second substrate BP2, Using the CCD camera device, alignment markers AM on the first substrate BP1 and the second substrate BP2 were confirmed, and alignment was performed. Subsequently, the first substrate BP1 and the second substrate BP2 were pressure-bonded by pressing with a pressure roller PR1 heated to 80 ° C. in advance (see FIG. 12B).

  Subsequently, using the IJ method, a solution OSL containing TIPS-Pentacene as the organic semiconductor OS is dropped into the opening HL of the first substrate BP1 (see FIG. 13B), and dried to dry the organic semiconductor layer OS. (See FIG. 13C). By dropping in the opening HL, application with high positional accuracy became possible.

Finally, the protective layer PT was formed. In this example, unlike the method illustrated in FIG. 14, a SiO ₂ film was used as the protective layer. First, in order to protect the organic semiconductor layer OS from damage during film formation of SiO ₂ , PVA (polyvinyl alcohol) was dropped into the opening HL of the first substrate BP1 using the IJ method. By dropping in the opening HL, application with high positional accuracy became possible. Subsequently, a SiO ₂ film having a thickness of 50 nm was formed by sputtering to form a protective layer PT.

  When the transistor characteristics of the organic TFT fabricated through the above steps were measured, it showed excellent performance. This is presumably because Au having high contact performance with the organic semiconductor was used as the source and drain electrodes.

(Example 2)
Example 2 is according to the second embodiment described above. As the first substrate BP1, an epoxy resin film substrate having a thickness of 60 μm was used. The opening HL in the first substrate BP1 was formed using a wavelength of 355 nm, which is the third harmonic of the YAG laser. After forming the opening HL, it was washed with a neutral detergent and dried (see FIG. 4).

  Subsequently, after masking the portions other than the portions where the source and drain electrodes are formed with a resist RG using photolithography (see FIG. 6), the first substrate BP1 is immersed in a solution in which AgPd fine particles are dispersed, An AgPd thin film was formed on the exposed portion of the substrate BP1 and the inner surface of the opening HL (see FIG. 7A). Further, the first substrate BP1 on which the AgPd thin film was formed was immersed in a solution in which Pd as the catalyst CT was dispersed, and Pd was adhered only to the portion where the AgPd layer was exposed (see FIG. 7B). ).

  Next, two portions of the opening HL were spread using a laser to separate the source electrode and the drain electrode (see FIGS. 7C and 7D). Next, electroless plating was performed by immersing the first substrate BP1 in a Ni plating solution to form a Ni layer on a Pd thin film as a catalyst (see FIG. 7E). Further, the surface of the Ni plating layer was replaced with Au using an Au plating solution (see FIG. 7F), and the resist RG was removed to form source and drain electrodes whose surfaces were covered with Au (FIG. 7). (See (g) and (h)).

  On the other hand, a glass substrate was used as the second substrate BP2. A Cr film having a thickness of 120 nm is formed as a gate electrode film GL by sputtering on the surface of the second substrate BP2 (see FIG. 9A), and patterning is performed by photolithography (FIGS. 9B to 9E). The gate electrode GE was formed (see FIG. 9F). Subsequently, a thermoplastic urethane material was applied to a thickness of 1 μm on the second substrate BP2 on which the gate electrode GE was formed, thereby forming a gate insulating film GIL.

  Subsequently, by using a dispenser method, a solution OSL containing TIPS-Pentacene as the organic semiconductor OS is dropped onto a position that becomes a channel portion of the TFT on the gate insulating film GIL (see FIG. 16B), and the solvent is dried. (See FIG. 16 (c)).

  Next, the first substrate BP1 and the second substrate BP2 were stacked. With the second substrate BP2 adsorbed and fixed on the pressure-bonded flat plate PP1 heated to 60 ° C., the first substrate BP1 is held by a holding jig, and one end of the second substrate BP2 is stacked on the second substrate BP2, Using the CCD camera device, alignment markers AM on the first substrate BP1 and the second substrate BP2 were confirmed, and alignment was performed. Subsequently, the first substrate BP1 and the second substrate BP2 were pressure-bonded by pressing with a pressure roller PR1 heated to 80 ° C. in advance (see FIG. 12B).

Finally, the protective layer PT was formed. In this example, unlike the method illustrated in FIG. 14, a SiO ₂ film was used as the protective layer. First, in order to protect the organic semiconductor layer OS from damage during film formation of SiO ₂ , PVA (polyvinyl alcohol) was dropped into the opening HL of the first substrate BP1 using the IJ method. By dropping in the opening HL, application with high positional accuracy became possible. Subsequently, a SiO ₂ film having a thickness of 50 nm was formed by sputtering to form a protective layer PT.

  When the transistor characteristics of the organic TFT fabricated through the above steps were measured, it showed excellent performance. This is because Au, which has high contact performance with an organic semiconductor, was used as the source and drain electrodes, and the organic semiconductor layer was formed by directly coating on a highly flat gate insulating film without a step. This is probably because an organic semiconductor thin film with high crystallinity could be obtained.

  As described above, according to the present invention, the opening is formed, the first substrate on which the source electrode and the drain electrode are formed through the opening, and the second substrate on which the gate electrode and the gate insulating film are formed. By laminating the substrate, it is possible to provide a thin film transistor manufacturing method, a thin film transistor, and a display device that can manufacture a high performance thin film transistor at a low cost with a simple process without damaging the organic semiconductor layer.

  In addition, the manufacturing method of the thin film transistor according to the present invention, and the detailed configuration and detailed operation of each component constituting the thin film transistor and the display device can be appropriately changed without departing from the gist of the present invention.

It is a schematic diagram which shows an example of a structure of the display apparatus using TFT in this invention. It is sectional drawing which shows an example of a structure of TFT manufactured by the manufacturing method of this invention. It is a main process figure which shows 1st Embodiment of the manufacturing method of TFT in this invention. It is a schematic diagram for demonstrating the sub process of an opening formation process. It is a sub-process figure of a source / drain electrode formation process. FIG. 6 is a diagram (1/2) showing a state of forming source / drain electrodes in each sub-process of FIG. 5. FIG. 6B is a diagram (2/2) illustrating a formation state of source / drain electrodes in each sub-process of FIG. 5. It is a sub-process figure of a gate electrode formation process. It is sectional drawing which shows the formation state of the gate electrode in each sub process of FIG. It is a schematic diagram for demonstrating the sub process of a gate insulating film formation process. It is a schematic diagram for demonstrating the subprocess of a lamination process. It is a schematic diagram which shows the example of the crimping | compression-bonding method used at a lamination process. It is a schematic diagram for demonstrating the sub process of a semiconductor layer formation process. It is a schematic diagram for demonstrating the sub process of a protective layer formation process. It is a main process figure which shows 2nd Embodiment of the manufacturing method of TFT in this invention. It is a schematic diagram for demonstrating the sub process of the semiconductor layer formation process in 2nd Embodiment. It is a schematic diagram for demonstrating the subprocess of the lamination process in 2nd Embodiment.

Explanation of symbols

1 Display Device 10 TFT Sheet 11 TFT (Thin Film Transistor)
DESCRIPTION OF SYMBOLS 13 Storage capacitor 15 Output element 20 Horizontal drive circuit 21 Gate bus line 30 Vertical drive circuit 31 Source bus line BP1 1st board | substrate BP2 2nd board | substrate GE Gate electrode GIL Gate insulating film OS Organic semiconductor (layer)
SE source electrode DE drain electrode PT protective layer HL opening

Claims (7)

An opening forming step of forming an opening in the first substrate;
A source / drain electrode forming step of forming a source electrode and a drain electrode by conducting both surfaces of the first substrate through the opening;
Forming a gate electrode on the second substrate; and
Forming a gate insulating film including the gate electrode on the second substrate; and
A laminating step of laminating the first substrate on the gate insulating film of the second substrate;
A method of manufacturing a thin film transistor, comprising: a semiconductor layer forming step of forming a semiconductor layer between the source electrode and the drain electrode. An opening forming step of forming an opening in the first substrate;
A source / drain electrode forming step of forming a source electrode and a drain electrode by conducting both surfaces of the first substrate through the opening;
Forming a gate electrode on the second substrate; and
Forming a gate insulating film including the gate electrode on the second substrate; and
A semiconductor layer forming step of forming a semiconductor layer on the gate insulating film;
And a laminating step of laminating the first substrate on the gate insulating film of the second substrate. 3. The method of manufacturing a thin film transistor according to claim 1, wherein the source / drain electrode forming step is a step using a plating method. 4. The method of manufacturing a thin film transistor according to claim 3, wherein the plating is performed by autocatalytic plating and displacement plating. 5. The method of manufacturing a thin film transistor according to claim 4, wherein the displacement plating deposits gold (Au). A thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1. A display device comprising a plurality of the thin film transistors according to claim 6 arranged in a two-dimensional matrix.

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