JP2009110028A - Image display system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To smoothly display a moving image of a high frame rate. <P>SOLUTION: A controller performs control of a frame memory so as to output an α frame of a frame rate m as an output video signal S1, to output an α+1 frame of the frame rate m as an output video signal S2 at the supply start time b delayed by 1/4m from the supply start time (a) of the α frame, to output an α+2 frame of the frame rate m as an output video signal S3 at the supply start time c delayed by 1/4m from the supply start time b of the α+1 frame, and to output an α+3 frame of the frame rate m as an output video signal S4 at the supply start time d delayed by 1/4m from the supply start time c of the α+2 frame. The time period required to output each frame is 1/m and the cycle of outputting the head of each frame is n×m Hz. This invention is applicable to an imaging device, an image signal processing device and an image display device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image display system, and more particularly to an image display system that can smoothly display a moving image.

  There is a need to improve the image quality of displayed images by improving signal processing techniques and image display element driving techniques.

  In general, in order to improve the image quality, it is only necessary to increase the resolution of the image and make the image finer. The information amount of an image is expressed in units of pixels indicating dots (dots) constituting the image, and the number of pixels is expressed by the number of vertical and horizontal dots of the image, such as 800 × 600 or 1024 × 768. Is done. That is, the larger the number of pixels (dots), the finer the texture of the image and the more information that constitutes the image.

  In order to be able to display an image with high resolution, for example, using two displays, display 1 and display 2, in normal single mode, an image is displayed on display 1, and in multi mode, By displaying the left half of the image on the display 1 and the right half on the display 2, for example, in a multi-mode, an image can be displayed with double the resolution in a system using only one display. There is a technique that can be used (for example, see Patent Document 1).

  When the image is displayed at a higher resolution, the amount of information constituting the image increases, so the amount of data transferred to the display 1 or 2 increases, and a higher data transfer speed is required. For this reason, in this system, the data amount per dot of the displays 1 and 2 is reduced, and the reduced data is converted by signal processing, thereby transferring the image data without increasing the data transfer speed. Has been made to be able to do.

  In particular, the image quality of moving images can be improved by increasing the frame rate, which is a value indicating the number of times the screen is updated per second.

  For example, when a moving image is projected and displayed on a screen using a projector, the projector scans and displays a frame image one line at a time in the horizontal direction, scans all lines of one frame image, and then The moving image can be displayed by starting the scanning of the image data of this frame.

  When capturing moving image data to be displayed, in general, in order to compensate for the invalid portion of the light receiving unit with a CCD camera or the like, the imaging position is set by 1 / n of the size of one pixel of the CCD image sensor at the time of imaging. There is a case where a so-called pixel shifting means for acquiring an image by shifting is used (for example, Non-Patent Document 1). This technology is used in a camera that captures images at the same time with a multi-plate image sensor, or a camera that captures images at different times by vibrating a single image sensor or an optical system.

JP 10-120242 A

Introduction to CCD camera technology, Corona, 1997, PP109-111

  As described above, the image quality of moving images can be particularly improved by increasing the frame rate. However, in order to perform display processing according to a high frame rate, it is necessary to speed up the processing of the drive circuit that drives the display element, and further, the reaction speed of the light quantity modulation element that determines the image intensity must be increased. Therefore, it was technically difficult and increased costs.

  In addition, when using two displays and displaying an image with a resolution twice that of a system using only one display, the data transfer rate is increased by reducing the amount of data per display dot. A technique for avoiding this has already been used, but this technique does not increase the frame rate of a moving image to be displayed. Therefore, even in a system that can display an image with high resolution using two displays, in order to smoothly display a moving image, the processing speed of the drive circuit that drives the display element and the light amount modulation are increased. It is necessary to increase the reaction speed of the element.

  In addition, the frame rate of conventional display devices is generally 60 Hz for NTSC and HD systems, 50 Hz for PAL systems, and 24 Hz for movies. At these frame rates, video quality degradation such as blur and jerkiness was significant. Moreover, even if high frame rate shooting is attempted to prevent these problems, the amount of information that can be recorded in real time is limited to the above level due to the limitations of the drive speed of image sensors such as CCDs and restrictions on data transmission to recording media. It was. Recently, a special high-speed imaging device using a CMOS sensor has appeared, but it is expensive and currently there is only a method of storing this video information in a memory, and the recording time is short (for example, several tens of seconds). There was an inconvenience in shooting, such as it took time to transfer data from the camera.

  The present invention has been made in view of such a situation, and a conventional image sensor (for example, a CCD) is used to capture an image with a high frame rate and display the captured image with a high frame rate smoothly. It is something that can be done.

  A first image display system of the present invention is an image display system including an image processing device that processes an image signal and an image display device that displays an image corresponding to the image signal processed by the image processing device. The output of the image processing apparatus is controlled by a storage unit that stores an image signal having a first frame rate of mHz, an output control unit that controls output of the image signal stored by the storage unit, and an output control unit. A display control unit that controls display of an image corresponding to the image signal, and the image display device draws the image by a plurality of image display processing units that draw an image by a dot sequential or line sequential method, and the image display processing unit Display means for displaying the image to be displayed, at least n image display processing means are provided, and the output control means is provided with one frame for each of the n image display processing means. In addition, the output of the image signal of the first frame rate is controlled so as to be sequentially output from the storage unit, and the display control unit controls the second frame rate which is a frame rate n times the first frame rate. The image signals sequentially output to the n image display processing means by the output control means are shifted by 1 / (m × n) of the scanning time of one frame so that the image is displayed on the image display device. The display of an image corresponding to an image signal is controlled so as to be sequentially drawn by a dot sequential or line sequential method.

  In the first image display system of the present invention, the image processing apparatus stores an image signal having a first frame rate of mHz, outputs the stored image signal, and outputs an image corresponding to the output image signal. The display is controlled, and the image display device draws the image in a dot-sequential or line-sequential manner. The image to be drawn is displayed, and the image display is executed by at least n processing means. The image signal of the first frame rate is output to the image display processing means so that it is sequentially output from the storage means for each frame, and the second frame rate is n times the first frame rate. The image signals sequentially output are shifted by 1 / (m × n) of the scanning time of one frame so that an image is displayed on the image display device at a frame rate of 1 frame rate or a line sequential method. Te, As sequential rendering, display of an image corresponding to the image signal is controlled.

  A second image display system of the present invention is an image display system including an image processing device that processes an image signal and an image display device that displays an image corresponding to the image signal processed by the image processing device. The output of the image processing apparatus is controlled by a storage unit that stores an image signal having a first frame rate of mHz, an output control unit that controls output of the image signal stored by the storage unit, and an output control unit. Display control means for controlling the display of an image corresponding to the image signal, and the image display device comprises a plurality of image display processing means for drawing an image by a dot sequential or line sequential method, and the image display processing means , At least n, and the output control means outputs the first frame rate to the n image display processing means so as to sequentially output from the storage means every frame. The output control means controls the output of the image signal, and the output control means causes the output control means to display n images so that an image is displayed on the image display device at a second frame rate that is n times the first frame rate. The image signals sequentially output to the image display processing means are shifted by 1 / (m × n) of the scanning time of one frame, and the image signals are sequentially drawn by the dot sequential or line sequential method. The display of the image to be controlled is controlled.

  The image display device can be constituted by a projector that projects and displays an image.

  In the second image display system of the present invention, the image processing device stores the image signal of the first frame rate of mHz, outputs the stored image signal, and outputs the image corresponding to the output image signal. The display is controlled, and the image display apparatus draws an image by at least n processing means in a dot-sequential or line-sequential manner, and the n image display processing means from the storage means for each frame. The image signal having the first frame rate is output so that the images are sequentially output, and the image is displayed on the image display device at the second frame rate that is n times the first frame rate. The image signal corresponding to the image signal is output so that the sequentially output image signal is sequentially shifted by 1 / (m × n) of the scanning time of one frame and dot-sequential or line-sequential. Display of is controlled.

  According to the present invention, it is possible to capture a moving image. In particular, it is possible to capture a moving image with a higher frame rate than a single image sensor captures.

  According to another aspect of the present invention, a moving image can be displayed. In particular, a high frame rate moving image can be displayed.

  According to another aspect of the present invention, a moving image can be taken. In particular, a high frame rate moving image can be captured using pixel shifting of the image sensor.

  According to another aspect of the present invention, a moving image can be taken. In particular, by acquiring and combining luminance information and color information, it is possible to capture a moving image with high image quality at a high frame rate.

It is a block diagram which shows the structure of the imaging device to which this invention is applied. It is a figure for demonstrating the structure of the prism of FIG. 1, and a CCD image sensor. It is a figure for demonstrating a reference | standard synchronizing signal and a delay signal. It is a figure for demonstrating the frame image data imaged. It is a figure for demonstrating the frame image data imaged in the case of n = 4. It is a figure for demonstrating the frame image data imaged in the case of n = 5. It is a figure for demonstrating the case where 4 series moving image data is memorize | stored as 2 series moving image data. 6 is a flowchart for explaining image acquisition processing 1; It is a block diagram which shows the structure of the image signal processing apparatus and image display apparatus to which this invention is applied. It is a figure for demonstrating the output video signal in the case of n = 2. It is a figure for demonstrating the output video signal in the case of n = 3. It is a figure for demonstrating the output video signal in the case of n = 4. It is a figure for demonstrating the output video signal in the case of n = 5. It is a figure for demonstrating the structural example of the image display apparatus of FIG. It is a figure for demonstrating the update rate of the edge part of the moving image displayed on the image display apparatus of FIG. It is a figure which shows the example of the actual scene where the thing to move and the thing which is fixing coexist. It is a figure for demonstrating fixed vision conditions. It is a figure for demonstrating following vision conditions. It is a figure for demonstrating the observer's appearance in following vision and fixed vision. It is a figure for demonstrating the appearance of the observer for every imaging | photography condition, a display condition, and observation conditions. It is a figure for demonstrating strobe failure. It is a figure for demonstrating the appearance of the observer for every imaging | photography condition in high frame rate, a display condition, and observation conditions. It is a figure for demonstrating the evaluation result of the moving image quality which paid its attention to jerkiness. It is a figure for demonstrating the evaluation result of the moving image quality which paid its attention to motion blur. 6 is a flowchart for explaining image display processing 1; It is a block diagram for demonstrating the other structure of the image signal processing apparatus and image display apparatus to which this invention is applied. It is a figure for demonstrating the output signal and synthetic | combination signal in the image processing apparatus of FIG. It is a block diagram for demonstrating the other structure of the image signal processing apparatus and image display apparatus to which this invention is applied. It is a figure for demonstrating the output signal and synthetic | combination signal in the image processing apparatus of FIG. 10 is a flowchart for explaining image display processing 2; It is a block diagram for demonstrating the other structure of the image signal processing apparatus and image display apparatus to which this invention is applied. 10 is a flowchart for explaining image display processing 3; It is a block diagram for demonstrating the other structural example of the imaging device to which this invention is applied. It is a figure for demonstrating pixel shift. It is a figure for demonstrating the case where the interpolation process is not performed to the image data imaged with the imaging device of FIG. It is a figure for demonstrating the case where the interpolation process is performed to the image data imaged with the imaging device of FIG. 10 is a flowchart for explaining image acquisition processing 2; It is a block diagram for demonstrating the other structural example of the imaging device to which this invention is applied. It is a figure for demonstrating the structure of the prism of FIG. 38, and a CCD image sensor. It is a figure for demonstrating the synthesis | combination of luminance information and color information. It is a figure for demonstrating the contrast sensitivity of a luminance pattern and a chromaticity pattern. 10 is a flowchart for explaining image acquisition processing 3;

  Embodiments of the present invention will be described below. The correspondence relationship between the invention described in this specification and the embodiments of the invention is exemplified as follows. This description is intended to confirm that the embodiments supporting the invention described in this specification are described in this specification. Therefore, even if there is an embodiment that is described in the embodiment of the invention but is not described here as corresponding to the invention, the fact that the embodiment is not It does not mean that it does not correspond to the invention. Conversely, even if an embodiment is described herein as corresponding to an invention, that means that the embodiment does not correspond to an invention other than the invention. Absent.

  Further, this description does not mean all the inventions described in this specification. In other words, this description is for the invention described in the present specification, which is not claimed in this application, that is, for the invention that will be applied for in the future or that will appear and be added by amendment. It does not deny existence.

  According to the present invention, an image display system can be provided. This image display system is compatible with an image processing device that processes image signals (for example, the image signal processing device 51 in FIG. 9 or the image signal processing device 101 in FIG. 26) and an image signal processed in the image processing device. An image display system configured to display an image to be displayed (for example, the image display device 52 or the scan control unit 81-1 in FIG. 9 or FIG. 26), and the image processing device Storage means (for example, the memory 61 in FIG. 9 or FIG. 26) for storing the image signal of the first frame rate (for example, mHz), and output control means for controlling the output of the image signal stored by the storage means (For example, the controller 62 in FIG. 9 or the controller 111 in FIG. 26) and the display of the image corresponding to the image signal whose output is controlled by the output control means. Display control means (for example, the display control unit 66 in FIG. 9 or FIG. 26), and the image display apparatus draws a plurality of image display processing means (for example, FIG. 9 or the scanning control unit 81-1 in FIG. 26, and a display unit (for example, the display unit 82 in FIG. 9 or FIG. 26) for displaying an image drawn by the image display processing unit. At least n display processing means are provided, and the output control means outputs the image signal of the first frame rate to the n image display processing means so that it is sequentially output from the storage means for each frame. The output control means controls the output so that an image is displayed on the image display device at a second frame rate (for example, m × n Hz) which is a frame rate n times the first frame rate. By means The image signals sequentially output to n image display processing means are shifted by 1 / (m × n) of the scanning time of one frame, and are sequentially drawn by a dot sequential or line sequential method. The display of the image corresponding to the signal can be controlled.

  Further, according to the present invention, an image display system can be provided. This image display system is compatible with an image processing device that processes image signals (for example, the image signal processing device 51 in FIG. 9 or the image signal processing device 101 in FIG. 26) and an image signal processed in the image processing device. An image display system configured to display an image to be displayed (for example, the image display device 52 or the scan control unit 81-1 in FIG. 9 or FIG. 26), and the image processing device Storage means (for example, the memory 61 in FIG. 9 or FIG. 26) for storing the image signal of the first frame rate (for example, mHz), and output control means for controlling the output of the image signal stored by the storage means (For example, the controller 62 in FIG. 9 or the controller 111 in FIG. 26) and the display of the image corresponding to the image signal whose output is controlled by the output control means. Display control means (for example, the display control unit 66 in FIG. 9 or FIG. 26), and the image display apparatus draws a plurality of image display processing means (for example, FIG. 9 or the scanning control section 81-1) of FIG. 26, and at least n image display processing means are provided, and the output control means is stored in n image display processing means for each frame. The output of the image signal of the first frame rate is controlled so as to be sequentially output from the means, and the display control means has a second frame rate (for example, m) which is a frame rate n times the first frame rate. The image signal sequentially output to the n image display processing means by the output control means is 1 / (m × n) of one frame scanning time so that an image is displayed on the image display device at × nHz). Misaligned, dot order Or by line sequential method, as sequential rendering, it is possible to control the display of an image corresponding to the image signal.

  The image display device can be constituted by a projector that projects and displays an image.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an imaging apparatus 1 to which the present invention is applied.

  As shown in FIG. 1, the imaging device 1 includes a lens 21, a prism 22, a CCD (Charge Coupled Devices) image sensor 23, a timing controller 24, a controller 25, a reference synchronization signal generator 26, and correlated double sampling (CDS: Correlated). A double sampling unit 27, an A / D converter 28, an image processing unit 29, a codec (CODEC: COmpression / DECompression) processing unit 30, a memory 31, an operation input unit 32, and a drive 33.

  The prism 22 is composed of a prism beam splitter in which the number of imaging elements included in the CCD image sensor 23 is n, and the reflectance of light incident through the lens 21 is 1 / n. The light thus divided is divided into n pieces and supplied to n pieces of image pickup devices of the CCD image sensor 23.

  The CCD is a semiconductor element that converts optical information into an electrical signal (photoelectric conversion). The CCD image sensor 23 includes a plurality of light receiving elements (pixels) that convert light into electricity, and changes in light for each pixel. The image sensor includes n imaging elements that are independently converted into electrical signals. The CCD image sensor 23 includes n imaging elements, but is not a so-called double-plate CCD image sensor. For example, RGB primary color filters are arranged in a mosaic pattern for each light receiving element. N common single-plate CCD image sensors having a color filter such as a Bayer array are used. The color filters of the respective image sensors of the CCD image sensor 23 may be arranged other than the Bayer arrangement.

  The plurality of image sensors of the CCD image sensor 23 acquire image information at different timings under the control of the timing controller 24. The timing controller 24 supplies a trigger signal obtained by delaying the reference synchronization signal supplied from the reference synchronization signal generator 26 by a predetermined time to a plurality of image sensors of the CCD image sensor 23 based on the control of the controller 25. To do.

  Based on the user's operation input input by the operation input unit 32, the controller 25 includes a timing controller 24, a correlated double sampling processing unit 27, an A / D converter 28, an image processing unit 29, a codec processing unit 30, and The memory 31 is controlled. The reference synchronization signal generator 26 generates a synchronization signal that serves as a reference for the timing controller 24 to control a plurality of image sensors of the CCD image sensor 23, and supplies the synchronization signal to the timing controller 24.

  The correlated double sampling circuit 27 samples the reset noise, which is the main component of the noise included in the output signal of the CCD image sensor 23, the video signal period of the output pixel signals, and the reference period. Is a circuit that removes the signal by subtracting the sampled signal. The A / D converter 28 converts the supplied analog signal after noise removal into a digital signal.

  The image processing unit 29 is a block having a signal processing processor and an image RAM. The signal processing processor performs pre-programmed image processing or hardware calculation on the image data stored in the image RAM. The image processing configured as processing is performed.

  The codec processing unit 30 executes processing based on a compression or expansion algorithm for digital image data. The memory 31 is composed of, for example, a semiconductor memory, a magnetic disk, a magneto-optical disk, or an optical disk, and stores supplied data or outputs stored data based on the control of the controller 25. To do. The memory 31 may be detachable from the imaging device 1.

  The operation input unit 32 includes, for example, a jog dial, a key, a lever, a button, or a touch panel as well as a button for instructing display of a moving image. The operation input unit 32 receives an operation input by a user and supplies it to the controller 25. In addition, a drive 33 is connected to the controller 25 as necessary, and a magnetic disk 41, an optical disk 42, a magneto-optical disk 43, a semiconductor memory 44, or the like is appropriately mounted, and a computer program read therefrom is It is executed by the controller 25 as necessary.

  Next, the operation of the imaging apparatus 1 will be described.

  The light input through the lens 21 is divided by the prism 22 and incident on the CCD image sensor 23, and is converted into an electric signal by photoelectric conversion at a timing controlled by the timing controller 24 in each of the n light receiving elements. It is converted and supplied to the correlated double sampling circuit 27. The correlated double sampling circuit 27 removes noise by subtracting the sampling of the video signal period and the sampling of the reference period from the pixel signals output from the CCD image sensor 23, and the A / D This is supplied to the converter 28. The A / D converter 28 converts the supplied analog signal after noise removal into a digital signal, and temporarily stores it in the image RAM of the image processing unit 29.

  The image processing unit 29 receives supply of pixel stream data at a constant rate, temporarily stores it in the image RAM, and the signal processing processor performs, for example, white balance adjustment, demosaicing on the temporarily stored image data. Various image processing such as processing, matrix processing, gamma correction, and YC conversion are executed.

  The codec processing unit 30 performs a predetermined encoding on the image data supplied from the image processing unit 29, and supplies the encoded image data to the memory 31 for storage.

  Next, with reference to FIGS. 2 and 3, taking as an example the case where the number n of image sensors included in the CCD image sensor 23 is 4, the reflectance of light incident through the lens 21 is ¼. A prism beam splitter, which is composed of a prism beam splitter, divides light incident through the lens 21 into four parts and supplies light to the four image sensors of the CCD image sensor 23, and four CCD image sensors 23. The image acquisition timing of the image sensor will be described.

  The prism 22 is composed of prism beam splitters 22-1 to 22-3 that cause 50% of incident light to travel straight and reflect the remaining 50% in the vertical direction from the incident light path.

  The light incident through the lens 21 is divided in half by the prism beam splitter 22-2 and supplied to the prism beam splitter 22-1 and the prism beam splitter 22-3. The light incident on the prism beam splitter 22-1 is further divided in half and supplied to the first image sensor 23-1 and the second image sensor 23-2 of the CCD image sensor 23. The light incident on the prism beam splitter 22-3 is further divided in half and supplied to the third image sensor 23-3 and the fourth image sensor 23-4 of the CCD image sensor 23. The optical path lengths from the lens 21 of incident light supplied to the first image sensor 23-1 to the fourth image sensor 23-4 are all equal.

  The first imaging device 23-1 to the fourth imaging device 23-4 are each supplied with a drive signal for instructing image acquisition timing (that is, timing for performing photoelectric conversion) from the timing controller 24.

  The timing controller 24 has three delay processing units, a delay processing unit 24-1 to a delay processing unit 24-3. The delay processing units 24-1 to 24-3 delay the synchronization signal by a predetermined time width and output the reference synchronization signal supplied from the reference synchronization signal generation unit 26.

  That is, the timing controller 24 is delayed by (1/4) t from the (1 / t) Hz reference synchronization signal supplied from the reference synchronization signal generator 26, as shown in FIG. Delay signal 1 of (1 / t) Hz, delay signal 2 of (1 / t) Hz delayed by (2/4) t from the reference synchronization signal, and delay by (3/4) t from the reference synchronization signal The (1 / t) Hz delayed signal 3 is supplied to the CCD image sensor 23.

  The reference synchronization signal is supplied to the first image sensor 23-1, the delay signal 1 is supplied to the second image sensor 23-2, and the delay signal 2 is supplied to the third image sensor 23-3. The delay signal 3 is supplied to the fourth image sensor 23-4.

  For example, when the drive speed limit of each image sensor of the CCD image sensor 23 is 60 Hz, the frequency of the reference synchronization signal is set to 60 Hz (that is, t = 1/60 seconds), and the delay signal 1 is determined from the reference synchronization signal. When the delay is delayed by 1/15 seconds, the delay signal 2 is delayed by 2/15 seconds from the reference synchronization signal, and the delay signal 3 is delayed by 3/15 seconds from the reference synchronization signal, the first image sensor 23-1 The frame rate of the image captured by the fourth image sensor 23-4 is 60 × 4 240 Hz. Further, by setting the shutter speed of each of the first image sensor 23-1 to the fourth image sensor 23-4 to 1/15 seconds, a more accurate moving image can be acquired.

  Similarly, even when the number n of image pickup elements included in the CCD image sensor 23 is a different number other than 4, the prism 22 is a prism whose reflectivity of light incident through the lens 21 is 1 / n. The beam splitter is configured to divide the light incident through the lens 21 into n pieces of light and supply the light to the n image pickup elements of the CCD image sensor 23. When the frequency of the reference synchronization signal is mHz, the timing controller 24 generates (n−1) delayed signals that are delayed by 1 / (n × m) seconds. It is possible to obtain an image with a high frame rate of (m × n) Hz.

  For example, when the number n of image sensors is 5, and the frequency of the reference synchronization signal is 50 Hz, an image with a high frame rate of 250 Hz is acquired by the five image sensors of the CCD image sensor 23.

  With such a configuration, it is possible to acquire an image with a frame rate faster than the limit of the driving speed of each image sensor of the CCD image sensor 23.

  The acquired image data is processed by the correlated double sampling processing unit 27, the A / D converter 28, the image processing unit 29, and the codec processing unit 30, and stored in the memory 31. At this time, the acquired image data may be processed and stored as moving image data having a high frame rate of (m × n) Hz, but the phase is shifted by 1 / n. As a series of moving image data, they may be individually processed and stored. When n-sequence moving image data of mHz each having a phase shift of 1 / n is individually processed and stored, the memory 31 generates four moving image data files. Are output individually.

  The case where the acquired image data is stored in the memory 31 as moving image data having a high frame rate of (m × n) Hz will be described with reference to FIG. Here, as described with reference to FIGS. 2 and 3, the case where n = 4 and the image data is acquired by the imaging device 23-1 to 23-4 of the CCD image sensor 23 will be described as an example. However, even if n is any value other than 4, since the moving image data of a high frame rate of (m × n) Hz is sequentially stored in the memory 31 as shown in FIG. Description of values other than n being 4 is omitted.

  For example, when the α frame, which is the αth frame, is acquired by the image sensor 23-1 of the CCD image sensor 23, the α + 1 frame is 1 / (m × n) seconds from the α frame by the image sensor 32-2. Acquired late. The α + 2 frame is acquired 1 / (m × n) seconds later than the α + 1 frame by the image sensor 32-3, and the α + 3 frame is 1 / (m × n) from the α + 2 frame by the image sensor 32-4. Acquired with a delay of seconds. Further, the α + 4 frame is acquired again by the image sensor 32-1 with a delay of 1 / (m × n) seconds from the α + 3 frame, and the α + 5 frame is 1 / (m × n from the α + 4 frame by the image sensor 32-2. ) Acquired with a delay of seconds.

  When the acquired image data is stored as moving image data with a high frame rate of (m × n) Hz in the memory 31, each image processed frame is sequentially stored in the memory 31. The difference in time of each stored frame is 1 / (m × n).

  The case where the acquired image data is stored in the memory 31 as n-sequence moving image data of mHz each having a phase shift of 1 / n will be described with reference to FIGS. 5 and 6. FIG. 5 shows an example when n = 4, and FIG. 6 shows an example when n = 5.

  In the case of n = 4, as shown in FIG. 5, the first moving image data stored in the memory 31 is moving image data of frame rate m of α frame, α + 4 frame,. The moving image data is moving image data of frame rate m of α + 1 frame, α + 5 frame,..., And the third moving image data is moving image data of frame rate m of α + 2 frame, α + 6 frame,. The fourth moving image data is moving image data having a frame rate m of α + 3 frames, α + 7 frames,. In FIG. 5, in order to clarify the relationship of acquisition time between frames, the respective frames are illustrated as being separated from each other, but are stored as first moving image data to fourth moving image data. It goes without saying that each frame image data may be stored continuously.

  For example, as described with reference to FIGS. 2 and 3, when n = 4 and image data is acquired by the image sensor 23-1 to 23-4 of the CCD image sensor 23, each image sensor It is preferable that the image data obtained by the above is subjected to image processing independently and stored in the memory 31 as the first to fourth moving image data.

  Further, when n = 5, as shown in FIG. 6, the first moving image data stored in the memory 31 is moving image data of frame rate m of α frame, α + 5 frame,. The moving image data of 2 is moving image data of frame rate m of α + 1 frame, α + 6 frame,..., And the third moving image data is moving image data of frame rate m of α + 2 frame, α + 7 frame,. The fourth moving image data is moving image data with a frame rate m of α + 3 frames, α + 8 frames,..., And the fifth moving image data has a frame rate m of α + 4 frames, α + 9 frames,. Video data. In FIG. 6, in order to clarify the relationship between the acquisition times between frames, the respective frames are illustrated as being separated from each other, but are stored as first moving image data to fifth moving image data. It goes without saying that each frame image data may be stored continuously.

  Note that, even if n is any value other than 4 or 5, for example, 2, 3, 6, etc., the memory 31 stores n-sequence moving image data of mHz each having a phase shift of 1 / n. Can be processed and stored individually. Further, the memory 31 is supplied with n-sequence moving image data of mHz each having a phase shift of 1 / n, and the n-sequence moving image data is, for example, n / 2 or n / 3. It may be possible to store together the moving image data of the number of sequences.

  For example, when the 4 series of moving image data as described with reference to FIG. 5 is supplied to the memory 31, the 4 sequences of moving image data are stored in the memory 31 as shown in FIG. It can be stored as a series of moving image data. In that case, α frame, α + 2 frame, α + 4 frame,... Are stored in the first moving image data, and α + 1 frame, α + 3 frame, α + 5 frame, etc. are stored in the second moving image data. The That is, the first moving image data and the second moving image data are moving image data having a frame rate of 2 m.

  Next, the image acquisition process 1 will be described with reference to the flowchart of FIG.

  In step S <b> 1, the prism 22 divides light incident through the lens 21 into n parts (in the case described with reference to FIG. 2, it is divided into four parts), and n image pickup elements (see FIG. 2 is supplied to the image sensors 23-1 to 23-4).

  In step S2, the timing controller 24, based on the mHz reference synchronization signal supplied from the reference synchronization signal generator 26, obtains image data acquisition timing signals by n image sensors, that is, 1 / (n Xm) A delay signal of (n-1) delayed by seconds is generated and supplied to n imaging elements of the CCD image sensor 23.

  In step S <b> 3, the CCD image sensor 23 acquires image data with a frame rate of (m × n) Hz using n imaging elements based on the timing signal supplied from the timing controller 24.

  In step S <b> 4, the correlated double sampling processing unit 27, the A / D converter 28, the image processing unit 29, and the codec processing unit 30 obtain an image with a frame rate of (m × n) Hz acquired by the CCD image sensor 23. Image processing is performed on the data.

  In step S5, the memory 31 receives and stores the processed image, and the process ends.

  By such processing, image data with a frame rate of (m × n) Hz is acquired and stored using n image sensors. Image data having a frame rate of (m × n) Hz may be stored in the memory 31 as n-sequence moving image data of mHz each having a phase shift of 1 / n.

  Next, a display method of image data having a frame rate of (m × n) Hz acquired in this way will be described.

  FIG. 9 is a block diagram showing the configuration of the image signal processing device 51 and the image display device 52 to which the present invention is applied.

  The image signal processing device 51 is individually supplied with n-sequence moving image data of mHz each having a phase shift of 1 / n constituting image data having a frame rate of (m × n) Hz, and the memory 61 The frame memories 61-1 to 61-n are supplied and held.

  The controller 62 receives images from the frame memories 61-1 to 61-n based on the mHz reference synchronization signal supplied from the reference synchronization signal generation unit 64 in accordance with a user operation input input from the operation input unit 63. While controlling the output of the signal, information related to the output of the video signal from the frame memories 61-1 to 61-n is supplied to the display control unit 66. The operation input unit 63 includes, for example, a jog dial, a key, a lever, a button, or a touch panel as well as a button for instructing display of a moving image. The reference synchronization signal generator 64 generates a synchronization signal that serves as a reference for the controller 62 to control the plurality of frame memories 61-1 to 61-n of the memory 61, and supplies the synchronization signal to the controller 62.

  The frame memories 61-1 to 61-n of the memory 61 output the supplied digital image signals S1 to S4 to the D / A converters 65-1 to 65-n based on the control of the controller 62.

  The D / A converters 65-1 to 65-n convert the digital image signals S1 to S4 supplied from the frame memories 61-1 to 61-n into analog image signals, and scan the image display device 52. It supplies to the control part 81-1 thru | or 81-n. The display control unit 66 controls display of a moving image by the image display device 52 based on the information supplied from the controller 62, and displays a frame image having a frame rate of (m × n) Hz.

  Further, a drive 67 is connected to the controller 62 as necessary, and a magnetic disk 71, an optical disk 72, a magneto-optical disk 73, a semiconductor memory 74, or the like is appropriately mounted, and a computer program read from them is It is executed by the controller 62 as necessary.

  The timing of image data read from the frame memories 61-1 to 61-n based on the control of the controller 62 will be described with reference to FIGS.

  The timing of image data read from the frame memories 61-1 to 61-n when n = 2 will be described with reference to FIG.

  The controller 62 controls the frame memories 61-1 and 61-2 to supply the α frame at the frame rate m from the frame memory 61-1 to the A / D conversion unit 65-1 as the output video signal S <b> 1. From the memory 61-2, the α + 1 frame at the frame rate m is set as the output video signal S2 at the supply start time b delayed by ½ m from the supply start time a of the α frame. To supply.

  The time taken to supply the α frame to the A / D conversion unit 65-1 is 1 / m, and the supply end time c is 1 from the supply start time b to the A / D conversion unit 65-2 of the α + 1 frame. / 2m later. Then, the α + 2 frame from the time c is supplied from the frame memory 61-1 to the A / D conversion unit 65-1 over time 1 / m. That is, the supply end time e of the α + 2 frame is 2 / m. Also, the time taken to supply the α + 1 frame to the A / D conversion unit 65-2 is 1 / m, and the supply end time d is from the supply start time c to the A / D conversion unit 65-2 of the α + 2 frame. ½m later. Then, the α + 3 frame from the time d is supplied from the frame memory 61-2 to the A / D conversion unit 65-2 over time 1 / m. That is, the supply end time f of the α + 3 frame is 5/2 m.

  Next, the timing of image data read from the frame memories 61-1 to 61-n when n = 3 will be described with reference to FIG.

  The controller 62 controls the frame memories 61-1 to 61-3 to supply the α frame of the frame rate m from the frame memory 61-1 to the A / D conversion unit 65-1 as the output video signal S1, and From the memory 61-2, the α + 1 frame at the frame rate m is set as the output video signal S2 at the supply start time b delayed by 1/3 m from the α frame supply start time a. From the frame memory 61-3, the α + 2 frame at the frame rate m is output as the output video signal S3 at the supply start time c delayed by 1/3 m from the supply start time b of the α + 1 frame. It is made to supply to the conversion part 65-3.

  The time taken to supply the α frame to the A / D conversion unit 65-1 is 1 / m, and the supply end time d is 2 from the supply start time b to the A / D conversion unit 65-2 of the α + 1 frame. / 3m later. Then, the α + 3 frame from the time d is supplied from the frame memory 61-1 to the A / D converter 65-1 over time 1 / m. That is, the supply end time g of the α + 3 frame is 2 / m. Also, the time taken to supply the α + 1 frame to the A / D conversion unit 65-2 is 1 / m, and the supply end time e is from the supply start time c to the A / D conversion unit 65-3 of the α + 2 frame. Only 2 / 3m later. Then, α + 4 frames are supplied from the time d to the A / D converter 65-2 from the frame memory 61-2 over time 1 / m. That is, the supply end time f of the α + 4 frame is 7/3 m. Also, the time taken to supply the α + 2 frame to the A / D conversion unit 65-3 is 1 / m, and the supply end time f is from the supply start time d to the A / D conversion unit 65-1 of the α + 3 frame. Only 2 / 3m later. Then, the α + 5 frame from the time f is supplied from the frame memory 61-3 to the A / D converter 65-3 over time 1 / m. That is, the supply end time i of the α + 5 frame is 8/3 m.

  Next, the timing of image data read from the frame memories 61-1 to 61-n when n = 4 will be described with reference to FIG.

  The controller 62 controls the frame memories 61-1 to 61-4 to supply the α frame of the frame rate m from the frame memory 61-1 to the A / D conversion unit 65-1 as the output video signal S1, and to From the memory 61-2, the α + 1 frame at the frame rate m is set as the output video signal S2 at the supply start time b delayed by ¼ m from the supply start time a of the α frame. From the frame memory 61-3, the α + 2 frame at the frame rate m as the output video signal S3 at the supply start time c delayed by 1/4 m from the supply start time b of the α + 1 frame. The conversion unit 65-3 supplies the frame memory 61-4 with α + 3 frames having a frame rate m as an output video signal S4. Than the supply start time c, at 1 / 4m only delayed supply start time d, it is supplied to the A / D converter 65-4.

  The time taken to supply the α frame to the A / D conversion unit 65-1 is 1 / m, and the supply end time e is 3 from the supply start time b to the A / D conversion unit 65-2 of the α + 1 frame. / 4m later. Then, α + 4 frames from time e are supplied from the frame memory 61-1 to the A / D converter 65-1 over time 1 / m. That is, the supply end time i of the α + 4 frame is 2 / m. Also, the time taken to supply the α + 1 frame to the A / D conversion unit 65-2 is 1 / m, and the supply end time f is from the supply start time c to the A / D conversion unit 65-3 of the α + 2 frame. 3 / 4m later. Then, the α + 5 frame from the time f is supplied from the frame memory 61-2 to the A / D conversion unit 65-2 over time 1 / m. That is, the supply end time j of the α + 5 frame is 9/4 m.

  Also, the time taken to supply the α + 2 frame to the A / D conversion unit 65-3 is 1 / m, and the supply end time g is from the supply start time d to the A / D conversion unit 65-4 of the α + 3 frame. 3 / 4m later. Then, α + 6 frames from time f are supplied from the frame memory 61-3 to the A / D converter 65-3 over time 1 / m. That is, the supply end time i of the α + 6 frame is 5/2 m. The time taken to supply the α + 3 frame to the A / D converter 65-4 is 1 / m, and the supply end time h is from the supply start time e to the A / D converter 65-1 of the α + 4 frame. 3 / 4m later. Then, the α + 7 frame from the time h is supplied from the frame memory 61-4 to the A / D conversion unit 65-4 over time 1 / m. That is, the supply end time 1 of the α + 7 frame is 11/4 m.

  Next, the timing of image data read from the frame memories 61-1 to 61-n when n = 5 will be described with reference to FIG.

  The controller 62 controls the frame memories 61-1 to 61-5 to supply the α frame at the frame rate m from the frame memory 61-1 to the A / D conversion unit 65-1 as the output video signal S1, thereby From the memory 61-2, the α + 1 frame at the frame rate m is set as the output video signal S2 at the supply start time b delayed by 1/5 m from the supply start time a of the α frame. From the frame memory 61-3, the α + 2 frame at the frame rate m as the output video signal S3 at the supply start time c delayed by 1/5 m from the supply start time b of the α + 1 frame. The conversion unit 65-3 supplies the frame memory 61-4 with α + 3 frames having a frame rate m as an output video signal S4. The A / D converter 65-4 is supplied with the supply start time d delayed by 1/5 m from the supply start time c, and α + 4 frame at the frame rate m is output from the frame memory 61-5 to the output video signal S5. As described above, the A / D converter 65-5 is supplied with the supply start time e delayed by 1/5 m from the supply start time d of the α + 3 frame.

  The time taken to supply the α frame to the A / D conversion unit 65-1 is 1 / m, and the supply end time f is 4 from the supply start time b to the A / D conversion unit 65-2 of the α + 1 frame. / 5m later. Then, from time f, α + 5 frame is supplied from the frame memory 61-1 to the A / D converter 65-1 over time 1 / m. That is, the supply end time f of α + 5 frame is 2 / m. Also, the time taken to supply the α + 1 frame to the A / D converter 65-2 is 1 / m, and the supply end time g is from the supply start time c to the A / D converter 65-3 of the α + 2 frame. 4 / 5m later. Then, from time g, α + 6 frame is supplied from the frame memory 61-2 to the A / D conversion unit 65-2 over time 1 / m. That is, the supply end time 1 of the α + 5 frame is 11/5 m.

  Also, the time taken to supply the α + 2 frame to the A / D conversion unit 65-3 is 1 / m, and the supply end time h is from the supply start time d to the A / D conversion unit 65-4 of the α + 3 frame. 4 / 5m later. Then, the next frame (α + 7 frame, not shown) is supplied from the frame memory 61-3 to the A / D converter 65-3 over time 1 / m from time h. The time taken to supply the α + 3 frame to the A / D conversion unit 65-4 is 1 / m, and the supply end time i is from the supply start time e to the A / D conversion unit 65-5 of the α + 4 frame. 4 / 5m later. Then, the next frame (α + 8 frame (not shown)) is supplied from the frame memory 61-4 to the A / D converter 65-4 over time 1 / m from time i. The time taken to supply the α + 4 frame to the A / D conversion unit 65-5 is 1 / m, and the supply end time j is determined from the supply start time f to the A / D conversion unit 65-1 of the α + 5 frame. 4 / 5m later. Then, from time j, the next frame (α + 9 frame, not shown) is supplied from the frame memory 61-5 to the A / D converter 65-5 over time 1 / m.

  Returning to FIG. 9 again, the image display device 52 will be described.

  The image display device 52 is supplied with n analog video signals supplied from the image signal processing device 51, and uses the scanning control units 81-1 to 81 -n based on the control of the display control unit 66. Then, a moving image of (m × n) Hz is displayed on the display unit 82.

  The scanning control units 81-1 to 81-n receive an analog video signal and cause the display unit 82 to display the supplied analog video signal by a dot sequential or line sequential scanning method. At this time, the scanning control units 81-1 to 81-n alternately scan successive frames with a shift of 1 / n frames, thereby independently performing image drawing in the scanning control units 81-1 to 81-n. Image display on the display unit 82 can be performed at a frame rate n times the frame rate.

  Further, the image display device 52 may be configured as an image display system including a plurality of devices in addition to being configured as a single device. When the image display device 52 is configured as an image display system, for example, as illustrated in FIG. 14, the image display device 52 can be configured by a projector 91-1 to a projector 91-n and a screen 92.

  The specific operation of the image display device 52 will be described by taking as an example the case of using the projectors 91-1 to 91-n and the screen 92 shown in FIG. The projector 91-1 corresponds to the scanning control unit 81-1 in FIG. 9, the projector 91-n corresponds to the scanning control unit 81-n in FIG. 9, and the screen 92 corresponds to the display unit 82 in FIG. To do.

  For example, the projectors 91-1 to 91-n are read from the frame memories 61-1 to 61-n at the timing described with reference to FIGS. 10 to 13 and converted into analog signals by the A / D conversion unit 65. The analog video signals corresponding to the output video signals S1 to Sn are supplied.

  Each of the projectors 91-1 to 91-n has a pixel (X, Y) = (0, 0) constituting a display image to be displayed at a timing based on the control of the display control unit 66. , Y) = (p, q) is scanned in the horizontal direction on the screen 92 to display a frame image corresponding to the supplied video signal. The frame rate of each frame image displayed on the screen 92 by each of the projectors 91-1 to 91-n is mHz, and the frame rate of the moving image displayed by the projectors 91-1 to 91-n. Is (m × n) Hz. Further, the scanning start timing of each frame displayed by the projector 91-1 through the projector 91-n is the same as in the output video signal S1 through the output video signal Sn described with reference to FIGS. −1 to each projector 91-n are shifted by 1 / n phase, that is, 1 / (m × n) with respect to each one frame display.

  For example, when the projector 91-2 scans the line indicated by the scan B on the screen 92 and the corresponding line of the α + 1 frame, the projector 91-3 moves to the line indicated by the scan A on the screen 92. , Α + 2 frame corresponding lines are scanned. The line indicated by the scan B is a line shifted from the line indicated by the scan A by 1 / n of the number of lines in one frame. That is, the moving image displayed on the screen 92 is sequentially rewritten by a plurality of scans including the scan A and the scan B every time 1 / (m × n).

  For example, when n = 2 and the frame rate of the display image output from the projector 91-1 and the projector 91-2 is 120 Hz, the frame rate of the moving image displayed on the screen is substantially And 240 Hz. For example, when n = 3 and the frame rate of the display image output from the projector 91-1 to the projector 91-3 is 80 Hz, the frame rate of the moving image displayed on the screen is It is substantially 240 Hz. For example, when n = 4 and the frame rate of the display image output from the projectors 91-1 to 91-4 is 60 Hz, the frame rate of the moving image displayed on the screen is substantially And 240 Hz. Further, for example, when n = 5 and the frame rate of the display image output from the projector 91-1 to the projector 91-5 is 50 Hz, the frame rate of the moving image displayed on the screen is In effect, it becomes 250 Hz.

  It should be noted that in order to prevent a shift of the scanning line at the same position by a plurality of scanning lines such as scanning A and scanning B shown in FIG. 14, the optical image used in the conventional so-called twin stack technique is used. It is possible to correct the scanning position of the pixel using a technique similar to the position correction. The twin stack technology is a technology that can display a bright image by using two projectors and simultaneously displaying the same image at the same position. When an image is displayed using a twin stack, the brightness of the displayed image is doubled, and clear projection is possible even when the surrounding environment is bright or the projection distance is long.

  In the case of using the twin stack technology, the occurrence of blurring of the image due to the displacement of the pixel position of the two projected images has become a problem. To solve this problem, the pixel of the pixel that is optically projected A so-called picture shift function capable of finely adjusting the position is widely used, and the positions of the images projected from the two projectors can be precisely matched. This technique is applicable even when a plurality of projectors are used.

  A technique for correcting a shift in pixel position between two projected images is disclosed in, for example, Japanese Patent Application No. 10-058291.

  In the image display device 52, the image is blurred due to the overlap with the image shifted by one frame by adjusting the shift of the scanning line by a plurality of scans to be within one pixel (one dot or one pixel). This makes it possible to display a moving image without any trouble.

  As described above, when a frame image is drawn by the projector 91-1 through the projector 91-n with a shift of 1 / n frame in order frame by frame, one frame is completely displayed by a certain projector. The scanning for drawing the image of the next frame is started by another projector earlier than the scanning and drawing. At this time, when the object C displayed on the screen 92 in FIG. 14 is displayed so as to move from the left to the right on the display screen, for example, for the user observing the moving image, the movement of the edge portion is performed. Smoothness is felt as the smoothness of the displayed video.

  The display of the edge portion β of the object C displayed on the screen 92 will be described with reference to FIG.

  The projector 91-1 displays the object C of the α frame, and after time 1 / (m × n), the projector 91-2 displays the object C of the α + 1 frame. At this time, the position of the edge portion β of the object C is rewritten at time 1 / (m × n) from the display of the α frame. Then, an object C of α + 2 frame is displayed after time 1 / (m × n) by the projector 91-3 (when n = 2, the projector 91-2). At this time, the edge portion β of the object C is rewritten at time 1 / (m × n) from the display of the α + 1 frame.

  For example, when the frame rate of the display image output from each of the projectors 91-1 to 91-n is mHz, a moving image displayed by any one of the projectors 91-1 to 91-n alone. In, the frame is rewritten every 1 / m (second). On the other hand, the edge portion β of the object C displayed on the screen 92 by displaying the frame images one frame at a time using the projectors 91-1 to 91-n is 1 / (m × n). Refreshed in (seconds). Therefore, the movement of the edge portion β of the object C observed by the user becomes very smooth.

  Here, the image display device 52 is described as controlling the display of an image under the control of the display control unit 66, but the image display device 52 has the display control unit 66 therein (that is, The image display device 52 and the display control unit 66 constitute a single device), and the controller 62 is supplied with a control signal necessary for image display, or is different from the display control unit 66 inside. For example, and controls the operations of the projectors 91-1 to 91-n described with reference to FIG. 14 by receiving a vertical synchronization signal, a dot clock signal, or the like from the display control unit 66. Also good.

  Here, the operation of the image display device 52 has been described by taking a projection display system including the projector 91-1 to the projector 91-n and the screen 92 as an example. However, the image display device 52 includes a plurality of displays. By using a device to shift 1 / n frames and sequentially scanning successive frames, a moving image is displayed at a frame rate of n times the frame rate mHz of each display device alone. Any display system that draws an image by a dot sequential or line sequential scanning method may be used as long as it can.

  Examples of the image display device 52 include CRT (Cathode Ray Tube), LCD (Liquid Crystal Display), GLV (Grating Light Valve), LED (Light Emitting Diode), and FED (Field Emission Display). A direct-view display, a projector, or the like that can draw an image by a dot-sequential or line-sequential scanning method can be used.

  For example, GLV is an image display technique using a microribbon array, which is a projection device that controls the direction and color of light using the diffraction effect of light. A microribbon array is an array of very small light diffraction elements arranged in a line. In the GLV, an image is projected by applying a laser beam to the array. The ribbon can be driven independently by an electrical signal, and the amount of light diffraction can be changed by adjusting the drive amount, and the brightness of the image can be created by the difference of each ribbon, so smooth gradation expression and High contrast can be realized.

  An LED is an element generated by joining two types of semiconductors, and can emit light by applying a current.

  The FED can obtain an image by the same light emission principle as the CRT in which electrons are taken out from the cathode and collided with a phosphor applied to the anode to emit light. However, as the cathode structure, the CRT uses a point electron source, while the FED uses a planar electron source.

  By the way, the moving image has a moving image-specific image quality degradation that does not occur in the still image. Currently, the most widely used displays of 50 Hz (PAL: Phase Alternating Line) and 60 Hz (NTSC: National Television System Committee and HD (High Definitions) video signal) have incomplete reproduction in the time direction and have specific conditions. Since the imperfection in the time direction is converted into the imperfection in the spatial direction below, for example, a shutter time when moving image data is acquired, a display element light emission time when moving image data is displayed, and a person Depending on the line-of-sight condition, the quality of the moving image may deteriorate.

  FIG. 16 shows an example of an actual scene in which a moving object and a fixed object coexist. This scene assumes that the car is moving to the right and the tree is fixed to the ground. FIGS. 17 and 18 show the appearance of the observer when the scene of FIG. 16 is observed.

  FIG. 17 is a diagram illustrating the appearance of an image from the observer when the observer is gazing at the tree. In this case, the vehicle moving in the right direction appears to be blurred from the observer. On the other hand, FIG. 18 is a diagram showing the appearance of the video from the observer when watching the car. In this case, the fixed tree appears blurred to the observer.

  Hereinafter, the case where the line of sight is fixed to a fixed object on the observation plane coordinates is referred to as a fixed visual condition, and the case where the line of sight follows a moving object on the observation plane coordinates is referred to as a tracking visual condition. That is, the case described with reference to FIG. 17 is the fixed viewing condition, and the case described with reference to FIG. 18 is the following viewing condition. In both fixed vision and following vision conditions, what you are watching looks clear. On the other hand, the object being watched and the object whose relative position changes appear blurred.

  This is because a human has a function of integrating light incident on the retina within a certain time as a visual characteristic. An object moving on the retina coordinates of the eye is perceived as a blurred image as a result of the change in position being integrated in the time direction. This blur increases in proportion to the moving speed on the retina coordinates. The moving speed on the retina coordinates is not an actual object speed but an angular speed (deg / sec).

  As described above, an object that is stationary on the retinal coordinates appears clear, and an object that moves on the retinal coordinates appears blurred. It is important to reproduce a video that matches the actual appearance in order to display a realistic moving image, that is, a moving image with high image quality that seems to move smoothly.

  The difference in the appearance of the observer described with reference to FIGS. 17 and 18 will be described with reference to FIG. The upper part of FIG. 19 shows the actual movement in the outside world. The vertical axis is the time axis, and the horizontal axis is the horizontal direction. Fixed dots (corresponding to trees in FIGS. 16 to 18 and indicated by x in the figure) and dots moving at a constant speed (FIGS. 16 to FIG. 18 corresponds to the car in FIG. 18 and shows the position of each dot for each time in a scene where there is a symbol y). The lower part of FIG. 19 shows the appearance in fixed vision and follow-up vision when observing the movement of the outside world. An arrow indicated by a dotted line indicates the movement of the observer's viewpoint, that is, the integration direction of the image on the retina. The vertical axis is the fixed view, and the oblique axis is the integration direction in the follow-up view. That is, when the observer is following, fixed dots (trees) appear blurred, but moving dots (cars) appear clear. On the other hand, when the observer is fixing, fixed dots (trees) appear clear, but moving dots (cars) appear blurred.

  Next, the appearance of the observer when the external movement shown in FIG. 16 is fixedly photographed and reproduced and displayed as a moving image will be described for each photographing condition, display condition, and observation condition with reference to FIG. The upper part of FIG. 20 shows the time change of moving image display. The lower part of FIG. 20 shows the result of integrating the light displayed in the moving image along the direction of movement of the line of sight in fixed vision and follow-up vision, that is, along the integration axis direction, as the appearance of the observer.

  20A shows a case where the shooting condition is an open shutter method and the display is a pulse type, FIG. 20B shows a case where the shooting condition is an open shutter method and a display is a hold type, and FIG. When the display is a pulse type, FIG. 20D shows the appearance of the observer when the imaging condition is a high-speed shutter method and the display is a hold type.

  20A to 20D, it can be seen that the moving image quality degradation that occurs varies depending on each condition. For example, compared with the appearance of the moving object in the tracking view of FIGS. 20A and 20C, the moving object in the tracking view of FIGS. This is a phenomenon called “motion blur”. “Motion blur” is an easy-to-understand degradation for the observer because the subject is blurred.

  In addition, deterioration such as strobe interference in the fixed vision of FIG. 20D and strobe interference in the tracking vision of FIGS. 20A and 20C occurs. As shown in FIG. 21, the strobe failure means that when a fixed object (for example, a tree) on a display is fixedly viewed, a moving object (for example, a car) looks like a multiple image or is not smooth. It is a degradation of the video quality such that there is no discrete motion. In this way, strobe obstructions that occur on moving objects in fixed vision and fixed objects in tracking vision are often deterioration that occurs in parts that are not the subject of gaze, compared to motion blur. Often not very noticeable. However, when the tracking of the line of sight is not performed completely, the relationship between the object to be watched and the line of sight is the same as a moving object in fixed vision or a fixed object in tracking vision. In this case, the strobe interference occurs in the object being watched, so that the deterioration becomes very conspicuous. This phenomenon is conspicuous in video sources that move quickly and the next movement is difficult to predict, such as sports broadcasts and action movies. In capturing moving images in movies and the like, for example, in order to prevent such moving image quality deterioration, for example, when shooting a moving object, follow the camera and shoot, and on the display screen, In order to suppress strobe interference, a technique such as adding blur called motion blur is used. However, the limitation by these methods also results in narrowing the expression means. In sports and the like, these means cannot be used because it is impossible to predict the movement of the subject to be noticed.

  Such degradation of moving image quality increases according to the angular velocity of the moving object. Therefore, even in the same video scene, when a moving image is displayed on a display with a larger viewing angle, the moving image quality is significantly degraded. Also, even with higher resolution, the video quality degradation described in this chapter is hardly improved. On the contrary, since the still image quality is further improved by increasing the resolution, the moving image quality is conspicuous. In the future, as the display becomes larger and higher in definition, it is expected that the deterioration of the moving image quality will become a big problem.

  The cause of video quality degradation is lack of time reproducibility. Therefore, improving the time reproducibility is a fundamental solution. That is, as a means for solving the problem, it is effective to increase the frame rate for both photographing and display.

  FIG. 22 shows improvement in the degradation of moving image quality when moving image data in the case described with reference to FIG. 20 is captured at a double frame rate and displayed at a double frame rate.

  22A shows a case where the shooting condition is an open shutter method and the display is a pulse type, FIG. 22B shows a case where the shooting condition is an open shutter method and a display is a hold type, and FIG. When the display is a pulse type, FIG. 22D is displayed at a frame rate twice that of the case described with reference to FIG. 20 when the shooting condition is a high-speed shutter method and the display is a hold type. The appearance of the observer with respect to the moving image is shown.

  As shown in FIGS. 22A to 22D, the blur amount is halved in each imaging and display method with respect to the blurring of the appearance of the display image. Also, with regard to strobe interference, the number of strobe-like discretes doubles, so image degradation is improved. That is, blur disturbance and strobe disturbance are shown to be improved linearly with increasing frame rate. Further, when the frame rate is increased, the difference in quality of moving image quality deterioration due to the shutter time and the light emission time is also reduced. That is, it can be said that increasing the frame rate is a very effective means for improving the moving image quality.

  Next, regarding the display of moving images taken with an open shutter, the evaluation of moving image quality focusing on jerkiness and motion blur under the following vision conditions was investigated by visual psychophysical experiments.

  FIG. 23 shows an evaluation result focusing on jerkiness, and FIG. 24 shows an evaluation result focusing on motion blur. In this evaluation, various types of moving images, such as natural moving images, CG movements, and images shot with an open shutter, were prepared. In addition, as for the evaluation point, regarding the deterioration scale, “I don't know deterioration” is evaluation 5, “I understand deterioration but I do n’t care” is evaluation 4, “I understand deterioration but do n’t get in the way” is evaluation 3, “Deterioration is obstructive” Becomes "Evaluation 2", "Deterioration is very disturbing" is evaluation 1, and the evaluation scale is "Very good" is evaluation 5, "Good" is evaluation 4, "Normal" is evaluation 3, “Poor” was rated 2, and “Very bad” was rated 1. In this experiment, evaluation is performed by a sufficient number of subjects to investigate general evaluation of moving image quality. In FIGS. 23 and 24, the average and standard deviation of all scenes and subjects are plotted.

  Compared with the jerkiness shown in FIG. 23, the evaluation value of the motion blur shown in FIG. 24 is large, and in common with both, the evaluation value of the moving image quality increases as the frame rate increases. There is a trend. In particular, with regard to motion blur, an evaluation value of around 4.5, which is a perceptual limit, was reached at around 250 fps, and at a higher frame rate, the evaluation value was 4.5 or more, showing a flat tendency that showed a flat value. In addition, with regard to jerkiness, an evaluation value of 4.5 is reached near 250 fps, and the evaluation value is 4.5 or more at a higher frame rate. It was.

  As described above, the motion blur in the follow-up vision that shows particularly noticeable video quality degradation is sufficiently solved by the frame rate near 250 fps, that is, the vicinity of 250 fps is considered in view of the effectiveness of the currently widely used video resources. It is suggested that this is the ideal frequency. Specifically, as described above, there are many video resources that are widely used at present, such as 50 Hz and 60 Hz. Therefore, 240 Hz and 250 Hz, which are integer multiples thereof, are considered when the effectiveness of video resources is considered. This suggests an ideal frequency.

  Next, image display processing 1 when the image signal processing device 51 and the image display device 52 of FIG. 9 are used will be described with reference to the flowchart of FIG.

  In step S21, the controller 62 reads out the frame image data from the frame memories 61-1 to 61-n of the memory 61, for example, at the predetermined timing described with reference to FIGS. / A converter 65-1 to D / A converter 65-n.

  In step S22, the D / A conversion unit 65-1 through D / A conversion unit 65-n performs D / A conversion on the supplied frame image data, and scan control unit 81-1 through scan control unit 81-. n.

  In step S23, the scanning control unit 81-1 to the scanning control unit 81-n, for example, based on the control of the display control unit 66, for example, a predetermined timing corresponding to the output video signal described with reference to FIGS. Then, each pixel of each frame image data is scanned and displayed, and the process is completed.

  By such processing, moving image data divided into n and each having a frame rate of mHz is converted into a moving image of (n × m) Hz by n operation control units 81-1 to 81-n. Displayed as data.

  In the above description, the case where (n × m) Hz moving images are displayed by scanning the n-divided frame image data of each mHz by shifting 1 / n the number of scanning lines on the display screen has been described. , N-divided frame image data of mHz may be displayed after being combined into a number smaller than n.

  That is, if the shutter open time at the time of capturing each frame image data is shorter than 1 / s × m, then each n Hz divided frame image data is converted to n / s series frame image data. After that, even if the n / s operation control units 81 are used for display, the moving image data is not blurred.

  FIG. 26 is a block diagram showing configurations of the image signal processing apparatus 101 and the image display apparatus 52 to which the present invention is applied. In FIG. 26, a case where n = 4 and s = 2 will be described.

  Note that portions corresponding to those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The image signal processing apparatus 101 is individually supplied with 4 series of moving image data of mHz each having a phase shift of 1 / n constituting image data of a frame rate of (m × n) Hz, and the memory 61 Are supplied to and held in the frame memories 61-1 to 61-4.

  The controller 111 receives images from the frame memories 61-1 to 61-4 based on the mHz reference synchronization signal supplied from the reference synchronization signal generation unit 64 in accordance with the user operation input input from the operation input unit 63. While controlling the output of the signal, information related to the output of the video signal from the frame memories 61-1 to 61-4 is supplied to the display control unit 66. The operation input unit 63 includes, for example, a jog dial, a key, a lever, a button, or a touch panel as well as a button for instructing display of a moving image. The operation input unit 63 receives an operation input by a user and supplies it to the controller 111. The reference synchronization signal generation unit 64 generates a synchronization signal serving as a reference for the controller 111 to control the plurality of frame memories 61-1 to 61-4 of the memory 61, and supplies the synchronization signal to the controller 111.

  The frame memory 61-1 and the frame memory 61-2 of the memory 61 supply the supplied digital image signals S1 and S2 to the signal processing unit 112-1 based on the control of the controller 111. The frame memory 61-3 and the frame memory 61-4 of the memory 61 supply the supplied digital image signals S3 and S4 to the signal processing unit 112-2 based on the control of the controller 111. The signal processing unit 112-1 and the signal processing unit 112-2 synthesize the supplied image signals, and the synthesized image signals S5 and S6 are converted into a D / A conversion unit 65-1 and a D / A conversion unit 65-. Output to 2. Details of signal synthesis executed by the signal processing unit 112-1 and the signal processing unit 112-2 will be described later with reference to FIG.

  The D / A conversion unit 65-1 and the D / A conversion unit 65-2 convert the digital image signal supplied from the signal processing unit 112-1 and the signal processing unit 112-2 into an analog image signal, This is supplied to the scanning control unit 81-1 and the scanning control unit 81-2 of the image display device 52. The display control unit 66 controls the display of moving images by the image display device 52 based on the information supplied from the controller 111, and displays a frame image with a frame rate of (m × n) Hz.

  Here, the frame rate of the moving image data supplied to the scan control unit 81-1 and the scan control unit 81-2 is 2 mHz, respectively. The scanning control unit 81-1 and the scanning control unit 81-2 have a function of displaying moving image data having a frame rate of 2 mHz with the number of pixels of the supplied frame image data (functions such as data processing and scanning speed). If not, the signal processing unit 112-1 and the signal processing unit 112-2 synthesize and output the image signal S5 so that it can be displayed by the scanning control unit 81-1 and the scanning control unit 81-2. For S6, appropriate image processing such as reduction in the number of pixels and thinning of the scanning lines is performed.

  In addition, a drive 67 is connected to the controller 111 as necessary, and a magnetic disk 71, an optical disk 72, a magneto-optical disk 73, a semiconductor memory 74, or the like is appropriately mounted, and a computer program read from them is It is executed by the controller 111 as necessary.

  27, the timing of image data read from the frame memories 61-1 to 61-4, and the signal processing unit 112-1 and the signal processing unit 112-2 when n = 4 and S = 2. A description will be given of the signal synthesis executed by.

  The controller 111 controls the frame memories 61-1 and 61-2, and outputs from the frame memory 61-1 an α frame having a frame rate m and a shutter speed of ½ m or less as an output video signal S1, as a signal processing unit 112-. 1, and the α + 2 frame at the frame rate m and the shutter speed of ½ m or less is delayed from the frame memory 61-2 by ½ m as the output video signal S2 from the α frame supply start time a. At the supply start time b, the signal processing unit 112-1 is supplied. Thereafter, the controller 111 alternately shifts the output signal S1 or the output signal S2 from the frame memories 61-1 and 61-2 and shifts the output signal S1 or the output signal S2 by 1 / 2m.

  The signal processing unit 112-1 combines the supplied signals to generate a combined signal S5 in which α + 2 frame continues 1 / 2m after α frame and further α + 4 frame 1 / 2m after α + 2 frame. / D converter 65-1.

  The controller 111 controls the frame memories 61-3 and 61-4, and outputs from the frame memory 61-3 an α + 1 frame having a frame rate m and a shutter speed of 1/2 m or less as an output video signal S3 as a signal processing unit 112- 2 and the α + 3 frame with the frame rate m and the shutter speed of ½ m or less from the frame memory 61-2 is delayed by ½ m from the supply start time a of the α + 1 frame as the output video signal S4. At the supply start time b, the signal processing unit 112-2 is supplied. Thereafter, the controller 111 alternately shifts the output signal S3 or the output signal S4 from the frame memories 61-1 and 61-2 and shifts it by 1 / 2m and supplies it to the signal processing unit 112-2.

  The signal processing unit 112-2 synthesizes the supplied signals, generates a combined signal S6 in which α + 3 frame continues 1 / 2m after α + 1 frame, and further α + 5 frame 1 / 2m after α + 1 frame. / D converter 65-2.

  Similarly to the output video signal S1 and the output video signal S2 described with reference to FIG. 10, the A / D conversion unit 65-1 and the A / D conversion unit 65-2 are each shifted by ½ m. The combined signal S5 and the combined signal S6 are supplied to the scanning control unit 81-1 and the scanning control unit 81-2. The scan control unit 81-1 and the scan control unit 81-2 are shifted by half the number of lines in one frame, alternately scan the frame image signal, and display the moving image data on the display unit 82.

  For example, when the output signals S1 to S4 are each 60 Hz, the combined signals S5 and S6 are each 120 Hz. Therefore, when the scanning control unit 81-1 and the scanning control unit 81-2 have a function of displaying 120 Hz moving image data, it is possible to display 240 Hz moving image data.

  In FIGS. 26 and 27, the case where n = 4 and s = 2 has been described, but it goes without saying that the present invention can be applied even when n or s have different values.

  For example, the case where n = 4 and s = 4 will be described with reference to FIGS.

  FIG. 28 is a block diagram showing the configuration of the image signal processing device 121 and the image display device 52 to which the present invention is applied.

  Note that portions corresponding to those in FIG. 26 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The image signal processing device 121 is individually supplied with 4 series of moving image data of mHz each having a phase shift of 1 / n constituting image data of a frame rate of (m × n) Hz, and the memory 61 Are supplied to and held in the frame memories 61-1 to 61-4.

  Based on the mHz reference synchronization signal supplied from the reference synchronization signal generator 64 in accordance with the user's operation input input from the operation input unit 63, the controller 131 outputs the video from the frame memories 61-1 to 61-4. While controlling the output of the signal, information related to the output of the video signal from the frame memories 61-1 to 61-4 is supplied to the display control unit 66. The operation input unit 63 includes, for example, a jog dial, a key, a lever, a button, or a touch panel as well as a button for instructing display of a moving image. The operation input unit 63 receives an operation input by a user and supplies the input to the controller 131. The reference synchronization signal generation unit 64 generates a synchronization signal that serves as a reference for the controller 131 to control the plurality of frame memories 61-1 to 61-4 of the memory 61, and supplies the synchronization signal to the controller 131.

  The frame memories 61-1 to 61-4 of the memory 61 supply the supplied digital image signals S1 to S4 to the signal processing unit 132 based on the control of the controller 131. The signal processing unit 132 combines the supplied image signals and outputs the combined image signal S5 to the D / A conversion unit 65-1. Details of signal synthesis performed by the signal processing unit 132 will be described later with reference to FIG.

  The D / A conversion unit 65-1 converts the digital image signal supplied from the signal processing unit 132 into an analog image signal and supplies the analog image signal to the scanning control unit 81-1 of the image display device 52. The display control unit 66 controls the display of moving images by the image display device 52 based on the information supplied from the controller 131, and displays a frame image at a frame rate of (m × n) Hz.

  Here, the frame rate of the moving image data supplied to the scanning control unit 81-1 is 4 mHz, respectively. When the scanning control unit 81-1 does not have a function (data processing, a function such as a scanning speed) to display moving image data having a frame rate of 4 mHz with the number of pixels included in the supplied frame image data, a signal The processing unit 132 performs appropriate image processing such as a reduction in the number of pixels or thinning out of the scanning lines on the image signal S5 that is combined and output so that it can be displayed by the scanning control unit 81-1. Apply.

  A drive 67 is connected to the controller 131 as necessary, and a magnetic disk 71, an optical disk 72, a magneto-optical disk 73, a semiconductor memory 74, or the like is appropriately mounted, and a computer program read from them is It is executed by the controller 131 as necessary.

  The timing of image data read from the frame memories 61-1 to 61-4 and the signal synthesis executed by the signal processing unit 132 when n = 4 and S = 4 will be described with reference to FIG. .

  The controller 131 controls the frame memories 61-1 and 61-2 and outputs from the frame memory 61-1 an α frame with a frame rate m and a shutter speed of ¼ m or less to the signal processing unit 132 as an output video signal S 1. Supply from the frame memory 61-2 is started by delaying the α + 1 frame at the frame rate m and the shutter speed of 1/4 m or less as the output video signal S2 by 1/4 m from the α frame supply start time a. At time b, the signal processing unit 132 is supplied, and from the frame memory 61-3, an α + 2 frame with a frame rate m and a shutter speed of ¼ m or less is set as an output video signal S3, and from the supply start time a of the α + 1 frame, The signal is supplied to the signal processing unit 132 at the supply start time c delayed by 1/4 m, and the frame memory 61 -4, the signal processing is performed at a supply start time d delayed by ¼ m from the supply start time a of the α + 2 frame, as an output video signal S4, with α + 3 frames having a frame rate m and a shutter speed of ¼ m or less. To the unit 132. Thereafter, the controller 111 sequentially reads out the output signals S1 to S4 from the frame memories 61-1 to 61-4 and shifts them by ¼ m and supplies them to the signal processing unit 132.

  The signal processing unit 112-1 synthesizes the supplied signals to generate a combined signal S5 in which α + 1 frame continues after 1/4 m of α frame, and further, α + 2 frame continues after 1/4 m of α + 1 frame. / D converter 65-1.

  The A / D conversion unit 65-1 supplies the combined signal S5 to the scanning control unit 81-1. The scan control unit 81-1 scans the frame image signal and causes the display unit 82 to display moving image data.

  For example, when the output signals S1 to S4 are each 60 Hz, the combined signal S5 is 240 Hz. Therefore, if the scanning control unit 81-1 does not have a function of displaying moving image data of 240 Hz in terms of the number of pixels of the frame image data supplied or the number of scanning lines, the signal processing unit 112-1 is appropriate. By performing the thinning process and the pixel number conversion (decrease) process on the synthesized signal S5, it is possible to display the 240 Hz moving image data on the scanning control unit 81-1.

  For example, when n = 5 and the output signals S1 to S5 are each 50 Hz, the combined signal is 250 Hz. Therefore, when the scanning control unit 81-1 does not have a function of displaying moving image data of 250 Hz in terms of the number of pixels of the frame image data supplied or the number of scanning lines, the signal processing unit 112-1 is appropriate. By performing the thinning process and the pixel number conversion (decrease) process on the combined signal S5, it is possible to display the moving image data of 250 Hz on the scanning control unit 81-1.

  Next, referring to the flowchart of FIG. 30, the image signal processing device 101 and the image display device 52 described with reference to FIG. 26 or FIG. 28, or the image signal processing device 121 and the image display device 52 are used. The image display process 2 will be described.

  In step S41, the controller 111 or the controller 131 sets the frame memory 61-1 to the frame memory 61-n of the memory 61 (n-4 in the case described with reference to FIG. 26 or FIG. 28, but n is other than 4). Therefore, for example, the frame image data is read at the predetermined timing described with reference to FIG. 27 or FIG. 29, and the signal processing unit 112-1 to the signal processing unit are read out. 112-t (where t = n / s) or supplied to the signal processing unit 132.

  In step S42, the signal processing unit 112-1 to signal processing unit 112-t or the signal processing unit 132 combines the output signals as described with reference to FIG. 27 or FIG. 29, and performs scanning control as necessary. The image data is converted into image data that can be displayed by the units 81-1 to 81-t (where t = n / s) (for example, the number of pixels is reduced or the scanning line is thinned out). , D / A converter 65-1 to D / A converter 65-t (where t = n / s).

  In step S43, the D / A conversion unit 65-1 to D / A conversion unit 65-t performs D / A conversion on the supplied frame image data, and scan control unit 81-1 to scan control unit 81-. to t.

  In step S44, the scanning control unit 81-1 to the scanning control unit 81-t scan and display each pixel of each frame image data at a predetermined timing based on the control of the display control unit 66. Is terminated.

  By such processing, the n-divided moving image data is combined with the n / s sequence moving image data, and then n / s operation control units 81-1 to 81-t (here, , T = n / s), it is displayed as moving image data of (n × m) Hz.

  Further, the image signal synthesized by an external device may be received and displayed.

  In FIG. 31, for example, the combined signal S5 combined by the processing of the signal processing unit 132 in FIG. 2 is a block diagram showing the configuration of an image signal processing device 141 and an image display device 52 that can be used.

  Note that portions corresponding to those in FIG. 28 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The image signal processing device 151 is supplied with moving image data constituting image data having a frame rate of (m × n) Hz and is held in the frame memory 61-1.

  The controller 151 outputs the video signal from the frame memory 61-1 based on the mHz reference synchronization signal supplied from the reference synchronization signal generation unit 64 in accordance with the user operation input input from the operation input unit 63. In addition to the control, information relating to the output of the video signal from the frame memory 61-1 is supplied to the display control unit 66. The operation input unit 63 is configured with, for example, a jog dial, a key, a lever, a button, a touch panel, or the like including a button for instructing display of a moving image, and receives an operation input by a user and supplies the operation to the controller 151. The reference synchronization signal generator 64 generates a synchronization signal that serves as a reference for the controller 151 to control the frame memory 61-1 and supplies it to the controller 151.

  The frame memory 61-1 supplies the supplied digital image signal to the signal processing unit 152 based on the control of the controller 151. The signal processing unit 152 performs signal processing on the supplied image signal and outputs it to the D / A conversion unit 65-1. Specifically, the frame rate of the moving image data supplied to the scanning control unit 81-1 is (n × m) Hz, and the scanning control unit 81-1 converts the moving image data at the frame rate (n × m) Hz. When the supplied frame image data does not have a function of displaying with the number of pixels, the signal processing unit 152 performs an output on the output image signal so that the scan control unit 81-1 can display the image signal. For example, appropriate image processing such as reduction in the number of pixels and thinning out of scanning lines is performed.

  The D / A conversion unit 65-1 converts the digital image signal supplied from the signal processing unit 152 into an analog image signal, and supplies the analog image signal to the scanning control unit 81-1 of the image display device 52. The display control unit 66 controls the display of moving images by the image display device 52 based on the information supplied from the controller 151, and displays a frame image having a frame rate of (m × n) Hz.

  A drive 67 is connected to the controller 151 as necessary, and a magnetic disk 71, an optical disk 72, a magneto-optical disk 73, a semiconductor memory 74, or the like is appropriately mounted, and a computer program read from them is It is executed by the controller 151 as necessary.

  Next, the image display processing 3 when the image signal processing device 141 and the image display device 52 described with reference to FIG. 31 are used will be described with reference to the flowchart of FIG.

  In step S61, the controller 151 reads frame image data from the frame memory 61-1 at a predetermined timing and supplies the frame image data to the signal processing unit 112-1.

  In step S <b> 62, the signal processing unit 112-1 performs processing (for example, reduction of the number of pixels, thinning processing of the scanning line, etc.) for conversion into image data that can be displayed by the scanning control unit 81-1 as necessary. Applied to the D / A converter 65-1.

  In step S63, the D / A conversion unit 65-1 performs D / A conversion on the supplied frame image data and supplies the frame image data to the scanning control unit 81-1.

  In step S64, the scanning control unit 81-1 scans and displays each pixel of each frame image data at a predetermined timing based on the control of the display control unit 66, and the process is terminated.

  By such processing, moving image data synthesized by an external device can be displayed smoothly.

  In the above, in order to display moving image data with a frame rate (n × m) Hz, moving image data with a frame rate m is acquired in an n sequence, and an n sequence or an n / s sequence obtained by synthesizing the n sequence. In the above description, the moving image data of the frame rate (n × m) Hz is displayed by sequentially shifting and moving the moving image data by a predetermined timing to display the moving image data. A method of acquiring moving image data at a frame rate (n × m) Hz by capturing images with a shift of 1 / n and expanding the display image in an n-fold space will be described.

  FIG. 33 is a block diagram illustrating a configuration of an imaging apparatus 171 to which the present invention is applied.

  Note that portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  As shown in FIG. 33, the imaging device 171 includes a lens 21, a CCD image sensor 181, a timing controller 24, a controller 183, a reference synchronization signal generator 26, a correlated double sampling processor 27, an A / D converter 28, and image processing. A unit 182, a codec processing unit 30, a memory 31, an operation input unit 32, and a drive 33.

  The CCD is a semiconductor element that converts light information into an electrical signal (photoelectric conversion). The CCD image sensor 181 includes a plurality of light receiving elements (pixels) that convert light into electricity, and changes in light for each pixel. A common single-plate type color filter having a single image pickup device that converts an electric signal independently, for example, a color filter such as a Bayer array in which color filters of three primary colors of RGB are arranged in a mosaic pattern This is a CCD image sensor. The color filter of each image sensor of the CCD image sensor 181 may be arranged other than the Bayer arrangement.

  The image pickup element of the CCD image sensor 181 is shifted by 1 / n of the pixel pitch as shown in FIG. 34 under the control of the timing controller 24 (in FIG. 34, n = 4 and 1/4 of the pixel pitch). Although the image is illustrated as being shifted, n may be any number other than 4), and the image information is acquired by shifting the timing by 1 / (m × n). Based on the control of the controller 25, the timing controller 24 generates a trigger signal obtained by delaying the mHz reference synchronization signal supplied from the reference synchronization signal generator 26 by 1 / (m × n) by the CCD image sensor 181. Supplied to the image sensor.

  Here, the description has been made on the assumption that the image sensor moves by 1 / n of the pixel pitch based on the timing signal generated by the timing controller 24. However, the timing signal generated by the timing controller 24 with the position of the image sensor fixed. Based on the above, the position of the optical system may be moved by 1 / n of the pixel pitch.

  Therefore, the frame rate of the frame image data captured by the CCD image sensor 181 is (m × n) Hz.

  In general, a pixel shifting means is used to compensate for the invalid portion of the light receiving unit in a CCD camera or the like, but these are used in a camera that captures images of the same time with a multi-plate image sensor, or at different times. It is used in a camera that picks up an image by vibrating a single image sensor or optical system (technique described in the above-mentioned CCD camera technology, Corona, 1997, PP109-111).

  However, there is no known example in which a technique corresponding to pixel shifting is applied as a configuration for capturing videos at different times. Here, the time resolution can be increased by imaging at different times. In addition, since either one of the image sensor or the optical system is fixed, a stable high resolution image can be obtained.

  The controller 183 is based on the user's operation input input by the operation input unit 32, the timing controller 24, the correlated double sampling processing unit 27, the A / D converter 28, the image processing unit 182, the codec processing unit 30, and the memory 31. And the operation input unit 32 is controlled.

  The image processing unit 182 is a block having a signal processing processor and an image RAM, and the signal processing processor performs pre-programmed image processing or hardware calculation on the image data stored in the image RAM. The image processing is configured as processing. Specifically, the pixel stream data is supplied at a constant rate, temporarily stored in the image RAM, and temporarily stored in the signal processing processor. For example, in addition to various types of image processing such as white balance adjustment, demosaic processing, matrix processing, gamma correction, and YC conversion, interpolation processing is performed on the data as necessary.

  Using FIG. 35 and FIG. Interpolation processing after pixel shifting imaging will be described.

  In FIG. 35, the ¼ pixels marked with the numbers shown in the figure are taken in the order of the numbers, and the ¼ pixels without the numbers mean that there is no data. is doing. In such image data, when the observer moves his / her line of sight in the pixel display direction at substantially the same speed as the pixel shift, that is, in the case of follow-up vision, the image appears discretely. In order to prevent the deterioration of the moving image quality, it is necessary to generate information on pixels that have not been acquired spatially from neighboring pixel information by linear or nonlinear interpolation.

  FIG. 36 shows data obtained by spatially interpolating each of the ¼ pixels not numbered in FIG. 35 and converting all the ¼ pixels to have data. Show. When these are fixed-viewed, that is, when the line of sight is fixed at one place on the screen, if the time frequency is sufficiently high, any of them can be viewed as a spatially continuous dense image due to the integral effect of the eyes.

  Therefore, image quality can be improved while maintaining the resolution in the time direction by performing image shifting with pixel shift and spatially interpolating and displaying.

  Next, the image acquisition process 2 executed by the imaging device 171 of FIG. 33 will be described with reference to the flowchart of FIG.

  In step S <b> 81, the timing controller 24 generates a timing signal for acquiring image data by shifting pixels based on the mHz reference synchronization signal generated by the reference synchronization signal generator 26, and supplies the timing signal to the CCD image sensor 181.

  In step S <b> 82, the CCD image sensor 181 acquires image data with a frame rate of (m × n) Hz by the pixel shift described with reference to FIG. 34 based on the timing signal supplied from the timing controller 24.

In step S <b> 83, the correlated double sampling processing unit 27, the A / D converter 28, the image processing unit 182, and the codec processing unit 30 obtain an image with a frame rate of (m × n) Hz acquired by the CCD image sensor 23. Image processing is performed on the data.
At this time, the image processing unit 182 performs image processing including interpolation processing as necessary.

In step S84, the memory 31 receives and stores the processed image, and the process ends.

  Through such processing, image data with a frame rate of (m × n) Hz is acquired and stored using a pixel shifting method.

  In addition, in order to obtain a high-resolution, high-frame-rate video, it is possible to separate the acquisition of luminance and color for each pixel for each frame and perform synthesis processing using inter-frame interpolation.

  FIG. 38 is a block diagram illustrating a configuration of an imaging apparatus 201 to which the present invention is applied.

  Note that portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  As shown in FIG. 38, the imaging apparatus 201 includes a lens 21, a prism 211, a CCD image sensor 212, a timing controller 24, a controller 214, a reference synchronization signal generation unit 26, a correlated double sampling) processing unit 27, and an A / D converter. 28, an image processing unit 213, a codec processing unit 30, a memory 31, an operation input unit 32, and a drive 33.

  As shown in FIG. 39, the prism 211 is configured by a prism beam splitter having a reflectance of 1 / n (here, n = 4) of light incident through the lens 21. The incident light is divided into n pieces and supplied to n image pickup devices 212-1 to 212-n of the CCD image sensor 212.

  The CCD image sensor 212 includes a plurality of light receiving elements (pixels) that convert light into electricity, and includes n imaging elements that convert light changes into electrical signals independently for each pixel. The CCD image sensor 212 includes n imaging elements, but is not a so-called double-plate CCD image sensor. For example, RGB primary color filters are arranged in a mosaic pattern for each light receiving element. A common single-plate CCD image sensor having a Bayer array color filter and the same number of light-receiving elements that acquire only luminance information without using a color filter. It is. The color filter of one image sensor of the CCD image sensor 212 may be arranged other than the Bayer arrangement.

  Each image sensor of the CCD image sensor 212 acquires image information at a timing shifted by 1 / (n × m) seconds under the control of the timing controller 24. The timing controller 24, based on the control of the controller 214, captures a trigger signal obtained by delaying the reference synchronization signal supplied from the reference synchronization signal generator 26 by 1 / (n × m) seconds, and the image sensor of the CCD image sensor 212. Supplied to 212-1 through 212-n.

  Based on the user's operation input input by the operation input unit 32, the controller 214 includes a timing controller 24, a correlated double sampling processing unit 27, an A / D converter 28, an image processing unit 213, a codec processing unit 30, and The memory 31 is controlled. The reference synchronization signal generator 26 generates a synchronization signal that serves as a reference for the timing controller 24 to control a plurality of image sensors of the CCD image sensor 212 and supplies the synchronization signal to the timing controller 24.

  With reference to FIG. 40, a description will be given of a mechanism for separating the acquisition of luminance and color for each pixel for each frame and obtaining a high-resolution, high-frame-rate video by using the inter-frame interpolation by the image processing unit 213.

  As an example, the color filter of 2 / n image sensors in the CCD image sensor 212 is 640 color pixels in RGB horizontal arrangement (1 pixel in RGB), and the remaining 2 / n image sensors are luminance. Consider a case where only information is acquired (horizontal 1920 monochrome pixels). An image sensor having a color filter is equivalent to a horizontal 640 × 3 = 1920 monochrome pixel as the scale of the image sensor. As the image quality, 1920 color pixels are ideal, but it is assumed that only the above-described image sensor can be used.

  For example, when the number of image sensors is four (n = 4), the first and third horizontal 640 color pixels and the second and fourth horizontal 1920 monochrome pixels are assigned in order of photographing. The image processing unit 213 creates a frame-interpolated image by interpolation processing from the image signals corresponding to the acquired second and fourth monochrome images. Then, the image processing unit 213 generates a monochrome image of horizontal 640 pixels in which the luminance is extracted by the calculation process of (R + G + B) / 3 from the image signal corresponding to the third color image acquired next. Then, the image processing unit 213 normalizes and multiplies the value of the corresponding one pixel by the value of the corresponding three pixels of the frame interpolation image, and generates a horizontal 1920 pixel monochrome image.

  This process corresponds to increasing the resolution of the luminance gradient three times without changing the luminance of each pixel of the video imaged using the color filter. By repeating the same procedure, a continuous monochrome image of 1920 pixels can be acquired. Next, color information is given to them. Since the color information has been acquired by the first and third imaging processes, this information is applied to the first and third horizontal 1920-pixel monochrome images.

  That is, assuming that the monochrome image value is Ymono, the color information is Rorg, Gorg, and Borg, respectively, and the new high-resolution RGB values after composition processing are Rnew, Gnew, and Bnew, respectively, the high-resolution RGB values Rnew , Gnew, Bnew are obtained by the following equations (1) to (3).

Rnew = Ymono * Rorg / (Rorg + Gorg + Borg) (1)
Gnew = Ymono * Gorg / (Rorg + Gorg + Borg) (2)
Bnew = Ymono * Gorg / (Rorg + Gorg + Borg) (3)

  The video signal obtained in this way is a video reflecting the resolution for three times the luminance without changing the balance of the three colors. Then, color information may be assigned to the second and fourth horizontal 1920 monochrome pixel images in the same manner.

  Here, in order to obtain each pixel data with high accuracy, there is a method in which a frame interpolation image is generated from an interpolated image of a color image, and a color image having a triple density is created by the above-described method using the color information. However, for example, in consideration of improvement in calculation cost, the first and third color information may be used as they are.

  When the first and third color information are used as they are, only the color information has a time frequency of ½ in the time direction, and the color information in the follow-up view is halved as a moving image. However, as shown in FIG. 41, for human vision, color information has a contrast sensitivity function lower than luminance information for an object having a normal spatial frequency. In other words, since color information has a property that blur is difficult to perceive for human vision, degradation of moving image quality can be suppressed low by increasing the time frequency of luminance information.

  In this way, high video quality can be obtained with limited video resources.

  It should be noted that the present invention is applicable to any color filter array other than the RGB horizontal array described above (for example, Bayer array, primary color four-color array, complementary color three-color array, complementary color four-color array, etc.). It goes without saying that it is possible.

  Next, the image acquisition process 3 executed by the imaging device 171 of FIG. 33 will be described with reference to the flowchart of FIG.

  In step S <b> 101, the prism 211 divides the light incident through the lens 21 into n and supplies the light to the two image pickup devices 212-1 to 212-n of the CCD image sensor 212.

  In step S102, the timing controller 24 supplies the mHz reference synchronization signal supplied from the reference synchronization signal generator 26 to the CCD image sensor 212, and the CCD image sensor 212 sets n based on the mHz reference synchronization signal. Image data having color information and image data having luminance information are respectively acquired by any one of the image pickup elements 212-1 to 212-n.

  In step S103, the correlated double sampling processing unit 27, the A / D converter 28, the image processing unit 213, and the codec processing unit 30 perform the mHz frame rate image data acquired by the CCD image sensor 212 on the image data. Perform image processing. At this time, the image processing unit 213 performs image processing including the composition processing described with reference to FIG.

  In step S104, the memory 31 receives and stores the processed image, and the process ends.

  By such processing, high moving image quality can be obtained with limited video resources.

  The series of processes described above can also be executed by software. The software is a computer in which the program constituting the software is incorporated in dedicated hardware, or various functions can be executed by installing various programs, for example, a general-purpose personal computer For example, it is installed from a recording medium.

  As shown in FIG. 1, FIG. 9, FIG. 26, FIG. 28, FIG. 31, FIG. 33 and FIG. 38, this recording medium is distributed to provide a program to the user separately from the computer. Magnetic disk 41 or 71 (including flexible disk), optical disk 42 or 72 (including compact disk-read only memory (CD-ROM), DVD (digital versatile disk)), magneto-optical disk 43 or 73 (MD (Including Mini-Disk) (trademark)) or a package medium made of semiconductor memory 44 or 74.

  Further, in the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.

  In the present specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

  1 imaging device, 22 prism, 23 CCD image sensor, 24 timing controller, 25 controller, 26 reference synchronization signal generator, 51 image signal processor, 52 image display device, 61 memory, 62 controller, 64 reference synchronization signal generator, 66 display control unit, 81 operation control unit, 82 display unit, 91 projector, 92 screen, 101 image signal processing device, 111 controller, 112 signal processing unit, 121 image signal processing device, 131 controller, 132 signal processing unit, 141 image Signal processing device 151 controller 152 signal processing unit 171 imaging device 181 CCD image sensor 182 image processing unit 183 controller 201 imaging device 211 Rhythm, 212 CCD image sensor, 213 an image processing unit, 214 controller

Claims (3)

An image processing device for processing an image signal;
In an image display system configured with an image display device that displays an image corresponding to the image signal processed in the image processing device,
The image processing apparatus includes:
storage means for storing the image signal at a first frame rate of mHz;
Output control means for controlling the output of the image signal stored by the storage means;
Display control means for controlling display of the image corresponding to the image signal whose output is controlled by the output control means, and
The image display device includes:
A plurality of image display processing means for drawing the image in a dot sequential or line sequential manner;
Display means for displaying the image drawn by the image display processing means,
At least n image display processing means are provided,
The output control means controls the output of the image signal at the first frame rate so that the image display processing means is sequentially output from the storage means every n frames.
The display control means causes the output control means to display the n images so that the image is displayed on the image display device at a second frame rate that is a frame rate n times the first frame rate. Corresponding to the image signals so that the image signals sequentially output to the display processing means are sequentially drawn by a dot-sequential or line-sequential method with a shift of 1 / (m × n) of the scanning time of one frame. Controlling the display of the image. An image processing device for processing an image signal;
In an image display system configured with an image display device that displays an image corresponding to the image signal processed in the image processing device,
The image processing apparatus includes:
storage means for storing the image signal at a first frame rate of mHz;
Output control means for controlling the output of the image signal stored by the storage means;
Display control means for controlling display of the image corresponding to the image signal whose output is controlled by the output control means, and
The image display device includes:
A plurality of image display processing means for drawing the image in a dot sequential or line sequential manner;
At least n image display processing means are provided,
The output control means controls the output of the image signal at the first frame rate so that the image display processing means is sequentially output from the storage means every n frames.
The display control means causes the output control means to display the n images so that the image is displayed on the image display device at a second frame rate that is a frame rate n times the first frame rate. Corresponding to the image signals so that the image signals sequentially output to the display processing means are sequentially drawn by a dot-sequential or line-sequential method with a shift of 1 / (m × n) of the scanning time of one frame. Controlling the display of the image. The image display system according to claim 2, wherein the image display device includes a projector that projects and displays the image.

Images