JP2009104387A - Test data generating program, test data generating device, and test data generating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test data generating program, a test data generating device, and a test data generating method, capable of improving exhaustiveness in validation for logic verification. <P>SOLUTION: A computer comprises a first test pattern storage means for storing test patterns generated by a user, a random pattern generating means for sequentially generating random test patterns, a second test pattern storage means for storing the random test patterns, and a pattern control means which monitors matching with a test pattern at the top of test patterns stored in a storage means by the first and second test pattern storage means, and if agreement is detected, outputs test patterns in the order specified in the test patterns, and if no agreement is detected, outputs the test patterns stored in the storage means by the second test pattern storage means in the order of storing. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a test data generation program, a test data generation apparatus, and a test data generation method, and more particularly to a test data generation program, a test data generation apparatus, and a test data generation method for generating test data of an integrated circuit.

  In recent years, LSIs (Large Scale Integration) used in electronic devices and the like have been integrated on a larger scale, and their functions have become more complex than before. LSIs are generally designed with RTL (Register Transfer Level) description using HDL (Hardware Description Language). In LSI design, logic verification using a simulator or the like is performed in order to verify the correctness of the design.

  In the logic verification, it is necessary to verify all the contents of the designed LSI. Coverage is used as an index indicating how much the contents of the designed LSI are verified. There are several types of coverage, such as code coverage, function coverage, and state (transition) coverage.

  The code coverage represents how much the RTL source code is covered. The function coverage represents how much the LSI functions are covered. The state (transition) coverage represents how much the state and state transition in the LSI are covered.

  In recent complicated LSIs, it is difficult to achieve 100% coverage, but there are many bugs lurking in the parts that could not be covered (cannot be verified) and cannot be overlooked. For this reason, it has become necessary to devise test data and design in order to improve coverage (verification comprehensiveness) in recent LSIs with various complexity.

  In recent years, in order to improve the coverage of verification, in addition to verification performed by creating test data from verification items created by the person in charge of verification (hereinafter referred to as direct verification), the test data is generated randomly. Verification (hereinafter referred to as random verification) has come to be used.

Conventionally, in LSI logic verification, there are a method for performing only direct verification, a method for performing only random verification, and a method for sequentially performing both direct verification and random verification. For example, Patent Document 1 discloses a verification support method including a selector for selecting either a basic pattern generation unit or a priority pattern generation unit, which is an invention relating to test pattern creation.
JP 2007-188443 A

  However, conventionally, in the logic verification of LSI, regardless of which of the method of performing only direct verification, the method of performing only random verification, and the method of sequentially performing both direct verification and random verification, coverage is used. It was difficult to make 100% (or close to 100%).

  For example, consider logic verification of a state transition (state machine) in an LSI in which a state transition “transition to state B when a specific condition is given in a certain arbitrary state” is designed. When the state transition in this LSI is to be logically verified using any one of a method for performing only direct verification, a method for performing only random verification, and a method for sequentially performing both direct verification and random verification. Had the following problems in terms of coverage.

  When only direct verification was performed, it was difficult to cover “any state”. When only random verification is performed, there is a problem that it is difficult to give a “specific condition”. When both direct verification and random verification are performed sequentially, it is difficult to cover the case where “a specific condition is given in an arbitrary state”.

  Note that Patent Document 1 performs a wide range of logical verifications with the basic pattern generated by the basic pattern generation unit while validating the validity of a certain function early with the priority pattern generated by the priority pattern generation unit. However, this does not solve the problem that it is difficult to cover the case where “a specific condition is given in an arbitrary state”.

  SUMMARY An advantage of some aspects of the invention is that it provides a test data generation program, a test data generation apparatus, and a test data generation method capable of improving the verification coverage in logic verification.

  In order to solve the above problems, the present invention provides a computer capable of accessing storage means, a first test pattern storage means for storing one or more test pattern groups created by a user in the storage means, and a random test. Random pattern generation means for sequentially generating patterns, second test pattern storage means for storing random test patterns generated by the random pattern generation means in the storage means, and storage means by the second test pattern storage means When the match between the stored test pattern and the test pattern at the head of the test pattern group stored in the storage means is monitored by the first test pattern storage means and a match is detected, the test pattern in which the match is detected The test patterns are arranged in the order of the test patterns defined for the group. If no match is detected, test data generation for causing the second test pattern storage means to function as pattern control means for outputting the test patterns stored in the storage means in the order of storage It is a program.

  In addition, what applied the component, expression, or arbitrary combination of the component of this invention to a method, an apparatus, a system, a computer program, a recording medium, a data structure, etc. is also effective as an aspect of this invention.

  As described above, according to the present invention, it is possible to provide a test data generation program, a test data generation device, and a test data generation method that can improve the verification coverage in logic verification.

  Next, the best mode for carrying out the present invention will be described based on the following embodiments with reference to the drawings. In this embodiment, an example in which an LSI test pattern is generated is described as an example of an integrated circuit. However, any integrated circuit that performs logic verification using a test pattern may be used.

  FIG. 1 is a configuration diagram of an example of a test data generation apparatus. The test data generation device is composed of an input device 11, an output device 12, a drive device 13, an auxiliary storage device 14, a main storage device 15, an arithmetic processing device 16, and an interface device 17 that are mutually connected by a bus B. .

  The input device 11 includes a keyboard and a mouse, and is used for inputting various signals. The output device 12 includes a display device and is used to display various windows and data. The interface device 17 is used to connect to an external device or network.

  The test data generation program of the present invention is at least a part of various programs that control the test data generation apparatus. The test data generation program is provided, for example, by distributing the recording medium 18 or downloading from the network. The recording medium 18 on which the test data generating program is recorded is a recording medium such as a CD-ROM, a flexible disk, a magneto-optical disk, etc. for recording information optically, electrically or magnetically, a ROM, a flash memory, etc. Various types of recording media such as a semiconductor memory for electrically recording information can be used.

  When the recording medium 18 on which the test data generation program is recorded is set in the drive device 13, the test data generation program is installed from the recording medium 18 to the auxiliary storage device 14 via the drive device 13. The test data generation program downloaded from the network is installed in the auxiliary storage device 14 via the interface device 17.

  The test data generation apparatus stores the installed test data generation program and stores necessary files, data, and the like. The main storage device 15 reads the test data generation program from the auxiliary storage device 14 and stores it. The arithmetic processing unit 16 implements various processes as will be described later in accordance with the test data generation program stored in the main storage unit 15. In the following embodiments, the test data generation program is called a test data generation module.

  FIG. 2 is an image diagram of an example of test data (test pattern) generated by the test data generation module. The test pattern generated by the test data generation module is basically a random test pattern, and the direct test pattern is interrupted at the timing described later. The direct test pattern is a test pattern created by a person in charge of verification. A plurality of direct test patterns can be defined, and priority can be set for each. The direct test pattern interrupts the random test pattern in order of priority. In the example of FIG. 2, the direct test pattern with priority 1 interrupts the random test pattern first, and the direct test pattern with priority 2 interrupts the random test pattern next.

  FIG. 3 is a configuration diagram of an example of the test data generation module. The test data generation module 20 in FIG. 3 includes a random pattern generation unit 21, a pattern control unit 22, an LSI I / F conversion unit 23, a pattern DB 24, and a direct DB 25.

  The random pattern generation unit 21 is realized by a random pattern generation function. The random pattern generation function generates a random test pattern and stores it in the pattern DB.

  The pattern control unit 22 is realized by a pattern control function. The pattern control function controls switching between the random test pattern and the direct test pattern, and outputs either the random test pattern or the direct test pattern to the LSI I / F conversion unit 23. The pattern control function outputs either a random test pattern or a direct test pattern at a timing based on a reception completion signal from the LSI to be verified. The reception completion signal indicates the timing for outputting either the random test pattern or the direct test pattern next.

  The LSI I / F conversion unit 23 is realized by an LSI I / F conversion function. Based on the transmission event from the pattern control unit 22, the LSI I / F conversion function receives either a random test pattern or a direct test pattern from the pattern control unit 22. The LSI I / F conversion function converts either the random test pattern or the direct test pattern received from the pattern control unit 22 according to the interface and timing of the LSI to be verified, and from outside the test data generation module 20. Output at timing based on the received clock.

  The pattern DB 24 is a database that stores a random test pattern generated by a random pattern generation function. The direct DB 25 is a database that stores the contents of the direct test pattern created by the person in charge of verification.

  FIG. 4 is a flowchart showing an outline of processing of the random pattern generation function. In step S1, the random pattern generation function sequentially generates random data values that satisfy a rule list described later. In step S2, the random pattern generation function stores sequentially generated random data values in the pattern DB 24 as test patterns. Note that the processing shown in the flowchart of FIG. 4 is repeated at a cycle that is extremely faster than the cycle of the reception completion signal described above.

  FIG. 5 is a flowchart showing an outline of processing of the pattern control function. First, the pattern control function proceeds to step S11 and enters a random state in which random verification is performed. The pattern control function retrieves test patterns from the pattern DB 24 in the oldest order (stored order) and outputs them as random test patterns. Note that when there are restrictions based on a rule list described later in the output of the random test pattern, the pattern control function outputs the random test pattern in consideration of the restrictions.

  In the random state, the pattern control function is used until the test pattern at the head of the direct test pattern (test pattern group) stored in the direct DB 25 matches any random test pattern stored in the pattern DB 24. Test patterns are searched from the pattern DB 24 in the oldest order, and output as random test patterns.

  On the other hand, in the random state, when the test pattern at the head of the direct test pattern stored in the direct DB 25 matches any random test pattern stored in the pattern DB 24, the pattern control function proceeds to step S12. In a direct state, direct verification is performed.

  In step S12, the test pattern is retrieved from the pattern DB 24 and output so that the pattern control function is in the order of the direct test patterns stored in the direct DB 25. The process of step S12 is performed in order from the test pattern at the beginning of the direct test pattern stored in the direct DB 25 to the test pattern at the end.

  When the process of step S12 reaches the test pattern at the end of the direct test pattern stored in the direct DB 25, the pattern control function returns to step S11 and enters a random state.

  FIG. 6 is a flowchart showing an outline of processing of the LSI I / F conversion function. In step S 21, the LSI I / F conversion function waits for a transmission event from the pattern control unit 22. When the transmission event from the pattern control unit 22 is received, the LSI I / F conversion function proceeds to step S22, and either the random test pattern or the direct test pattern received from the pattern control unit 22 is verified by the LSI to be verified. The data is converted according to the interface and timing, and transmitted at a timing based on the clock received from outside the test data generation module 20.

  FIG. 7 is an image diagram showing how the test data generation module generates a test pattern. In FIG. 7, the difference in the test pattern is represented by a color. FIG. 7 shows an example in which the contents of the direct test pattern with priority 1 and the contents of the direct test pattern with priority 2 are stored in the direct DB 25.

  The contents of the direct test pattern with priority 1 store test patterns red, orange, and yellow from the top. The contents of the direct test pattern with priority 2 store the test patterns green, white, and white from the top.

  The pattern DB 24 shown in FIG. 7A stores test patterns blue, purple, orange, white, and white in order from the oldest. In FIG. 7A, since there is no test pattern in the pattern DB 24 that matches the test pattern red at the head of the direct test pattern of priority 1 stored in the direct DB 25, the oldest stored in the pattern DB 24 is stored. The test pattern blue is output as a random test pattern.

  The pattern DB 24 shown in FIG. 7B stores the test patterns purple, orange, white, white, and red in order from the oldest. In FIG. 7 (2), the test DB stored in the pattern DB 24 is added to the pattern DB 24 because the test pattern red that matches the test pattern red at the head of the direct test pattern of priority 1 stored in the direct DB 25 is added. The pattern red is output as a direct test pattern.

  The pattern DB 24 shown in FIG. 7 (3) stores the test patterns purple, orange, white, white, and white in order from the oldest. In FIG. 7 (3), since there is a test pattern orange in the pattern DB 24 that matches the second test pattern orange of the direct test pattern of priority 1 stored in the direct DB 25, the test stored in the pattern DB 24 The pattern orange is output as a direct test pattern.

  The pattern DB 24 shown in FIG. 7 (4) stores test patterns purple, white, white, white, and yellow in order from the oldest. In FIG. 7 (4), the process waits until a test pattern yellow that matches the test pattern yellow at the end of the direct test pattern of priority 1 stored in the direct DB 25 is added to the pattern DB 24. 7 (4), when the test pattern yellow is added to the pattern DB 24, the test pattern yellow stored in the pattern DB 24 is output as a direct test pattern.

  The pattern DB 24 shown in FIG. 7 (5) stores the test patterns purple, white, white, white, and white in chronological order. In FIG. 7 (5), since the test patterns have already been output from the pattern DB 24 in the order defined in the direct test pattern with priority 1, the process moves to the direct test pattern with priority 2.

  In FIG. 7 (5), since there is no test pattern in the pattern DB 24 that matches the test pattern green at the head of the direct test pattern of priority 2 stored in the direct DB 25, the oldest stored in the pattern DB 24 is stored. The test pattern purple is output as a random test pattern.

  The pattern DB 24 shown in FIG. 7 (6) stores test patterns white, white, white, white, and green in order from the oldest. In FIG. 7 (6), the process waits until a test pattern green that matches the test pattern green at the head of the direct test pattern of priority 2 stored in the direct DB 25 is added to the pattern DB 24. 7 (6), when the test pattern green is added to the pattern DB 24, the test pattern green stored in the pattern DB 24 is output as a direct test pattern. Thereafter, the processing is continued in the same manner.

  The test data generation module 20 according to the present invention has a mechanism for shifting from random verification to direct verification when a randomly generated test pattern matches the test pattern at the head of the direct test pattern. Therefore, in the test data generation module 20 according to the present invention, a random test pattern is generated at a very high speed than the cycle of the test pattern required by the LSI to be verified, and stored in the pattern DB 24 at random. The generated test pattern is easily matched with the test pattern at the head of the direct test pattern (it is easy to shift to direct verification).

  Incidentally, it is inefficient to manually generate the test data generation module 20 for each type of LSI to be verified. Therefore, the test data generation module 20 according to the present invention is automatically generated using a module generation tool.

  FIG. 8 is a flowchart showing the generation procedure of the test data generation module using the module generation tool. The premise of the flowchart shown in FIG. 8 is as follows. The test data generation module 20 is generated by SystemC (C ++ class library for hardware description). After receiving the reception completion signal from the LSI, the test data generation module 20 transmits the next test pattern (either a random test pattern or a direct test pattern) to the LSI.

  The contents of the test pattern are virtual frame data. Also, 1 frame = 1 test pattern = 16 bit data. The LSI is a specification for receiving virtual frame data from the test data generation module 20. The LSI is a specification for transmitting a reception completion signal to the test data generation module 20 after receiving frame data from the test data generation module 20. The LSI is a specification in which an internal state transitions according to a frame data value.

  When generating the test data generation module 20, a configuration 31, a rule list 32, and a pattern list 33 that are inputs for generating the test data generation module 20 are generated.

  FIG. 9 is a configuration diagram of an example of the configuration. The configuration 31 is a file for setting various attributes of the test data generation module 20. For example, in the configuration 31, various attributes such as a test pattern generation module name, a frame size, the number of times of random frame data generation, an LSI clock frequency, an LSI I / F bit width, and an LSI I / F endian direction are set. Note that the LSI I / F endian direction indicates whether the frame data is transferred in order from the highest order or in order from the lowest order when the frame data is divided and transferred.

  FIG. 10 is a configuration diagram of an example of the rule list. The rule list 32 is a file for setting restrictions when there are restrictions on the contents of the test pattern in the LSI specifications. For example, the rule list 32 issues a test pattern value “0x0002” next to the test pattern value “0x00001”, prohibits the test pattern value “0xe000”, and sets the range of the test pattern value to “0x0000 to 0x7fff”. Etc. are set as restrictions.

  FIG. 11 is a configuration diagram of an example of a pattern list. The pattern list 33 is a file indicating a direct test pattern for direct verification created by a person in charge of verification. In the pattern list 33 of FIG. 11, a direct test pattern name (pattern_name), a priority (prio), and a test pattern value (data) are set. The pattern list 33 in FIG. 11 is set so that the direct test pattern includes one or more test pattern values that are determined in order.

  When the configuration 31 of FIG. 9, the rule list 32 of FIG. 10, and the pattern list of FIG. 11 are input, the module generation tool 30 generates the test data generation module 20 as described later.

  The generated test data generation module 20 is incorporated into an LSI logic verification environment (test bench) 40 as shown in FIG. 12, for example. FIG. 12 is a configuration diagram of an example of a test bench. An LSI 41 to be verified is connected to the test data generation module 20 in FIG. The signal monitor 42 is a module that monitors a signal output from the LSI 41. Since the signal monitor 42 is not directly related to the present invention, the description is omitted.

  The generated test data generation module 20 may be incorporated into an LSI logic verification environment (test bench) 50 as shown in FIG. 13, for example. FIG. 13 is a configuration diagram of another example of the test bench. An LSI 41 to be verified is connected to the test data generation module 20 in FIG. A reference model 51 is connected to the test data generation module 20. The reference model 51 is realized by software that performs the same operation as the LSI 41 to be verified. The same test pattern as that of the LSI 41 to be verified is input to the reference model 51.

  The signal checker 52 is a module that checks whether the signal output from the LSI 41 matches the signal output from the reference model 51. Since the signal checker 52 is not directly related to the present invention, the description thereof is omitted.

  In the example of FIG. 12, the test data generation module 20, the test bench 40, the LSI 41 to be verified, and the signal monitor 42 are compiled by the simulator, and the simulation is executed. A test pattern is generated and the LSI 41 to be verified can be logically verified.

  In the example of FIG. 13, the test data generation module 20, the LSI 41 to be verified, the test bench 50, the reference model 51, and the signal checker 52 are compiled by the simulator, and the simulation is executed. The test pattern as shown in FIG. 6 is generated, and the LSI 41 to be verified can be logically verified.

  FIG. 14 is a configuration diagram showing an internal image of the pattern DB. The pattern DB 24 of FIG. 14 has an index, data, and next data as data items. The index indicates that the smaller the value, the older. The data is a random test pattern value generated by a random pattern generation function. In the next data, when there is a restriction on the next test pattern value, a test pattern value with the restriction is set, and when there is no restriction, “−1” is set.

  FIG. 15 is a configuration diagram showing an internal image of the direct DB. A direct DB 25 in FIG. 15 represents an internal image of the direct DB 25 when the direct pattern in FIG. 11 is read. The direct DB 25 has an item number, an index, and data as data items.

  The item number represents the priority. The item number represents a higher priority as the value is smaller. The index represents the order of the test pattern from the smallest value. Data are test pattern values.

  FIG. 16 is a flowchart showing the processing of the random pattern generation function. In step S31, the random pattern generation function randomly generates data values. Proceeding to step S32, the random pattern generation function determines whether the previous test data value (previous data value) is “0x0001” and the data value generated in step S31 is not “0x0002”.

  If the previous data value is “0x0001” and the data value is not “0x0002”, the random pattern generation function sets “true” in the flag 1 and then proceeds to step S33. On the other hand, if the previous data value is “0x0001” and the data value is other than “0x0002”, the random pattern generation function proceeds from step S32 to step S33.

  In step S33, the random pattern generation function determines whether the data value is not “0xe000”. If the data value is not “0xe000”, the random pattern generation function sets “true” in the flag 1 and then proceeds to step S34. On the other hand, if the data value is “0xe000”, the random pattern generation function proceeds from step S33 to step S34.

  Proceeding to step S34, the random pattern generation function determines whether or not the range of the data value is “0x0000” to “0x7fff”. If the data value range of the random pattern generation function is “0x0000” to “0x7fff”, “true” is set in the flag 3 and the process proceeds to step S35. On the other hand, if the data value range of the random pattern generation function is not “0x0000” to “0x7fff”, the process proceeds from step S34 to step S35.

  In step S35, the random pattern generation function determines whether the data value is “0x0001”. If the data value is “0x0001”, the random pattern generation function sets “0x0002” in the data item “next data” of the pattern DB 24. If the data value is not “0x0001”, the random pattern generation function proceeds from step S35 to step S36.

  Proceeding to step S36, the random pattern generation function determines whether or not “true” is set in all of the flags 1 to 3. If “true” is not set for all of the flags 1 to 3, a data value that does not satisfy the restrictions based on the rule list of FIG. 10 has been generated, and the random pattern generation function returns to step S 31. On the other hand, if “true” is set in all of the flags 1 to 3, the data value satisfying the restriction items based on the rule list of FIG. 10 has been generated, and the random pattern generation function proceeds to step S37.

  In step S37, the random pattern generation function adds the data and the next data to the pattern DB 24. In step S38, the random pattern generation function sets the data added to the pattern DB 24 in step S37 as previous data. Then, the process proceeds to step S39, and the random pattern generation function waits for a period of time that is much faster than the period of the reception completion signal, and then returns to step S31.

  The random pattern generation function can sequentially generate random data values satisfying the rule list 32 by the processing of the flowchart shown in FIG.

  FIG. 17 is a flowchart showing processing of the pattern control function. In step S41, the pattern control function sets state = random, next data = −1, item number = 0, and direct DB index = 0 as initial values. In step S42, the pattern control function sets pattern DB index = 0.

  In step S43, the pattern control function determines whether the state is a random state or a direct state. If it is in the random state, the pattern control function proceeds to step S44 and searches the pattern DB 24 for a test pattern that matches the head (test pattern) of the direct test pattern stored in the direct DB 25.

  Proceeding to step S45, the pattern control function proceeds to step S46 if there is no test pattern in the pattern DB 24 that matches the head (test pattern) of the direct test pattern stored in the direct DB 25. In step S46, the pattern control function outputs the oldest (youngest index) test pattern from the pattern DB 24 as a random test pattern.

  If it is determined in step S43 that the pattern is in the direct state, or if it is determined in step S45 that the test pattern matching the beginning of the direct test pattern (test pattern) stored in the direct DB 25 is in the pattern DB 24, the pattern The control function proceeds to step S47.

  Proceeding to step S47, the pattern control function retrieves and outputs test patterns from the pattern DB 24 such that the order of the direct test patterns stored in the direct DB 25 is obtained. Progressing to step S48 following step S46 or S47, the pattern control function waits until the reception completion signal is received, and then returns to step S42.

  Next, the process of pattern matching search at step S44, random pattern output at step S46, and direct pattern output at step S47 will be described.

  FIG. 18 is a flowchart showing a pattern matching search process. First, proceeding to step S51, the pattern control function determines whether or not the pattern DB index is within the range of the index of the pattern DB 24. If the pattern DB index is within the range of the index of the pattern DB 24, the pattern control function proceeds to step S52.

  In step S52, the pattern control function determines whether the test pattern value corresponding to the item number of the direct DB 25 and the direct DB index matches the test pattern value corresponding to the pattern DB index of the pattern DB 24. If the test pattern value corresponding to the item number of the direct DB 25 and the direct DB index matches the test pattern value corresponding to the pattern DB index of the pattern DB 24, the process proceeds to step S54. In step S54, the pattern control function shifts from the random state to the direct state.

  If the test pattern value corresponding to the item number of the direct DB 25 and the direct DB index does not match the test pattern value corresponding to the pattern DB index of the pattern DB 24, the pattern control function proceeds to step S53, and 1 is added to the pattern DB index. Then, the process returns to step S51.

  After the process of step S54 or after determining in step S51 that the pattern DB index is not within the range of the index of the pattern DB 24, the pattern control function ends the pattern matching search process shown in FIG.

  FIG. 19 is a flowchart showing a random pattern output process. First, proceeding to step S61, the pattern control function sets 0 to the pattern DB index. In step S62, the pattern control function determines whether the next data is -1 or whether the next data other than -1 matches the test pattern value corresponding to the next pattern DB index.

  If the next data is not -1 or the next data other than -1 does not match the test pattern value corresponding to the next pattern DB index, the pattern control function proceeds to step S64, and 1 is added to the pattern DB index. After that, the process returns to step S62.

  On the other hand, if the next data is -1 or the next data other than -1 matches the test pattern value corresponding to the next pattern DB index, the pattern control function proceeds to step S63, and the pattern data is transferred from the pattern DB 24 to the pattern. Data corresponding to the DB index and the next data are read, and a transmission event is notified. Further, the pattern control function deletes the test pattern corresponding to the pattern DB index from the pattern DB 24, and then ends the random pattern output process shown in FIG.

  FIG. 20 is a flowchart showing a direct pattern output process. In addition, when progressing from step S43 of FIG. 17, it progresses to step S71. If the process proceeds from step S45 in FIG. 17, the process proceeds to step S74. In step S71, the pattern control function determines whether or not the pattern DB index is within the range of the index of the pattern DB 24. If the pattern DB index is within the range of the index of the pattern DB 24, the pattern control function proceeds to step S72.

  Proceeding to step S72, the pattern control function determines whether or not the test pattern value corresponding to the item number and direct DB index matches the test pattern value corresponding to the pattern DB index. If the test pattern value corresponding to the item number and the direct DB index matches the test pattern value corresponding to the pattern DB index, the pattern control function reads the data corresponding to the pattern DB index and the next data from the pattern DB 24, and transmits them. Notify the event. The pattern control function deletes the test pattern corresponding to the pattern DB index from the pattern DB 24, and then proceeds to step S75.

  Proceeding to step S75, the pattern control function determines whether the direct DB index is terminated. If the direct DB index is at the end, the pattern control function proceeds to step S77, shifts from the direct state to the random state, adds 1 to the item number, sets direct DB index = 0, and then is shown in FIG. The direct pattern output process ends. If the direct DB index is not the end, the pattern control function proceeds to step S76, adds 1 to the direct DB index, and then ends the direct pattern output processing shown in FIG.

  If the pattern DB index is not within the range of the index of the pattern DB 24 in step S71, the pattern control function ends the direct pattern output process shown in FIG.

  FIG. 21 is a flowchart showing the processing procedure of the module generation tool. In step S81, the module generation tool 30 reads the configuration 31, the rule list 32, and the pattern list 33, which are inputs for generating the test data generation module 20, and expands them into an internal table.

  In step S82, the module generation tool 30 outputs the class definition unit to a header file. In step S83, the module generation tool 30 outputs the random pattern generation function definition to the source file. In step S84, the module generation tool 30 outputs the pattern control function definition to the source file. In step S85, the module generation tool 30 outputs the LSI I / F conversion function definition to the source file.

  21 are items to which values are assigned from the configuration 31, the rule list 32, and the pattern list 33. 22 to 25 are image diagrams showing examples of the source code of the test data generation module 20.

  In FIG. 22 to FIG. 25, how variable description elements based on the configuration 31, the rule list 32, and the pattern list 33 are assigned in the source code is described with annotations. Specifically, in FIG. 22 to FIG. 25, the part described by the comment “/ *** to *** /” indicates a variable description element of the source code (test data generation module 20). ing.

  Using the parameter values and pattern values read from the configuration 31, rule list 32, and pattern list 33, the module generation tool 30 determines the variable description elements of the source code. Other parts are output in a fixed form.

  The test data generation module 20 according to the present invention randomly generates a test pattern at the random pattern generation unit 21 and monitors whether the generated test pattern matches the head (test pattern) of a predetermined direct pattern. The test data generation module 20 preferentially outputs the test patterns in the order of the direct pattern from the test pattern generated by the random pattern generation unit 21 when the generated test pattern matches the head of the predetermined direct pattern (test pattern). If the test patterns are output in the order in which they are generated by the random pattern generator 21 when they do not match, the processing of complicated conditions that are difficult to cover simply by performing a wide range of verification using the random test patterns is covered by the direct test pattern. Made possible.

  As described above, the test data generation module 20 according to the present invention performs an operation in which direct verification interrupts during random verification, and can cover functions (state transitions) that are difficult to cover by the conventional method. Therefore, the test data generation module 20 according to the present invention prevents the lack of verification coverage that is likely to occur when verification is performed using only direct verification, only random verification, or sequential verification thereof, and improves LSI quality. Can do.

  As described above, the test data generation module 20 according to the present invention can improve the verification coverage in the logic verification of the LSI. In addition, although the structure which outputs a test pattern from pattern DB24 was demonstrated in the present Example mentioned above, the structure which outputs a test pattern from direct DB25 at the time of direct verification is also possible.

The present invention may have the following configurations as described below.
(Appendix 1)
A computer accessible to the storage means,
First test pattern storage means for storing one or more test pattern groups created by a user in the storage means;
Random pattern generating means for sequentially generating random test patterns;
Second test pattern storage means for storing a random test pattern generated by the random pattern generation means in the storage means;
Monitoring the match between the test pattern stored in the storage unit by the second test pattern storage unit and the test pattern at the head of the test pattern group stored in the storage unit by the first test pattern storage unit; When the coincidence is detected, the test patterns are output in the order of the test patterns defined in the test pattern group in which the coincidence is detected. When no coincidence is detected, the test pattern is stored in the storage unit by the second test pattern storage unit. A test data generation program for functioning as pattern control means for outputting the test patterns in the stored order.
(Appendix 2)
When the pattern control unit detects a match, the pattern control unit causes the storage unit to store the first test pattern and the last test pattern defined in the test pattern group in which the match is detected, in order. 2. The test data generation program according to appendix 1, wherein the test pattern stored by the test pattern storage means is read and output.
(Appendix 3)
The first test pattern storage means stores the one or more test pattern groups for which priority is set in the storage means,
The test data generation program according to claim 1 or 2, wherein the pattern control means outputs the test patterns in the order of the test patterns defined in the test pattern group in the order according to the priority. .
(Appendix 4)
The random pattern generation means sequentially generates the test patterns according to the restrictions when there are restrictions on the contents of the test patterns that are sequentially generated according to the specifications of the test target integrated circuit. The test data generation program according to any one of 1 to 3.
(Appendix 5)
The test data generation program includes a file for setting the attributes of the test data generation device, and a file for setting the restrictions when the contents of the test patterns that are sequentially generated are limited due to the specifications of the integrated circuit to be tested. The test data generation program according to any one of appendices 1 to 4, wherein the test data generation program is generated based on a file for setting the one or more test pattern groups stored in the first test pattern storage means. .
(Appendix 6)
A test data generation device that generates and outputs test data,
First test pattern storage means for storing one or more test pattern groups created by a user;
Random pattern generating means for sequentially generating random test patterns;
Second test pattern storage means for storing a random test pattern generated by the random pattern generation means;
A match between the test pattern stored in the second test pattern storage means and the test pattern at the head of the test pattern group stored in the first test pattern storage means is monitored, and if a match is detected, a match is detected. If the test patterns are output in the order of the test patterns defined in the test pattern group and no match is detected, the test patterns stored in the second test pattern storage means are output in the stored order. A test data generation apparatus comprising: pattern control means for outputting.
(Appendix 7)
A test data generation method in a test data generation device that generates and outputs test data,
A computer accessible to the storage means,
A first test pattern storage procedure for storing one or more test pattern groups created by a user in the storage means;
Random pattern generation procedure for generating random test patterns sequentially,
A second test pattern storage procedure for storing a random test pattern generated by the random pattern generation means in the storage means;
Monitoring for monitoring the coincidence between the test pattern stored in the storage means in the second test pattern storage procedure and the test pattern at the head of the test pattern group stored in the storage means in the first test pattern storage procedure Procedure and
When a match is detected in the monitoring procedure, the test patterns are output in the order of the test patterns defined in the test pattern group in which the match is detected. If no match is detected, the second test pattern storage means A test data generation method comprising: a pattern control procedure for outputting the test patterns stored in the storage means in the order of storage.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

It is a block diagram of an example of a test data generation device. It is an image figure of an example of the test data (test pattern) which a test data generation module generates. It is a block diagram of an example of a test data generation module. It is a flowchart which shows the process outline | summary of a random pattern generation function. It is a flowchart which shows the process outline | summary of a pattern control function. It is a flowchart which shows the process outline | summary of a LSI I / F conversion function. It is the image figure which showed how the test data generation module is generating the test pattern. It is a flowchart showing the production | generation procedure of the test data production | generation module using a module production | generation tool. It is a block diagram of an example of a configuration. It is a block diagram of an example of a rule list. It is a block diagram of an example of a pattern list. It is a block diagram of an example of a test bench. It is a block diagram of the other example of a test bench. It is a block diagram showing the internal image of pattern DB. It is a block diagram showing the internal image of direct DB. It is a flowchart which shows the process of a random pattern generation function. It is a flowchart which shows the process of a pattern control function. It is a flowchart which shows the process of a pattern matching search. It is a flowchart which shows the process of a random pattern output. It is a flowchart which shows the process of a direct pattern output. It is a flowchart showing the processing procedure of the module generation tool. 3 is an image diagram of an example representing a source code (1/4) of a test data generation module 20. FIG. 3 is an image diagram of an example representing a source code (2/4) of a test data generation module 20. FIG. 3 is an image diagram of an example representing a source code (3/4) of a test data generation module 20. FIG. 3 is an image diagram of an example representing a source code (4/4) of a test data generation module 20. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Input device 12 Output device 13 Drive device 14 Auxiliary storage device 15 Main storage device 16 Arithmetic processing device 17 Interface device 20 Test data generation module 21 Random pattern generation unit 22 Pattern control unit 23 LSI I / F conversion unit 24 Pattern DB
25 Direct DB
30 Module generation tool 31 Configuration 32 Rule list 33 Pattern list 40, 50 LSI logic verification environment (test bench)
41 LSI to be verified
42 Signal monitor 51 Reference model 52 Signal checker

Claims (7)

A computer accessible to the storage means,
First test pattern storage means for storing one or more test pattern groups created by a user in the storage means;
Random pattern generating means for sequentially generating random test patterns;
Second test pattern storage means for storing a random test pattern generated by the random pattern generation means in the storage means;
Monitoring the match between the test pattern stored in the storage unit by the second test pattern storage unit and the test pattern at the head of the test pattern group stored in the storage unit by the first test pattern storage unit; When the coincidence is detected, the test patterns are output in the order of the test patterns defined in the test pattern group in which the coincidence is detected. When no coincidence is detected, the test pattern is stored in the storage unit by the second test pattern storage unit. A test data generation program for functioning as pattern control means for outputting the test patterns in the stored order.   When the pattern control unit detects a match, the pattern control unit causes the storage unit to store the first test pattern and the last test pattern defined in the test pattern group in which the match is detected, in order. 2. The test data generation program according to claim 1, wherein the test pattern stored by the two test pattern storage means is read and output. The first test pattern storage means stores the one or more test pattern groups for which priority is set in the storage means,
3. The test data generation according to claim 1, wherein the pattern control means outputs the test patterns in the order of the test patterns defined in the test pattern group in the order according to the priority. program.   The random pattern generation means sequentially generates the test patterns according to the restrictions when there are restrictions on the contents of the test patterns that are sequentially generated according to the specifications of the test target integrated circuit. Item 4. The test data generation program according to any one of Items 1 to 3.   The test data generation program includes a file for setting the attributes of the test data generation device, and a file for setting the restrictions when the contents of the test patterns that are sequentially generated are limited due to the specifications of the integrated circuit to be tested. 5. The test data generation according to claim 1, wherein the test data is generated based on a file for setting the one or more test pattern groups stored in the first test pattern storage unit. program. A test data generation device that generates and outputs test data,
First test pattern storage means for storing one or more test pattern groups created by a user;
Random pattern generating means for sequentially generating random test patterns;
Second test pattern storage means for storing a random test pattern generated by the random pattern generation means;
A match between the test pattern stored in the second test pattern storage means and the test pattern at the head of the test pattern group stored in the first test pattern storage means is monitored, and if a match is detected, a match is detected. If the test patterns are output in the order of the test patterns defined in the test pattern group and no match is detected, the test patterns stored in the second test pattern storage means are output in the stored order. A test data generation apparatus comprising: pattern control means for outputting. A test data generation method in a test data generation device that generates and outputs test data,
A computer accessible to the storage means,
A first test pattern storage procedure for storing one or more test pattern groups created by a user in the storage means;
Random pattern generation procedure for generating random test patterns sequentially,
A second test pattern storage procedure for storing a random test pattern generated by the random pattern generation means in the storage means;
Monitoring for monitoring the coincidence between the test pattern stored in the storage means in the second test pattern storage procedure and the test pattern at the head of the test pattern group stored in the storage means in the first test pattern storage procedure Procedure and
When a match is detected in the monitoring procedure, the test patterns are output in the order of the test patterns defined in the test pattern group in which the match is detected. If no match is detected, the second test pattern storage means A test data generation method comprising: a pattern control procedure for outputting the test patterns stored in the storage means in the order of storage.

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