JP2009100236A - Video signal processing method and video signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video signal processing technology in which a memory access amount is reduced more. <P>SOLUTION: In this video signal processor which converts an interlace video signal in an input video signal into a non-interlace video signal, the video signal processor is characterized by including: an input part which inputs an interlace video signal with a predetermined frame frequency f; first to fourth memories to which interlace video signals are sequentially written; first and second scanning line interpolation parts which read field data adjacent to the input signal with a frequency of approximately n times of f from the memory, perform scanning line interpolation, and create frame data; and an interpolation frame creation part which creates interpolation frame data equivalent to time of the scanning line interpolation from the two pieces of adjacent frame data to which the scanning line interpolation is performed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a video signal processing technique related to interpolation frames and non-interlaced conversion.

  In a television, personal computer (PC), mobile phone, or other device for displaying an image signal, an interpolation frame for interpolating the image frame is created from the image frame constituting the image signal, and the created interpolation frame is converted into an image. A technique for displaying by interpolating in a frame is known. This technique is used, for example, for the purpose of smoothly displaying an image signal transmitted at a low frame rate in order to reduce the amount of information. On the other hand, a technique for converting an interlace signal into a non-interlace signal is also known.

  As the former, for example, Patent Document 1 shows a technique for doubling the frame frequency by generating a signal of a frame between two frames by calculation and displaying the original frame and a newly generated frame alternately. ing.

As the latter, for example, Patent Document 2 (FIG. 2) shows a conversion (scanning line interpolation) circuit from interlace to non-interlace using adjacent field signals.
JP 2005-6275 A JP-A-4-320180

  However, the conventional circuit configuration has a large memory access amount and is not suitable for high-speed processing. An object of the present invention is to provide a video signal processing technique with a further reduced memory access amount.

  In order to solve the above-described problems, an image signal processing apparatus according to the present invention inputs an interlaced video signal having a predetermined frame frequency f in a video signal processing apparatus that converts an interlaced video signal in an input video signal into a non-interlaced video signal. An input unit, first to fourth memories in which the interlaced video signal is sequentially written, field data adjacent to the input signal at a frequency approximately n times f from the memory, and scanning line interpolation are performed to obtain frame data. The first and second scanning line interpolation units to be created, and an interpolation frame creation unit to create interpolation frame data corresponding to the time between the two scanning line interpolated adjacent frame data And

  According to the present invention, a video signal processing technique with a further reduced memory access amount can be obtained.

  Examples of the present invention will be described below.

A first embodiment of the present invention will be described with reference to FIGS. 1 to 3 and FIGS.
FIG. 8 schematically shows an appearance of a digital television broadcast receiving apparatus 111 to which the present invention is applied, and an example of a network system configured around the digital television broadcast receiving apparatus 111.

  That is, the digital television broadcast receiver 111 mainly includes a thin cabinet 112 and a support base 113 that supports the cabinet 112 upright. Then, it is transmitted to the cabinet 112 from, for example, an SED (Surface-conduction Electron-emitter Display) display panel, a flat panel type video display 114 made up of a liquid crystal display panel, a speaker 115, an operation unit 116, and a remote controller 117. A light receiving unit 118 for receiving operation information is installed.

  Further, for example, a first memory card 119 such as an SD (Secure Digital) memory card, an MMC (Multimedia Card), and a memory stick can be attached to and detached from the digital television broadcast receiving apparatus 111. Information such as programs and photographs is recorded on and reproduced from the memory card 119.

  Further, for example, a second memory card (IC card) 120 in which contract information or the like is recorded can be attached to and detached from the digital television broadcast receiving apparatus 111. Information is stored in the second memory card 120. Recording / reproduction is performed.

  The digital television broadcast receiver 111 includes a first LAN (Local Area Network) terminal 121, a second LAN terminal 122, a USB (Universal Serial Bus) terminal 123, and an i. A LINK terminal 124 is provided.

  Among these, the first LAN terminal 121 is used as a LAN-compatible HDD dedicated port, and information is transferred to the LAN-compatible HDD 125 which is a NAS (Network Attached Storage) by Ethernet (registered trademark). Used for recording and playback.

  Thus, by providing the first LAN terminal 121 as a LAN-compatible HDD dedicated port, program information can be recorded on the HDD 125 with high-definition image quality without being affected by other network environments or network usage conditions. It can be performed stably.

  The second LAN terminal 122 is used as a general LAN-compatible port using Ethernet (registered trademark). For example, the LAN-compatible HDD 127, PC (Personal Computer) 128, It is used to connect devices such as a DVD recorder 129 with a built-in HDD and to transmit information with these devices.

  The PC 128 has a function for operating as a content server device in a home network, and further includes UPnP (Universal Plug and Play) provided with a service for providing URI (Uniform Resource Identifier) information necessary for content access. ) Configured as a compatible device.

  As for the DVD recorder 129, since the digital information communicated via the second LAN terminal 122 is information only for the control system, analog video and audio information is exchanged with the digital television broadcast receiver 111. In order to transmit, it is necessary to provide a dedicated analog transmission line 130.

  Further, the second LAN terminal 122 is connected to a network 132 such as the Internet via a broadband router 131 connected to the hub 126, and transmits information to and from the PC 133, the mobile phone 134, etc. via the network 132. Used to do.

  The USB terminal 123 is used as a general USB-compatible port. For example, a mobile phone 136, a digital camera 137, a card reader / writer 138 for a memory card, an HDD 139, a keyboard 140, etc. via a hub 135. USB devices are connected to each other and used for information transmission with these USB devices.

  Further, i. The LINK terminal 124 is used to serially connect, for example, an AV-HDD 141, a D (Digital) -VHS (Video Home System) 142, and the like and perform information transmission with these devices.

  FIG. 9 shows a general configuration of a digital broadcast receiving apparatus. In addition to broadcasting, content may also be received from media such as DVDs and HDDs, and networks such as IP networks and LANs. The broadcast reception signal is supplied from a demodulation circuit (not shown) to the Demux circuit 9-2. When receiving content from the IP network, the content is once taken into the memory 9-1 by processing by the CPU 9-6 and then supplied to the Demux circuit 9-2. The Demux circuit 9-2 separates the received stream into Video and Audio signals and writes them into the memory. The stream compressed with AudioDecoder 9-3 or VideoDecoder 9-4 is decoded. The decoded result is written into the memory 9-1. Video and audio signals supplied from the outside are taken into the memory 9-1 by the Capture circuit 9-7. Scanning line interpolation circuit Interpolation frame creation circuit 9-5 reads out video data from memory 9-1, interlaced data is interpolated and converted to non-interlaced structure, and from non-interlaced structure two frames Create the frame data and the frame data corresponding to the position between them in time, and the frequency higher than the original field frequency of the video signal (usually twice but may be non-integer times such as n times or 1.5 times) ) To output frame data. The graphics circuit 9-8 reads the graphic data on the memory 9-1, superimposes it on the data output from the scanning line interpolation circuit interpolation frame generation circuit 9-5, and outputs an image (not shown) Display on a device or output to an external device.

Memory 9-1 is Demux9-2, AudioDecoder9-3, VideoDecoder9-4, Scan line interpolation circuit Interpolation frame creation circuit 9-5, CPU9-6, Capture9-7, Graphics9-8 -1 is shared and accessed in a time-sharing manner.

  FIG. 1 shows the flow of signal processing in the apparatus of FIG. The received broadcast video signal and the video signal supplied from the outside are recorded in the memory 1-2, the memory 1-3, the memory 1-4, and the memory 1-5.

<Reducing memory bandwidth>
When the video signals recorded in the memory 1-2 to 1-5 are in interlace format, the scanning line interpolator 1-6 uses the three adjacent field data from the memory 1-2, memory 1-3, and memory 1-4. Is read and converted to non-interlaced format. Further, the scanning line interpolation circuit 1-7 reads three adjacent field data from the memory 1-3, the memory 1-4, and the memory 1-5, and converts them into non-interlaced frame data (to non-interlaced data). See the publicly known literature for the conversion process). In this embodiment, two scanning line interpolation circuits 1-6 and 1-7 are provided, and two frame data are created simultaneously. Also, by operating at twice the processing speed, one frame data is output in 1/2 field time. FIG. 8 shows an example of a scanning line interpolation circuit.

  The interpolated frame creation circuit 1-8 generally uses the non-interlaced adjacent frame data output from the scanning line interpolator, and is temporally intermediate between the two frame data (typically centered in time). Interpolated frame data located at (but not necessarily limited to) is created (refer to publicly known literature for a method of creating interpolated frame data).

  When the input video signal is a non-interlace video signal, the process of converting the interlace video signal into a non-interlace video signal is bypassed.

FIG. 2 shows memory read timing and interpolation frame output timing. Reference numeral 2-1 denotes one field period of the input image signal.
The scanning line interpolation circuit 1-7 performs the frame data 1 from the field data 0, 1, 2 in the period 2-2, the frame data 1 from the field data 0, 1, 2 in the period 2-3, and the scanning line interpolation. The circuit 1-6 creates frame data 2 from the field data 1, 2, and 3.

When viewed in one field period, the memory access amount required for scanning line interpolation and frame interpolation processing is memory reading for seven fields.
It is necessary to provide a scanning line interpolation circuit that executes processing for two frames at twice the frequency and an interpolation frame generation circuit that operates in a half field period, as compared to known documents.
<Periodic operation of scanning line interpolation circuit and interpolation frame creation circuit>
In this case, the output signal from the interpolation frame generation circuit 1-8 outputs two frame data in one field period. The interpolation frame creation circuit 1-8 outputs the frame data 1 from the scanning line interpolation circuit 1-6 in the 1/2 field period 2-2 during the period 2-2. In period 2-3, interpolated frame data 1.5 between the frame data 1 from the scanning line interpolation circuit 1-6 and the frame data 2 from the scanning line interpolation circuit 1-7 is created and output. Since the frame data 2 is unnecessary in the period 2-2, the scanning line interpolation circuit 1-7 does not need to perform the scanning line interpolation process during this period, and the interpolation frame data generation circuit 1-8 performs the interpolation frame generation process. There is no need to read from the memory 1-2. Therefore, in the period 2-2, the memories 1-3, 1-4, and 1-5 are read out, and in the period 2-3, the memories 1-2, 1-3, 1-4, and 1-5 are read out.

  When the memory 1-2, 1-3, 1-4, and 1-5 are configured with a physically common device, the read data rate (consumed memory band) from that device is period 2-2. However, the design of the memory system is required to satisfy the memory band in the period 2-3.

<Equalization of memory access>
In general, a decoder or a capture circuit of a compressed stream once writes a video signal in a memory by executing a decoding process or the like. The field period 2-1 shows the memory access amount when the decoding process is executed using the period evenly. As the total memory band, the amount of memory band consumed in the period 2-3 increases from the period 2-2. Therefore, the memory system needs to be designed to withstand the memory access amount in the period 2-3.

  On the other hand, in the period 2-4, the operation of the decoding circuit 1-1 is distributed in the first half so that the processing amount is increased. 3-1 indicates the top position of the screen, and 3-2 indicates the bottom position of the screen.

  FIG. 3 shows an image of how the decoding process proceeds. Reference numerals 3-4 and 3-6 indicate positions in one screen processed by the scanning line interpolation circuit interpolation frame generation circuit 9-5. The scanning line interpolation circuit / interpolation frame creation circuit 9-5 outputs the frame twice during one field time period of the input image. Reference numerals 3-3, 3-5, and 3-7 indicate positions on one screen processed by the decoder capture circuit 1-1. In 3-3, the decoder capture circuit 1-1 performs the decoding process by equally using one field time of the input image. Scanning line interpolation circuit Interpolation frame creation circuit 9-5 reads 3 fields in period 3-4 and 4 fields in period 3-6, so the memory access amount is higher in the second half, and the memory system has this bandwidth. You need something to satisfy. In 3-5, 1/2 or more of one screen is processed in the first half of one field period, and 1/2 or less is processed in the second half. In this way, the amount of memory access can be made evenly as a whole. Compared with the first half and the second half of one field, the second half has a larger read amount for one field, so the memory access amount in the second half can be reduced by one half field by making the operation of the decoding circuit non-uniform in the first half and the second half. . As a result, more processing can be executed as a whole system.

A third embodiment according to the present invention will be described with reference to FIGS. Description of the parts common to the first embodiment is omitted.
FIG. 4 shows a memory access when 3 frames are output in one field period. One field period is divided into three, and three fields are read in the first frame output period, and four fields are read in the second and third frame output periods. In total, the memory access amount is 11 fields during the period of one input signal field.

The processing of the decoder 1-1 is concentrated on the period 4-1 rather than the periods 4-2 and 4-3, so that the memory access amount can be equalized as a whole and the maximum value of the memory band can be kept low.

FIG. 5 shows a different memory access method when the scanning line interpolation circuit is provided with a noise reduction (NR) function. FIG. 7 shows a configuration example of the scanning line interpolation circuit with NR. The scanning line interpolation circuit with NR reads the four field data from the memory and converts the interlace format signal into the non-interlace format. For the field to be converted to non-interlace and the field for obtaining the scanning line to be interpolated, the average value when the difference value of the signals of two frames is small, the value of one field when the difference value is large, Use.

In the first half of one field period of the input signal, data of 4 fields is read, and in the second half, data of 5 fields is read. A total of 9 fields of data are read out.

  FIG. 10 shows a configuration when the scanning line interpolation circuit and the frame interpolation circuit shown in the conventional example are simply combined. According to this configuration, the memory 10-1, 10-2, 10-3 is read once in one field period, the frame data is written to, read from, and the memory 10-5 is written to one each. Times, the frame data of the memories 10-4 and 10-5 is read once. When converted to field data, the total is 3+ (2 * 3) + 2 * 2 = 13 sheets. Considering half the period of one field, it is 6.5 sheets.

According to the embodiment of FIG. 1, since the scanning line interpolation circuit is executed in 1/2 field, the required memory bandwidth is 3 sheets in the first half of one field time and 4 sheets in the second half. The effect of reducing 2.5 sheets to 6.5 is obtained.

In addition, by changing the balance between the first half and the second half as in the embodiment of FIG. 2, the memory access amount in the entire system can be averaged, and the access amount excluding processing such as decoding is as follows. It can be considered as 3.5 sheets, and the effect of reducing by 3 sheets is obtained compared to 6.5 sheets of the known example.

  In order to progressively convert an interlace video signal as described above and output it at twice the frame rate, the field memory read in interlace format for progressive conversion is performed three times, and the signal converted to progressive format is 1 time to write to memory, 1 time to read interpolated frame, 1 time to write interpolated frame, 2 times to read frame memory at double speed, converted to interlaced field data, 1 field time The memory access amount was 13 sheets.

As an effect, the amount of memory access can be reduced to seven by converting it into interlaced field data.
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.
Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements according to different embodiments may be appropriately combined.

The figure which shows the flow of the signal processing which is one Example of this invention. The figure which shows the read-out timing of the memory of the Example, and the output timing of an interpolation frame. Explanatory drawing which shows the image of how to advance the decoding process of the Example. The figure which shows the memory access of the other example of the Example. The block diagram from which the method of the memory access used for the other example differs. The block block diagram which shows the scanning line interpolation circuit of the other example. The block block diagram which shows the scanning line interpolation circuit with NR in the other example. 1 is a configuration diagram schematically showing an example of a network system configured around the appearance and surroundings of a broadcast receiving apparatus 111. FIG. The block diagram which shows the general structure of a digital broadcast receiver. The block diagram which shows a structure when a scanning line interpolation circuit and a frame interpolation circuit are simply combined.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 111 ... Digital television broadcast receiver, 112 ... Cabinet, 113 ... Support stand, 114 ... Video display, 115 ... Speaker, 116 ... Operation part, 117 ... Remote controller, 118 ... Light receiving part, 119 ... First memory card 120 ... second memory card 121 ... first LAN terminal 122 ... second LAN terminal 123 ... USB terminal 124 ... i. LINK terminal, 125, 127, 139 ... HDD, 126, 135 ... hub, 128 ... PC, 129 ... DVD recorder, 130 ... analog transmission line, 131 ... broadband router, 132 ... network, 133 ... PC, 134,136 ... mobile Telephone: 137: Digital camera, 138: Card reader / writer, 140: Keyboard, 141: AV-HDD, 142: D-VHS.

Claims (6)

A video signal processing method in a video signal processing apparatus for converting an interlace video signal in an input video signal into a non-interlace video signal,
Input an interlaced video signal having a predetermined frame frequency f, sequentially write it to the first to fourth memories, read out the field data adjacent to the input signal at a frequency approximately n times f from the memory, and perform two scanning line interpolations A video signal processing method comprising: generating adjacent frame data, and generating and outputting interpolated frame data corresponding to a time between the two frame data.   2. The video signal processing method according to claim 1, wherein a period in which the interpolation frame is created and a period in which the interpolation frame is not created are periodically repeated.   The video signal processing method according to claim 1, wherein one of the two scanning line interpolation circuits periodically repeats the operation period and the non-operation period.   2. The video signal processing method according to claim 1, wherein the operation frequency, the processing amount, and the like of the video decoder are switched between a period in which the interpolated frame data is created and a period in which it is not. In a video signal processing apparatus that converts an interlace video signal in an input video signal into a non-interlace video signal,
An input unit for inputting an interlaced video signal having a predetermined frame frequency f;
First to fourth memories in which the interlaced video signals are sequentially written;
First and second scanning line interpolation units for reading out field data adjacent to the input signal at a frequency approximately n times f from the memory and performing scanning line interpolation to generate frame data;
An image signal processing apparatus comprising: an interpolation frame creating unit that creates an interpolated frame data corresponding to a time between two adjacent scan line interpolated frame data. In a video signal processing apparatus that converts an interlace video signal in an input video signal into a non-interlace video signal,
An input unit for inputting an interlaced video signal having a predetermined frame frequency f;
First to fourth memories in which the interlaced video signals are sequentially written;
First and second scanning line interpolation units for reading out field data adjacent to the input signal at a frequency approximately n times f from the memory and performing scanning line interpolation to generate frame data;
An interpolated frame creation unit that creates interpolated frame data corresponding to the time between these two scan line interpolated adjacent frame data;
A video signal processing apparatus comprising: a display unit that outputs the interpolated frame data.

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