JP4775351B2 - Imaging device - Google Patents

Description

The present invention relates to an imaging apparatus , and more particularly to an imaging apparatus suitable for use when outputting an image in a predetermined format.

  In digital cameras (digital still cameras, digital video cameras, and digital cameras capable of capturing still images and moving images), a liquid crystal finder is used instead of an optical finder in order to confirm an image to be captured. In addition, the digital camera has a video output terminal for outputting image data recorded therein to an external display device in order to display a captured image using a monitor such as a television receiver. I have.

  Examples of the video output format include the NTSC (National Television System Committee) system and the PAL (Phase Alternating Line) system. PAL is a color television broadcasting standard proposed in West Germany in 1962, with 625 scanning lines (50 fields), a frame rate of 25 frames / second, and a screen ratio (aspect ratio) of 3: 4. It is mainly used in Western European countries except France. NTSC is a color television signal system standardized in 1953, with 525 scanning lines (60 fields), a frame rate of 29.97 frames / second, and a screen ratio (aspect ratio) of 3: 4. Adopted in the United States and Japan.

  In conventional digital cameras, the entire processing in the device was operated with a reference clock that matched the frame rate of PAL or NTSC in accordance with the video output format, so PAL or NTSC video was also displayed on the LCD finder. It had been.

  FIG. 1 is a block diagram showing a configuration of a conventional digital camera 1. In the figure, the solid line indicates the transmission / reception of the image signal, the dotted line indicates the transmission / reception of the control signal, the one-dot broken line indicates the transmission / reception of the code signal, and the two-dot broken line indicates the transmission / reception of the synchronization signal. Is shown.

  An image signal captured by a CCD (Charge Coupled Device) camera unit 11 is converted into a digital signal by an A / D conversion unit 12 and input to a signal processing unit 13. The signal processing unit 13 performs, for example, gamma processing or processing to convert an RGB signal into a Y / Cb / Cr signal on the input signal, and supplies the processed image data to the memory controller 14. .

  Under the control of a CPU (Central Processing Unit) 15, the memory controller 14 writes input image data into the memory 19 via the bus 16 and records it, or stores image data written in the memory 19 on the bus 19 The image data is supplied to the image compression processing unit 17 and the resolution conversion processing unit 18 via 16 and processed, and recorded in the memory 19 again. The memory controller 14 also stores image data processed by the signal processing unit 13 recorded in the memory 19 or an image processed by the image compression processing unit 17 or the resolution conversion processing unit 18 as necessary. Data is supplied to the display signal processing unit 20 via the bus 16, read via the bus 16, and output to the drive 23.

  The CPU 15 controls the operation of the digital camera 1, receives a reference timing signal from a synchronization signal generation unit 31 described later, receives the signal processing unit 13, the memory controller 14, and the display signal processing unit 20. A control signal for controlling the operation is generated and output.

  The image compression processing unit 17 performs compression coding (software coding) on the supplied image data by a predetermined compression coding method such as JPEG. The resolution conversion processing unit 18 performs horizontal or vertical image resolution conversion processing on the supplied data.

  The display signal processing unit 20 receives the input of the image data recorded in the memory 19 via the bus 16 and outputs it to the display unit 21 based on the reference signal generated by the synchronization signal generation unit 31 included therein. A process of converting the signal into a signal suitable for display or a signal suitable for output to an external device via the video output interface 22 is executed. The reference signal generated by the synchronization signal generation unit 31 is supplied to the CCD camera unit 11, the signal processing unit 13, and the CPU 15.

  The display unit 21 is composed of a liquid crystal panel, for example, and displays image data of a predetermined display format (for example, PAL or NTSC) supplied from the display signal processing unit 20. The video output interface 22 is connected to an external device in a predetermined interface format, and outputs image data of a predetermined video output format (for example, PAL or NTSC) supplied from the display signal processing unit 20 to the external device. . Note that the video output interface 22 and an external device may be connected by wire or may be connected wirelessly.

  The memory controller 14 is connected to a drive 23 as necessary, and a magnetic disk 41, an optical disk 42, a magneto-optical disk 43, a semiconductor memory 44, or the like is mounted. For example, by the processing of the memory controller 14, The image compressed by the image compression processing unit 17 is supplied and recorded on these recording media.

  At the time of shooting, a signal input from the CCD camera unit 11 is converted into a digital signal by the A / D conversion unit 12 and input to the signal processing unit 13. The signal processing unit 13 performs, for example, gamma processing or processing to convert an RGB signal into a Y / Cb / Cr signal on the input signal, and supplies the processed image data to the memory controller 14. . When there is an image size conversion, the image data is supplied to the resolution conversion processing unit 18 via the bus 16 by the processing of the memory controller 14, and horizontal and vertical image conversion is performed. The data is recorded in the memory 19 via the bus 16 by the processing of the memory controller 14.

  When the image data is recorded on a recording medium mounted on the drive 23, the image data is supplied to the image compression processing unit 17 via the bus 16 by the processing of the memory controller 14, for example, JPEG or the like. Are compressed by a predetermined compression encoding method. The compressed image data is output to the drive 23 again by the processing of the memory controller 14 and recorded on a recording medium such as the magnetic disk 41, the optical disk 42, the magneto-optical disk 43, or the semiconductor memory 44.

  In particular, when a moving image is captured, an image signal captured by the CCD camera unit 11 and subjected to predetermined processing by the A / D conversion unit 12 and the signal processing unit 13 is framed in the memory 19 by processing of the memory controller 14. Recorded every time. Under the control of the CPU 15, the memory controller 14 supplies the image signal recorded in the memory 19 to the image compression processing unit 17. The image compression processing unit 17 performs image compression on the supplied image signal in accordance with the specification of the frame rate of the moving image (for example, 15 frames / second or 16.6 frames / second). That is, when the frame rate specification is 15 frames / second, the image compression processing unit 17 compresses the supplied image signal into an image every 66.6 msec, and the frame rate specification is 16.6 frames / second. In the case of, the supplied image signal is compressed into images every 60 msec. The compressed image data is written to the memory 19 or a recording medium attached to the drive 23 by the processing of the memory controller 14.

  The reference of the processing timing described above is the vertical synchronization signal VD generated by the synchronization signal generation unit 31 in the display signal processing unit 20, and this signal is sent to the CPU 15 and the signal processing unit 13. The input signal is used as a reference for necessary signal processing and CPU 15 processing.

  Conventionally, this reference timing (vertical synchronization signal VD) has been generated based on the frame rate of the video signal format (for example, NTSC or PAL) output from the video output interface.

  In many cases, the number of scanning lines of the liquid crystal panel of the display unit 21 used in the liquid crystal finder is 240 in accordance with NTSC. In a digital still camera that operates in PAL using such a liquid crystal panel, thinning of scanning lines is performed when an image is displayed on the liquid crystal panel.

  When a PAL image is displayed on a liquid crystal panel having scanning lines matched to NTSC, the scanning line is thinned out, so that the image deteriorates. Further, in such a case, when the display content includes character information by OSD (On Screen Display), there arises a problem that characters are lost due to thinning of scanning lines.

  In recent years, with the improvement in performance of a CCD, which is an image sensor, there has been a demand for an improvement in frame rate and an improvement in image quality in displaying moving images. As described above, in the conventional digital camera 1, the reference for processing is the vertical synchronization signal VD generated in accordance with the video output format. Accordingly, the CCD camera unit 11, the signal processing unit 13, and the CPU 15 operate at a timing based on the PAL system or the NTSC system in accordance with the video output format.

  However, when the processing standard is NTSC or PAL, it is not preferable that two formats are produced as product forms, and it is necessary to process image data having different frame rates when shooting a moving image. I want to avoid that. Therefore, the conventional digital camera is set to perform image processing in accordance with a frame rate of 25 frames / second in the case of PAL, which is a lower frame rate, and even in NTSC operation, 25 frames / second. Will be processed at the frame rate. That is, a high frame rate cannot be realized.

  In addition, when a compressed video file is created by software by the processing of the image compression processing unit 17, the frequency of 29.97 Hz in accordance with the NTSC system is a frequency that makes it difficult to synchronize the image and the sound. For this reason, when the image compression processing unit 17 actually encodes with software, a frame rate not based on the NTSC system (for example, 15 frames / second, 16.6 frames / second, or 30 frames / second), etc. Was selected.

  However, when encoding is performed by software processing in the image compression processing unit 17, since high compression using a motion vector or the like cannot be performed, the bit rate cannot be greatly reduced, and high image quality cannot be obtained. . When encoding is performed by software processing, the reference timing must be the same in the shooting mode and the playback mode.

  On the other hand, in order to capture and record a moving image with high image quality, it is preferable to perform encoding using a dedicated codec IC (Integrated Circuit). In recent years, many dedicated codec ICs suitable for capturing and recording moving images with high image quality have been developed and commercialized.

  However, already commercialized codec ICs are set to operate in the PAL system or NTSC system in accordance with the conventional video output. Also, since the use of a codec IC increases costs, there is a need for a system that can perform both a high-frame-rate encoding method using software and a high-quality encoding method using a dedicated codec IC. Yes. If it is a system capable of both encoding methods, it is possible to cope with both a configuration not using a codec IC and a video camera using a codec IC based on cost and quality requirements. That is, a video camera to which a codec IC can be connected can be configured.

  The present invention has been made in view of such a situation, and enables both video encoding with high frame rate software and high-quality video encoding with an external codec IC. It is performed at a fixed timing regardless of the format of a moving image to be output as a video, and deterioration of displayed image quality can be eliminated.

An imaging apparatus according to an aspect of the present invention includes an imaging unit that captures a subject image at a predetermined first frame rate, a second frame rate lower than the first frame rate , or the first frame rate . lower than the frame rate, and display means for displaying an image based on the image data of the third frame rate different from the second frame rate, the image data of the second frame rate, or the third the frame rate image data, performing a video output means for outputting to an external device, connected to an external codec IC, the second frame rate, or, the input and output of the image data of the third frame rate and connecting means, by thinning the image at a rate of one in 1001 sheets, the image data of the first frame rate, the second frame rate A first frame rate conversion process for converting to image data, a first frame rate conversion process that converts image data of the first frame rate into image data of the third frame rate by thinning out at a rate of 1 out of 6 frames. 2 of the frame rate conversion processing by adding one image 1000, the image data of the second frame rate, the third frame rate conversion process for converting the image data of the first frame rate, And conversion means for performing a fourth frame rate conversion process for converting the image data of the third frame rate into the image data of the first frame rate by adding one image to five images , For image data input / output to / from the external codec IC, the image data corresponding to the frame rate supported by the external codec IC One of the first to fourth frame rate conversion processes is executed by the conversion means, and the frame rate of the image to be displayed on the display means is set to the same frame rate as the external codec IC, and the video The frame rate of the image output from the output means is set to the second or third frame rate that can be processed by the external device, and the image data of the first frame rate is set to the set frame rate. In order to obtain image data, the image forming apparatus includes control means for performing control for causing the conversion means to execute the first or second frame rate conversion processing .

In one aspect of the present invention, any one of the first to fourth frame rate conversion processes corresponding to the frame rate supported by the external codec IC is performed on image data input / output to / from the external codec IC. Is executed by the conversion means, and the frame rate of the image to be displayed on the display means is set to the same frame rate as that of the external codec IC, and the frame rate of the image output from the video output means is The second or third frame rate that can be processed, and the image data of the first frame rate is converted to image data of the set frame rate, so that the conversion means converts the first or second frame rate. The video output means executes the second or third process that can be processed by an external device after the first or second conversion process. The image data of the frame rate is output, and the display means converts the image data of the second or third frame rate after the first or second conversion processing, which is the same as the frame rate supported by the external codec IC. Based on this, an image is displayed.

According to the present invention, image data obtained by imaging can be output at a predetermined frame rate.
Further, according to the present invention, image data obtained by imaging can be processed at a frame rate that is not related to output, and then converted into a frame rate suitable for output. Both video encoding and high-quality video encoding using an external codec IC can be performed.
Furthermore, according to the present invention, the reference timing of image processing can be performed at a constant timing regardless of the format of a moving image to be output as a video, and further, deterioration of displayed image quality can be eliminated.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a block diagram showing a configuration of the digital camera 51 to which the present invention is applied.

  In addition, the same code | symbol is attached | subjected to the part corresponding to the conventional case, The description is abbreviate | omitted suitably.

  That is, the digital camera 51 of FIG. 2 includes a memory controller 61 instead of the memory controller 14, a CPU 62 instead of the CPU 15, and changes to the display signal processing unit 20 having the synchronization signal generation unit 31. The digital camera 1 basically has the same configuration as that of the digital camera 1 of FIG. 1 except that a display signal processing unit 63 having a synchronization signal generation unit 71 is provided and a codec IC interface 64 is newly provided.

  Also in FIG. 2, as in FIG. 1, in the figure, the solid line indicates transmission / reception of an image signal, the dotted line indicates transmission / reception of a control signal, and the dashed line indicates transmission / reception of a code signal. The two-dot broken line indicates transmission / reception of the synchronization signal.

  In addition to the vertical synchronization signal VD1, which is the first reference signal supplied to the CCD camera unit 11, the signal processing unit 13, and the CPU 62, the synchronization signal generation unit 71 is supplied to the CPU 62 and the codec IC interface 64. The vertical synchronizing signal VD2 and the horizontal synchronizing signal HD1 are generated.

  The vertical synchronization signal VD1 that is the first reference signal corresponds to the vertical synchronization signal VD that is the conventional reference signal, but unlike the conventional case, the vertical synchronization signal VD1 is based on the NTSC or PAL of the output video signal. Instead of generating a frequency, a predetermined frequency such as 60 Hz or 120 Hz is generated. The vertical synchronization signal VD2 and the horizontal synchronization signal HD1, which are the second reference signals, are supplied to the CPU 62 and the codec IC interface 64, and a frequency based on an image format such as PAL or NTSC is generated. . In the following description, it is assumed that the vertical synchronization signal VD1 has a field frequency of 60 Hz (frame frequency of 30 Hz).

  Under the control of the CPU 62, the memory controller 61 writes the input image data into the memory 19 via the bus 16 and records it, or if necessary, the image data recorded in the memory 19 on the bus 16 To the image compression processing unit 17 and the resolution conversion processing unit 18. Further, the memory controller 61 converts the image data recorded in the memory 19 (image data processed by the image compression processing unit 17 or the resolution conversion processing unit 18 as necessary) under the control of the CPU 62. The data is supplied to the display signal processing unit 63 via the bus 16, read out via the bus 16, and output to the drive 23. In these processes, the memory controller 61 records image data at a predetermined address in the memory 19 or reads image data from a predetermined address in the memory 19 based on an address setting signal supplied from the CPU 62.

  In addition, the memory controller 61 outputs the image data processed by the codec IC, which is input via the codec IC interface 64 and the display signal processing unit 63, to the drive 23 and records it on the attached recording medium. .

  The CPU 62 controls the operation of the digital camera 51. From the synchronization signal generation unit 71, the CPU 62 controls a reference timing signal (vertical synchronization signal VD1, which is a first reference signal, and vertical, which is a second reference signal). Receiving the synchronization signal VD2 and the horizontal synchronization signal HD1), generating and outputting control signals for controlling the operations of the signal processing unit 13, the memory controller 61, and the display signal processing unit 63; An address setting signal is generated and output to the memory controller 61.

  The display signal processing unit 63 receives the input of the image data recorded in the memory 19 by the processing of the memory controller 14 and outputs it to the display unit 21 based on the reference signal generated by the synchronization signal generation unit 71 included therein. A signal suitable for display, a signal suitable for output to an external device via the video output interface 22, or a codec IC connected to the outside of the digital camera 51 via a codec IC interface 64. The signal is converted into a signal suitable for output. In addition, the display signal processing unit 63 receives input of image data processed by the codec IC via the codec IC interface 64, and outputs it to the memory 19 under the control of the memory controller 61.

  The reference signals generated by the synchronization signal generator 71 are two series of a vertical synchronization signal VD1 that is a first reference signal, a vertical synchronization signal VD2 that is a second reference signal, and a horizontal synchronization signal HD1. As described above, the vertical synchronization signal VD1 that is the first reference signal is supplied to the CCD camera unit 11, the signal processing unit 13, and the CPU 62, and the second reference signal is supplied to the CPU 62 and the codec IC interface 64. A certain vertical synchronizing signal VD2 and horizontal synchronizing signal HD1 are supplied.

  The codec IC interface 64 is an interface with a codec IC (not shown) connected to the outside of the digital camera 51, and outputs image data supplied from the display signal processing unit 63 to the codec IC and is processed by the codec IC. The received image data is received and supplied to the display signal processing unit 63.

  Further, an image signal subjected to necessary processing is recorded by the processing of the memory controller 61 on the magnetic disk 41, the optical disk 42, the magneto-optical disk 43, or the semiconductor memory 44 mounted in the drive 23. . Further, the recorded program such as the magnetic disk 41, the optical disk 42, the magneto-optical disk 43, or the semiconductor memory 44 mounted on the drive 23 is read and executed by the CPU 62 as necessary, or a memory controller. It is recorded in the memory 19 by the process 61 and read and executed by the CPU 62.

  In such a digital camera 51, in order to improve the frame rate, the image processing in the digital video camera 51 is performed at a constant cycle regardless of the PAL or NTSC of the video output, and the format of the display image on the display unit 21 It is sufficient that the image formats supported by the codec IC are the same and only video output can be arbitrarily performed by PAL or NTSC. If the image processing in the digital video camera 51 is performed at a constant cycle regardless of the video output PAL or NTSC, for example, the performance of an element such as a CCD is improved, so that the output image data Regardless of the frame rate, the frame rate of image processing can be further increased. That is, processing such as software coding can be performed at a higher frame rate.

  In this case, since the display signal processing unit 63 can output an image signal having the number of scanning lines that matches the liquid crystal panel constituting the display unit 21, problems such as image degradation and missing characters in the OSD are solved. be able to. Further, the digital camera 51 can record / reproduce high-quality moving images regardless of the video output format by adopting such a configuration. Then, regardless of whether the image format supported by the codec IC connected to the codec IC interface 64 is the NTSC system or the PAL system, the video output is performed by the device connected to the video output interface 22. The frame rate can be arbitrarily selected by either the NTSC system or the PAL system.

  Next, the operation of the digital video camera 51 will be described.

  At the time of shooting, the CCD camera unit 11 and the signal processing unit 13 receive the input of the vertical synchronization signal VD1 that is the first reference signal generated by the synchronization signal generation unit 71, and at a timing with the field frequency of 60 Hz as the minimum unit. Perform the action.

  The image signal captured by the CCD camera unit 11 is converted into a digital signal by the A / D conversion unit 12 and input to the signal processing unit 13. The signal processing unit 13 performs, for example, gamma processing or processing for converting an RGB signal into a Y / Cb / Cr signal on the input signal, and supplies the processed image data to the memory controller 61. .

  The memory controller 61 writes and records the input image data in the memory 19 via the bus 16 under the control of the CPU 62. Further, the memory controller 61 supplies the image data recorded in the memory 19 to the image compression processing unit 17 and the resolution conversion processing unit 18 via the bus 16 as necessary, and processes them again. To record. The memory controller 61 supplies the image data recorded in the memory 19 to the display signal processing unit 63 via the bus 16 under the control of the CPU 62.

  Here, the image data supplied to the memory controller 61 and recorded in the memory 19 or processed in the image compression processing unit 17 or the resolution conversion processing unit 18 is based on the vertical synchronization signal VD1 which is the first reference signal. The image data has a frame rate of 30 Hz.

  When displaying the input image data, the display signal processing unit 63 outputs to the display unit 21 an image signal having the number of scanning lines that matches the liquid crystal panel constituting the display unit 21. That is, the display signal processing unit 63 converts the input image data having a frame rate of 30 Hz into a format of displayed image data and outputs the converted image data.

  Further, when the input image data is output from the video output interface 22, the display signal processing unit 63 can process the input image data having a frame rate of 30 Hz by a device connected to the video output interface 22. The frame rate is converted to a frame rate that matches a proper image format, and output from the video output interface 22 to the outside.

  When the display signal processing unit 63 outputs the input image data from the codec IC interface 64 to a codec IC (not shown), the codec IC can process the input image data having a frame rate of 30 Hz. The frame rate is converted to an image format frame rate and output to the codec IC interface 64.

  Further, in the reproduction processing by the processing of the codec IC, the display signal processing unit 63 receives the reproduction image data of the image format that can be processed by the codec IC from the codec IC interface 64, and enters the memory 19 through the bus 16. Output. The display signal processing unit 63 reads out the reproduced image signal recorded in the memory 19 according to the address control by the memory controller 61, and outputs it to the display unit 22 configured to display an image in the same image format. Then, the image data is converted into a frame rate that matches an image format that can be processed by a device connected to the video output interface 22 and output from the video output interface 22 to the outside.

  A frame rate conversion process at the time of image recording will be described with reference to FIGS.

  As shown in FIG. 3, the frame rate of the 30 Hz frame 81 having a frame frequency of 30 Hz and the 29.97 Hz frame 82 by NTSC, which is generated by performing signal processing in the signal processing unit 13, is 1001: 1000. There is a proportional relationship. Accordingly, the display signal processing unit 63 thins out one image from 1001 images of the 30 Hz frame 81 supplied from the memory controller 61, thereby converting the 30 Hz frame 81 having the frame frequency of 30 Hz into the NTSC frame rate. A process of converting to a 97 Hz frame 82 is executed.

  For example, when the display format of the display unit 21 and the format of the image data that can be processed by the codec IC are the NTSC system, the input 30 Hz frame 81 is converted to the 29. After being converted to the 97 Hz frame 82, it is output to the codec IC interface 64 or output to the display unit 21 and displayed. In this case, as shown in FIG. 3, the 1001st frame of the 30 Hz frame 81 and the 1000th frame of the 29.97 Hz frame 82 by NTSC are the same time, so the 1000th frame of the 30 Hz frame 81 is It is not displayed because it is thinned out when converting to NTSC.

  Similarly, as shown in FIG. 4, since the PAL is 25 Hz with respect to the 30 Hz frame 81 having the frame frequency of 30 Hz, the display signal processing unit 63 is connected to the 30 Hz frame 81 supplied by the memory controller 61. By thinning out one of the six images, it can be converted into a 25 Hz frame 91 having a PAL frame rate.

  For example, when the display format of the display unit 21 and the format of image data that can be processed by the codec IC are the PAL system, the input 30 Hz frame 81 in the display signal processing unit 63 is a 25 Hz frame of the PAL system. After being converted to 91, it is output to the codec IC interface 64 or output to the display unit 21 and displayed. In this case, as shown in FIG. 4, the sixth frame of the 30 Hz frame 81 and the fifth frame of the 25 Hz frame 91 by PAL have the same time, so the fifth frame of the 30 Hz frame 81 goes to the PAL. Is not displayed when thinned out.

  In such a conversion process, in order to prevent overtaking of an image due to thinning out, an area for temporarily storing frame images in the display signal processing unit 63 is provided for at least three frames (shown in FIGS. 3 and 4). It is only necessary to provide frames A, B, and C).

  Also, when the recorded image data is output as video from the video output interface 22, the input 30 Hz frame 81 is converted to the NTSC format 29 by the same process as described with reference to FIGS. .97 Hz frame 82 or PAL 25 Hz frame 91 can be converted into a conversion, so that display signal processing unit 63 processes input 30 Hz frame 81 by a device connected to video output interface 22. It can be converted to a frame rate that matches a possible image format and output from the video output interface 22 to the outside.

  By performing such conversion, even when the video output and the processing format of the codec IC are different, signals of appropriate frame rates are supplied and suitable for the number of scanning lines such as liquid crystal panels used for display. Display processing can be performed at a different frame rate.

  Next, the conversion process at the time of reproducing the codec IC will be described. FIG. 5 illustrates frame rate conversion when the codec IC playback mode is NTSC and the video output is NTSC and PAL. The operation of the digital camera 51 in this case will be described.

  Based on the vertical synchronization signal VD1 that is the first reference signal, that is, the CPU 62 sets an address setting indicating which surface of the memory 19 the input image from the codec IC is stretched in a frame A, The memory controller 61 is controlled so that the frames B, C, D, and E are performed in this order. Then, the set address is latched at the timing of NTSC by the processing of the display signal processing unit 63, and the actual address is determined. That is, an address that is not reflected is generated once per 1001 times with respect to an address set at a cycle of 30 Hz, so that surface is skipped and an image is written on the next surface.

  As shown in FIG. 5, the CPU 62 sets the C plane at the 1000th frame of the CPU setting frame 101, but in the actual writing plane 102, the C plane is skipped, and the D is next to the B plane. An image is written on the surface. By re-latching the writing surface 102 at this time at the frame rate of the actual video output, as shown on the video output NTSC display surface 103 or the video output PAL display surface 104, the video output surface (frame) is displayed. ) Is determined.

  When the video output from the video output interface 22 is in the PAL format, the codec IC playback mode is NTSC (frame rate is 29.97 Hz), so the frame rate of the output image data is shown in FIG. In other words, after converting to 30 Hz once by adding one frame out of 1001 frames that have been thinned out, 1 in 6 frames is used as described with reference to FIG. Frames are thinned out and converted to a PAL frame rate of 25 Hz.

  When both the playback mode of the codec IC and the video output from the video output interface 22 are NTSC, in order not to cause overtaking, the display signal processing unit 63 has an area for temporarily storing images for this processing in 4 frames. Just prepare. On the other hand, when the playback mode of the codec IC is the NTSC system and the video output from the video output interface 22 is the PAL system, the display signal processing unit 63 performs this process in order to prevent overtaking. It is necessary to provide an area for temporarily storing images for 5 frames. Therefore, when the video output from the video output interface 22 is to be compatible with both NTSC and PAL, the display signal processing unit 63 must be provided with an area for temporarily storing images for five frames.

FIG. 6 shows an example of a circuit configuration for setting an address for executing the thinning process. Address setting circuit 111 of FIG. 6, the flip-flops 121-1 to 121-6 is a D flip-flop of the enable with, and is composed of selectors 122 1 and 122 -2, in particular, at the time of shooting and the codec IC regeneration In order to cope with both, a circuit for generating a VIDEO AD signal is provided with a selector 122-1, which is a selector for an address on the codec IC side. In FIG. 6, the flip-flops 121-1 to 121-6, as well, it is not shown in the clock input terminals of the selectors 122 1 and 122 2.

  FIG. 7 shows a truth table of the flip-flops 121-1 to 121-6. The flip-flops 121-1 to 121-6 are D flip-flops with an enable that outputs input data at a clock edge (for example, the rising timing of the input clock).

Figure 8 shows a truth table of the selector 122 1 and 122 2. Selectors 122 1 and 121 - 2, when the S terminal (selector input terminals) input is L (i.e. 0) 0 outputs the input logic input terminal, S terminal input H (i.e. 1 ), The logic input to one input terminal is output.

  Returning to FIG. 6, the operation of the address setting circuit 111 will be described. At the time of shooting, the CPU 62 sets the memory addresses of A, B, and C at a 30 Hz cycle as VIDEO AD and codec IC AD. FIG. 9 shows shooting modes and control signals. An EN (enable) signal is input to EN1 once every 30 Hz. An EN signal having a 29.97 Hz cycle is input to EN2 if the video output is NTSC, and a 25 Hz cycle EN signal is input if the video output is PAL. EN3 is input with an EN signal having a cycle of 29.97 Hz if the processing of the codec IC (codec mode) is NTSC and 25 Hz if the processing is PAL.

In the circuit of FIG. 6, VIDEO AD is input to the flip-flop 121-1, and EN1 is given as an EN signal. The output of the flip-flop 121-1, CONT1 to the S terminal is supplied to the 0 input terminal of the selector 122 -1 supplied. Here, 0 is input to CONT1 at the time of shooting. Therefore, the output from the selector 122 -1, since the output from the flip-flop 121-1, at the time of photographing, the input of CONT2 is irrelevant. The output of the selector 122 -1 is input to the flip-flop 121-2, as an EN signal of the flip-flop 121-2, EN2 is given. The output of the flip-flop 121-2 is output as VIDEO AD OUT for the memory controller 16 to set the video output address.

  Further, the codec IC AD is input to the flip-flop 121-3, and EN1 is given as the EN signal. The output of the flip-flop 121-3 is input to the flip-flop 121-4 to which EN3 is given as the EN signal. The output of the flip-flop 121-4 is output as a codec IC AD OUT for setting the address of the codec IC.

  Similarly, during playback processing using the codec IC, the CPU 62 writes addresses A, B, C, D, and E as a codec IC AD in a cycle of 30 Hz. FIG. 10 shows modes and control signals during reproduction processing using the codec IC. EN1 has an EN signal once every 30 Hz, EN2 has a 29.97 Hz cycle if the video output is NTSC, 25 Hz if the video output is PAL, EN3 has a 29 Hz cycle if the codec mode is NTSC. In the case of 97 Hz period and PAL, an EN signal having a period of 25 Hz is input.

In the circuit of FIG. 6, the codec IC AD is input to the flip-flop 121-3, and EN1 is given as the EN signal. The output of the flip-flop 121-3 is input to the flip-flop 121-4 to which EN3 is given as the EN signal. The output of the flip-flop 121-4 is output as CODEC IC AD OUT to set the address of the codec IC, CONT2 to the S terminal is supplied to the 0 input terminal of the selector 122 -1 supplied, and, EN signal Is input to the flip-flop 121-5 to which EN1 is given. The output of the flip-flop 121-5 is input to the flip-flop 121-6 to which EN1 is given as the EN signal.

The output of the flip-flop 121-6 is, CONT2 to the S terminal is supplied to one input terminal of the selector 122 -1 supplied. When the video output and the codec mode of the codec IC are different, 1 is input to CONT2, so that the output of the selector 122-2 becomes the output of the flip-flop 121-6. The address indicated by the output of the selector 122-2 is obtained by changing the latest address for which writing has been completed from the codec IC to 30 Hz.

The output of the selector 122-2 is input to one input terminal of the selector 122-1, but 1 is input to CONT1 during the reproduction process using the codec IC. Output from selector 122-1. The output of the selector 122 -1 is input to the flip-flop 121-2, as an EN signal of the flip-flop 121-2, EN2 is given. The output of the flip-flop 121-2 is output as VIDEO AD for the memory controller 61 to set the video output address.

On the other hand, when the video output and the codec mode of the codec IC are the same, since 0 is input to CONT2, the output of the selector 122-2 becomes the output of the flip-flop 121-4, and the output of the selector 122-2 Is output from the selector 122-1. The output of the selector 122 -1 is input to the flip-flop 121-2, as an EN signal of the flip-flop 121-2, EN2 is given. The output of the flip-flop 121-2 is output as VIDEO AD for the memory controller 61 to set the video output address.

  Regarding the frame rate conversion processing described above, the conversion of the frame rate for each video output when the codec mode of the codec IC and the display format of the display unit 21 are NTSC will be described with reference to FIGS. . In FIGS. 11 to 14, illustrations other than the memory 19, the display signal processing unit 63, the display unit 21, the video output interface 22, and the codec IC interface 64 are omitted.

  In the image data recording process when the video output is NTSC, as shown in FIG. 11, the display signal processing unit 63 records image data with a frame rate of 30 Hz recorded in the memory 19 via the bus 16. The frame rate is converted to NTSC 29.97 Hz by the above-described conversion method, and is output to the display unit 21, the video output interface 22, and the codec IC interface 64.

  In the image data recording process when the video output is PAL, the display signal processing unit 63, as shown in FIG. 12, stores image data with a frame rate of 30 Hz recorded in the memory 19 via the bus 16. The frame rate is converted to NTSC 29.97 Hz by the conversion method described above, output to the display unit 21 and the codec IC interface 64, and the frame rate is converted to PAL 25 Hz. To the video output interface 22.

  In the reproduction process using the codec IC when the video output is NTSC, the display signal processing unit 63 inputs NTSC image data with a frame rate of 29.97 Hz from the codec IC interface 64 as shown in FIG. receive. The NTSC image data is written into the memory 19 via the bus 16 by processing of the memory controller 61. The display signal processing unit 63 receives the NTSC image data written in the memory 19 and having a frame rate of 29.97 Hz, and outputs it to the display unit 21 and the video output interface 22 without conversion. .

  In the reproduction process using the codec IC when the video output is PAL, as shown in FIG. 14, the display signal processing unit 63 inputs NTSC image data with a frame rate of 29.97 Hz from the codec IC interface 64. receive. The NTSC image data is written into the memory 19 via the bus 16 by processing of the memory controller 61. The display signal processing unit 63 receives the NTSC image data written in the memory 19 and having a frame rate of 29.97 Hz. The display signal processing unit 63 outputs the NTSC image data without conversion to the display unit 21 and outputs the frame rate of 29.97 Hz. The NTSC image data is once converted into image data with a frame rate of 30 Hz, and then the frame rate is converted into PAL of 25 Hz and output to the video output interface 22.

  As described above, processing is performed based on a predetermined timing (for example, 60 Hz) irrespective of the frame rate of the output format at the time of shooting and playback, and the frame rate conversion of the image data to NTSC or PAL is output. Therefore, a moving image with a high frame rate can be taken regardless of the video output mode, and recording / reproduction using a codec IC can be performed.

  In addition, at the time of shooting and playback, processing such as image data capture and software coding can be designed to operate in a predetermined timing unit such as 30 Hz regardless of the video output mode. Software design becomes easy and costs can be reduced.

  Further, regarding the image quality of the image displayed on the display unit 21, for example, when the processing format of the codec IC is NTSC, the number of scanning lines such as a liquid crystal panel constituting the display unit 21 is also NTSC compatible. Since it is sufficient to always display a signal converted into NTSC, it is possible to output an image without image quality deterioration such as lack of OSD.

  The series of processes described above can also be executed by software. The software is a computer in which the program constituting the software is incorporated in dedicated hardware, or various functions can be executed by installing various programs, for example, a general-purpose personal computer For example, it is installed from a recording medium.

  As shown in FIGS. 1 and 2, the recording medium is distributed to provide a program to the user separately from the computer, and includes a magnetic disk 41 (including a flexible disk) on which the program is recorded, an optical disk 42 (including CD-ROM (compact disk-read only memory), DVD (digital versatile disk)), magneto-optical disk 43 (including MD (mini-disk) (trademark)), or semiconductor memory 44 Consists of media.

  Further, in the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.

It is a block diagram which shows the structure of the conventional digital camera. It is a block diagram which shows the structure of the digital camera to which this invention is applied. It is a figure which shows the relationship between a 30Hz frame and the 29.97Hz frame of NTSC. It is a figure which shows the relationship between a 30 Hz frame and a 25 Hz frame of PAL. It is a figure explaining the frame conversion at the time of reproduction | regeneration by a codec IC. It is a figure which shows the example of the circuit structure for addressing of a memory. It is a figure for demonstrating operation | movement of D flip-flop. It is a figure for demonstrating operation | movement of a selector. It is a figure for demonstrating the control signal at the time of imaging | photography. It is a figure for demonstrating the control signal at the time of the reproduction | regeneration by a codec IC. It is a figure for demonstrating operation | movement of the display signal process part of FIG. It is a figure for demonstrating operation | movement of the display signal process part of FIG. It is a figure for demonstrating operation | movement of the display signal process part of FIG. It is a figure for demonstrating operation | movement of the display signal process part of FIG.

Explanation of symbols

  11 CCD camera section, 12 A / D conversion section, 13 signal processing section, 17 image compression processing section, 18 resolution conversion processing section, 19 memory, 21 display section, 22 video output interface, 61 memory controller, 62 CPU, 63 display Signal processor, 64 codec IC interface, 71 synchronization signal generator

Claims (1)

Imaging means for imaging a subject image at a first frame rate determined in advance;
Displaying an image based on image data having a second frame rate lower than the first frame rate or a third frame rate lower than the first frame rate and different from the second frame rate. Display means to perform;
Video output means for outputting the image data of the second frame rate or the image data of the third frame rate to an external device;
Connection means for connecting to an external codec IC and inputting / outputting image data of the second frame rate or the third frame rate;
A first frame rate conversion process for converting the image data of the first frame rate into the image data of the second frame rate by thinning out the image at a rate of one per 1001 sheets, 1 in 6 A second frame rate conversion process for converting the image data of the first frame rate into the image data of the third frame rate by thinning out at a rate of one sheet, adding one image per 1000 sheets Thus, the third frame rate conversion process for converting the image data of the second frame rate into the image data of the first frame rate, and adding the image of one sheet to five sheets, the third Conversion means for performing a fourth frame rate conversion process for converting image data of the frame rate into image data of the first frame rate;
One of the first to fourth frame rate conversion processes corresponding to the frame rate supported by the external codec IC is applied to the conversion means for image data input / output to / from the external codec IC. The frame rate of the image to be executed and displayed on the display unit is set to the same frame rate as that of the external codec IC, and the external device processes the frame rate of the image output from the video output unit. In order to set the second or third frame rate possible, and to convert the image data of the first frame rate into image data of the set frame rate, the conversion means is provided with the first or second frame. An imaging device comprising: control means for performing control for executing rate conversion processing.

Images