JP2009098431A - Display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device of a control system capable of dividing a period into a signal write period and a mobility correction period. <P>SOLUTION: A sampling transistor Tr1 is switched on according to a control signal supplied to a scan line WS, when a signal line SL is in a signal potential Vsig, and a supply line VL is in a floating state, and the signal potential Vsig is sampled from the signal line SL and written in a holding capacitance Cs. In a drive transistor Trd, within a period after the supply line VL is changed from the floating state to the power supply state, while the sampling transistor Tr1 remains in an on-state, until the sampling transistor Tr1 is switched off, negative feed-back of a current which flows in the drive transistor Trd, to the holding capacitor Cs is performed, and thereby, variations in mobility of the drive transistor Trd are corrected. A light emitting element EL emits light according to the current supplied from the drive transistor Trd, after the sampling transistor Tr1 is switched off. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device using a light emitting element for a pixel. The present invention also relates to an electronic device provided with this type of display device.

  In a display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel according to image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A JP 2006-215213 A

  A conventional pixel circuit is arranged at a portion where a row scanning line supplying a control signal and a column signal line supplying a video signal intersect, and includes at least a sampling transistor, a storage capacitor, a drive transistor, and a light emitting element. . The sampling transistor conducts in response to the control signal supplied from the scanning line and samples the video signal supplied from the signal line. The holding capacitor holds an input voltage corresponding to the signal potential of the sampled video signal. The drive transistor supplies an output current as a drive current during a predetermined light emission period according to the input voltage held in the holding capacitor. In general, the output current depends on the carrier mobility and threshold voltage of the channel region of the drive transistor. The light emitting element emits light with luminance according to the video signal by the output current supplied from the drive transistor.

  The drive transistor receives the input voltage held in the holding capacitor at the gate that is the control end, passes an output current between the source and drain that is the current end, and energizes the light emitting element. In general, the light emission luminance of a light emitting element is proportional to the amount of current applied. Further, the output current supply amount of the drive transistor is controlled by the gate voltage, that is, the input voltage written in the storage capacitor. The conventional pixel circuit controls the amount of current supplied to the light emitting element by changing the input voltage applied to the gate of the drive transistor in accordance with the input video signal.

Here, the operating characteristic of the drive transistor is expressed by the following characteristic equation.
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) ²
In this transistor characteristic formula, Ids represents a drain current flowing between the source and the drain, and is an output current supplied to the light emitting element in the pixel circuit. Vgs represents a gate voltage applied to the gate with reference to the source, and is the above-described input voltage in the pixel circuit. Vth is the threshold voltage of the transistor. Μ represents the mobility of the semiconductor thin film constituting the channel of the transistor. In addition, W represents the channel width, L represents the channel length, and Cox represents the gate capacitance. As is apparent from this transistor characteristic equation, when the thin film transistor operates in the saturation region, if the gate voltage Vgs increases beyond the threshold voltage Vth, the thin film transistor is turned on and the drain current Ids flows. In principle, as the above transistor characteristic equation shows, the same amount of drain current Ids is always supplied to the light emitting element if the gate voltage Vgs is constant. Therefore, if video signals of the same level are supplied to all the pixels constituting the screen, all the pixels should emit light with the same luminance, and the uniformity of the screen should be obtained.

  However, in reality, thin film transistors (TFTs) composed of semiconductor thin films such as polysilicon have variations in individual device characteristics. In particular, the threshold voltage Vth is not constant and varies from pixel to pixel. As apparent from the transistor characteristic equation described above, if the threshold voltage Vth of each drive transistor varies, even if the gate voltage Vgs is constant, the drain current Ids varies, and the luminance varies from pixel to pixel. The screen uniformity is damaged. Conventionally, a pixel circuit incorporating a function for canceling variations in threshold voltages of drive transistors has been developed, and is disclosed in, for example, Patent Document 3 described above.

  However, the variation factor of the output current with respect to the light emitting element is not only the threshold voltage Vth of the drive transistor. As is apparent from the above transistor characteristic equation, the output current Ids varies even when the mobility μ of the drive transistor varies. As a result, the uniformity of the screen is impaired. Conventionally, a pixel circuit incorporating a function for correcting a variation in mobility of a drive transistor has been developed, and for example, disclosed in Patent Document 6 described above.

  A conventional pixel circuit simultaneously performs a signal writing operation for sampling a video signal and writing it to a storage capacitor, and a mobility correction operation. In the mobility correction, the signal potential is applied to the gate that is the control terminal of the drive transistor, and the current flowing between the drain and the source that is a pair of current terminals is negatively fed back to the storage capacitor, thereby driving the mobility of the drive transistor. The variation is canceled. Due to such an operation sequence relationship, the conventional display device is configured to simultaneously perform the signal writing operation and the mobility correction operation.

  However, even though the optimal signal writing period and the optimal mobility correction period are not necessarily the same, the conventional display device always performs the signal writing operation and the mobility correction operation during the same period, so that the optimal operation state is not necessarily required. There was a problem that could not be secured. For example, as the pixels of a display device become higher in definition and density, the mobility correction time needs to be shortened for optimization while ensuring a certain signal writing time. Since the conventional display device cannot separate the signal writing time and the mobility correction time, it cannot meet the above-mentioned request and cannot cope with the high definition and high density of the display device.

  In view of the above-described problems of the conventional technology, an object of the present invention is to provide a control-type display device that can divide a signal writing period and a mobility correction period. In order to achieve this purpose, the following measures were taken. That is, the display device according to the present invention includes a pixel array unit and a drive unit, and the pixel array unit includes a row-shaped scanning line, a column-shaped signal line, and a portion where each scanning line and each signal line intersect. A matrix of pixels arranged in parallel to each scanning line, and a feeder line arranged in parallel with each scanning line, each pixel including at least a sampling transistor, a drive transistor, a storage capacitor, and a light emitting element, and the sampling The transistor has a control end connected to the scanning line, a pair of current ends connected between the signal line and the control end of the drive transistor, and the drive transistor has one of a pair of current ends. The light emitting element is connected, the other is connected to the power supply line, the holding capacitor is connected between the control terminal and the current terminal of the drive transistor, and the driving unit sequentially supplies a control signal to at least each scanning line. Shi A light scanner that performs line sequential scanning, a signal selector that switches and supplies signal potential and reference potential to each signal line in synchronization with line sequential scanning, and a power supply state and a floating state for each power supply line according to line sequential scanning The sampling transistor is turned on in response to a control signal supplied to the scanning line when the signal line is at a signal potential and the power supply line is in a floating state. The potential is sampled and written to the storage capacitor, and the drive transistor is in a period from when the sampling transistor is continuously turned on to when the power supply line is switched from the floating state to the power supply state until the sampling transistor is turned off. And negatively feeding back the current flowing through the drive transistor to the storage capacitor, Correcting the variation of the mobility of data, the light emitting element, the sampling transistor after turning off, characterized in that it emits light in response to current supplied from the drive transistor.

  Preferably, the power scanner includes a shift register that outputs an input signal for each stage in accordance with line sequential scanning, and a buffer disposed between each stage of the shift register and each feeder line corresponding thereto. The buffer switches the corresponding power supply line between the floating state and the power supply state in accordance with the input signal. The power scanner has a switch corresponding to each power supply line, and switches each power supply line between a floating state and a power supply state by controlling each switch on and off in accordance with the line sequential scanning. The sampling transistor is turned on in response to a control signal supplied to the scanning line when the signal line is at a reference potential and the power supply line is at a predetermined fixed potential, and the control terminal of the drive transistor is set at the reference potential. Then, the current end of the drive transistor is set to a fixed potential, and the power scanner returns the power supply line from the fixed potential to the power supply state and flows the current until the drive transistor is cut off. A voltage corresponding to the threshold voltage is held in the holding capacitor.

  According to the present invention, in the signal writing period, the power supply line for the pixel is set in a floating state, the sampling transistor is turned on, and the video signal is written from the signal line to the control terminal (gate) of the drive transistor. At this time, since the power supply line is in a floating state, no current flows through the drive transistor while the video signal is written to the storage capacitor, so that the mobility correction operation is not performed. Thereafter, when the signal potential of the video signal is sufficiently written in the storage capacitor, the power supply line is switched from the floating state to the power supply state, and current is supplied to the pixel. As a result, the drive transistor performs a desired mobility correction operation by negatively feeding back the current to the storage capacitor in a state where the signal potential of the video signal is applied to its gate. With this operation sequence, the signal potential writing period and the mobility correction period can be divided, and each period can be optimally adjusted. Accordingly, it becomes possible to cope with high definition and high density of the display device, and high image quality can be achieved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Before that, in order to facilitate understanding of the present invention and clarify the background, a display device according to prior development will be described as a reference example. FIG. 1 is a block diagram showing the overall configuration of a display device according to this reference example. As shown in the figure, the display device includes a pixel array unit 1 and a drive unit that drives the pixel array unit 1. The pixel array section 1 corresponds to a row-shaped scanning line WS, a column-shaped signal line (signal line) SL, a matrix-shaped pixel 2 arranged at a portion where both intersect, and each row of each pixel 2. The power supply line (power supply line) VL is provided. In this example, any one of the three RGB primary colors is assigned to each pixel 2, and color display is possible. However, the present invention is not limited to this, and includes a monochrome display device. The drive unit sequentially supplies a control signal to each scanning line WS to scan the pixels 2 line-sequentially in units of rows, and the first potential and the second potential to each power supply line VL in accordance with the line sequential scanning. And a signal selector (horizontal selector) 3 for supplying a signal potential as a drive signal and a reference potential to the column-like signal lines SL in accordance with the line sequential scanning. Yes.

  FIG. 2 is a circuit diagram showing a specific configuration and connection relationship of the pixel 2 included in the display device according to the prior development shown in FIG. As illustrated, the pixel 2 includes a light emitting element EL represented by an organic EL device, a sampling transistor Tr1, a drive transistor Trd, and a storage capacitor Cs. The control terminal (gate) of the sampling transistor Tr1 is connected to the corresponding scanning line WS, one of the pair of current terminals (source and drain) is connected to the corresponding signal line SL, and the other is connected to the control terminal of the drive transistor Trd. Connect to (Gate G). In the drive transistor Trd, one of a pair of current ends (source S and drain) is connected to the light emitting element EL, and the other is connected to the corresponding power supply line VL. In this example, the drive transistor Trd is an N-channel type, and its drain is connected to the power supply line VL, while the source S is connected to the anode of the light emitting element EL as an output node. The cathode of the light emitting element EL is connected to a predetermined cathode potential Vcath. The storage capacitor Cs is connected between the source S that is one of the current ends of the drive transistor Trd and the gate G that is the control end.

  In such a configuration, the sampling transistor Tr1 is turned on in response to a control signal supplied from the scanning line WS, samples the signal potential supplied from the signal line SL, and holds it in the holding capacitor Cs. The drive transistor Trd is supplied with current from the power supply line VL at the first potential (high potential Vcc), and flows drive current to the light emitting element EL in accordance with the signal potential held in the holding capacitor Cs. The write scanner 4 outputs a control signal having a predetermined pulse width to the control line WS in order to bring the sampling transistor Tr1 into a conductive state in a time zone in which the signal line SL is at the signal potential, and thus the signal potential to the holding capacitor Cs. At the same time, a correction for the mobility μ of the drive transistor Trd is added to the signal potential. Thereafter, the drive transistor Trd supplies a drive current corresponding to the signal potential Vsig written in the storage capacitor Cs to the light emitting element EL, and starts a light emitting operation.

  The pixel circuit 2 has a threshold voltage correction function in addition to the mobility correction function described above. That is, the power supply scanner 6 switches the power supply line VL from the first potential (high potential Vcc) to the second potential (low potential Vss2) at the first timing before the sampling transistor Tr1 samples the signal potential Vsig. Similarly, the write scanner 4 applies the reference potential Vss1 from the signal line SL to the gate G of the drive transistor Trd from the signal line SL by making the sampling transistor Tr1 conductive at the second timing before the sampling transistor Tr1 samples the signal potential Vsig. The source S of Trd is set to the second potential (Vss2). The power supply scanner 6 switches the power supply line VL from the second potential Vss2 to the first potential Vcc at a third timing after the second timing, and holds a voltage corresponding to the threshold voltage Vth of the drive transistor Trd in the holding capacitor Cs. With this threshold voltage correction function, the display device can cancel the influence of the threshold voltage Vth of the drive transistor Trd that varies from pixel to pixel.

  The pixel circuit 2 further has a bootstrap function. That is, the write scanner 4 cancels the application of the control signal to the scanning line WS at the stage where the signal potential Vsig is held in the holding capacitor Cs, and the sampling transistor Tr1 is turned off to connect the gate G of the drive transistor Trd from the signal line SL. By electrically disconnecting, the potential of the gate G is interlocked with the potential fluctuation of the source S of the drive transistor Trd, and the voltage Vgs between the gate G and the source S can be maintained constant.

  FIG. 3 is a timing chart for explaining the operation of the pixel circuit 2 according to the prior development shown in FIG. The time axis is shared, and the potential change of the scanning line WS, the potential change of the power supply line VL, and the potential change of the signal line SL are represented. In parallel with these potential changes, the potential changes of the gate G and the source S of the drive transistor are also shown.

  A control signal pulse for turning on the sampling transistor Tr1 is applied to the scanning line WS. This control signal pulse is applied to the scanning line WS in one field (1f) cycle in accordance with the line sequential scanning of the pixel array section. This control signal pulse includes two pulses during one horizontal scanning period (1H). The first pulse may be referred to as a first pulse P1, and the subsequent pulse may be referred to as a second pulse P2. Similarly, the power supply line VL is switched between the high potential Vcc and the low potential Vss2 in one field period (1f). The signal line SL is supplied with a drive signal for switching between the signal potential Vsig and the reference potential Vss1 within one horizontal scanning period (1H).

  As shown in the timing chart of FIG. 3, the pixel enters the non-light emission period of the field from the light emission period of the previous field, and then becomes the light emission period of the field. During this non-emission period, a preparation operation, a threshold voltage correction operation, a signal writing operation, a mobility correction operation, and the like are performed.

  In the light emission period of the previous field, the power supply line VL is at the high potential Vcc, and the drive transistor Trd supplies the drive current Ids to the light emitting element EL. The drive current Ids flows from the power supply line VL at the high potential Vcc through the light emitting element EL through the drive transistor Trd to the cathode line.

  Subsequently, when the non-light-emission period of the field starts, the power supply line VL is first switched from the high potential Vcc to the low potential Vss2 at timing T1. As a result, the power supply line VL is discharged to Vss2, and the potential of the source S of the drive transistor Trd drops to Vss2. As a result, the anode potential of the light emitting element EL (that is, the source potential of the drive transistor Trd) is in a reverse bias state, so that the drive current does not flow and the light is turned off. Further, the potential of the gate G also drops in conjunction with the potential drop of the source S of the drive transistor.

  Subsequently, at timing T2, the sampling transistor Tr1 becomes conductive by switching the scanning line WS from the low level to the high level. At this time, the signal line SL is at the reference potential Vss1. Therefore, the potential of the gate G of the drive transistor Trd becomes the reference potential Vss1 of the signal line SL through the conducting sampling transistor Tr1. At this time, the potential of the source S of the drive transistor Trd is at a potential Vss2 that is sufficiently lower than Vss1. In this way, the voltage Vgs between the gate G and the source S of the drive transistor Trd is initialized so as to be larger than the threshold voltage Vth of the drive transistor Trd. A period T1-T3 from the timing T1 to the timing T3 is a preparation period in which the gate G / source S voltage Vgs of the drive transistor Trd is set to Vth or higher in advance.

  Thereafter, at timing T3, the power supply line VL changes from the low potential Vss2 to the high potential Vcc, and the potential of the source S of the drive transistor Trd starts to rise. Eventually, the current is cut off when the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes the threshold voltage Vth. In this way, a voltage corresponding to the threshold voltage Vth of the drive transistor Trd is written into the storage capacitor Cs. This is the threshold voltage correction operation. At this time, the cathode potential Vcath is set so that the light emitting element EL is cut off in order to prevent the current from flowing to the storage capacitor Cs and not to the light emitting element EL.

  At timing T4, the scanning line WS returns from the high level to the low level. In other words, the first pulse P1 applied to the scanning line WS is released, and the sampling transistor is turned off. As is clear from the above description, the first pulse P1 is applied to the gate of the sampling transistor Tr1 in order to perform the threshold voltage correction operation.

  Thereafter, the signal line SL is switched from the reference potential Vss1 to the signal potential Vsig. Subsequently, at timing T5, the scanning line WS rises again from the low level to the high level. In other words, the second pulse P2 is applied to the gate of the sampling transistor Tr1. As a result, the sampling transistor Tr1 is turned on again, and the signal potential Vsig is sampled from the signal line SL. Therefore, the potential of the gate G of the drive transistor Trd becomes the signal potential Vsig. Here, since the light emitting element EL is initially in the cut-off state (high impedance state), the current flowing between the drain and the source of the drive transistor Trd flows exclusively into the holding capacitor Cs and the equivalent capacity of the light emitting element EL and starts charging. Thereafter, by the timing T6 when the sampling transistor Tr1 is turned off, the potential of the source S of the drive transistor Trd rises by ΔV. In this way, the signal potential Vsig of the video signal is written to the storage capacitor Cs in a form added to Vth, and the mobility correction voltage ΔV is subtracted from the voltage stored in the storage capacitor Cs. Therefore, the period T5-T6 from the timing T5 to the timing T6 becomes a signal writing period & mobility correction period. In other words, when the second pulse P2 is applied to the scanning line WS, a signal writing operation and a mobility correction operation are performed. The signal writing period & mobility correction period T5-T6 is equal to the pulse width of the second pulse P2. That is, the pulse width of the second pulse P2 defines the mobility correction period.

  In this way, in the signal writing period T5-T6, the signal voltage is written to Vsig and the correction amount ΔV is adjusted simultaneously. As Vsig increases, the current Ids supplied from the drive transistor Trd increases and the absolute value of ΔV also increases. Therefore, mobility correction is performed according to the light emission luminance level. When Vsig is constant, the absolute value of ΔV increases as the mobility μ of the drive transistor Trd increases. In other words, the larger the mobility μ is, the larger the negative feedback amount ΔV with respect to the storage capacitor Cs is, so that variations in the mobility μ for each pixel can be removed.

  Finally, at timing T6, as described above, the scanning line WS shifts to the low level side, and the sampling transistor Tr1 is turned off. This state is schematically shown in FIG. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. At this time, the drain current Ids starts to flow through the light emitting element EL as shown in FIG. As a result, the anode potential of the light emitting element EL rises according to the drive current Ids. The increase in the anode potential of the light emitting element EL is none other than the increase in the potential of the source S of the drive transistor Trd. When the potential of the source S of the drive transistor Trd rises, the potential of the gate G of the drive transistor Trd also rises in conjunction with the bootstrap operation of the storage capacitor Cs. The amount of increase in gate potential is equal to the amount of increase in source potential. Therefore, the input voltage Vgs between the gate G and the source S of the drive transistor Trd is kept constant during the light emission period. The value of the gate voltage Vgs is obtained by correcting the signal potential Vsig with the threshold voltage Vth and the movement amount μ. The drive transistor Trd operates in the saturation region. That is, the drive transistor Trd outputs a drive current Ids according to the input voltage Vgs between the gate G and the source S. The value of the gate voltage Vgs is obtained by correcting the signal potential Vsig with the threshold voltage Vth and the movement amount μ.

  FIG. 5 is an enlarged schematic view of the power supply scanner 6 of the display device according to the prior development shown in FIG. As shown in the figure, the power supply scanner 6 has an output buffer composed of an inverter for each stage corresponding to each power supply line VL. The power supply line VL is set to the high potential Vcc while matching the line sequential scanning according to the input signal IN. And the low potential Vss2. The input signal IN supplied to the output buffer is sequentially supplied for each stage from a shift register (not shown) incorporated in the power supply scanner 6. When the input signal IN is at a low level, the P-channel transistor side of the inverter constituting the output buffer is turned on, and the high potential Vcc is applied to the power supply line VL. This is a power supply state, and the pixels 2 on the pixel array section 1 side are basically placed in a light emitting state. On the other hand, when the input signal IN is switched to the high level, the N channel transistor side of the inverter is turned on, and the low potential Vss2 is applied to the power supply line VL. At this time, the light emitting element EL on the pixel array section 1 side is basically placed in a non-light emitting state.

  The display device according to the above-described prior development example simultaneously performs the signal writing operation and the mobility correction operation when the second control pulse P2 is applied to the scanning line WS from the light scanner. Referring to the timing chart of FIG. 3, a period T5-T6 that is just equal to the pulse width of the control pulse P2 corresponds to the signal writing and mobility correction time. In the display device according to the prior development, since the signal writing period and the mobility correction period are not separated, it is difficult to cope with high definition and high density of the display device.

  FIG. 6 shows an embodiment of a display device according to the present invention, which is configured to cope with the problems of the above-described prior development example. Basically, it is the same as the prior development example shown in FIGS. 2 and 5, and corresponding parts are denoted by corresponding reference numerals for easy understanding. A particularly different point is the configuration of the power supply scanner 6. As apparent from the comparison with the power scanner 6 of the prior development example shown in FIG. 5, the configuration of the output buffer is different.

  As shown in FIG. 6, the display device according to the present invention basically includes a pixel array unit 1 and a drive unit. The pixel array unit 1 includes a row-like scanning line WS, a column-like signal line SL, a matrix-like pixel 2 arranged at a portion where each scanning line WS and each signal line SL intersect, and each scanning line WS. And a power supply line VL arranged in parallel. Each pixel 2 includes at least a sampling transistor Tr1, a drive transistor Trd, a storage capacitor Cs, and a light emitting element EL. The sampling transistor Tr1 has a control terminal (gate) connected to the scanning line WS, and a pair of current terminals (source / drain) connected between the signal line SL and the control terminal (gate G) of the drive transistor Trd. Yes. In the drive transistor Trd, one (source S) of a pair of current ends (source / drain) is connected to the light emitting element EL, and the other (drain) is connected to the power supply line VL. The storage capacitor Cs is connected between the gate G and the source S of the drive transistor Trd.

  The drive unit supplies at least a control signal to each scanning line WS and performs a line sequential scanning to switch the signal potential Vsig and the reference potential Vss1 to each signal line SL in synchronization with the line sequential scanning. And a power supply scanner 6 for switching each power supply line VL between a power supply state and a floating state in accordance with line sequential scanning. Each power supply line VL is applied with a high potential Vcc when in a power supply state, and has a high impedance when in a floating state. The power supply line VL is held at a fixed potential (low potential) Vss2 for a predetermined period other than these potentials.

  The sampling transistor Tr1 is turned on in response to a control signal supplied to the scanning line WS when the signal line SL is at the signal potential Vsig and the power supply line VL is in a floating state, and samples Vsig from the signal line SL to the signal potential. Write to Cs. The drive transistor Trd has a current flowing through the drive transistor Trd after the sampling transistor Tr1 is turned on and the power supply line VL is switched from the floating state to the power supply state (Vcc) until the sampling transistor Tr1 is turned off. By negatively feeding back to the storage capacitor Cs, the variation in mobility of the drive transistor Trd is corrected. The light emitting element EL emits light according to the current supplied from the drive transistor Trd after the sampling transistor Tr1 is turned off.

  As is clear from the above description, in the display device according to the present embodiment, the power supply scanner 6 puts the power supply line VL in a floating state while the sampling transistor Tr1 is turned on and the signal potential Vsig is written in the storage capacitor Cs. Since no power is supplied to the pixel 2, no current flows into the storage capacitor Cs while the signal potential is being written, so the mobility correction operation is not performed. Subsequently, the sampling transistor Tr1 is turned on, and the power supply scanner 6 switches the power supply line VL from the floating state to the power supply state. Thus, the mobility correction operation is performed by supplying a current to the drive transistor Trd in a state where the signal potential Vsig is applied to the gate G of the drive transistor Trd and negatively feeding it back to the storage capacitor Cs. With this configuration, it is possible to divide the signal writing period and the mobility correction period, and it is possible to cope with higher definition and higher density of the display device (panel).

  In a specific configuration, as shown in FIG. 6, the power supply scanner 6 includes a shift register and a buffer. For ease of understanding, only the buffers constituting the output stage of the shift register are shown in the figure, and the shift register itself is not shown. The shift register outputs input signals IN1 and IN2 for each stage in accordance with line sequential scanning. Note that IN1 and IN2 have different phases. The output buffer switches the corresponding power supply line VL between the floating state and the power supply state according to the input signals IN1 and IN2. In the embodiment, the output buffer is composed of an inverter composed of a P-channel transistor and an N-channel transistor. The P channel transistor is connected between the high potential Vcc and the output terminal. The N channel transistor is connected between the output terminal and the low potential Vss2. The output terminal is connected to the power supply line VL of the corresponding row. When the input signals IN1 and IN2 are both at the low level, the P-channel transistor is turned on and the high potential Vcc is applied to the power supply line VL. This is the power supply state. Conversely, when the input signals IN1 and IN2 are both at the high level, the N-channel transistor side is turned on and the power supply line VL is fixed at the low potential Vss2. Further, when the input signal IN1 is at a high level and IN2 is at a low level, both the P-channel transistor and the N-channel transistor are turned off, and the power supply line VL is disconnected from Vcc and Vss2 and is in a floating state (high impedance).

  As described above, in this embodiment, the output buffer of the power scanner 6 is improved to switch the power supply line VL between the power supply state and the floating state. However, the present invention is not limited to this. For example, the power supply scanner 6 may be configured such that a switch is inserted between each power supply line VL and the corresponding output buffer. In this case, the power supply scanner 6 can turn on and off this switch in accordance with line sequential scanning to switch the power supply line VL between the floating state and the power supply state.

  Preferably, in the present embodiment, the threshold voltage correction operation is performed prior to the signal potential writing operation and the mobility correction operation. That is, the sampling transistor Tr1 is turned on in response to a control signal supplied to the scanning line WS when the signal line SL is at the reference potential Vss1 and the power supply line VL is at the predetermined fixed potential Vss2, and the control terminal (gate G ) Is set to the reference potential Vss1, and the current end (source S) of the drive transistor Trd is set to the fixed potential Vss2. After that, the power supply scanner 6 returns the power supply line VL from the fixed potential (Vss2) to the power supply state (Vcc) and flows a current until the drive transistor Trd is cut off, and thus a voltage corresponding to the threshold voltage Vth of the drive transistor Trd. Is held in the holding capacitor Cs.

  FIG. 7 is a timing chart for explaining the operation of the display device according to the present invention shown in FIG. In order to facilitate understanding, the same notation as the timing chart of the display device according to the prior development shown in FIG. 3 is adopted. The timing chart of FIG. 7 also shows potential changes of the input signals IN1 and IN2 applied to the output buffer of the power supply scanner in addition to the potential changes of the scanning line WS, the power supply line VL, the gate G and the source S of the drive transistor. . As described above, when IN1 and IN2 are at a high level, the power supply line VL is held at the fixed potential Vss2. When both IN1 and IN2 are at a low level, the power supply line VL is at a high potential Vcc and is in a power supply state. In addition, when IN1 is at a high level and IN2 is at a low level, the feeder line VL is in a floating state.

  As shown in the timing chart of FIG. 7, the pixel enters the non-light emission period of the field from the light emission period of the previous field, and then becomes the light emission period of the field. During this non-emission period, a preparation operation, a threshold voltage correction operation, a signal writing operation, a mobility correction operation, and the like are performed.

  In the light emission period of the previous field, the power supply line VL is at the high potential Vcc, and the drive transistor Trd supplies the drive current Ids to the light emitting element EL. The drive current Ids flows from the power supply line VL at the high potential Vcc through the light emitting element EL through the drive transistor Trd to the cathode line.

  Subsequently, when the non-light-emission period of the field starts, the power supply line VL is first switched from the high potential Vcc to the low potential Vss2 at timing T1. As a result, the power supply line VL is discharged to Vss2, and the potential of the source S of the drive transistor Trd drops to Vss2. As a result, the anode potential of the light emitting element EL (that is, the source potential of the drive transistor Trd) is in a reverse bias state, so that the drive current does not flow and the light is turned off. Further, the potential of the gate G also drops in conjunction with the potential drop of the source S of the drive transistor.

  Subsequently, at timing T2, the sampling transistor Tr1 becomes conductive by switching the scanning line WS from the low level to the high level. At this time, the signal line SL is at the reference potential Vss1. Therefore, the potential of the gate G of the drive transistor Trd becomes the reference potential Vss1 of the signal line SL through the conducting sampling transistor Tr1. At this time, the potential of the source S of the drive transistor Trd is at a potential Vss2 that is sufficiently lower than Vss1. In this way, the voltage Vgs between the gate G and the source S of the drive transistor Trd is initialized so as to be larger than the threshold voltage Vth of the drive transistor Trd. A period T1-T3 from the timing T1 to the timing T3 thereafter is a preparation period in which the gate G / source S voltage Vgs of the drive transistor Trd is set to Vth or higher in advance.

  At timing T3, the power supply line VL changes from the low potential Vss2 to the high potential Vcc, and the potential of the source S of the drive transistor Trd starts to rise. Eventually, the current is cut off when the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes the threshold voltage Vth. In this way, a voltage corresponding to the threshold voltage Vth of the drive transistor Trd is written into the storage capacitor Cs. This is the threshold voltage correction operation. At this time, the cathode potential Vcath is set so that the light emitting element EL is cut off in order to prevent the current from flowing to the storage capacitor Cs and not to the light emitting element EL.

  At timing T4, the scanning line WS returns from the high level to the low level. In other words, the first pulse P1 applied to the scanning line WS is released, and the sampling transistor is turned off. As is clear from the above description, the first pulse P1 is applied to the gate of the sampling transistor Tr1 in order to perform the threshold voltage correction operation.

  Thereafter, at the timing Ta, the signal line SL is switched from the reference potential Vss1 to the signal potential Vsig. At this time, since IN1 is switched from the low level to the high level, the power supply line VL is in a floating state.

  Thereafter, the second pulse P2 is applied to the control line WS at timing Tb, and the sampling transistor Tr1 is turned on. At this time, since the signal line SL has already been switched to the signal potential Vsig, the signal potential Vsig is applied to the gate G of the drive transistor Trd, and the signal writing operation is started. At this time, since the power supply line VL is in a floating state, no current flows through the drive transistor Trd, and thus no negative current feedback is applied to the storage capacitor Cs, so that mobility correction is not performed. In other words, only the signal writing operation can be executed without performing the mobility correction operation.

  In this manner, after the signal potential Vsig is sufficiently written to the gate G of the drive transistor Trd, IN1 is set to the low level at the timing T5, and the power supply line VL is returned to the power supply state. At this time, since the sampling transistor Tr1 is still on, the signal potential Vsig is applied to the gate G of the drive transistor Trd. On the other hand, since the power supply line VL is in a power supply state, a current starts to flow through the drive transistor Trd. Since the light emitting element EL is in a cut-off state (high impedance state) at the timing T5, the current flowing between the drain and source of the drive transistor Trd exclusively flows into the holding capacitor Cs and the equivalent capacity of the light emitting element EL and starts charging. . Thereafter, the potential of the source S of the drive transistor Trd rises by ΔV by timing T6 when the sampling transistor Tr1 is turned off. In this way, the mobility correction voltage ΔV is subtracted from the voltage held in the holding capacitor Cs. Therefore, a period T5-T6 from timing T5 to timing T6 is a mobility correction period.

  Finally, at timing T6, as described above, the scanning line WS shifts to the low level side, and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. At this time, the drain current Ids starts to flow through the light emitting element EL, and the anode potential of the light emitting element EL rises according to the driving current Ids. The increase in the anode potential of the light emitting element EL is none other than the increase in the potential of the source S of the drive transistor Trd. When the potential of the source S of the drive transistor Trd rises, the potential of the gate G of the drive transistor Trd also rises in conjunction with the bootstrap operation of the storage capacitor Cs. The amount of increase in gate potential is equal to the amount of increase in source potential. Therefore, the input voltage Vgs between the gate G and the source S of the drive transistor Trd is kept constant during the light emission period. The value of the gate voltage Vgs is obtained by correcting the signal potential Vsig with the threshold voltage Vth and the movement amount μ. The drive transistor Trd operates in the saturation region. That is, the drive transistor Trd outputs a drive current Ids according to the input voltage Vgs between the gate G and the source S. The value of the gate voltage Vgs is obtained by correcting the signal potential Vsig with the threshold voltage Vth and the movement amount μ.

  As is apparent from the above description, in the present invention, the period from timing Tb to timing T6 is the signal writing period, and the period from timing T5 to T6 is the mobility correction period. In this way, the signal writing period and the mobility correction period can be divided. It is possible to adjust the mobility correction period to an optimum length while ensuring a sufficient signal writing period, and it becomes possible to cope with higher definition and higher density of the panel.

  FIG. 8 is a graph showing the relationship between panel brightness (Nit) and mobility correction time (μs). A curve A represents the relationship between the mobility correction time / panel luminance of the display device according to the present invention, and a curve B represents the panel luminance / mobility correction time of the display device according to the prior development. In the case of the present invention, as shown by the curve A, the signal potential writing operation is sufficiently advanced at the time of starting the mobility correction, and the panel luminance is 1600 Nit. Thereafter, as the mobility correction time becomes longer, negative current feedback with respect to the storage capacitor Cs proceeds, so that Vgs of the drive transistor Trd is compressed and the panel luminance is lowered. As shown by curve A, in the present invention, the signal writing is almost completed when the mobility correction time starts, so the mobility correction time itself is set to an optimum period regardless of the signal writing operation. I can do it. For example, if the optimum mobility correction time is 0.2 μs, the timing T5 or T6 in the timing chart of FIG. 7 can be set as it is.

  On the other hand, as shown by curve B, in the preceding development example, the signal potential writing operation and the mobility correction operation proceed simultaneously, and therefore the mobility correction time cannot be set too short. That is, if the mobility correction time is set to 0.5 μs or less, the signal potential cannot be sufficiently written in this time width, and the panel luminance does not increase. If the mobility correction time is longer than 0.5 μs, there is no problem in operation because the curve A overlaps with the curve A. However, as the density of the panel increases, the equivalent capacitance of the pixel decreases, and the optimum mobility correction time is shortened accordingly. However, in the prior development example, as shown by the curve B, the mobility correction time cannot be made shorter than 0.5 μs, and the optimum mobility correction cannot be performed. As a result, streaky irregularities occur on the screen of the panel, and the uniformity of the screen is impaired.

  The display device according to the present invention has a thin film device configuration as shown in FIG. This figure shows a schematic cross-sectional structure of a pixel formed on an insulating substrate. As shown in the figure, the pixel includes a transistor part (a single TFT is illustrated in the figure) including a plurality of thin film transistors, a capacitor part such as a storage capacitor, and a light emitting part such as an organic EL element. A transistor portion and a capacitor portion are formed on a substrate by a TFT process, and a light emitting portion such as an organic EL element is laminated thereon. A transparent counter substrate is pasted thereon via an adhesive to form a flat panel.

  The display device according to the present invention includes a flat module-shaped display as shown in FIG. For example, a pixel array unit in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated in a matrix is provided on an insulating substrate, and an adhesive is disposed so as to surround the pixel array unit (pixel matrix unit). Then, a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and is input to an electronic device such as a digital camera, a notebook personal computer, a mobile phone, or a video camera, or an electronic device. It is possible to apply to the display of the electronic device of all the fields which display the drive signal produced | generated in the inside as an image or an image | video. Examples of electronic devices to which such a display device is applied are shown below.

  FIG. 11 shows a television to which the present invention is applied, which includes a video display screen 11 including a front panel 12, a filter glass 13, and the like, and is manufactured by using the display device of the present invention for the video display screen 11. .

  FIG. 12 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a rear view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 13 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 that is operated when inputting characters and the like, and the main body cover includes a display unit 22 that displays an image. This display device is used for the display portion 22.

  FIG. 14 shows a mobile terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub-display 27, a picture light 28, a camera 29, and the like, and includes the display device of the present invention. The display 26 and the sub-display 27 are used.

  FIG. 15 shows a video camera to which the present invention is applied. The video camera includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. on the side facing forward. It is manufactured by using the device for its monitor 36.

It is a block diagram which shows the whole structure of the display apparatus concerning a prior development example. FIG. 3 is a circuit diagram illustrating a specific configuration of the display device illustrated in FIG. 2. 3 is a timing chart for explaining the operation of the display device illustrated in FIG. 2. It is a schematic diagram with which it uses for description of operation | movement of the display apparatus shown in FIG. It is a circuit diagram which similarly shows the display apparatus concerning a prior development example. It is a circuit diagram which shows the structure of the display apparatus concerning this invention. 7 is a timing chart for explaining the operation of the display device illustrated in FIG. 6. 7 is a graph for explaining an operation of the display device shown in FIG. 6. It is sectional drawing which shows the device structure of the display apparatus concerning this invention. It is a top view which shows the module structure of the display apparatus concerning this invention. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array part, 2 ... Pixel, 3 ... Horizontal selector (signal selector), 4 ... Write scanner, 5 ... Drive scanner, Tr1 ... Sampling transistor, Trd ... Drive transistor, Tr2 ... switching transistor, Cs ... holding capacitor, EL ... light emitting element

Claims (5)

It consists of a pixel array part and a drive part,
The pixel array section is arranged in parallel with each scanning line, row-shaped scanning lines, columnar signal lines, matrix-like pixels arranged at the intersection of each scanning line and each signal line, and Power supply line,
Each pixel includes at least a sampling transistor, a drive transistor, a storage capacitor, and a light emitting element,
The sampling transistor has a control end connected to the scanning line, a pair of current ends connected between the signal line and the control end of the drive transistor,
The drive transistor has one of a pair of current ends connected to the light emitting element, the other connected to a power supply line,
The storage capacitor is connected between a control terminal and a current terminal of the drive transistor,
The drive unit includes at least a write scanner that sequentially supplies a control signal to each scanning line to perform line sequential scanning, and a signal selector that switches and supplies a signal potential and a reference potential to each signal line in synchronization with the line sequential scanning. A power scanner that switches each power supply line between a power supply state and a floating state according to line sequential scanning,
The sampling transistor is turned on in response to a control signal supplied to the scanning line when the signal line is a signal potential and the power supply line is in a floating state, and the signal potential is sampled from the signal line to the storage capacitor. writing,
The drive transistor holds the current flowing through the drive transistor after the sampling transistor is continuously turned on and the power supply line is switched from the floating state to the power supply state until the sampling transistor is turned off. By negatively feeding back to the capacitance, correcting the variation in mobility of the drive transistor,
The display device, wherein the light emitting element emits light according to a current supplied from the drive transistor after the sampling transistor is turned off. The power scanner includes a shift register that outputs an input signal for each stage in accordance with line sequential scanning, and a buffer that is disposed between each stage of the shift register and each feeder line corresponding thereto.
The display device according to claim 1, wherein the buffer switches a corresponding feeder line between a floating state and a power supply state in accordance with the input signal.   The power supply scanner has a switch corresponding to each power supply line, and switches each power supply line between a floating state and a power supply state by controlling each switch on and off in accordance with line sequential scanning. The display device according to claim 1. The sampling transistor is turned on in response to a control signal supplied to the scanning line when the signal line is at a reference potential and the power supply line is at a predetermined fixed potential, and the control terminal of the drive transistor is set to the reference potential. , Set the current end of the drive transistor to a fixed potential,
The power supply scanner returns a power supply line from a fixed potential to a power supply state and allows a current to flow until the drive transistor is cut off, thereby holding a voltage corresponding to the threshold voltage of the drive transistor in the storage capacitor. The display device according to claim 1.   An electronic apparatus comprising the display device according to claim 1.

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