JP2010139897A - Display device and its driving method, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of suppressing the enhancement shift of threshold voltage in a drive transistor. <P>SOLUTION: A pixel 2 includes at least a sampling transistor Tr1, drive transistor Trd, and a light-emitting element EL. A sampling transistor Tr1 captures a video signal from a signal line SL according to a control signal supplied from a scanning line WS. The drive transistor Trd is brought into a normal bias state during the light emission period of one field period, and a drive current is supplied according to the captured video signal. The light-emitting element EL emits light in luminance according to the video signal by means of the drive current. Driving sections (3, 4) switch the drive transistor Trd of each pixel 2 from a normal bias state to a reverse bias state via the scanning line WS and signal line SL during the light non-emission period of the one field period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an active matrix display device using a light emitting element for a pixel and a driving method thereof. The present invention also relates to an electronic device incorporating such a display device.

  In a display device such as a liquid crystal display, an image is displayed by arranging a large number of liquid crystal pixels in a matrix and controlling the transmission intensity or reflection intensity of incident light for each pixel according to image information to be displayed. This also applies to an organic EL display using an organic EL element as a pixel, but unlike a liquid crystal pixel, the organic EL element is a self-luminous element. Therefore, the organic EL display has advantages such as higher image visibility than the liquid crystal display, no backlight, and high response speed. Further, the luminance level (gradation) of each light emitting element can be controlled by the value of the current flowing therethrough, and is greatly different from a voltage control type such as a liquid crystal display in that it is a so-called current control type.

In the organic EL display, similarly to the liquid crystal display, there are a simple matrix method and an active matrix method as driving methods. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display. Therefore, the active matrix method is actively developed at present. In this method, a current flowing through a light emitting element in each pixel circuit is controlled by an active element (generally a thin film transistor or TFT) provided in the pixel circuit, and is described in the following patent documents.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A JP 2006-215213 A

  A conventional display device basically includes a pixel array unit and a drive unit. The pixel array section includes scanning lines arranged in rows, signal lines arranged in columns, and matrix-like pixels arranged in portions where the scanning lines and the signal lines intersect. The driving unit sequentially supplies a control signal to each scanning line over one field period and supplies a video signal to each signal line. The pixel includes at least a sampling transistor, a drive transistor, and a light emitting element. The sampling transistor takes in the video signal from the signal line in accordance with the control signal supplied from the scanning line. The drive transistor is in a forward bias state during the light emission period in one field period, and supplies a drive current according to the captured video signal. The light emitting element emits light with luminance according to the video signal by the drive current.

  In the conventional display device, the drive transistor is in a forward bias state during the light emission period. That is, the gate potential becomes equal to or higher than the threshold voltage with respect to the source potential of the drive transistor, and the drive transistor is turned on to supply the drive current to the light emitting element. However, if the forward bias state of the drive transistor continues for a long time, the threshold voltage characteristic shifts to the enhancement side. If the threshold voltage characteristic of the drive transistor shifts to the enhancement side, a problem occurs in the operation of the pixel, which is a problem to be solved.

In view of the above-described problems of the conventional technology, an object of the present invention is to provide a display device capable of suppressing an enhancement shift of a threshold voltage of a drive transistor. The following measures were taken in order to achieve this purpose. That is, the display device according to the present invention includes a pixel array unit and a drive unit. The pixel array unit includes scanning lines arranged in rows, signal lines arranged in columns, and matrix-like pixels arranged in portions where the scanning lines intersect with the signal lines. The driving unit sequentially supplies a control signal to each scanning line over one field period and supplies a video signal to each signal line. The pixel includes at least a sampling transistor, a drive transistor, and a light emitting element. The sampling transistor captures a video signal from the signal line in accordance with a control signal supplied from the scanning line. The drive transistor is in a forward bias state during the light emission period of one field period, and supplies a drive current according to the captured video signal. The light emitting element emits light with luminance according to the video signal by the driving current. The driving unit switches the drive transistor of each pixel from the forward bias state to the reverse bias state through the scanning line and the signal line in a non-light emitting period of one field period.

Preferably, the driving unit outputs a control signal to the scanning line in one horizontal cycle and outputs a video signal in which the signal potential and the reference potential are switched in one horizontal cycle to the signal line. The sampling transistor captures a signal potential in accordance with the first control signal, so that the drive transistor is in a forward bias state during the light emission period and supplies a drive current corresponding to the signal potential to the light emitting element. The sampling transistor takes in a reference potential according to the second control signal in the non-light emitting period, and thereby the drive transistor is in a reverse bias state.
The sampling transistor repeatedly captures a reference potential in accordance with a second control signal that is repeatedly output over a plurality of horizontal periods in a non-light emitting period.
The driving unit supplies the signal line with a video signal that is switched between a signal potential, a first reference potential, and a second reference potential that is further away from the signal potential within one horizontal period. The sampling transistor captures a first reference potential according to a control signal preceding the first control signal and initializes the drive transistor, and then captures a signal potential according to the first control signal. The sampling transistor captures a second reference potential in response to a second control signal.
The drive transistor has a gate connected to the sampling transistor, a source connected to the light emitting element, and a pixel capacitor connected between the gate and the source. The sampling transistor is turned on in response to the first control signal, and the signal potential is written between the gate and the source of the drive transistor to be in a forward bias state. The drive transistor has a source potential that rises while maintaining a potential difference between the gate and the source in a light emission period in which a driving current is supplied to the light emitting element according to the signal potential after the sampling transistor is turned off. The sampling transistor is turned on in response to the second control signal, writes a reference potential to the gate of the drive transistor, and reverses the potential of the source and gate to switch to the reverse bias state.
The absolute value of the potential difference between the gate and the source when the drive transistor is in the reverse bias state is larger than the absolute value of the potential difference between the gate and the source when the drive transistor is in the forward bias state.
Further, the non-light emission period in which the drive transistor is in the reverse bias state within one field period is longer than the light emission period in which the drive transistor is in the forward bias state.

  According to the present invention, the drive unit switches the drive transistor of each pixel from the forward bias state to the reverse bias state via the scanning line and the signal line in the non-light emission period of one field period. As described above, since the drive transistor is placed in the forward bias state during the light emission period, the threshold voltage characteristic shifts to the enhancement side. On the other hand, since the drive transistor is switched to the reverse bias state during the non-light emitting period, the threshold voltage characteristic is shifted to the depletion side. Thus, by alternately switching between the forward bias state and the reverse bias state, the enhancement shift of the threshold voltage characteristic of the drive transistor can be suppressed. Note that when the drive transistor is placed in a reverse bias state, the drive transistor is turned off, but there is no problem in operation because the pixel is in a non-light emitting period.

The best mode for carrying out the invention (referred to as an embodiment) will be described below with reference to the drawings. The description will be given in the following order.
First embodiment
Second embodiment
Third embodiment
Fourth embodiment
Fifth embodiment
Application form

<First embodiment>
[overall structure]
FIG. 1 is a schematic block diagram showing the overall configuration of the first embodiment of the display device according to the present invention. As shown in the figure, the display device includes a pixel array section 1 (screen section) and a drive section for driving the pixel array section 1 (screen section). The pixel array section 1 corresponds to a row-shaped scanning line WS, a column-shaped signal line (signal line) SL, a matrix-shaped pixel 2 arranged at a portion where both intersect, and each row of each pixel 2. The power supply line (power supply line) VL is provided. In this example, any one of the three RGB primary colors is assigned to each pixel 2, and color display is possible. However, the present invention is not limited to this, and includes a single-color display device. The drive unit sequentially supplies a control signal to each scanning line WS to scan the pixels 2 line-sequentially in units of rows, and the first potential and the second potential to each power supply line VL in accordance with the line sequential scanning. And a horizontal selector 3 for supplying a signal potential as a video signal and a reference potential to the column-shaped signal lines SL in accordance with the line sequential scanning.

[Pixel circuit configuration]
FIG. 2 is a circuit diagram showing a specific configuration and connection relationship of the pixel 2 included in the display device shown in FIG. As shown in the drawing, the pixel 2 includes a light emitting element EL represented by an organic EL device, a sampling transistor Tr1, a drive transistor Trd, and a pixel capacitor Cs. The control terminal (gate) of the sampling transistor Tr1 is connected to the corresponding scanning line WS, one of the pair of current terminals (source and drain) is connected to the corresponding signal line SL, and the other is connected to the control terminal of the drive transistor Trd. Connect to (Gate G). In the drive transistor Trd, one of a pair of current ends (source S and drain) is connected to the light emitting element EL, and the other is connected to the corresponding power supply line VL. In this example, the drive transistor Trd is an N-channel type, and its drain is connected to the power supply line VL, while the source S is connected to the anode of the light emitting element EL as an output node. The cathode of the light emitting element EL is connected to a predetermined cathode potential Vcath. The pixel capacitor Cs is connected between the source S that is one of the current ends of the drive transistor Trd and the gate G that is the control end.

  In such a configuration, the sampling transistor Tr1 is turned on in response to the control signal supplied from the scanning line WS, samples the signal potential supplied from the signal line SL, and holds it in the pixel capacitor Cs. The drive transistor Trd is supplied with current from the power supply line VL at the first potential (high potential Vdd), and flows drive current to the light emitting element EL in accordance with the signal potential held in the pixel capacitor Cs. The write scanner 4 outputs a control signal having a predetermined pulse width to the control line WS in order to bring the sampling transistor Tr1 into a conductive state in a time zone in which the signal line SL is at the signal potential, thereby causing the signal potential to be applied to the pixel capacitor Cs. At the same time, a correction for the mobility μ of the drive transistor Trd is added to the signal potential. Thereafter, the drive transistor Trd supplies a drive current corresponding to the signal potential Vsig written in the pixel capacitor Cs to the light emitting element EL, and starts a light emitting operation.

  The pixel circuit 2 has a threshold voltage correction function in addition to the mobility correction function described above. That is, the power supply scanner 6 switches the power supply line VL from the first potential (high potential Vdd) to the second potential (low potential Vss) at the first timing before the sampling transistor Tr1 samples the signal potential Vsig. Similarly, before the sampling transistor Tr1 samples the signal potential Vsig, the write scanner 4 conducts the sampling transistor Tr1 at the second timing to apply the reference potential Vref from the signal line SL to the gate G of the drive transistor Trd and the drive transistor. The source S of Trd is set to the second potential (Vss). The power supply scanner 6 switches the power supply line VL from the second potential Vss to the first potential Vdd at a third timing after the second timing, and holds a voltage corresponding to the threshold voltage Vth of the drive transistor Trd in the pixel capacitor Cs. With this threshold voltage correction function, the display device can cancel the influence of the threshold voltage Vth of the drive transistor Trd that varies from pixel to pixel.

  The pixel circuit 2 further has a bootstrap function. That is, the write scanner 4 cancels the application of the control signal to the scanning line WS at the stage where the signal potential Vsig is held in the pixel capacitor Cs, and the sampling transistor Tr1 is turned off to connect the gate G of the drive transistor Trd from the signal line SL. By electrically disconnecting, the potential of the gate G is interlocked with the potential fluctuation of the source S of the drive transistor Trd, and the voltage Vgs between the gate G and the source S can be maintained constant.

[Reference example 1 of timing chart]
FIG. 3 is a timing chart for explaining the operation of the pixel circuit 2 shown in FIG. The time axis is shared, and the potential change of the scanning line WS, the potential change of the power supply line VL, and the potential change of the signal line SL are represented. In parallel with these potential changes, the potential changes of the gate G and the source S of the drive transistor are also shown.

  A control signal pulse for turning on the sampling transistor Tr1 is applied to the scanning line WS. This control signal pulse is applied to the scanning line WS in one field (1f) cycle in accordance with the line sequential scanning of the pixel array section. This control signal pulse includes two pulses during one horizontal scanning period (1H). The first pulse may be referred to as a first pulse P1, and the subsequent pulse may be referred to as a second pulse P2. Similarly, the power supply line VL is switched between the high potential Vdd and the low potential Vss in one field period (1f). A video signal for switching between the signal potential Vsig and the reference potential Vref within one horizontal scanning period (1H) is supplied to the signal line SL.

  As shown in the timing chart of FIG. 3, the pixel enters the non-light emission period of the field from the light emission period of the previous field, and then becomes the light emission period of the field. During this non-emission period, a preparation operation, a threshold voltage correction operation, a signal writing operation, a mobility correction operation, and the like are performed.

  In the light emission period of the previous field, the power supply line VL is at the high potential Vdd, and the drive transistor Trd supplies the drive current Ids to the light emitting element EL. The drive current Ids flows from the power supply line VL at the high potential Vdd through the light emitting element EL through the drive transistor Trd to the cathode line.

  Subsequently, when the non-light emission period of the field starts, first, at timing T1, the power supply line VL is switched from the high potential Vdd to the low potential Vss. As a result, the power supply line VL is discharged to Vss, and the potential of the source S of the drive transistor Trd drops to Vss. As a result, the anode potential of the light emitting element EL (that is, the source potential of the drive transistor Trd) is in a reverse bias state, so that the drive current does not flow and the light is turned off. Further, the potential of the gate G also drops in conjunction with the potential drop of the source S of the drive transistor.

  Subsequently, at timing T2, the sampling transistor Tr1 becomes conductive by switching the scanning line WS from the low level to the high level. At this time, the signal line SL is at the reference potential Vref. Therefore, the potential of the gate G of the drive transistor Trd becomes the reference potential Vref of the signal line SL through the conducting sampling transistor Tr1. At this time, the potential of the source S of the drive transistor Trd is at a potential Vss sufficiently lower than Vref. In this way, the voltage Vgs between the gate G and the source S of the drive transistor Trd is initialized so as to be larger than the threshold voltage Vth of the drive transistor Trd. A period T1-T3 from the timing T1 to the timing T3 is a preparation period in which the gate G / source S voltage Vgs of the drive transistor Trd is set to Vth or higher in advance.

  Thereafter, at timing T3, the power supply line VL changes from the low potential Vss to the high potential Vdd, and the potential of the source S of the drive transistor Trd starts to rise. Eventually, the current is cut off when the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes the threshold voltage Vth. In this way, a voltage corresponding to the threshold voltage Vth of the drive transistor Trd is written to the pixel capacitor Cs. This is the threshold voltage correction operation. At this time, the cathode potential Vcath is set so that the light emitting element EL is cut off in order to prevent the current from flowing to the pixel capacitor Cs and not to the light emitting element EL.

  At timing T4, the scanning line WS returns from the high level to the low level. In other words, the first pulse P1 applied to the scanning line WS is released, and the sampling transistor is turned off. As is clear from the above description, the first pulse P1 is applied to the gate of the sampling transistor Tr1 in order to perform the threshold voltage correction operation.

  Thereafter, the signal line SL is switched from the reference potential Vref to the signal potential Vsig. Subsequently, at timing T5, the scanning line WS rises again from the low level to the high level. In other words, the second pulse P2 is applied to the gate of the sampling transistor Tr1. As a result, the sampling transistor Tr1 is turned on again, and the signal potential Vsig is sampled from the signal line SL. Therefore, the potential of the gate G of the drive transistor Trd becomes the signal potential Vsig. Here, since the light emitting element EL is initially in a cut-off state (high impedance state), the current flowing between the drain and source of the drive transistor Trd flows exclusively into the pixel capacitor Cs and the equivalent capacity of the light emitting element EL and starts charging. Thereafter, by the timing T6 when the sampling transistor Tr1 is turned off, the potential of the source S of the drive transistor Trd rises by ΔV. In this manner, the signal potential Vsig of the video signal is written to the pixel capacitor Cs in a form added to Vth, and the mobility correction voltage ΔV is subtracted from the voltage held in the pixel capacitor Cs. Therefore, the period T5-T6 from the timing T5 to the timing T6 becomes a signal writing period & mobility correction period. In other words, when the second pulse P2 is applied to the scanning line WS, a signal writing operation and a mobility correction operation are performed. The signal writing period & mobility correction period T5-T6 is equal to the pulse width of the second pulse P2. That is, the pulse width of the second pulse P2 defines the mobility correction period.

  In this way, in the signal writing period T5-T6, the signal voltage is written to Vsig and the correction amount ΔV is adjusted simultaneously. As Vsig increases, the current Ids supplied from the drive transistor Trd increases and the absolute value of ΔV also increases. Therefore, mobility correction is performed according to the light emission luminance level. When Vsig is constant, the absolute value of ΔV increases as the mobility μ of the drive transistor Trd increases. In other words, since the negative feedback amount ΔV with respect to the pixel capacitance Cs increases as the mobility μ increases, variations in the mobility μ for each pixel can be removed.

  Finally, at timing T6, as described above, the scanning line WS shifts to the low level side, and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. At this time, the drain current Ids starts to flow through the light emitting element EL. As a result, the anode potential of the light emitting element EL rises according to the drive current Ids. The increase in the anode potential of the light emitting element EL is none other than the increase in the potential of the source S of the drive transistor Trd. When the potential of the source S of the drive transistor Trd rises, the potential of the gate G of the drive transistor Trd also rises in conjunction with the bootstrap operation of the pixel capacitor Cs. The amount of increase in gate potential is equal to the amount of increase in source potential. Therefore, the input voltage Vgs between the gate G and the source S of the drive transistor Trd is kept constant during the light emission period. The value of the gate voltage Vgs is obtained by correcting the signal potential Vsig with the threshold voltage Vth and the movement amount μ. The drive transistor Trd operates in the saturation region. That is, the drive transistor Trd outputs a drive current Ids according to the input voltage Vgs between the gate G and the source S. The value of the gate voltage Vgs is obtained by correcting the signal potential Vsig with the threshold voltage Vth and the movement amount μ.

[Reference example 2 of timing chart]
FIG. 4 is another timing chart for explaining the operation of the pixel circuit 2 shown in FIG. Basically, it is the same as the timing chart shown in FIG. 2, and corresponding portions are given corresponding reference numbers. The difference is that the threshold voltage correction operation is repeated in a time division manner over a plurality of horizontal periods. In the example of the timing chart of FIG. 4, the Vth correction operation for each 1H period is performed twice. As the screen portion becomes higher in definition, the number of pixels increases and the number of scanning lines also increases accordingly. The 1H period is shortened by increasing the number of scanning lines. When the line sequential scanning speeds up in this way, the Vth correction operation may not be completed in the 1H period. Therefore, in the timing chart of FIG. 4, the threshold voltage correction operation is performed twice in a time-sharing manner so that the potential Vgs between the gate G and the source S of the drive transistor Trd can be reliably initialized to Vth. Note that the number of repetitions of Vth correction is not limited to two, and the number of time divisions can be increased as necessary.

[Timing chart of embodiment]
FIG. 5 is a timing chart for explaining the operation of the display device according to the present invention, and represents the first embodiment of the present invention. In the timing chart of the reference example shown in FIGS. 3 and 4, the drive transistor is placed in a forward bias state in both the light emission period and the non-light emission period. That is, the gate potential of the drive transistor is held at a threshold voltage or higher with respect to the source potential. This forward bias causes a problem that the threshold voltage of the drive transistor shifts in the enhancement direction. The first embodiment shown in FIG. 5 addresses this problem, and suppresses the enhancement shift of the threshold voltage of the drive transistor. In order to facilitate understanding, the same notation as the timing charts shown in FIGS. 3 and 4 is employed.

The sampling transistor takes in the video signal Vsig from the signal line SL in accordance with the control signal P2 supplied from the scanning line WS. The drive transistor is in a forward bias state in the light emission period within one field period, and supplies a drive current according to the captured video signal Vsig. The light emitting element emits light with luminance according to the video signal Vsig by this driving current. As a feature, the driving unit switches the drive transistor of each pixel from the forward bias state to the reverse bias state through the scanning line WS and the signal line SL in the non-light emitting period in one field period. As shown in the timing chart, the drive transistor is in a forward bias state during the light emission period, and the gate potential (G) is higher than the source potential (S). On the other hand, the drive transistor is in a reverse bias state during the non-light emitting period, and the source potential (S) is higher than the gate potential (G). In the forward bias state, the enhancement direction shift of the threshold voltage Vth of the drive transistor proceeds. Conversely, in the reverse bias state during the non-light emitting period, the depletion direction shift of the threshold voltage of the drive transistor proceeds. Thereby, the enhancement direction shift of the threshold voltage of the drive transistor can be suppressed.
The driving unit outputs a control signal to the scanning line WS in one horizontal cycle (1H) and outputs a video signal in which the signal potential Vsig and the reference potential Vref are switched in one horizontal cycle to the signal line SL. The sampling transistor takes in the signal potential Vsig in accordance with the first control signal P2, so that the drive transistor is in a forward bias state during the light emission period and supplies a drive current in accordance with the signal potential Vsig to the light emitting element. The sampling transistor takes in the reference potential Vref according to the second control signal P3 in the non-light emitting period, and thereby the drive transistor is in a reverse bias state.

  More specifically, the sampling transistor is turned on in response to the first control signal P2, and the signal potential Vsig is written between the gate G and the source S of the drive transistor to be in a forward bias state. In the drive transistor, after the sampling transistor is turned off, the source potential rises while maintaining the potential difference Vsig between the gate G and the source S in the light emission period in which the drive current is supplied to the light emitting element according to the signal potential Vsig. A so-called bootstrap phenomenon occurs. Thereafter, in the non-light emitting period, the sampling transistor is turned on according to the second control signal P3, the reference potential Vref is written to the gate G of the drive transistor, and the potentials of the source S and the gate G are reversed and reversed. Switch to the bias state. While the source potential rises by bootstrap, by applying Vref lower than the signal potential Vsig to the gate, the source potential and the gate potential are reversed to obtain a reverse bias state.

[Description of operation]
FIG. 6A is a graph showing Vth variation at the time of reverse bias. The elapsed time is taken on the horizontal axis, and the change amount ΔVth of the threshold voltage of the N-channel type drive transistor is taken on the vertical axis. As can be seen from the graph, in the reverse bias state, the threshold voltage Vth of the drive transistor shifts in the negative direction (depletion direction) with the passage of time. Conversely, in the forward bias state, the threshold voltage Vth shifts to the plus side (enhancement side). In the present invention, the temporal change of the threshold voltage of the drive transistor is suppressed by alternately switching the forward bias and the reverse bias.

  FIG. 6B is a schematic diagram showing an operating point of the drive transistor Trd at the time of reverse bias. The signal potential Vsig has a dynamic range from 0V to 6V. The off voltage applied to the gate of the sampling transistor Tr1 is −3V. The reference voltage is set to 0V. The high potential of the power supply line VL is 15V. During the light emission period, the source potential of the drive transistor Trd (that is, the anode potential of the light emitting element EL) is increased by bootstrap, and is at a level of 5V, for example. In the non-light emitting period, the reference potential 0V is written to the gate of the drive transistor Trd. In this way, Vgs of the drive transistor Trd becomes 0V−5V = −5V and becomes reverse bias (minus bias).

[Current degradation phenomenon of light emitting elements]
FIG. 7 is a schematic diagram showing a current deterioration phenomenon of the light emitting element. (A) is a graph which shows the relationship between the voltage Voled applied to a light emitting element, and the electric current Ioled which flows through a light emitting element. A solid line (1) represents the initial characteristics, and a dotted line (2) represents the characteristics after aging. Generally, a light emitting element emits light by passing a current. As apparent from the graph, the light emitting element tends to deteriorate with time, and the luminance decreases with time. That is, even when the same voltage Voled is applied, the current Ioled decreases with time, and the luminance also decreases accordingly.

  (B) is an equivalent circuit diagram showing a pixel circuit for driving such a light emitting element. This equivalent circuit diagram shows, in addition to the sampling transistor Tr1, the drive transistor Trd, the pixel capacitor Cs, and the light emitting element EL, the gate / drain parasitic capacitance Cp of the drive transistor Trd, the equivalent capacity Coled of the light emitting element EL, and the cathode potential Vcath of the light emitting element EL. Etc. are written.

  (C) is a timing chart showing a light emitting operation of the light emitting element. The fluctuations of the gate potential and the source potential of the drive transistor in the vicinity of the timings T5 to T7 shown in FIGS. As shown in the figure, in the light emission operation after writing the signal potential Vsig, a bootstrap operation including the pixel capacitor Cs and the parasitic capacitor Cp occurs. As a result, Vgs during light emission is reduced by Cp / (Cs + Cp) × ΔVs with respect to Vgs immediately before light emission. ΔVs represents a change in the source potential of the drive transistor. When the current / voltage characteristic of the light emitting element is deteriorated, Voled required for flowing the same current increases. As a result, ΔVs during light emission increases, and the amount of decrease in Vgs due to the bootstrap operation increases. As a result, the emission luminance decreases with time. This is the cause of current deterioration of the self-luminous pixel.

  As shown in (C), the voltage change ΔVs of the source potential Vs during light emission is ΔVs = Vcath−Vref−ΔV + Voled + Vth. Here, ΔV is a mobility correction voltage as described above. Here, Vcath−Vref−ΔV is always a constant value, but Voled is increased by the energized light emitting operation as described above. This caused current degradation. In the present invention, Vth is reduced by the depletion direction shift operation of the Vth characteristic during the non-light emitting period. This depletion shift can suppress an increase in ΔVs caused by deterioration of the current / voltage characteristics of the light emitting element. As a result, current degradation can be suppressed by the Vth depletion shift.

  In the case of a color display device, each pixel includes one of a red light emitting element, a green light emitting element, and a blue light emitting element. The degree of current degradation differs between red light emitting elements, green light emitting elements, and blue light emitting elements. Preferably, the reverse bias state setting is adjusted separately for the red pixel, the green pixel, and the blue pixel. According to the present invention, in a display device using a light emitting element for a pixel, a reverse bias is applied to the drive transistor in a non-light emitting period to shift the Vth characteristic to the depletion side. As a result, the current deterioration due to the current / voltage characteristic deterioration of the light emitting element due to the light emitting operation can be alleviated.

<Second embodiment>
[Timing chart]
FIG. 8 is a timing chart showing the second embodiment of the display device according to the present invention. In order to facilitate understanding, the same notation as the timing chart of the first embodiment shown in FIG. 5 is adopted. The difference from the first embodiment is that the sampling transistor repeatedly captures the reference potential Vref according to the second control signal P3 that is repeatedly output over a plurality of horizontal periods in the non-light emitting period. In this embodiment, when the power supply line VL is at a high level and the signal line SL is at the reference potential Vref, a reverse bias (minus bias) is applied to the drive transistor by turning on the sampling transistor a plurality of times. First, when the power supply line is at a high potential and the signal line SL is at the reference potential Vref, the drive transistor is cut off by turning on the sampling transistor. The light emitting element EL is disconnected from the current supply source and self-discharges. Here, it takes time to self-discharge the light emitting element EL. For this reason, if the panel has a higher definition and a higher frequency, one horizontal period (1H) is shortened accordingly, so that a sufficient discharge time cannot be secured and a sufficient reverse bias cannot be applied. Therefore, in this embodiment, by turning on the sampling transistor a plurality of times, it is possible to secure a time for the light emitting element EL to discharge to the cutoff.

  Since the anode potential after self-discharge (that is, the source potential of the drive transistor) becomes higher than the gate potential of the drive transistor, a negative bias is applied to the drive transistor. As a result, even if the panel has higher definition and higher frequency, reverse bias can be applied to the drive transistor, and the Vth characteristic can be shifted to the depletion side. As a result, the enhancement-side shift of the drive transistor in the light emitting operation can be suppressed, and at the same time, current deterioration due to current / voltage characteristic deterioration of the light emitting element EL can be suppressed.

<Third embodiment>
[Timing chart]
FIG. 9 is a timing chart showing the third embodiment of the display device according to the present invention. In order to facilitate understanding, the same notation as the timing chart of the second embodiment shown in FIG. 8 is adopted. In the present embodiment, the driving unit switches between the signal potential Vsig, the first reference potential Vref, and the second reference potential Vofs that is further away from the signal potential Vsig within one horizontal period (1H). The sampling transistor initializes the drive transistor by taking in the first reference potential Vref in accordance with the control signal P1 preceding the first control signal P2. In the illustrated example, the initialization operation is repeated twice. As a result, a correction operation for canceling the variation in the threshold voltage Vth of the drive transistor is performed. Thereafter, the signal potential Vsig is taken in according to the first control signal P2, and the light emission period starts. Further, after that, in the non-light emission period, the second reference potential Vofs is taken in accordance with the second control signal P3, and the drive transistor is set in a negative bias state. By setting the reference potential Vofs used for applying the reverse bias lower than the reference potential Vref used for initializing the drive transistor, it becomes possible to apply a deep negative bias to the drive transistor. As a result, the enhancement direction shift of the threshold voltage of the drive transistor can be more effectively suppressed.

  Preferably, the absolute value of the potential difference between the gate G and the source S when the drive transistor is in the reverse bias state is larger than the absolute value of the potential difference between the gate G and the source S when the drive transistor is in the forward bias state. Thereby, the enhancement direction shift of the threshold voltage of the drive transistor can be more effectively suppressed.

  Preferably, the non-light emitting period in which the drive transistor is in the reverse bias state within one field period is set longer than the light emitting period in which the drive transistor is in the forward bias state as shown in the figure. This makes it possible to more effectively suppress the enhancement direction shift of Vth of the drive transistor.

<Fourth embodiment>
[Overall configuration of display device]
FIG. 10 is a block diagram showing a panel configuration of the fourth embodiment of the display device according to the present invention. In order to facilitate understanding, the same notation as the panel block diagram of the first embodiment shown in FIG. 1 is adopted. This display device basically includes a pixel array unit (screen unit) 1 and a drive unit that drives the pixel array unit (screen unit) 1. The pixel array unit 1 is arranged in a row-shaped first scanning line WS, a row-shaped second scanning line DS, a column-shaped signal line SL, and a portion where each first scanning line WS and each signal line SL intersect. The matrix-like pixels 2 are provided. On the other hand, the drive unit includes a write scanner 4, a drive scanner 5, and a horizontal selector 3. The write scanner 4 outputs a control signal to each first scanning line WS to scan the pixels 2 line-sequentially in units of rows. The drive scanner 5 also outputs a control signal to each second scanning line DS to scan the pixels 2 line-sequentially in units of rows. However, the write scanner 4 and the drive scanner 5 have different timings for outputting control signals. The drive scanner 5 is arranged in the drive unit in place of the power supply scanner 6 used in the first embodiment. By eliminating the power supply scanner, the power supply line is also removed from the pixel array unit 1. Instead, although not shown, the pixel array section 1 is provided with a power supply line for supplying a constant power supply potential Vdd. On the other hand, the horizontal selector (signal driver) 3 supplies the signal potential of the video signal and the reference potential to the column-shaped signal lines SL in accordance with the line sequential scanning on the scanner 4 and 5 side.

[Pixel circuit configuration]
FIG. 11 shows a configuration of a pixel circuit included in the display panel of the fourth embodiment shown in FIG. The pixel circuit of the first embodiment is configured by two transistors, whereas the pixel circuit of the present embodiment is configured by three transistors. As shown in the figure, the main pixel 2 basically includes a light emitting element EL, a sampling transistor Tr1, a drive transistor Trd, a switching transistor Tr3, and a pixel capacitor Cs. The sampling transistor Tr1 has a control terminal (gate) connected to the scanning line WS, one of a pair of current terminals (source and drain) connected to the signal line SL, and the other connected to a control terminal (gate G) of the drive transistor Trd. Connected to. In the drive transistor Trd, one (drain) of a pair of current ends (source and drain) is connected to the power supply line Vdd, and the other (source S) is connected to the anode of the light emitting element EL. The cathode of the light emitting element EL is connected to a predetermined cathode potential Vcath. The switching transistor Tr3 has a control terminal (gate) connected to the scanning line DS, one of a pair of current terminals (source and drain) connected to the fixed potential Vss, and the other connected to the source S of the drive transistor Trd. Yes. One end of the pixel capacitor Cs is connected to the control end (gate G) of the drive transistor Trd, and the other end is connected to the other current end (source S) of the drive transistor Trd. The other current end of the drive transistor Trd is an output current end for the light emitting element EL and the pixel capacitor Cs. In the pixel circuit 2, the auxiliary capacitor Csub is connected between the source S of the drive transistor Trd and the power source Vdd for the purpose of assisting the pixel capacitor Cs.

  In this configuration, the write scanner 4 on the drive unit side supplies a control signal for controlling the opening and closing of the sampling transistor Tr1 to the first scanning line WS. The drive scanner 5 outputs a control signal for controlling opening / closing of the switching transistor Tr3 to the second scanning line DS. The horizontal selector 3 supplies a video signal (input signal) that switches between the signal potential Vsig and the reference potential Vref to the signal line SL. As described above, the potentials of the scanning lines WS and DS and the signal line SL change in accordance with the line sequential scanning, but the power supply line is fixed at Vdd. The cathode potential Vcath and the fixed potential Vss are also constant.

[Operation of pixel circuit]
FIG. 12 is a timing chart for explaining the operation of the pixel circuit shown in FIG. As shown in the figure, this timing chart shows potential changes of the scanning line WS, the scanning line DS, and the signal line SL with the time axis aligned. The sampling transistor Tr1 is an N-channel type and is turned on when the scanning line WS becomes high level. The switching transistor Tr3 is also an N-channel type and is turned on when the scanning line DS becomes a high level. On the other hand, the video signal supplied to the signal line SL is switched between the signal potential Vsig and the reference potential Vref in one horizontal cycle (1H). This timing chart represents changes in the potentials of the gate G and the source S of the drive transistor Trd by matching the potential changes of the first scan line WS, the second scan line DS, and the signal line SL with the time axis. The operation state of the drive transistor Trd is controlled according to the potential difference Vgs between the gate G and the source S.

  First, when the light emission period of the previous field shifts to the non-light emission period of the field, the scanning line DS is switched to the high level at timing T1, and the switching transistor Tr3 is turned on. As a result, the potential of the source S of the drive transistor Trd is set to the fixed potential Vss. At this time, the fixed potential Vss is set smaller than the sum of the threshold voltage Vthel and the cathode potential Vcath of the light emitting element EL. That is, Vss <Vthel + Vcath is set, and the light emitting element EL is placed in a reverse bias state, so that the drive current Ids does not flow into the light emitting element EL. However, the output current Ids supplied from the drive transistor Trd flows through the source S to the fixed potential Vss.

  Subsequently, at timing T2, the sampling transistor Trd is turned on while the potential of the signal line SL is at Vref. As a result, the gate G of the drive transistor Trd is set to the reference potential Vref. As a result, the voltage Vgs between the gate G and the source S of the drive transistor Trd takes a value of Vref−Vss. Here, Vgs = Vref−Vss> Vth is set. If this Vref−Vss is not larger than the threshold voltage Vth of the drive transistor Trd, the subsequent threshold voltage correcting operation cannot be performed normally. However, since Vgs = Vref−Vss> Vth, the drive transistor Trd is in the ON state, and the drain current flows from the power supply potential Vdd toward the fixed potential Vss.

  Thereafter, at timing T3, a threshold voltage correction period starts, the switching transistor Tr3 is turned off, and the source S of the drive transistor Trd is disconnected from the fixed potential Vss. Here, as long as the potential of the source S (that is, the anode potential of the light-emitting element) is lower than the value obtained by adding the cathode voltage Vcath to the threshold voltage Vthel of the light-emitting element EL, the light-emitting element EL is still placed in the reverse bias state and a slight leak is caused. Only current flows. Therefore, most of the current supplied from the power supply line Vdd through the drive transistor Trd is used to charge the pixel capacitor Cs and the auxiliary capacitor Csub. Since the pixel capacitor Cs is charged in this way, the source potential of the drive transistor Trd rises from Vss over time. After a certain period, the source potential of the drive transistor Trd reaches the level of Vref−Vth, and Vgs is just Vth. At this time, the drive transistor Trd is cut off, and a voltage corresponding to Vth is written to the pixel capacitor Cs disposed between the source S and the gate G of the drive transistor Trd. Even when the threshold voltage correction operation is completed, the source voltage Vref−Vth is lower than the value obtained by adding the threshold voltage Vthel of the light emitting element to the cathode potential Vcath.

  Subsequently, at timing T4, the process proceeds to the writing period / mobility correction period. At timing T4, the signal line SL is switched from the reference potential Vref to the signal potential Vsig. The signal potential Vsig is a voltage corresponding to the gradation. Since the sampling transistor Tr1 is on at this time, the potential of the gate G of the drive transistor Trd becomes Vsig. As a result, the drive transistor Trd is turned on and a current flows from the power supply line Vdd, so that the potential of the source S increases with time. At this time, since the potential of the source S still does not exceed the sum of the threshold voltage Vthel and the cathode voltage Vcath of the light emitting element EL, only a slight leakage current flows through the light emitting element EL and is supplied from the drive transistor Trd. Most of the current is used to charge the pixel capacitor Cs and the auxiliary capacitor Csub. As described above, the potential of the source S rises during this charging process.

  Since the threshold voltage correction operation of the drive transistor Trd has already been completed in this writing period, the current supplied by the drive transistor Trd reflects its mobility μ. Specifically, when the mobility μ of the drive transistor Trd is large, the amount of current supplied by the drive transistor Trd is large and the potential of the source S is rapidly increased. Conversely, when the mobility μ is small, the current supply amount of the drive transistor Trd is small, and the potential rise of the source S is delayed. In this way, by negatively feeding back the output current of the drive transistor Trd to the pixel capacitor Cs, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a value reflecting the mobility μ, and moves completely after a certain period of time. The value of Vgs is obtained by correcting the degree μ. That is, during this writing period, the current μ flowing out of the drive transistor Trd is negatively fed back to the pixel capacitor Cs, so that the mobility μ of the drive transistor Trd is corrected at the same time.

  Finally, when the light emission period of the field starts at timing T5, the sampling transistor Tr1 is turned off, and the gate G of the drive transistor Trd is disconnected from the signal line SL. As a result, the potential of the gate G can be increased, and the potential of the source S is increased in conjunction with the increase in the potential of the gate G while keeping the value of Vgs held in the pixel capacitor Cs constant. As a result, the reverse bias state of the light emitting element EL is eliminated, and the drive transistor Trd causes the drain current Ids corresponding to Vgs to flow through the light emitting element EL. The potential of the source S rises until a current flows through the light emitting element EL, and the light emitting element EL emits light. Here, the current / voltage characteristic of the light emitting element changes as the light emission time becomes longer. For this reason, the potential of the source S also changes. However, since the gate / source voltage Vgs of the drive transistor Trd is maintained at a constant value by the bootstrap operation, the current flowing through the light emitting element EL does not change. Therefore, even if the current / voltage characteristics of the light emitting element EL deteriorate, the constant current Ids always flows and the luminance of the light emitting element EL does not change. Further, by incorporating the burn-in suppression system of the present invention, the luminance deterioration of the light emitting element is compensated.

  Also in the fourth embodiment, the drive transistor is in a forward bias state during the light emission period. Further, the source potential and gate potential of the drive transistor are increased by bootstrap after the signal writing operation. Therefore, also in this embodiment, it is desirable to switch the drive transistor of the pixel from the forward bias state to the reverse bias state via the scanning line WS and the signal line SL during the non-light emitting period. Thereby, the enhancement direction shift of the threshold voltage of the drive transistor can be suppressed.

<Fifth embodiment>
[overall structure]
FIG. 13 is a block diagram showing a display panel of a fifth embodiment of the display device according to the present invention. This display device basically includes a pixel array unit 1, a scanner unit, and a signal unit. The scanner unit and the signal unit constitute a drive unit. The pixel array unit 1 includes a first scanning line WS, a second scanning line DS, a third scanning line AZ1 and a fourth scanning line AZ2 arranged in a row, a signal line SL arranged in a column, and these scannings. A matrix pixel circuit 2 connected to the lines WS, DS, AZ1, AZ2 and the signal line SL, and a plurality of first potentials Vss1, second potential Vss2, and third potential Vdd necessary for the operation of each pixel circuit 2. Power line. The signal unit includes a horizontal selector 3 and supplies a video signal to the signal line SL. The scanner unit includes a write scanner 4, a drive scanner 5, a first correction scanner 71, and a second correction scanner 72. The first scan line WS, the second scan line DS, the third scan line AZ1, and the fourth scan, respectively. A control signal is supplied to the line AZ2 to sequentially scan the pixel circuit 2 for each row.

[Pixel circuit configuration]
FIG. 14 is a circuit diagram showing a configuration of a pixel incorporated in the display device shown in FIG. The pixel of this embodiment is characterized in that it is composed of five transistors. As illustrated, the pixel circuit 2 includes a sampling transistor Tr1, a drive transistor Trd, a first switching transistor Tr2, a second switching transistor Tr3, a third switching transistor Tr4, a pixel capacitor Cs, and a light emitting element EL. Including. The sampling transistor Tr1 conducts in response to a control signal supplied from the scanning line WS during a predetermined sampling period, and samples the signal potential of the video signal supplied from the signal line SL into the pixel capacitor Cs. The pixel capacitor Cs applies an input voltage Vgs to the gate G of the drive transistor Trd in accordance with the signal potential of the sampled video signal. The drive transistor Trd supplies an output current Ids corresponding to the input voltage Vgs to the light emitting element EL. The light emitting element EL emits light with a luminance corresponding to the signal potential of the video signal by the output current Ids supplied from the drive transistor Trd during a predetermined light emission period.

  The first switching transistor Tr2 conducts in response to a control signal supplied from the scanning line AZ1 prior to the sampling period (video signal writing period), and sets the gate G, which is the control terminal of the drive transistor Trd, to the first potential Vss1. . The second switching transistor Tr3 conducts in response to a control signal supplied from the scanning line AZ2 prior to the sampling period, and sets the source S, which is one current end of the drive transistor Trd, to the second potential Vss2. The third switching transistor Tr4 is turned on in response to a control signal supplied from the scanning line DS prior to the sampling period, and connects the drain which is the other current end of the drive transistor Trd to the third potential Vdd. A voltage corresponding to the threshold voltage Vth of Trd is held in the pixel capacitor Cs to correct the influence of the threshold voltage Vth. Further, the third switching transistor Tr4 is turned on again in response to the control signal supplied from the scanning line DS during the light emission period, connects the drive transistor Trd to the third potential Vdd, and causes the output current Ids to flow through the light emitting element EL.

  As is apparent from the above description, the pixel circuit 2 is composed of five transistors Tr1 to Tr4 and Trd, one pixel capacitor Cs, and one light emitting element EL. The transistors Tr1 to Tr3 and Trd are N channel type polysilicon TFTs. Only the transistor Tr4 is a P-channel type polysilicon TFT. However, the present invention is not limited to this, and N-channel and P-channel TFTs can be mixed as appropriate. The light emitting element EL is, for example, a diode type organic EL device having an anode and a cathode. However, the present invention is not limited to this, and the light emitting element generally includes all devices that emit light by current drive.

  FIG. 15 is a schematic diagram in which only the pixel circuit 2 is extracted from the display panel shown in FIG. In order to facilitate understanding, the signal potential Vsig of the video signal sampled by the sampling transistor Tr1, the input voltage Vgs and output current Ids of the drive transistor Trd, and the capacitance component Coled of the light emitting element EL are added. . The operation of the pixel circuit 2 according to the present invention will be described below with reference to FIG.

[Operation of Fifth Embodiment]
FIG. 16 is a timing chart of the pixel circuit shown in FIG. FIG. 16 shows the waveforms of control signals applied to the scanning lines WS, AZ1, AZ2, and DS along the time axis T. In order to simplify the notation, the control signals are also represented by the same reference numerals as the corresponding scanning lines. Since the transistors Tr1, Tr2 and Tr3 are N-channel type, they are turned on when the scanning lines WS, AZ1 and AZ2 are at a high level, and turned off when the scanning lines are at a low level. On the other hand, since the transistor Tr4 is a P-channel type, it is turned off when the scanning line DS is at a high level and turned on when it is at a low level. This timing chart also shows the change in the potential of the gate G and the change in the potential of the source S of the drive transistor Trd, along with the waveforms of the control signals WS, AZ1, AZ2, and DS.

  In the timing chart of FIG. 16, timings T1 to T8 are defined as one field (1f). Each row of the pixel array is sequentially scanned once during one field. The timing chart shows the waveforms of the control signals WS, AZ1, AZ2, DS applied to the pixels for one row.

  At timing T0 before the field starts, all control line numbers WS, AZ1, AZ2, DS are at a low level. Therefore, the N-channel transistors Tr1, Tr2, Tr3 are in the off state, while only the P-channel transistor Tr4 is in the on state. Therefore, since the drive transistor Trd is connected to the power supply Vdd via the transistor Tr4 in the on state, the output current Ids is supplied to the light emitting element EL according to the predetermined input voltage Vgs. Therefore, the light emitting element EL emits light at the timing T0. At this time, the input voltage Vgs applied to the drive transistor Trd is expressed by the difference between the gate potential (G) and the source potential (S).

  At the timing T1 when the field starts, the control signal DS is switched from the low level to the high level. As a result, the switching transistor Tr4 is turned off and the drive transistor Trd is disconnected from the power supply Vdd, so that the light emission stops and the non-light emission period starts. Therefore, at the timing T1, all the transistors Tr1 to Tr4 are turned off.

  Subsequently, at timing T2, since the control signals AZ1 and AZ2 are at a high level, the switching transistors Tr2 and Tr3 are turned on. As a result, the gate G of the drive transistor Trd is connected to the reference potential Vss1, and the source S is connected to the reference potential Vss2. Here, Vss1−Vss2> Vth is satisfied, and by setting Vss1−Vss2 = Vgs> Vth, preparation for Vth correction performed at timing T3 is performed. In other words, the period T2-T3 corresponds to a reset period of the drive transistor Trd. Further, when the threshold voltage of the light emitting element EL is VthEL, VthEL> Vss2 is set. Thereby, a minus bias is applied to the light emitting element EL, and a so-called reverse bias state is obtained. This reverse bias state is necessary for normally performing the Vth correction operation and the mobility correction operation to be performed later.

  At timing T3, the control signal AZ2 is set to the low level, and the control signal DS is also set to the low level. As a result, the transistor Tr3 is turned off while the transistor Tr4 is turned on. As a result, the drain current Ids flows into the pixel capacitor Cs, and the Vth correction operation is started. At this time, the gate G of the drive transistor Trd is held at Vss1, and the current Ids flows until the drive transistor Trd is cut off. When cut off, the source potential (S) of the drive transistor Trd becomes Vss1-Vth. At timing T4 after the drain current is cut off, the control signal DS is returned to the high level again, and the switching transistor Tr4 is turned off. Further, the control signal AZ1 is also returned to the low level, and the switching transistor Tr2 is also turned off. As a result, Vth is held and fixed in the pixel capacitor Cs. Thus, the timing T3-T4 is a period for detecting the threshold voltage Vth of the drive transistor Trd. Here, this detection period T3-T4 is called a Vth correction period.

  After performing the Vth correction in this way, the control signal WS is switched to the high level at timing T5, the sampling transistor Tr1 is turned on, and the video signal Vsig is written into the pixel capacitor Cs. The pixel capacitance Cs is sufficiently smaller than the equivalent capacitance Coled of the light emitting element EL. As a result, most of the video signal Vsig is written into the pixel capacitor Cs. Precisely, the difference Vsig−Vss1 of Vsig with respect to Vss1 is written in the pixel capacitor Cs. Therefore, the voltage Vgs between the gate G and the source S of the drive transistor Trd becomes a level (Vsig−Vss1 + Vth) obtained by adding Vth previously detected and held and Vsig−Vss1 sampled this time. In the following description, assuming Vss1 = 0V for simplification of explanation, the gate / source voltage Vgs becomes Vsig + Vth as shown in the timing chart of FIG. The sampling of the video signal Vsig is performed until timing T7 when the control signal WS returns to the low level. That is, the timing T5-T7 corresponds to the sampling period (video signal writing period).

  At timing T6 before the end of the sampling period T7, the control signal DS becomes low level and the switching transistor Tr4 is turned on. As a result, the drive transistor Trd is connected to the power supply Vdd, so that the pixel circuit proceeds from the non-light emitting period to the light emitting period. In this manner, the mobility correction of the drive transistor Trd is performed in the period T6-T7 in which the sampling transistor Tr1 is still on and the switching transistor Tr4 is on. That is, in this example, the mobility correction is performed in a period T6-T7 in which the rear part of the sampling period and the head part of the light emission period overlap. Note that, at the beginning of the light emission period in which the mobility correction is performed, the light emitting element EL is actually in a reverse bias state, and thus does not emit light. In the mobility correction period T6-T7, the drain current Ids flows through the drive transistor Trd while the gate G of the drive transistor Trd is fixed at the level of the video signal Vsig. Here, by setting Vss1−Vth <VthEL, the light emitting element EL is placed in a reverse bias state, so that it exhibits simple capacitance characteristics instead of diode characteristics. Therefore, the current Ids flowing through the drive transistor Trd is written into a capacitor C = Cs + Coled obtained by combining both the pixel capacitor Cs and the equivalent capacitor Coled of the light emitting element EL. As a result, the source potential (S) of the drive transistor Trd increases. In the timing chart of FIG. 23, this increase is represented by ΔV. Since this increase ΔV is eventually subtracted from the gate / source voltage Vgs held in the pixel capacitor Cs, negative feedback is applied. In this way, the mobility μ can be corrected by negatively feeding back the output current Ids of the drive transistor Trd to the input voltage Vgs of the drive transistor Trd. The negative feedback amount ΔV can be optimized by adjusting the time width t of the mobility correction period T6-T7.

At timing T7, the control signal WS becomes low level and the sampling transistor Tr1 is turned off. As a result, the gate G of the drive transistor Trd is disconnected from the signal line SL. Since the application of the video signal Vsig is cancelled, the gate potential (G) of the drive transistor Trd can be increased and increases with the source potential (S). Meanwhile, the gate / source voltage Vgs held in the pixel capacitor Cs maintains a value of (Vsig−ΔV + Vth). As the source potential (S) rises, the reverse bias state of the light emitting element EL is canceled, so that the light emitting element EL actually starts to emit light by the inflow of the output current Ids. The relationship between the drain current Ids and the gate voltage Vgs at this time is given by the following equation by substituting Vsig−ΔV + Vth into Vgs of the previous transistor characteristic equation 1.
Ids = kμ (Vgs−Vth) ² = kμ (Vsig−ΔV) ²
In the above formula, k = (1/2) (W / L) Cox. From this characteristic equation, it can be seen that the term Vth is canceled and the output current Ids supplied to the light emitting element EL does not depend on the threshold voltage Vth of the drive transistor Trd. Basically, the drain current Ids is determined by the signal voltage Vsig of the video signal. In other words, the light emitting element EL emits light with a luminance corresponding to the video signal Vsig. At that time, Vsig is corrected by the negative feedback amount ΔV. This correction amount ΔV works so as to cancel the effect of mobility μ located just in the coefficient part of the characteristic equation. Therefore, the drain current Ids substantially depends only on the video signal Vsig.

  Finally, when the timing T8 is reached, the control signal DS becomes high level, the switching transistor Tr4 is turned off, the light emission ends, and the field ends. Thereafter, the operation proceeds to the next field, and the Vth correction operation, the mobility correction operation, and the light emission operation are repeated again.

  In the fifth embodiment described above, the drive transistor is in a forward bias state during the light emission period. Further, after the signal writing operation, the gate potential and the source potential of the drive transistor are raised by the bootstrap. Therefore, also in this embodiment, it is desirable to switch the drive transistor of each pixel from the forward bias state to the reverse bias state via the scanning line WS and the signal line in the non-light emitting period.

<Application form>
The display device according to the present invention has a thin film device configuration as shown in FIG. In FIG. 17, the TFT portion has a bottom gate structure (the gate electrode is below the channel PS layer). In addition, the TFT portion has variations such as a Sandwich gate structure (a channel PS layer is sandwiched between upper and lower gate electrodes) and a Top gate structure (a gate electrode is above the channel PS layer). This figure shows a schematic cross-sectional structure of a pixel formed on an insulating substrate. As shown in the figure, the pixel includes a transistor portion (a single TFT is illustrated in the figure) including a plurality of thin film transistors, a capacitor portion such as a pixel capacitor, and a light emitting portion such as an organic EL element. A transistor portion and a capacitor portion are formed on a substrate by a TFT process, and a light emitting portion such as an organic EL element is stacked thereon. A transparent counter substrate is pasted thereon via an adhesive to form a flat panel.

  The display device according to the present invention includes a flat module-shaped display as shown in FIG. For example, a pixel array unit in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated in a matrix is provided on an insulating substrate, and an adhesive is disposed so as to surround the pixel array unit (pixel matrix unit). Then, a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and can be applied to various electronic devices such as a digital camera, a notebook personal computer, a mobile phone, and a video camera. The present invention can be applied to a display of an electronic device in any field that displays a drive signal input to the electronic device or generated in the electronic device as an image or a video. Examples of electronic devices to which such a display device is applied are shown below. The electronic device basically includes a main body that processes information, and a display that displays information input to the main body or information output from the main body.

  FIG. 19 shows a television to which the present invention is applied, including a video display screen 11 composed of a front panel 12, a filter glass 13, and the like, and is produced by using the display device of the present invention for the video display screen 11. .

  FIG. 20 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a rear view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 21 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 operated when inputting characters and the like, and the main body cover includes a display unit 22 for displaying an image. This display device is used for the display portion 22.

  FIG. 22 shows a portable terminal device to which the present invention is applied. The left represents an open state, and the right represents a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub display 27, a picture light 28, a camera 29, and the like. It is manufactured by using the display device of the present invention for the display 26 or the sub-display 27.

  FIG. 23 shows a video camera to which the present invention is applied, which includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. on the side facing forward. It is manufactured by using the device for its monitor 36.

1 is a block diagram showing an overall configuration of a first embodiment of a display device according to the present invention. It is a circuit diagram which shows the structure of the pixel of 1st embodiment. It is a reference example of a timing chart. It is a reference example of a timing chart. It is a timing chart with which it uses for operation | movement description of 1st embodiment of the display apparatus which concerns on this invention. It is a schematic diagram similarly used for operation | movement description of 1st embodiment. It is a schematic diagram similarly used for operation | movement description of 1st embodiment. It is a timing chart with which it uses for operation | movement description of 2nd embodiment of the display apparatus which concerns on this invention. 12 is a timing chart for explaining the operation of the third embodiment. It is a block diagram which shows the panel structure of 4th embodiment of the display apparatus which concerns on this invention. It is a circuit diagram which shows the structure of a pixel circuit. It is a timing chart with which operation | movement description is provided. It is a block diagram which shows the display panel of 5th embodiment of the display apparatus which concerns on this invention. It is a pixel circuit diagram of a fifth embodiment. It is a pixel circuit diagram similarly. It is a timing chart used for operation | movement description of 5th embodiment. It is sectional drawing which shows the device structure of the display apparatus concerning the application form of this invention. It is a top view which shows the module structure of the display apparatus concerning the application form of this invention. It is a perspective view which shows the television set provided with the display apparatus concerning the application form of this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning the application form of this invention. It is a perspective view which shows the notebook type personal computer provided with the display apparatus concerning the application form of this invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning the application form of this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning the application form of this invention.

Explanation of symbols

1: Pixel array unit 2: Pixel 3: Horizontal selector 4: Write scanner 6: Power supply scanner Tr1: Sampling transistor Trd: Drive transistor Cs: Pixel capacitance EL: Light emitting element

Claims (9)

A pixel array unit and a drive unit;
The pixel array unit includes scanning lines arranged in rows, signal lines arranged in columns, and matrix-like pixels arranged in portions where each scanning line and each signal line intersect,
The driving unit sequentially supplies a control signal to each scanning line over one field period, and supplies a video signal to each signal line,
The pixel includes at least a sampling transistor, a drive transistor, and a light emitting element,
The sampling transistor captures a video signal from the signal line according to a control signal supplied from the scanning line,
The drive transistor is in a forward bias state in the light emission period of one field period, and supplies a drive current according to the captured video signal.
The light emitting element emits light with luminance according to the video signal by the driving current,
The drive unit switches a drive transistor of each pixel from a forward bias state to a reverse bias state via the scanning line and the signal line in a non-light emission period of one field period. The driving unit outputs a control signal to the scanning line in one horizontal cycle and outputs a video signal in which the signal potential and the reference potential are switched in one horizontal cycle to the signal line,
The sampling transistor captures a signal potential in response to a first control signal, so that the drive transistor is in a forward bias state during a light emission period and supplies a drive current corresponding to the signal potential to the light emitting element.
The display device according to claim 1, wherein the sampling transistor captures a reference potential according to a second control signal in a non-light emitting period, and thereby the drive transistor is in a reverse bias state.   The display device according to claim 2, wherein the sampling transistor repeatedly captures a reference potential according to a second control signal that is repeatedly output over a plurality of horizontal periods in a non-light emitting period. The driving unit supplies a video signal that is switched between a signal potential, a first reference potential, and a second reference potential that is further away from the signal potential within one horizontal cycle to the signal line,
The sampling transistor captures a first reference potential according to a control signal preceding the first control signal and initializes the drive transistor, and then captures a signal potential according to the first control signal,
The display device according to claim 2, wherein the sampling transistor captures a second reference potential in accordance with a second control signal. The drive transistor has a gate connected to the sampling transistor, a source connected to the light emitting element, and a pixel capacitor connected between the gate and the source,
The sampling transistor is turned on in response to the first control signal, and the signal potential is written between the gate and the source of the drive transistor to be in a forward bias state.
The drive transistor is a light emission period in which a drive current is supplied to the light emitting element according to the signal potential after the sampling transistor is turned off, and the source potential is increased while maintaining a potential difference between the gate and the source,
3. The sampling transistor according to claim 2, wherein the sampling transistor is turned on in response to the second control signal, a reference potential is written to the gate of the drive transistor, and the source and gate potentials are reversed to switch to a reverse bias state. Display device.   The display device according to claim 5, wherein the absolute value of the potential difference between the gate and the source when the drive transistor is in the reverse bias state is larger than the absolute value of the potential difference between the gate and the source when the drive transistor is in the forward bias state.   The display device according to claim 1, wherein a non-light emission period in which the drive transistor is in a reverse bias state within one field period is longer than a light emission period in which the drive transistor is in a forward bias state. A main body and a display for displaying information input to the main body or information output from the main body,
The display device includes a pixel array unit and a drive unit,
The pixel array unit includes scanning lines arranged in rows, signal lines arranged in columns, and matrix-like pixels arranged in portions where each scanning line and each signal line intersect,
The driving unit sequentially supplies a control signal to each scanning line over one field period, and supplies a video signal to each signal line,
The pixel includes at least a sampling transistor, a drive transistor, and a light emitting element,
The sampling transistor captures a video signal from the signal line according to a control signal supplied from the scanning line,
The drive transistor is in a forward bias state in the light emission period of one field period, and supplies a drive current according to the captured video signal.
The light emitting element emits light with luminance according to the video signal by the driving current,
The electronic device is an electronic device that switches a drive transistor of each pixel from a forward bias state to a reverse bias state via the scanning line and the signal line in a non-light emission period of one field period. It consists of a pixel array part and a drive part,
The pixel array unit includes scanning lines arranged in rows, signal lines arranged in columns, and matrix-like pixels arranged in portions where each scanning line and each signal line intersect,
The driving unit sequentially supplies a control signal to each scanning line over one field period, and supplies a video signal to each signal line,
The pixel drives a display device including at least a sampling transistor, a drive transistor, and a light emitting element.
The sampling transistor captures a video signal from the signal line according to a control signal supplied from the scanning line,
The drive transistor is in a forward bias state in a light emission period of one field period, and supplies a drive current according to the captured video signal,
The light emitting element emits light with a luminance corresponding to the video signal by the driving current;
The method for driving a display device, wherein the driving unit switches a drive transistor of each pixel from a forward bias state to a reverse bias state via the scanning line and the signal line in a non-light emitting period of one field period.

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