JP2009090416A - Method of manufacturing membrane structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a membrane structure capable of preventing a membrane from being damaged. <P>SOLUTION: This method comprises a step of forming a resist film pattern on the Si base of an SOI wafer, a step of pasting a support plate with grooves and the Si film of the SOI wafer through an adhesive layer, a step of dry-etching the resist film pattern as an etching mask to the Si oxidized film of the SOI wafer, and a step of separating the SOI wafer and the support plate from each other. The adhesive layer uses a silicone oil of 20-1,000 mm<SP>2</SP>/s in kinematic viscosity at 25°C. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a membrane structure using an SOI (Silicon On Insulator) wafer.

  The membrane structure is a structure having a membrane (thin film). For example, Patent Document 1 is manufactured by bonding a support (for example, Si wafer) to an SOI wafer having a silicon substrate, a silicon oxide film, and a silicon film. A chip-shaped structure (membrane chip) has been proposed.

  The membrane chip is manufactured as follows, for example. First, a resist film pattern is formed on a silicon substrate of an SOI wafer having a silicon substrate, a silicon oxide film, and a silicon film, and a support (for example, a Si wafer) is bonded to the silicon film side of the SOI wafer via an adhesive layer. Next, the silicon substrate is etched away using the resist film pattern as an etching mask to form an opening, and the silicon oxide film is exposed in the opening. Then, after separating the support, the exposed silicon oxide film is removed with hydrofluoric acid or the like to form a membrane made of a silicon film, and then the chip is formed into individual pieces.

  However, the silicon film as a membrane is a thin film having a thickness of about several μm, and is not strong enough against external impacts and stresses, and the membrane is easily damaged when separated from the support.

In Patent Document 1, a photoresist or the like is used for an adhesive layer for bonding an SOI wafer and a support. However, when such a solid material is used, the SOI wafer and the support are separated. In addition, a part of the adhesive layer tends to adhere and remain on the silicon film side of the SOI wafer. Although a process of removing the adhesive layer remaining on the silicon film side of the SOI wafer (for example, a cleaning process) is further required, the membrane is easily damaged.
JP 2006-32716 A

  The objective of this invention is providing the manufacturing method of the membrane structure which can prevent damage to a membrane.

The method for manufacturing a membrane structure according to one aspect of the present invention includes a step of forming a mask pattern on one surface of a substrate, a surface opposite to the mask pattern forming surface of the substrate, and a groove on at least one surface. Bonding the groove-formed surface of the support formed with an adhesive layer, etching the substrate using the mask pattern as an etching mask, and separating the substrate and the support And the adhesive layer is a silicone oil having a kinematic viscosity of 20 to 1000 mm ² / s at 25 ° C.

  In the present invention, the membrane means a free-standing thin film having a thickness of, for example, several nanometers to several tens of micrometers composed of at least one layer made of a metal material or a semiconductor material.

  With the above configuration, the membrane can be prevented from being damaged.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, although embodiment of this invention is described below based on drawing, those drawings are provided for illustration and this invention is not limited to those drawings.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing a membrane structure (hereinafter referred to as a membrane chip) according to the first embodiment of the present invention.

  As shown in FIG. 1, the membrane chip 1 has an opening 5 in the approximate center, and a membrane composed of a silicon film 4 is exposed in the opening 5. Further, the membrane chip 1 is composed of a silicon substrate 2, a silicon oxide film 3 and a silicon film 4 in order from the surface in FIG. 1, and the thickness of each layer is, for example, 400 μm for the silicon substrate 2 and 1 μm for the silicon oxide film 3. The silicon film 4 is 6 μm.

  The membrane chip 1 of this embodiment described above is manufactured, for example, as follows. FIG. 2 is a flowchart showing the flow of the manufacturing process of the membrane chip 1 shown in FIG. 3-10 is sectional drawing which shows typically the manufacturing process of the membrane chip shown in FIG.

  As shown in FIG. 3, an SOI wafer 31 (substrate) composed of a silicon substrate 2, a silicon oxide film 3, and a silicon film 4 is prepared in order from the surface, washed and dried. As shown in FIG. 4, after applying a photoresist on the silicon substrate 2 of the SOI wafer 31, exposure and development are sequentially performed to remove unnecessary portions of the photoresist, thereby forming a resist film pattern 6 (step). 1).

  Next, a support plate 21 (support) having a first main surface (hereinafter referred to as a groove formation surface) in which the groove 20 is formed is prepared, and as shown in FIG. 5, the silicon film 4 of the SOI wafer 31 and It bonds together through the adhesive layer 100 so that the groove formation surface of the support plate 21 may face (step 2).

  In this embodiment, a Si wafer is used as a constituent material of the support plate 21. However, the groove 20 can be easily formed, and is particularly limited as long as the SOI wafer 31 can be reinforced and supported in the etching process of the SOI wafer 31. For example, an insulating film (for example, an oxide film, a nitride film, or the like) may be formed on the surface of the Si wafer. In addition, an insulating substrate such as glass or synthetic resin may be used. Further, the shape and size of the support plate 21 are not particularly limited, and those having the same shape and size as those of the SOI wafer 31 can be suitably used. In the present embodiment, the support plate 21 has a substantially circular shape similar to that of the SOI wafer 31, and the diameter thereof is substantially the same as the diameter of the SOI wafer 31. The thickness of the support plate 21 may be any thickness as long as the groove 20 can be easily formed and can support the SOI wafer 31 in the etching process, and is preferably 400 to 800 μm, for example.

  The shape of the groove 20 of the support plate 21 preferably has a straight line and / or curved line continuous from one edge to the other edge. In addition to the straight line and / or curved line, a centrally symmetric circular shape or rectangular shape is used. It is more preferable to have. For example, FIG. 11 shows a plurality of straight lines that extend from one edge to the other edge through the center P of the groove forming surface, and a circular groove centered on the point P. FIG. 12 shows a plurality of straight lines that extend from one edge portion to the other edge portion through the center P of the groove forming surface, and a rectangular groove having the point P as the center. Such a groove 20 can be formed by dry etching such as RIE (Reactive Ion Etching), for example, when a Si wafer is used for the support plate 21 as in this embodiment.

  The width of the groove 20 is preferably 10 to 100 μm, and the depth of the groove 20 is preferably 10 to 100 μm. By forming the groove 20 having such a shape, the adhesive layer 100 spreads over the entire groove forming surface without being biased to a part of the groove forming surface, and therefore, the SOI wafer 31 can be removed from the support plate 21 without damaging the membrane. Can be easily separated.

The adhesive layer 100, in order to prevent damage to the membrane during the separation of the SOI wafer 31 from the support plate 21, 25 kinematic viscosity at ℃ is 20~1000mm ² / s, the silicone preferably 50 to 500 mm ² / s Use oil. The kinematic viscosity is measured by a capillary tube viscometer in accordance with JIS Z 8809.

  Compared with a solid material such as a photoresist, the silicone oil further requires a cleaning process in which the solid matter adheres to the silicon film 4 of the SOI wafer 31 and is removed when the SOI wafer 31 is separated from the support plate 21. There is no such thing. For this reason, the membrane can be prevented from being damaged by the cleaning process, and the working efficiency is improved. Silicone oil is more stable in viscosity than other oils and is less affected by contamination of the membrane chip 1.

Further, among the silicone oils, those having a kinematic viscosity in the above range are used. When the kinematic viscosity is less than 20 mm ² / s, not only the membrane is easily damaged during separation from the support plate 21, but also when the support plate 21 having grooves and the SOI wafer 31 are bonded together, It is difficult to maintain adhesion. In addition, when the SOI wafer 31 is dry-etched after the support plate 21 and the SOI wafer 31 are bonded together, the temperature during the dry etching is usually 50 to 100 ° C., so there is a possibility of volatilization and ignition. is there.

On the other hand, when the kinematic viscosity exceeds 1000 mm ² / s, not only the membrane is easily damaged during separation from the support plate 21, but also it is difficult to apply uniformly.

  As described above, since the silicone oil having a specific kinematic viscosity is used for the adhesive layer 100, the support plate 21 and the SOI wafer are slid by sliding the support plate 21 in the horizontal direction (the horizontal direction with respect to the SOI wafer 31). 31 can be easily separated, and the membrane can be effectively prevented from being damaged during the separation.

  Next, as shown in FIG. 6, dry etching (for example, RIE: reactive ion etching) is performed using the resist film pattern 6 as an etching mask and the silicon oxide film 3 as an etching stop layer. As a result, unnecessary portions of the silicon substrate 2 are removed to form the opening 5, and the silicon oxide film 3 is exposed in the opening 5 (step 3).

  Subsequently, the support plate 21 is slid in the horizontal direction (the horizontal direction with respect to the SOI wafer 31) to separate the SOI wafer 31 and the support plate 21 as shown in FIG. 7 (step 4).

  Next, after the used resist film pattern 6 is removed (step 5), the silicon oxide film 3 in the opening 5 is removed with hydrofluoric acid (step 6). Thereby, the silicon film 4 remaining in the opening 5 becomes a membrane (see FIG. 8).

  Subsequently, as shown in FIG. 9, along the dicing lines 90, the SOI wafer 31 is divided into chips (step 7).

  In this way, the membrane chip 1 as shown in FIG. 10 is manufactured.

As described above, in this embodiment, the groove 20 is formed in the support plate 21, and the kinematic viscosity at 25 ° C. is 20 so that the silicon film 4 of the SOI wafer 31 and the groove formation surface of the support plate 21 face each other. Bonding is performed through an adhesive layer 100 of ˜1000 mm ² / s. Thereby, the membrane chip 1 can be manufactured without damaging the membrane formed in the opening 5 of the SOI wafer 31. Therefore, the yield can be improved and the highly reliable membrane chip 1 can be provided.

  In the present embodiment, the resist substrate pattern 6 is used as an etching mask, the silicon oxide film 3 is used as an etching stop layer, and the silicon substrate 2 of the SOI wafer 31 is removed by etching to form the opening 5. The support plate 21 is separated, the resist film pattern 6 is removed, and the silicon oxide film 3 remaining in the opening 5 is removed to produce a membrane. However, the present invention is not limited to this.

  For example, after the silicon oxide film 3 is used as an etching stop layer and the silicon substrate 2 of the SOI wafer 31 is removed by etching to form the opening 5, the SOI wafer is separated into chips along the dicing lines 90. The SOI wafer 31 and the support plate 21 may be separated, the resist film pattern 6 may be removed, and the silicon oxide film 3 remaining in the opening 5 may be removed to produce a membrane.

  In this embodiment, a resist film is used as an etching mask. However, the present invention is not limited to this. For example, a silicon oxide film, a silicon nitride film, a metal, or the like may be used.

The present invention is illustrated by examples. In this example, it is preferable to use a silicone oil having a kinematic viscosity of 20 to 1000 mm ² / s at 25 ° C. in the adhesive layer in the manufacturing process of the membrane structure according to the embodiment shown in FIGS. The reason will be described with reference to Table 1. The peelability, adhesiveness, applicability, and flash point shown in Table 1 were evaluated as follows. The silicone oil used in Examples and Comparative Examples is SH200 manufactured by Toray Dow Corning Co., Ltd., and each has different kinematic viscosities as shown in Table 1.

[Peelability]
When the SOI wafer having a multifaceted membrane chip was separated from the support plate, the breakage rate of the membrane was observed with an optical microscope and measured visually. The breakage rate was 0 to 10% as ◎, 10 to 30% as ○, 30 to 50% as Δ, and 50% or more as ×.

[Adhesiveness]
In the manufacturing process of the membrane chip, the case where the adhesion between the SOI wafer and the support plate was maintained was evaluated as ◯, and the case where the adhesion was not maintained was evaluated as ×.

[Applicability]
A sample that could be applied uniformly was marked with ◯, and a sample with uneven coating was marked with ×.

[Flash point]
In the membrane chip manufacturing process, when the support plate and SOI wafer are bonded together via silicone oil, and the SOI wafer is dry-etched, the silicone oil volatilizes and a process error (process stop due to an error on the device) occurs. Those that occurred were marked with ×, and those where no process abnormality occurred were marked with ○.

As it is evident from Table 1, as an adhesive layer, 25 a kinematic viscosity at ℃ is 20~1000mm ² / s, in particular the membrane chip embodiment using the silicone oil of 50 to 500 mm ² / s is an SOI wafer support plate The membrane can be effectively prevented from being damaged when separated from the membrane. Furthermore, it can be applied uniformly, has excellent adhesion between the SOI wafer and the support plate, and does not volatilize and cause a process abnormality.

1 is a cross-sectional view schematically showing a membrane chip according to a first embodiment of the present invention. The flowchart which showed the flow of the manufacturing process of the membrane chip | tip shown in FIG. Sectional drawing which shows the manufacturing process of the membrane chip | tip shown in FIG. Sectional drawing which shows the manufacturing process of the membrane chip | tip shown in FIG. Sectional drawing which shows the manufacturing process of the membrane chip | tip shown in FIG. Sectional drawing which shows the manufacturing process of the membrane chip | tip shown in FIG. Sectional drawing which shows the manufacturing process of the membrane chip | tip shown in FIG. Sectional drawing which shows the manufacturing process of the membrane chip | tip shown in FIG. Sectional drawing which shows the manufacturing process of the membrane chip | tip shown in FIG. Sectional drawing which shows the manufacturing process of the membrane chip | tip shown in FIG. The top view which shows typically the shape of the groove | channel formed in the support plate. The top view which shows typically the shape of the groove | channel formed in the support plate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Membrane chip, 2 ... Silicon substrate, 3 ... Silicon oxide film, 4 ... Silicon film, 5 ... Opening part, 6 ... Resist film pattern, 31 ... SOI wafer, 20 ... Groove, 21 ... Support plate, 100 ... Adhesive layer .

Claims (4)

Forming a mask pattern on one side of the substrate;
Bonding the surface on the opposite side of the mask pattern forming surface of the substrate and the groove forming surface of the support having grooves formed on at least one surface via an adhesive layer;
Etching the substrate using the mask pattern as an etching mask;
Separating the substrate and the support; and
The method for producing a membrane structure, wherein the adhesive layer is a silicone oil having a kinematic viscosity of 20 to 1000 mm ² / s at 25 ° C.   2. The method for manufacturing a membrane structure according to claim 1, wherein the shape of the groove on the groove forming surface has a straight line and / or a curved line continuous from one edge to the other edge.   The method of manufacturing a membrane structure according to claim 1 or 2, wherein the support is a Si wafer or a Si wafer on which an insulating film is formed.   The substrate is an SOI wafer composed of a silicon substrate, a silicon oxide film, and a silicon film, the mask pattern is formed on the silicon substrate of the SOI wafer, and a groove forming surface of the silicon film of the SOI wafer and the support body The method for producing a membrane structure according to any one of claims 1 to 3, wherein the two are bonded together via the adhesive layer.

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