CN105712287A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN105712287A CN105712287A CN201410720639.7A CN201410720639A CN105712287A CN 105712287 A CN105712287 A CN 105712287A CN 201410720639 A CN201410720639 A CN 201410720639A CN 105712287 A CN105712287 A CN 105712287A
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Abstract
A semiconductor device manufacturing method is as follows: a gold layer is patterned by multi-times of wet etching, a wet etching solution is an aqueous solution comprising KI and I2, the time of each time of wet etching is less than 2 minutes, and after each time of wet etching, deionized water is used for rinsing, so that byproducts produced in each time of wet etching can be peeled off in time, further etching rate slow down of the gold layer caused by coating of the gold layer with etching byproducts produced by one-time long-time etching of the gold layer can be avoided, and the problems of gold residues and low undercut quantity uniformity of a plurality of formed gold pattern blocks caused by different etching rates of different areas can be avoided.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the manufacture method of a kind of semiconductor device.
Background technology
In semiconductor device, some devices, need to perform etching gold (Au) layer to form gold pattern block, for instance in MEMS, the Au-Si eutectic bonding between two wafers need to form gold pattern block on a wafer, to be bonded with the silicon on another wafer.Au-Si eutectic bonding is the feature utilizing Au-Si eutectic alloy melt temperature relatively low (363 DEG C, more much lower than proof gold or pure silicon fusing point), using it as middle dielectric layer, passes through to add heat fusing at a lower temperature and realizes eutectic bonding.
In actual process find, there are some problems in the existing etching process to layer gold, for instance one, easily go out cash residual；Two, it is not high that uniformity is measured in undercutting (Undercut), and the amount of laterally removing of the multiple gold pattern blocks namely formed with a collection of etching not etc., does not have many, and what have lacks.The problems referred to above all will affect the firmness of two wafers of eutectic bonding.
For the problems referred to above, the present invention provides the manufacture method of a kind of new semiconductor device to solve.
Summary of the invention
The etching that the problem that this invention address that is existing layer gold easily goes out cash residual, and the undercutting amount uniformity of multiple gold pattern block is not high.
For solving the problems referred to above, the present invention provides the manufacture method of a kind of semiconductor device, including:
Semiconductor substrate is provided, described Semiconductor substrate has layer gold, described layer gold has patterned mask layer；
Described layer gold is patterned with described patterned mask layer for mask, described layer gold be patterned into wet etching, the solution of employing is for comprising KI and I2Aqueous solution, described wet etching carries out several times, the time of each wet etching less than 2 minutes, each wet etching complete after adopts deionized water rinsing.
Alternatively, the time of each wet etching was less than 1 minute.
Alternatively, the number of times of described wet etching is more than 4 times.
Alternatively, the time of each deionized water rinsing was more than 2 minutes.
Alternatively, the time range of each deionized water rinsing is: 2 minutes～5 minutes.
Alternatively, in the aqueous solution that wet etching adopts, I2Mass percent less than 2%, the mass percent of KI is less than 5%, and the mass percent of deionized water is more than 93%.
Alternatively, in the aqueous solution that wet etching adopts, I2Mass percent be 1.3%, the mass percent of KI is 4%, and the mass percent of deionized water is 94.7%.
Alternatively, the thickness of described layer gold is 300 nanometers, and the undercutting amount of the graphical each gold pattern block formed is less than 3 microns.
Alternatively, described Semiconductor substrate material is silicon, and described mask layer material is photoresist.
Alternatively, after described layer gold is graphical, low-pressure air current is adopted to dry up.
Alternatively, described semiconductor device is MEMS, and described patterned layer gold is used for wafer bonding.
Alternatively, described semiconductor device is MEMS, and described MEMS has movable sensitive thin film and fixed electrode, and described patterned layer gold draws the contact electrode of movable sensitive thin film and the fixed electrode signal of telecommunication for being formed.
Compared with prior art, technical scheme has the advantage that 1) adopt repeatedly wet etching that layer gold is patterned, wet etching solution is for comprising KI and I2Aqueous solution, the time of each wet etching was less than 2 minutes, deionized water rinsing is adopted after each wet etching is complete, so, the by-product that corrosion produces every time can be able to timely stripping, avoid once corroding for a long time the etch by-products that layer gold produces to be coated with this layer gold and cause the further corrosion rate of this layer gold to slow down, avoid the gold residual that zones of different corrosion rate difference causes simultaneously and the multiple gold pattern blocks formed exists the not high problem of undercutting amount uniformity.
2) in alternative, the time of each wet etching, research showed less than 1 minute, and the undercutting amount uniformity of multiple gold pattern blocks that above-mentioned time-triggered protocol is formed is higher.
3) in alternative, the time range of each deionized water rinsing is: 2 minutes～5 minutes, research showed, etch by-products can be removed by the deionized water rinsing of above-mentioned time range completely, and total process time is short, and treatment effeciency is high.
Accompanying drawing explanation
Semiconductor device in Fig. 1 to Fig. 4 one embodiment of the invention is at the structural representation of each production phase.
Detailed description of the invention
As described in the background art, there are some problems in the existing etching process to layer gold, one, easily go out cash residual；Two, it is not high that uniformity is measured in undercutting (Undercut), and the amount of laterally removing of the multiple gold pattern blocks namely formed with a collection of etching not etc., does not have many, and what have lacks.For the problems referred to above, present inventor has performed analysis, it has been found that the reason come into question is: if layer gold is corroded for a long time, for instance adopt and comprise KI and I2Aqueous solution corrode, above-mentioned corrosion is isotropic etch, then can find: elapse over time, the increasing etch by-products of layer gold surface aggregation, owing to layer gold is etched by-product cladding, thus affects the further corrosion rate of layer gold, how much different the etch by-products amount of zones of different cladding is, the layer gold possibility of subregion cannot contact with etchant solution, thus on the one hand, in the vertical, it is likely to result in gold residual, on the other hand, in the horizontal, the undercutting amount of different gold pattern blocks is different.Based on above-mentioned analysis, the present invention proposes: change repeatedly once long-time corrosion into wet etching and layer gold is patterned, the time of each wet etching was less than 2 minutes, deionized water rinsing is adopted after each wet etching is complete, so, the by-product that corrosion produces every time can be able to timely stripping, does not affect the further corrosion rate of layer gold, thus can solve the problem that gold residual is uneven with undercutting amount simultaneously.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.For knowing explanation principles of the invention, chart not in scale below.
Fig. 1 to Fig. 4 is the semiconductor device structural representation in each production phase of one embodiment of the invention offer.Below in conjunction with Fig. 1 to Fig. 4, manufacture method is described in detail.
As shown in Figure 1, it is provided that Semiconductor substrate 1, described Semiconductor substrate 1 has layer gold 11, described layer gold 11 has patterned mask layer 12.
The substrate 10 of above-mentioned Semiconductor substrate 1 is such as silicon substrate, germanium substrate, silicon-on-insulator etc., it is such as MEMS that the present embodiment makes the semiconductor device formed, in one embodiment, above-mentioned MEMS includes the substrate and the cap rock that are bonded together to be formed cavity, the substrate 10 of above-mentioned Semiconductor substrate 1 can be the substrate of MEMS, namely above-mentioned substrate 10 is formed various active, passive device, layer gold 11 is formed active, on passive device or formed with active, on the metal interconnection structure of passive device electrical connection, the substrate 10 of above-mentioned Semiconductor substrate 1 can also be the cap rock of MEMS, namely above-mentioned substrate 10 is formed without other device, layer gold 11 is formed directly on silicon or SOI.
The thickness of layer gold 11 is such as 300 nanometers.In other embodiments, layer gold 11 can also select other thickness as required.
In the present embodiment, patterned mask layer 12 is the photoresist of patterning, adopts exposure, developing technique to be formed.In other embodiments, this patterned mask layer 12 can also be other material, for instance silicon nitride etc..
Then, as shown in Figure 2 and Figure 3, described layer gold 11 is patterned with described patterned mask layer 12 for mask, described layer gold 11 be patterned into wet etching, the solution of employing is for comprising KI and I2Aqueous solution, described wet etching carries out several times, the time of each wet etching less than 2 minutes, each wet etching complete after adopts deionized water rinsing.
First, with reference to shown in Fig. 2, first Semiconductor substrate 1 (with reference to Fig. 1 Suo Shi) is placed in and comprises KI and I2Aqueous solution 2 in.I2Having strong oxidizing property, gold can carry out oxidation and generate etch by-products 111, above-mentioned by-product 111 can be dissolved in KI solution, for weakening the cladding of by-product 111, it is achieved preferably by-product 111 produces/remove ratio, it is preferable that, in the aqueous solution 2 that layer gold 11 is corroded, I2Mass percent less than 2%, the mass percent of KI is less than 5%, and the mass percent of deionized water is more than 93%.It is highly preferred that I2Mass percent be 1.3%, the mass percent of KI is 4%, and the mass percent of deionized water is 94.7%.
Although considering the removal of by-product 111 in the selection of corrosive liquid aqueous solution 2, but, for realizing layer gold 11 corrosion rate faster, the mass percent of KI selects to cause the residual still suffering from by-product 111 in above-mentioned corrosion process.
Considering the residual quantity of above-mentioned by-product 111, the process time of this step was less than 2 minutes, it is preferable that less than 1 minute.
For the remaining bi-products 111 still suffered from above-mentioned corrosion process is removed, to avoid its cladding layer gold 11 to affect the further corrosion of layer gold, as it is shown on figure 3, also adopt deionized water 3 to rinse above-mentioned Semiconductor substrate 1.
The time that above-mentioned deionized water 3 rinses was more than 2 minutes, preferably, the time range that deionized water 3 rinses is: 2 minutes～5 minutes, and the deionized water 3 of above-mentioned time range rinses and can etch by-products 111 be removed completely, and total process time is short, treatment effeciency is high.
The step of above-mentioned Fig. 2 to Fig. 3 can circulate and carry out repeatedly, to realize layer gold 11 removal amount demand (namely on thickness direction) in the vertical, in the present embodiment, it is contemplated that batch processing, it is preferable that more than 4 times.In other embodiments, it is also possible to adopt other number of times according to actual needs.
Finally, the golden pattern block 11 ' formed after described layer gold 11 is graphical, adopt inactive gas to dry up, for instance nitrogen, it is preferable that low-pressure air current.
Can be seen that, in the present embodiment, owing to each wet etching time is shorter, etch by-products 111 having carried out timely removal afterwards, above-mentioned corrosive liquid aqueous solution 2 burn into deionized water 3 rinses after repeatedly carrying out thus removing mask layer 12, as shown in Figure 4, the golden pattern block 11 ' formed: in the vertical, without gold residual, in the horizontal, the undercutting amount of gold pattern block 11 ' is less than 3 microns, and the undercutting amount of different gold pattern block 11 ' is roughly equal.
In the present embodiment, the material of mask layer 12 is photoresist, for instance adopt ashing method to remove.In other embodiments, for instance for the mask layer 12 that material is silicon nitride, for instance adopt hot phosphoric acid to remove.
In the present embodiment, MEMS includes the substrate and the cap rock that are bonded together to be formed cavity, and the golden pattern block 11 ' after graphical is for forming the projection of two wafer eutectic bondings, for instance be positioned at cavity both sides.In other embodiments, the cavity of above-mentioned MEMS directly can also be formed on semiconductor substrate 1 by the sacrifice layer in the substrate 10 of corrosion resistant semiconductor substrate 1 or substrate 10, in such cases, being also formed with movable sensitive thin film and fixed electrode in Semiconductor substrate 1, the golden pattern block 11 ' after graphical may be used for forming the contact electrode drawing movable sensitive thin film and the fixed electrode signal of telecommunication.Certainly, the MEMS formed is bonded with substrate for the cap rock that adopts in this enforcement, when having movable sensitive thin film and fixed electrode in the substrate of this MEMS, the golden pattern block 11 ' after graphical can be used for forming the contact electrode drawing movable sensitive thin film and the fixed electrode signal of telecommunication.For in other embodiments, the above-mentioned patterned method of layer gold be can be used for forms the parts that other material is gold.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (12)
1. the manufacture method of a semiconductor device, it is characterised in that including:
Semiconductor substrate is provided, described Semiconductor substrate has layer gold, described layer gold has patterned mask layer；
Described layer gold is patterned with described patterned mask layer for mask, described layer gold be patterned into wet etching, the solution of employing is for comprising KI and I2Aqueous solution, described wet etching carries out several times, the time of each wet etching less than 2 minutes, each wet etching complete after adopts deionized water rinsing.
2. manufacture method according to claim 1, it is characterised in that the time of wet etching was less than 1 minute every time.
3. manufacture method according to claim 1, it is characterised in that the number of times of described wet etching is more than 4 times.
4. manufacture method according to claim 1, it is characterised in that the time of deionized water rinsing was more than 2 minutes every time.
5. manufacture method according to claim 4, it is characterised in that the time range of deionized water rinsing is every time: 2 minutes～5 minutes.
6. manufacture method according to claim 1, it is characterised in that in the aqueous solution that wet etching adopts, I2Mass percent less than 2%, the mass percent of KI is less than 5%, and the mass percent of deionized water is more than 93%.
7. manufacture method according to claim 6, it is characterised in that in the aqueous solution that wet etching adopts, I2Mass percent be 1.3%, the mass percent of KI is 4%, and the mass percent of deionized water is 94.7%.
8. manufacture method according to claim 7, it is characterised in that the thickness of described layer gold is 300 nanometers, the undercutting amount of the graphical each gold pattern block formed is less than 3 microns.
9. manufacture method according to claim 1, it is characterised in that described Semiconductor substrate material is silicon, described mask layer material is photoresist.
10. manufacture method according to claim 1, it is characterised in that after described layer gold is graphical, adopts low-pressure air current to dry up.
11. manufacture method according to claim 1, it is characterised in that described semiconductor device is MEMS, described patterned layer gold is used for wafer bonding.
12. manufacture method according to claim 1, it is characterized in that, described semiconductor device is MEMS, and described MEMS has movable sensitive thin film and fixed electrode, and described patterned layer gold draws the contact electrode of movable sensitive thin film and the fixed electrode signal of telecommunication for being formed.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113725723A (en) * | 2021-07-21 | 2021-11-30 | 华芯半导体研究院(北京)有限公司 | Metal etching method for VCSEL chip electroplating seed layer based on SiN passivation layer protection |
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| CN102569054A (en) * | 2012-02-27 | 2012-07-11 | 中国科学院微电子研究所 | Preparation method of T-shaped grid |
| CN102867880A (en) * | 2011-07-06 | 2013-01-09 | 长沙理工大学 | Method for preparing double acid etching textures on polycrystalline silicon surface |
| CN103326695A (en) * | 2013-06-20 | 2013-09-25 | 南通大学 | Reconfigurable matching network matcher with MEMS switch |
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| JPH09106959A (en) * | 1995-10-13 | 1997-04-22 | Shin Etsu Handotai Co Ltd | Ohmic electrode of compound semiconductor and formation thereof |
| CN101082523A (en) * | 2007-06-27 | 2007-12-05 | 中国科学院上海微系统与信息技术研究所 | Method for making flexibility temperature sensor |
| CN102867880A (en) * | 2011-07-06 | 2013-01-09 | 长沙理工大学 | Method for preparing double acid etching textures on polycrystalline silicon surface |
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| CN113725723A (en) * | 2021-07-21 | 2021-11-30 | 华芯半导体研究院(北京)有限公司 | Metal etching method for VCSEL chip electroplating seed layer based on SiN passivation layer protection |
| CN113725723B (en) * | 2021-07-21 | 2023-03-03 | 华芯半导体研究院(北京)有限公司 | Metal etching method for VCSEL chip electroplating seed layer based on SiN passivation layer protection |
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