CN113725723B - Metal etching method for VCSEL chip electroplating seed layer based on SiN passivation layer protection - Google Patents

Metal etching method for VCSEL chip electroplating seed layer based on SiN passivation layer protection Download PDF

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CN113725723B
CN113725723B CN202110826233.7A CN202110826233A CN113725723B CN 113725723 B CN113725723 B CN 113725723B CN 202110826233 A CN202110826233 A CN 202110826233A CN 113725723 B CN113725723 B CN 113725723B
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layer
etching
electroplating seed
seed layer
vcsel chip
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CN113725723A (en
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王健军
江蔼庭
王青
赵风春
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China Semiconductor Technology Co ltd
Huaxin Semiconductor Research Institute Beijing Co ltd
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China Semiconductor Technology Co ltd
Huaxin Semiconductor Research Institute Beijing Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04252—Electrodes, e.g. characterised by the structure characterised by the material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers

Abstract

The invention discloses a metal etching method for a VCSEL chip electroplating seed layer based on SiN passivation layer protection. The VCSEL chip includes: the electroplating seed layer comprises a TiW layer and an Au layer, and a SiN passivation layer is arranged between the epitaxial structure and the electroplating seed layer; the method comprises the following steps: (1) carrying out first wet etching on the Au layer; wherein, the first wet etching is carried out by using KI solution; (2) Performing ICP dry etching and second wet etching on the TiW layer to finish the etching of the metal of the electroplating seed layer; wherein, the second wet etching is carried out by using hydrogen peroxide or fluorine-containing reagent. The method can avoid the problem of multiple superimposed side etching amount caused by wet etching of the TiW layer, can completely remove the TiW possibly remaining on the side wall in ICP dry etching, and cannot influence the appearance of a scribing channel.

Description

Metal etching method for VCSEL chip electroplating seed layer based on SiN passivation layer protection
Technical Field
The invention relates to the field of optoelectronic devices, in particular to a metal etching method for a VCSEL chip electroplating seed layer based on SiN passivation layer protection.
Background
In the production process of the prior VCSEL chip (vertical cavity surface emitting laser), tiW metal and Au metal of a seed layer are sputtered and electroplated on the whole surface, and the TiW metal and the Au metal of the seed layer in an electroless plating area need to be removed cleanly after an electroplating process. However, the existing VCSEL chip plating seed layer metal etching method still needs to be improved.
Disclosure of Invention
The present application is based on the discovery by the inventors of the following facts and problems:
in principle, the Au metal can be subjected to wet etching operation by adopting a KI solution; the TiW metal can be etched by a wet method by using hydrogen peroxide or a fluorine-containing reagent, and can also be removed by adopting a fluorine-based ICP dry etching operation; however, the following problems arise in the above-described work flow:
1. the scheme of wet etching Au metal and hydrogen peroxide or fluorine-containing reagent to TiW metal by adopting a KI solution comprises the following steps:
due to the characteristic of isotropy of wet etching, a small amount of side etching can occur when the KI solution corrodes the Au metal layer; then, hydrogen peroxide or fluorine-containing reagent is used for corroding the TiW metal, so that the transverse side corrosion of the TiW metal layer can be caused, and the side corrosion amount of the two-time superposition is larger; moreover, as TiW is arranged between the epitaxial layer and the Au plating metal layer, excessive lateral erosion can cause that the area can not be effectively covered when a dielectric film (a passivation film) is deposited by PECVD, and a cavity is caused; this can affect aging and reliability results.
2. The scheme of etching Au metal by a KI solution wet method and etching TiW metal by an ICP dry method is as follows:
as described above, a small amount of lateral etching inevitably occurs when the KI solution corrodes the Au metal layer; then, etching the TiW metal by using an ICP dry method, so that the transverse side etching of the TiW metal layer can be effectively avoided; however, the TiW layer has lower density and the thickness of the TiW layer is lower (lower than that of the TiW layer) under the existing condition
Figure BDA0003173893900000011
). Therefore, when the KI wet etching method is used for etching Au metal, KI solution can penetrate into the TiW metal layer and corrode an epitaxial layer exposed in a scribing channel area, so that microscopic step difference is caused; the step difference is amplified in the subsequent process of etching TiW metal by an ICP dry method to form a plurality of black dot anomalies of water drop dots; meanwhile, because the ICP dry etching has directionality, the TiW metal on the sidewall of a portion of the region cannot be etched clean effectively.
In view of the above, the invention provides a metal etching method for a VCSEL chip electroplating seed layer based on SiN passivation layer protection. The method can avoid the problem of multiple superimposed side etching amount caused by wet etching of the TiW layer, can completely remove the TiW possibly remaining on the side wall in ICP dry etching, and cannot influence the appearance of a scribing channel.
In one aspect of the invention, the invention provides a metal etching method for a VCSEL chip electroplating seed layer based on SiN passivation layer protection. According to an embodiment of the invention, the VCSEL chip comprises: the electroplating seed layer comprises a TiW layer and an Au layer, and a SiN passivation layer is arranged between the epitaxial structure and the electroplating seed layer; the method comprises the following steps: (1) carrying out first wet etching on the Au layer; wherein, the first wet etching is carried out by using KI solution; (2) Performing ICP dry etching and second wet etching on the TiW layer to finish the etching of the electroplating seed layer; wherein, the second wet etching is carried out by using hydrogen peroxide or fluorine-containing reagent.
According to the VCSEL chip electroplating seed layer metal etching method based on the protection of the SiN passivation layer, the KI solution is combined to perform wet etching on the Au layer, the ICP dry etching on the TiW layer and the hydrogen peroxide or fluorine-containing reagent is combined to perform wet etching on the TiW layer, so that the problem of multiple overlapping side etching amount caused by wet etching on the TiW layer can be avoided, and TiW possibly remaining on the side wall in ICP dry etching can be completely removed. In addition, the SiN passivation layer is still reserved on the upper surface of the epitaxial structure after etching, so that wet or dry etching operation cannot affect the epitaxial structure, and abnormal scribing channel appearance cannot be caused.
In addition, the method for etching the metal of the VCSEL chip electroplating seed layer based on the protection of the SiN passivation layer according to the embodiment of the invention may further have the following additional technical features:
in some embodiments of the invention, the KI solution is at a concentration of 10% to 30%.
In some embodiments of the present invention, the first wet etching is performed for 1min to 3min.
In some embodiments of the present invention, the operating conditions of the dry ICP etching include: using 30 sccm-70 sccm fluorine-based gas and 30 sccm-70 sccm inert gas to ionize under 100W-500W upper electrode ICP power to provide plasma required by the reaction; under the power of a lower electrode bias of 20W-60W, an accelerating electric field is manufactured for physical bombardment; the treatment pressure is 0.5Pa to 1.0Pa, and the treatment temperature is 10 ℃ to 30 ℃.
In some embodiments of the present invention, the concentration of the hydrogen peroxide is 10% to 20%.
In some embodiments of the invention, the fluorine-containing reagent is selected from at least one of hydrofluoric acid, BOE solution.
In some embodiments of the invention, the concentration of the fluorine-containing agent is 5% to 20%.
In some embodiments of the invention, the second wet etching is performed for 15s to 1min.
In some embodiments of the present invention, the epitaxial structure includes an N contact layer, an N-DBR layer, an MQW layer, an oxide layer, a P-DBR layer, and a P contact layer in this order from bottom to top.
In some embodiments of the present invention, the VCSEL chip further includes a substrate formed on a lower surface of the epitaxial structure.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
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The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic cross-sectional structure of a VCSEL chip etched by the method of the present invention;
fig. 2 is a schematic cross-sectional structure diagram of a VCSEL chip etched by a conventional method.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The examples do not specify particular techniques or conditions, and are performed according to techniques or conditions described in literature in the art or according to the product specification. The reagents or instruments used are conventional products which are commercially available, and are not indicated by manufacturers. The concentration of the solution referred to in the present application is a mass concentration unless otherwise specified.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
In the present invention, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the second feature or the first and second features may be indirectly contacting each other through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In one aspect of the invention, the invention provides a metal etching method for a VCSEL chip electroplating seed layer based on SiN passivation layer protection.
Fig. 1 and fig. 2 are schematic cross-sectional structural diagrams of VCSEL chips etched by the method of the present invention and conventional method, respectively.
Referring to fig. 1, according to an embodiment of the present invention, the VCSEL chip includes: the epitaxial structure comprises an epitaxial structure 1 and a plating seed layer formed on the epitaxial structure 1, wherein the plating seed layer comprises a TiW layer 3 and an Au layer 4, and a SiN passivation layer 2 is arranged between the epitaxial structure 1 and the plating seed layer. The method comprises the following steps: (1) carrying out first wet etching on the Au layer 4; wherein, the first wet etching is carried out by using KI solution; (2) Performing ICP dry etching and second wet etching on the TiW layer 3 to finish the etching of the electroplating seed layer; wherein, the second wet etching is carried out by using hydrogen peroxide or fluorine-containing reagent.
As can be seen from comparing fig. 1 and fig. 2, the SiN passivation layer in the scribe line region of the VCSEL chip in the conventional process flow has a "windowing" structure, that is, the SiN passivation layer does not cover the epitaxial structure in the scribe line region, and the upper surface of the epitaxial structure in the scribe line region is exposed. Under the condition, when the KI solution is used for etching Au metal by a wet method, the TiW layer can penetrate, the upper surface of the epitaxial structure of the scribing channel area is corroded, and the appearance of the scribing channel is influenced or other undetected potential problems are brought. In the technical scheme of the invention, the windowing is cancelled, so that the SiN passivation layer covers the upper surface of the epitaxial structure in the scribing channel area, and the influence of the etching action on the epitaxial structure is avoided. On the other hand, because the ICP dry etching has directionality, the method is independently used for etching the TiW layer, tiW residues are easily generated on the etched chip step side wall 5, and the microscopic morphology, the aging and the reliability results of the chip are further influenced.
The metal etching method of the VCSEL chip plating seed layer based on the SiN passivation layer protection according to the embodiment of the invention is further described in detail below.
According to some embodiments of the present invention, the KI solution may have a concentration of 10% to 30%. If the concentration of the KI solution is too low, the corrosion time possibly required is too long, and the corrosion rate is difficult to control; if the concentration of the KI solution is too high, the corrosion rate is too high, the corrosion uniformity is poor, and the lateral corrosion is aggravated.
According to some embodiments of the present invention, the first wet etching may be performed for 1min to 3min. If the first wet etching is performed for too long, lateral etching may be excessive, the product size may shrink, and the bottom undercut amount may be large. In addition, the specific first wet etching time can be calculated according to the thickness of the Au layer and the concentration of the chemical agent, and 15% -30% of over-etching amount is given.
According to some embodiments of the invention, the operating conditions of the dry ICP etching include: a fluorine-based gas of 30sccm to 70sccm is used (for example, CHF can be used) 3 、CF 4 、SF 6 At least one of them), 30 to 70sccm of an inert gas (for example, N can be used 2 Or Ar) is ionized under the ICP power of the upper electrode of 100W-500W to provide plasma needed by the reaction; under the power of a lower electrode bias of 20W-60W, an accelerating electric field is manufactured for physical bombardment; the treatment pressure is 0.5Pa to 1.0Pa, and the treatment temperature is 10 ℃ to 30 ℃. By adopting the above conditions, the balance of the gas environment in the ICP reaction cavity can be stabilized, and the etching effect is improved. In addition, the etching time can be calculated according to the thickness of a specific layer to be etched and the parameters of an etching formula, and 15% -30% of over-etching amount is given.
According to some embodiments of the present invention, the concentration of the hydrogen peroxide may be 10% to 20%. If the concentration of the hydrogen peroxide is too low, the corrosion time possibly required is too long, and the corrosion rate is difficult to control; if the concentration of the hydrogen peroxide is too high, the corrosion rate is too high, the corrosion uniformity is poor, and the side corrosion is aggravated.
According to some embodiments of the present invention, the fluorine-containing reagent may be selected from hydrofluoric acid, BOE solution (HF and NH) 4 Mixed aqueous solution of F). Specifically, NH in BOE solution 4 The ratio of F and HF may be 12.
According to some embodiments of the invention, the concentration of the fluorine-containing agent may be 5% to 20%. If the concentration of the fluorine-containing reagent is too low, the possible required etching time is too long, and the etching rate is difficult to control; if the concentration of the fluorine-containing reagent is too high, the etching rate may be too fast, the etching uniformity may be poor, and the side etching may be aggravated.
According to some embodiments of the present invention, the second wet etching may be performed for 15s to 1min. If the second wet etching is performed for too long, the TiW layer may be subjected to a large side etching, which affects the performance of the chip. In addition, the specific second wet etching time can be calculated according to the thickness of the TiW layer on the side wall and the concentration of the medicament, and a certain amount of corrosion is given.
In addition, it should be noted that the etching method provided by the present invention does not limit the specific structure of the epitaxial structure of the VCSEL chip. That is to say, the etching method provided by the invention is suitable for etching the electroplating seed layer in the VCSEL chip with different epitaxial structures. According to some embodiments of the present invention, the epitaxial structure 1 includes an N-contact layer, an N-DBR layer, an MQW layer, an oxide layer, a P-DBR layer, a P-contact layer, and a passivation layer (the specific layer structures are not shown in the drawings) sequentially grown on a substrate. In addition, according to some embodiments of the present invention, the VCSEL chip may further include a substrate (not shown in the drawings), which is formed on a lower surface of the epitaxial structure. The etching method provided by the invention is adopted to etch the metal of the electroplating seed layer in the VCSEL chip with the substrate, and the adverse effect on the substrate in the chip can be avoided.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (10)

1. A metal etching method of VCSEL chip electroplating seed layer based on SiN passivation layer protection is characterized in that,
the VCSEL chip includes:
the device comprises an epitaxial structure and an electroplating seed layer formed on the epitaxial structure, wherein the electroplating seed layer comprises a TiW layer and an Au layer, a SiN passivation layer is arranged between the epitaxial structure and the electroplating seed layer, and the SiN passivation layer covers the upper surface of the epitaxial structure in a scribing way region;
the method comprises the following steps:
(1) Carrying out first wet etching on the Au layer; wherein, the first wet etching is carried out by using KI solution;
(2) Performing ICP dry etching and second wet etching on the TiW layer to finish the etching of the metal of the electroplating seed layer; wherein, the second wet etching is carried out by using hydrogen peroxide or fluorine-containing reagent.
2. The VCSEL chip electroplating seed layer metal etching method based on SiN passivation layer protection of claim 1, wherein the concentration of the KI solution is 10% -30%.
3. The method for etching the metal of the electroplating seed layer of the VCSEL chip based on the protection of the SiN passivation layer according to claim 1, wherein the first wet etching is performed for 1-3 min.
4. The VCSEL chip electroplating seed layer metal etching method based on SiN passivation layer protection of claim 1, wherein the operating conditions of the dry ICP etching include: using 30 sccm-70 sccm fluorine-based gas and 30 sccm-70 sccm inert gas to ionize under 100W-500W upper electrode ICP power to provide plasma required by the reaction; under the power of a lower electrode bias of 20W-60W, an accelerating electric field is manufactured for physical bombardment; the treatment pressure is 0.5Pa to 1.0Pa, and the treatment temperature is 10 ℃ to 30 ℃.
5. The metal etching method for the VCSEL chip electroplating seed layer based on SiN passivation layer protection of claim 1, wherein the concentration of hydrogen peroxide is 10% -20%.
6. The method of claim 1, wherein the fluorine-containing reagent is at least one selected from hydrofluoric acid and BOE solution.
7. The method of claim 6, wherein the fluorine-containing reagent is present at a concentration of 5% to 20%.
8. The method for etching the metal of the electroplating seed layer of the VCSEL chip based on the protection of the SiN passivation layer according to claim 1, wherein the second wet etching is performed for 15 s-1 min.
9. The metal etching method for the VCSEL chip electroplating seed layer based on the protection of the SiN passivation layer of claim 1, wherein the epitaxial structure comprises an N contact layer, an N-DBR layer, an MQW layer, an oxide layer, a P-DBR layer and a P contact layer from bottom to top in sequence.
10. The SiN passivation layer protection-based VCSEL chip electroplating seed layer metal etching method of claim 1, wherein the VCSEL chip further comprises a substrate formed on a lower surface of the epitaxial structure.
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