US20150221627A1 - Multi-layer devices utilizing layer transfer - Google Patents
Multi-layer devices utilizing layer transfer Download PDFInfo
- Publication number
- US20150221627A1 US20150221627A1 US14/576,068 US201314576068A US2015221627A1 US 20150221627 A1 US20150221627 A1 US 20150221627A1 US 201314576068 A US201314576068 A US 201314576068A US 2015221627 A1 US2015221627 A1 US 2015221627A1
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- devices
- receiving
- semiconductor material
- dielectric layer
- substrate
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- H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Definitions
- the present invention relates in general to semiconductor devices having multiple functionalities, in particular integrally formed semiconductor devices having microelectronic and optoelectronic applications.
- Silicon wafers are used in the fabrication of integrated circuits (ICs) and other microelectronic systems (MEMS) devices.
- the wafer serves as the substrate for fabrication of microelectronic devices built in and over the wafer.
- the wafer therefore undergoes many microfabrication process steps. Once the desired functionality is achieved, the individual devices are separated and packaged.
- Silicon wafers have limited functionality.
- silicon wafers can be fabricated for the purposes of digital or analog processing but are unable to efficiently serve as light emitters and detectors.
- light emitters and light detectors are typically fabricated from wafers made of compound semiconductor materials, such as group III-V semiconductor materials.
- compound semiconductor devices have stronger optical absorption, electrically driven optical emission, high and low band-gaps and higher carrier mobilities than silicon devices.
- Silicon devices however, have the advantage of high performance IC processing, materials and micromachining technology.
- MEMS microelectronic systems
- optoelectronic applications it is desirable to use compound semiconductor devices and silicon devices in combination. Combining the devices into one structure, however, has been challenging from a technical standpoint making it commercially unfeasible.
- a method for fabricating devices that are made of multiple layers of different semiconductor devices having different functionalities may include forming a release layer over a donor substrate.
- a plurality of devices made of a first semiconductor material can be formed over the release layer.
- the first semiconductor material can be a compound semiconductor material such as a III-V semiconductor material that can be used to form a device having optoelectronic functionalities.
- a first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer.
- the plurality of devices can be attached to a receiving device made of a second semiconductor material different than or same as the first semiconductor material.
- the resulting device can be attached to a receiving substrate.
- the receiving substrate is a silicon semiconductor structure having devices that can be processed to have microelectronic and/or optoelectronic functionality.
- the release layer can be etched to release the donor substrate from the plurality of devices.
- a second dielectric layer can be applied over the plurality of devices and the receiving substrate to mechanically attach the plurality of cells to the receiving substrate.
- a second plurality of cells made of a compound semiconductor material may further be attached to the cells already bonded to the receiving substrate to provide further functionality to the resulting device.
- the resulting device may include a first plurality of devices made of a compound semiconductor material.
- the compound semiconductor material may be a III-V semiconductor material.
- a second plurality of devices made of a semiconductor material different than the first plurality of devices can be bonded to the first plurality of devices.
- the semiconductor material of the second plurality of devices may be silicon.
- a dielectric layer may surround the first plurality of devices and the second plurality of devices to mechanically bond the first plurality of devices to the second plurality of devices.
- the resulting device is therefore an integrated device having the combined characteristics of a compound semiconductor and a silicon semiconductor.
- FIG. 1 schematically illustrates a cross-sectional view of one embodiment of a donor substrate having a release layer formed thereon.
- FIG. 2 schematically illustrates a cross-sectional view of one embodiment of a compound semiconductor device layer formed on a release layer.
- FIG. 3 schematically illustrates a cross-sectional view of one embodiment of compound semiconductor device formed from a compound semiconductor device layer.
- FIG. 4 schematically illustrates a cross-sectional view of one embodiment of compound semiconductor devices covered with a dielectric layer.
- FIG. 5 schematically illustrates a cross-sectional view of one embodiment of an etched dielectric layer.
- FIG. 6 schematically illustrates a cross-sectional view of one embodiment of compound semiconductor devices attached to a receiving device.
- FIG. 7 schematically illustrates a cross-sectional view of one embodiment in which a donor substrate is released from the compound semiconductor devices.
- FIG. 8 schematically illustrates a cross-sectional view of one embodiment of compound semiconductor devices attached to a receiving substrate.
- FIG. 9 schematically illustrates a cross-sectional view of one embodiment of a dielectric layer mechanically attaching the compound semiconductor devices to the receiving substrate.
- FIG. 10 schematically illustrates a cross-sectional view of one embodiment of a second set of devices attached to the compound semiconductor devices.
- FIG. 11 schematically illustrates a cross-sectional view of one embodiment of metal contacts applied to compound semiconductor devices.
- FIG. 12 schematically illustrates a cross-sectional view of one embodiment in which trenches are formed between devices of a receiving substrate.
- FIG. 13 schematically illustrates a cross-sectional view of one embodiment of a handle substrate attached to compound semiconductor devices.
- FIG. 14 schematically illustrates a cross-sectional view of one embodiment in which a completed device is released from a receiving substrate.
- FIG. 15 schematically illustrates a cross-sectional view of one embodiment in which receiving structure and compound semiconductor devices are attached to opposite sides of a receiving substrate.
- FIG. 16 is a flow diagram of one embodiment of a method of processing devices on a receiving substrate.
- FIG. 1 schematically illustrates a cross-sectional view of one embodiment of a donor substrate.
- Donor substrate 102 may be any type of donor substrate capable of forming a semiconductor device thereon.
- donor substrate 102 is a wafer made of a compound semiconductor material capable of creating a semiconductor device made of a similar material.
- donor substrate 102 is made of a group III-V semiconductor material such that a semiconductor device made of a III-V semiconductor material can be epitaxially grown thereon.
- the III-V semiconductor material is a compound material such as gallium arsenide (GaAs) or indium gallium phosphide (InGaP).
- the donor substrate 102 may be made of a non-compound semiconductor material capable of forming a semiconductor device thereon.
- donor substrate 102 is a non-compound material other than silicon, for example, a group IV material such as silicon (Si) or germanium (Ge).
- a sacrificial release layer 104 may be deposited on top of donor substrate 102 .
- Release layer 104 may be made of any material capable of being removed by an etchant that will not substantially remove a protective layer formed on the semiconductor device.
- release layer 104 may be made of aluminum indium phosphide (AlInP) and, during a later step, etched using hydrogen chloride (HCl).
- release layer 104 may be made of silicon (Si) and removed with xenon difluoride (XeF2).
- release layer 104 can be made of any material that is different from the protective material, for example, amorphous-Si, porous silicon or spin-on glass.
- Release layer 104 may be grown over donor substrate 102 using a molecular beam epitaxy (MBE) or metallo-organic chemical vapor deposition (MOCVD) growth process. Alternatively, release layer 104 may be formed by other material deposition processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) (e.g. sputtering).
- MBE molecular beam epitaxy
- MOCVD metalo-organic chemical vapor deposition
- release layer 104 may be formed by other material deposition processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) (e.g. sputtering).
- CVD chemical vapor deposition
- PVD physical vapor deposition
- FIG. 2 schematically illustrates a cross-sectional view of one embodiment of a device layer formed on donor substrate 102 .
- Device layer 202 may be formed on donor substrate 102 after the formation of release layer 104 such that release layer 104 is between compound device layer 202 and donor substrate 102 .
- Device layer 202 may be made of a compound semiconductor material, which in some embodiments, is the same material as donor substrate 102 .
- donor substrate 102 may be made of a III-V semiconductor material and device layer 202 may also be a III-V semiconductor material.
- device layer 202 is grown over donor substrate 102 using a molecular beam epitaxy (MBE) or metallo-organic chemical vapor deposition (MOCVD) growth process.
- MBE molecular beam epitaxy
- MOCVD metalo-organic chemical vapor deposition
- device layer 202 may be made of a single semiconductor material, for example a group IV semiconductor material such as Ge.
- Device layer 202 may be made of multiple layers or may be a single layer of semiconductor material.
- An overall thickness of compound semiconductor device layer 202 may be from about 0.5 ⁇ m to about 5 ⁇ m.
- compound semiconductor devices 302 may be formed from device layer 202 as illustrated in FIG. 3 .
- Compound semiconductor devices 302 may be, for example, cells having the same or different functionalities. Although devices 302 are referred to as “compound” devices, it is contemplated that compound semiconductor devices 302 are not necessarily made of compound materials. Rather, compound devices 302 may be made of a compound semiconductor material or a single semiconductor material, depending upon the material of device layer 202 , as previously discussed. Compound semiconductor devices 302 may be formed by etching trenches 304 down to release layer 104 . For example, although not shown, a mask layer (e.g.
- an oxide layer may be formed over device layer 202 and patterned to include openings over portions of device layer 202 where trenches 304 are to be formed.
- a chemical etch e.g., wet etch or plasma etch
- Trenches 304 may extend through an entire thickness of device layer 202 and stop at release layer 202 .
- trenches 304 may be etched through release layer 202 .
- dielectric layer 402 is formed over compound semiconductor devices 302 as illustrated in FIG. 4 .
- Dielectric layer 402 may also be formed over portions of release layer 104 which are exposed between compound semiconductor devices 302 .
- Dielectric layer 402 may be formed according to any suitable technique, for example, a plasma enhanced chemical vapor deposition technique.
- Dielectric layer 402 serves several purposes. Representatively, dielectric layer 402 helps to bond compound semiconductor devices 302 to a receiving structure as will be described in more detail below. Also, as can be seen from FIG. 4 , dielectric layer 402 covers all exposed surfaces of compound semiconductor devices 302 . Dielectric layer 402 can therefore also serve as a passivation and sidewall protection layer during etching of release layer 104 as will also be described in more detail below. Dielectric layer 402 may be made of any type of material suitable for serving at least these purposes. Representatively, in one embodiment, dielectric layer 402 may be made of silicon nitride or silicon oxide.
- dielectric layer 402 may be a relatively thin layer such that it does not substantially affect the passage of light between compound semiconductor devices 302 and the associated receiving structure.
- dielectric layer 402 may have a thickness of from about 0.01 ⁇ m to about 1 ⁇ m. The thickness of dielectric layer 402 may be selected depending upon the desired characteristics of compound semiconductor devices 302 . Representatively, a thinner layer may be selected where the optical characteristics of compound semiconductor devices 302 are critical and a thicker layer may be selected where the electrical characteristics of compound semiconductor devices 302 are more important.
- Portions of dielectric layer 402 between each of the compound semiconductor devices 302 are etched to expose release layer 104 as illustrated in FIG. 5 .
- a masking layer is applied over compound semiconductor devices 302 and a chemical etch (e.g., wet etch or plasma etch) is used to remove the unmasked portions of dielectric layer 402 .
- An example, of a masking layer is an oxide layer that is patterned such that portions of dielectric layer 402 to be removed are exposed. Exposing release layer 104 facilitates removal of release layer 104 during a later processing step.
- Receiving structure 602 may be made of a material other than that of compound semiconductor devices 302 .
- compound semiconductor devices are made of a III-V semiconductor material
- receiving structure 602 may be made of silicon.
- Receiving structure 602 may include receiving devices 610 formed therein which are aligned with and bonded to respective compound semiconductor devices 302 .
- Receiving devices 610 may be silicon semiconductor devices capable of a different functionality than compound devices 302 .
- receiving devices 610 may be fabricated to have microelectronic functionalities while compound semiconductor devices 302 can be fabricated to have optoelectronic functionalities. More specifically, in one embodiment, compound semiconductor devices 302 may have the ability to absorb, generate and modulate different wavelengths of light or generate a piezoelectric response to a mechanical input while receiving devices 610 do not have such functionalities.
- a dielectric layer 608 may be formed over each of receiving devices 610 to facilitate the bonding process.
- a surface activation (plasma) process is performed on compound semiconductor devices 302 according to recognized techniques.
- a surface activation process may further be performed on receiving devices 610 .
- compound semiconductor devices 302 are aligned and brought into contact with receiving devices 610 .
- Chemical bonding between compound semiconductor devices 302 and receiving devices 610 occurs through hydrogen bonding and van der Waals forces between the dielectric layer 402 on compound semiconductor devices 302 and a dielectric layer formed over receiving devices 610 .
- bonding occurs at room temperature.
- room temperature may be considered a temperature of from about 15 to about 30 degrees Celsius, for example, from 20 to 25 degrees Celsius, or about 23 degrees Celsius.
- the ability to bond the devices together at room temperature is important because, in embodiments where dielectric layer 402 on compound semiconductor devices 302 and the dielectric layer on receiving devices 610 are made of different materials (e.g. silicon dioxide and silicon nitride), the coefficient of thermal expansion between the dissimilar materials is not the same. Furthermore, the coefficient of thermal expansion of the donor and receiving substrates may have different coefficients of thermal expansion which can cause problems with bonding if the bonding is not done at room temperature. In addition, typical bonding procedures which occur at elevated temperatures can create stress on the device. The ability to bond at room temperature eliminates this stress.
- dielectric layer 402 on compound semiconductor devices 302 and the dielectric layer on receiving devices 610 are made of different materials (e.g. silicon dioxide and silicon nitride)
- the coefficient of thermal expansion between the dissimilar materials is not the same.
- the coefficient of thermal expansion of the donor and receiving substrates may have different coefficients of thermal expansion which can cause problems with bonding if the bonding is not done at room temperature.
- the surfaces of compound semiconductor devices 302 and receiving devices 610 should be cleaned (no particulates) and smooth (less than a few nm rms roughness).
- a high temperature annealing process may be used to transform the bonds between the two surfaces into covalent bonds.
- the bonded compound semiconductor devices 302 and receiving devices 610 can be annealed by heating to a temperature between about 150 degrees Celsius and 600 degrees Celsius to strengthen the bond.
- compound semiconductor devices 302 and receiving devices 610 are clamped together under a mechanical load to facilitate the bonding step.
- no external load is applied depending on the characteristics of the material stack and coefficient of thermal expansion (CTE) mismatches between compound semiconductor devices 302 and receiving devices 610 .
- CTE coefficient of thermal expansion
- receiving structure 602 is attached to receiving substrate 604 along a surface opposite compound semiconductor devices 302 .
- An optional release layer 606 may further be formed between receiving structure 602 and receiving substrate 604 to facilitate removal of receiving substrate 604 .
- receiving substrate 604 is a structured wafer that includes multiple through holes (e.g., holes 612 ) (not drawn to scale) that form a pattern on the top surface of receiving substrate 604 .
- Each of holes 612 extends vertically through the thickness of receiving substrate 604 .
- holes 612 can be formed with uniform spacing among them, with non-uniform spacing among them, or at random locations. Holes 612 can be of the same size or different sizes (e.g., a diameter in the range of 50-500 microns ( ⁇ m)).
- receiving substrate 604 is made of silicon or any silicon-based materials. It is appreciated that receiving substrate 604 can be single crystalline or polycrystalline silicon.
- receiving substrate 604 can be made of other materials such as ceramic materials. In one embodiment, various additional layers cover the entire surface of receiving substrate 604 . It is appreciated that the shape and dimensions of receiving substrate 604 will be dictated, in one embodiment, by the requirements of receiving structure 602 adhered to receiving substrate 604 .
- Receiving substrate 604 can be manufactured with standard semiconductor processing techniques.
- receiving substrate 604 can be formed from a base wafer (e.g., a silicon wafer) with a hard mask deposited thereon.
- a base wafer e.g., a silicon wafer
- a hard mask deposited thereon.
- An example of the hard mask is an oxide layer that is patterned to define the size(s) and locations of holes 612 .
- the hard mask exposes the part of the silicon wafer where holes 612 are to be formed.
- An etchant or a plasma process can then be used to etch through the silicon wafer to form holes 612 .
- the hard mask is removed after holes 612 are formed.
- a dielectric layer 614 (e.g., an oxide layer and/or a nitride layer) is formed on the entire exposed surface (including the inner surfaces of holes 612 —i.e., the surface that defines the passage or lumen) of receiving substrate 604 , as shown in FIG. 6 .
- dielectric layer 614 is a thin layer of silicon dioxide with a thickness in the range of 1000 ⁇ -1 ⁇ m. It is noted that receiving substrate 604 is formed prior to application of receiving structure 602 . Still further, although a structured receiving substrate 604 is described and illustrated it is contemplated that receiving substrate 604 may be any standard, non-structured wafer suitable for processing of a receiving structure 602 and any associated components as described herein. For example, in another embodiment, receiving substrate 604 is solid, without through holes 612 .
- the features on the surfaces of compound devices 302 and receiving devices 610 are critical to allow the hydrogen gas that is evolving during the bonding process to escape and not cause bonding defects.
- certain gases e.g., hydrogen
- the through passages within receiving substrate 604 as described herein provide a route for the gas such that it can escape the interface.
- release layer 104 is removed so that donor substrate 102 can be separated from compound semiconductor devices 302 as illustrated in FIG. 7 .
- a chemical etching process e.g., wet etch or plasma etch
- HCl or XeF 2 can be used as an etchant. Since receiving devices 610 and compound semiconductor devices 302 are coated all around their surfaces with dielectric layers 608 and 402 , respectively, which are made of a material that is not etched by the etchant, they are not affected by the etchant. Only release layer 104 is exposed to the etchant and will be etched away.
- donor substrate 402 may have a structure similar to receiving substrate 604 such that there are holes through which the etchant can pass to reach release layer 104 from its bottom surface. It is also contemplated that neither donor substrate 402 nor receiving substrate 604 is required to have through holes through which the etchant can pass to accomplish the etching
- release layer 104 may be made of aluminum indium phosphide (AlInP) and etched using hydrogen chloride (HCl).
- release layer 104 may be made of silicon (Si) and removed with xenon difluoride (XeF 2 ). Both HCl and XeF 2 are selective etchants in that they will not remove the silicon nitride or oxide dielectric layers 402 , 608 .
- release layer 104 can be made of spin-on glass, amorphous-Si or porous silicon and dielectric layer 402 can be made of oxide. In other embodiments, release layer 104 is made of oxide and dielectric layer 402 can be made of amorphous-Si or Si-nitrite.
- donor substrate 102 can be cleaned for reuse.
- Compound semiconductor devices 302 remain attached to receiving devices 610 as illustrated in FIG. 8 with a bottom surface 802 exposed.
- a further dielectric layer 902 is then applied over each of compound semiconductor devices 302 and receiving structure 602 as illustrated in FIG. 9 .
- Dielectric layer 902 may be substantially the same as dielectric layer 402 and applied in a similar manner.
- Dielectric layer 902 covers exposed surface 802 of compound semiconductor devices 302 such that all surfaces of compound semiconductor devices 302 are covered. Additionally, dielectric layer 902 acts to mechanically attach compound semiconductor devices 302 to receiving devices 610 to further reinforce the bonding between the two structures.
- the initial bonding strength between compound semiconductor devices 302 and receiving devices 610 does not need to be extremely high since a mechanical bonding step, through the encapsulation by dielectric layer 902 , is also performed.
- the dielectric encapsulation is not a necessary part of the invention for bond strength or utility of the bonded structures.
- a second set of compound semiconductor devices 1002 may also be bonded to the first set of compound semiconductor devices 302 and covered with a further dielectric layer 1004 as illustrated in FIG. 10 .
- Compound semiconductor devices 1002 may be formed and bonded to compound semiconductor devices 302 using substantially the same process steps previously discussed with reference to FIGS. 1-9 .
- a representative process flow for forming the cell stack shown in FIG. 10 is illustrated in FIG. 16 .
- process 1600 may include forming the first plurality of devices (e.g., compound semiconductor devices 302 ) on a first donor substrate (e.g., substrate 102 )(block 1602 ). The first plurality of devices can then be attached to a receiving structure (e.g., structure 602 ) as previously discussed (block 1604 ).
- the receiving structure may include receiving devices which are aligned with the first plurality of devices.
- the first donor substrate can then be removed from the first plurality of devices as previously discussed to expose a surface of the first plurality of devices (block 1606 ).
- the second plurality of devices are formed on a second donor substrate (block 1608 ) and then attached to the exposed surface of the first plurality of devices (block 1610 ).
- the second plurality of devices can be attached to the first plurality of devices using the chemical and/or mechanical bonding steps previously discussed in reference to FIGS. 8-9 .
- the second donor substrate is removed (block 1612 ). Further processing may then be performed on the resulting device stack (e.g., compound semiconductor devices 302 , devices 1002 and devices 610 ) to provide the desired functionality (block 1614 ).
- the second set of compound semiconductor devices 1002 may be made of the same material or a different material than compound semiconductor devices 302 .
- compound semiconductor devices 302 and compound semiconductor devices 1002 may be made of the same or different III-V semiconductor materials.
- compound semiconductor devices 302 may be made of gallium arsenide (GaAs) and compound semiconductor devices 1002 may be made of indium gallium phosphide (InGaP).
- GaAs gallium arsenide
- InGaP indium gallium phosphide
- one of compound semiconductor devices 302 or compound semiconductor devices 1002 may be made of a group IV material (e.g. germanium or silicon) while the other is made of a compound group III-V material.
- both may be made of the same or a different group IV material.
- compound semiconductor devices 302 and 1002 can be processed further, mostly with back-end of the line processes (e.g., deposition/patterning of dielectrics and metals) to complete the desired device configuration.
- the temperatures used for the further processing should remain below critical levels (e.g., 250 degrees Celsius) to prevent disruption of the stack of compound semiconductor devices 302 and 1002 .
- metal contacts 1102 are deposited and patterned onto compound semiconductor devices 302 and 1002 .
- Metal contacts 1102 e.g., solder bumps
- Handle substrate 1302 can be a temporary handle (e.g., a tape) or a final assembly substrate.
- portions of receiving structure 602 between receiving devices 610 are removed to form trenches 1202 as illustrated in FIG. 12 . These portions may be removed through any of the previously discussed etching processes (e.g., a chemical etch).
- receiving substrate 604 is removed to release the resulting devices 1402 (i.e., receiving devices 610 , compound semiconductor devices 302 and compound semiconductor devices 1002 ), as shown in FIG. 14 .
- a chemical etching process e.g., wet etch or plasma etch
- xenon difluoride (XeF 2 ) can be used as an etchant. Since each of devices 610 , 302 and 1002 have dielectric layers 402 , 902 and 1004 all around their surfaces, they are not affected by the etchant. Only release layer 606 is exposed to the etchant and will be etched away.
- receiving substrate 604 is solid, without through holes 612 , and the release etchant etches the release layer from the side and/or edge surfaces only.
- devices 1402 After devices 1402 are released from receiving substrate 604 with handle substrate 1302 , devices 1402 can be separated and re-assembled for a specific configuration, without needing dicing or sawing of the parts.
- receiving substrate 604 can be made available for further reuse. Reusing receiving substrate 604 reduces fabrication and materials costs. This is in contrast to a conventional wafer, which is consumed by the process of device fabrication and cannot be reused.
- the resulting devices 1402 are integrally formed devices that are made of different materials having different functionalities.
- devices 1402 can be devices having microelectronic functionalities typically associated with silicon semiconductor devices as well as optoelectronic functionalities typically associated with compound semiconductor devices.
- devices 1402 may have the functionality of detectors, sensors, photovoltaic (PV) cells, integrated circuits (ICs), micro-machine parts, micro-mechanical parts or electronic components in combination with the light emitting and/or detecting functionalities typically associated with compound semiconductor devices.
- FIG. 15 schematically illustrates a cross-sectional view of another embodiment for forming a device in which compound devices are bonded to receiving structure positioned along opposing sides of a receiving substrate.
- each of the process steps and components described in references to FIGS. 1-10 which were performed on a first side 1502 of receiving substrate 604 , may be duplicated and performed on second side 1504 of receiving substrate 604 .
- second side 1504 may have formed thereon release layer 1506 , receiving device 1508 having receiving devices 1510 and a stack of compound devices 1512 and 1514 bonded to receiving devices 1510 .
- Each of receiving devices 1510 and compound devices 1512 and 1514 may be covered with dielectric layer 1516 .
- the resulting device stack 1501 formed on first side 1502 and device stack 1503 formed on second side 1504 may be formed simultaneously or one formed followed by formation of the other.
- the further processing steps described in reference to FIGS. 11-14 may also be performed on device stack 1503 to form devices similar to devices 1402 .
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Abstract
Description
- This application claims benefit of U.S. Nonprovisional Patent Application No. 13/627,425, “PROCESSES FOR MULTI-LAYER DEVICES UTILIZING LAYER TRANSFER”, filed Sep. 26, 2012, and PCT Patent Application No. PCT/US13/61641, filed Sep. 25, 2013, which are incorporated by reference herein in their entireties.
- This invention was made with Government support under Contract No. DE-AC04-94AL85000 awarded by the U.S. Department of Energy. The Government has certain rights in the invention.
- The present invention relates in general to semiconductor devices having multiple functionalities, in particular integrally formed semiconductor devices having microelectronic and optoelectronic applications.
- Silicon wafers are used in the fabrication of integrated circuits (ICs) and other microelectronic systems (MEMS) devices. The wafer serves as the substrate for fabrication of microelectronic devices built in and over the wafer. The wafer therefore undergoes many microfabrication process steps. Once the desired functionality is achieved, the individual devices are separated and packaged.
- Silicon wafers, however, have limited functionality. For example, silicon wafers can be fabricated for the purposes of digital or analog processing but are unable to efficiently serve as light emitters and detectors. Rather light emitters and light detectors are typically fabricated from wafers made of compound semiconductor materials, such as group III-V semiconductor materials. In particular, compound semiconductor devices have stronger optical absorption, electrically driven optical emission, high and low band-gaps and higher carrier mobilities than silicon devices. Silicon devices, however, have the advantage of high performance IC processing, materials and micromachining technology.
- In many microelectronic systems (MEMS) and optoelectronic applications, it is desirable to use compound semiconductor devices and silicon devices in combination. Combining the devices into one structure, however, has been challenging from a technical standpoint making it commercially unfeasible.
- A method for fabricating devices that are made of multiple layers of different semiconductor devices having different functionalities is disclosed. The method may include forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material can be formed over the release layer. In one embodiment, the first semiconductor material can be a compound semiconductor material such as a III-V semiconductor material that can be used to form a device having optoelectronic functionalities. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices can be attached to a receiving device made of a second semiconductor material different than or same as the first semiconductor material. The resulting device can be attached to a receiving substrate. In some embodiments, the receiving substrate is a silicon semiconductor structure having devices that can be processed to have microelectronic and/or optoelectronic functionality. Once the devices are attached together, the release layer can be etched to release the donor substrate from the plurality of devices. A second dielectric layer can be applied over the plurality of devices and the receiving substrate to mechanically attach the plurality of cells to the receiving substrate. A second plurality of cells made of a compound semiconductor material may further be attached to the cells already bonded to the receiving substrate to provide further functionality to the resulting device.
- In one embodiment, the resulting device may include a first plurality of devices made of a compound semiconductor material. The compound semiconductor material may be a III-V semiconductor material. A second plurality of devices made of a semiconductor material different than the first plurality of devices can be bonded to the first plurality of devices. For example, the semiconductor material of the second plurality of devices may be silicon. In addition, a dielectric layer may surround the first plurality of devices and the second plurality of devices to mechanically bond the first plurality of devices to the second plurality of devices. The resulting device is therefore an integrated device having the combined characteristics of a compound semiconductor and a silicon semiconductor.
- The above summary does not include an exhaustive list of all aspects of the present invention. It is contemplated that the invention includes all systems and methods that can be practiced from all suitable combinations of the various aspects summarized above, as well as those disclosed in the Detailed Description below and particularly pointed out in the claims filed with the application. Such combinations have particular advantages not specifically recited in the above summary.
- The embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment of the invention in this disclosure are not necessarily to the same embodiment, and they mean at least one.
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FIG. 1 schematically illustrates a cross-sectional view of one embodiment of a donor substrate having a release layer formed thereon. -
FIG. 2 schematically illustrates a cross-sectional view of one embodiment of a compound semiconductor device layer formed on a release layer. -
FIG. 3 schematically illustrates a cross-sectional view of one embodiment of compound semiconductor device formed from a compound semiconductor device layer. -
FIG. 4 schematically illustrates a cross-sectional view of one embodiment of compound semiconductor devices covered with a dielectric layer. -
FIG. 5 schematically illustrates a cross-sectional view of one embodiment of an etched dielectric layer. -
FIG. 6 schematically illustrates a cross-sectional view of one embodiment of compound semiconductor devices attached to a receiving device. -
FIG. 7 schematically illustrates a cross-sectional view of one embodiment in which a donor substrate is released from the compound semiconductor devices. -
FIG. 8 schematically illustrates a cross-sectional view of one embodiment of compound semiconductor devices attached to a receiving substrate. -
FIG. 9 schematically illustrates a cross-sectional view of one embodiment of a dielectric layer mechanically attaching the compound semiconductor devices to the receiving substrate. -
FIG. 10 schematically illustrates a cross-sectional view of one embodiment of a second set of devices attached to the compound semiconductor devices. -
FIG. 11 schematically illustrates a cross-sectional view of one embodiment of metal contacts applied to compound semiconductor devices. -
FIG. 12 schematically illustrates a cross-sectional view of one embodiment in which trenches are formed between devices of a receiving substrate. -
FIG. 13 schematically illustrates a cross-sectional view of one embodiment of a handle substrate attached to compound semiconductor devices. -
FIG. 14 schematically illustrates a cross-sectional view of one embodiment in which a completed device is released from a receiving substrate. -
FIG. 15 schematically illustrates a cross-sectional view of one embodiment in which receiving structure and compound semiconductor devices are attached to opposite sides of a receiving substrate. -
FIG. 16 is a flow diagram of one embodiment of a method of processing devices on a receiving substrate. - In this section we shall explain several preferred embodiments of this invention with reference to the appended drawings. Whenever the shapes, relative positions and other aspects of the parts described in the embodiments are not clearly defined, the scope of the invention is not limited only to the parts shown, which are meant merely for the purpose of illustration. Also, while numerous details are set forth, it is understood that some embodiments of the invention may be practiced without these details. In other instances, well-known structures and techniques have not been shown in detail so as not to obscure the understanding of this description.
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FIG. 1 schematically illustrates a cross-sectional view of one embodiment of a donor substrate.Donor substrate 102 may be any type of donor substrate capable of forming a semiconductor device thereon. Representatively, in one embodiment,donor substrate 102 is a wafer made of a compound semiconductor material capable of creating a semiconductor device made of a similar material. For example,donor substrate 102 is made of a group III-V semiconductor material such that a semiconductor device made of a III-V semiconductor material can be epitaxially grown thereon. In one embodiment, the III-V semiconductor material is a compound material such as gallium arsenide (GaAs) or indium gallium phosphide (InGaP). Although specific group III-V semiconductor materials are disclosed, it is contemplated that any semiconductor material may be used. In still further embodiments, thedonor substrate 102 may be made of a non-compound semiconductor material capable of forming a semiconductor device thereon. For example, in one embodiment,donor substrate 102 is a non-compound material other than silicon, for example, a group IV material such as silicon (Si) or germanium (Ge). - A
sacrificial release layer 104 may be deposited on top ofdonor substrate 102.Release layer 104 may be made of any material capable of being removed by an etchant that will not substantially remove a protective layer formed on the semiconductor device. Representatively, in one embodiment,release layer 104 may be made of aluminum indium phosphide (AlInP) and, during a later step, etched using hydrogen chloride (HCl). Alternatively,release layer 104 may be made of silicon (Si) and removed with xenon difluoride (XeF2). In still further embodiments,release layer 104 can be made of any material that is different from the protective material, for example, amorphous-Si, porous silicon or spin-on glass.Release layer 104 may be grown overdonor substrate 102 using a molecular beam epitaxy (MBE) or metallo-organic chemical vapor deposition (MOCVD) growth process. Alternatively,release layer 104 may be formed by other material deposition processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) (e.g. sputtering). -
FIG. 2 schematically illustrates a cross-sectional view of one embodiment of a device layer formed ondonor substrate 102.Device layer 202 may be formed ondonor substrate 102 after the formation ofrelease layer 104 such thatrelease layer 104 is betweencompound device layer 202 anddonor substrate 102.Device layer 202 may be made of a compound semiconductor material, which in some embodiments, is the same material asdonor substrate 102. Representatively,donor substrate 102 may be made of a III-V semiconductor material anddevice layer 202 may also be a III-V semiconductor material. In one embodiment,device layer 202 is grown overdonor substrate 102 using a molecular beam epitaxy (MBE) or metallo-organic chemical vapor deposition (MOCVD) growth process. Alternatively,device layer 202 may be made of a single semiconductor material, for example a group IV semiconductor material such as Ge.Device layer 202 may be made of multiple layers or may be a single layer of semiconductor material. An overall thickness of compoundsemiconductor device layer 202 may be from about 0.5 μm to about 5 μm. - Once
device layer 202 is formed,compound semiconductor devices 302 may be formed fromdevice layer 202 as illustrated inFIG. 3 .Compound semiconductor devices 302, may be, for example, cells having the same or different functionalities. Althoughdevices 302 are referred to as “compound” devices, it is contemplated thatcompound semiconductor devices 302 are not necessarily made of compound materials. Rather,compound devices 302 may be made of a compound semiconductor material or a single semiconductor material, depending upon the material ofdevice layer 202, as previously discussed.Compound semiconductor devices 302 may be formed by etchingtrenches 304 down torelease layer 104. For example, although not shown, a mask layer (e.g. an oxide layer) may be formed overdevice layer 202 and patterned to include openings over portions ofdevice layer 202 wheretrenches 304 are to be formed. A chemical etch (e.g., wet etch or plasma etch) may then be performed to etch throughdevice layer 202.Trenches 304 may extend through an entire thickness ofdevice layer 202 and stop atrelease layer 202. Alternatively,trenches 304 may be etched throughrelease layer 202. - Next,
dielectric layer 402 is formed overcompound semiconductor devices 302 as illustrated inFIG. 4 .Dielectric layer 402 may also be formed over portions ofrelease layer 104 which are exposed betweencompound semiconductor devices 302.Dielectric layer 402 may be formed according to any suitable technique, for example, a plasma enhanced chemical vapor deposition technique. -
Dielectric layer 402 serves several purposes. Representatively,dielectric layer 402 helps to bondcompound semiconductor devices 302 to a receiving structure as will be described in more detail below. Also, as can be seen fromFIG. 4 ,dielectric layer 402 covers all exposed surfaces ofcompound semiconductor devices 302.Dielectric layer 402 can therefore also serve as a passivation and sidewall protection layer during etching ofrelease layer 104 as will also be described in more detail below.Dielectric layer 402 may be made of any type of material suitable for serving at least these purposes. Representatively, in one embodiment,dielectric layer 402 may be made of silicon nitride or silicon oxide. In one embodiment,dielectric layer 402 may be a relatively thin layer such that it does not substantially affect the passage of light betweencompound semiconductor devices 302 and the associated receiving structure. For example,dielectric layer 402 may have a thickness of from about 0.01 μm to about 1 μm. The thickness ofdielectric layer 402 may be selected depending upon the desired characteristics ofcompound semiconductor devices 302. Representatively, a thinner layer may be selected where the optical characteristics ofcompound semiconductor devices 302 are critical and a thicker layer may be selected where the electrical characteristics ofcompound semiconductor devices 302 are more important. - Portions of
dielectric layer 402 between each of thecompound semiconductor devices 302 are etched to exposerelease layer 104 as illustrated inFIG. 5 . Representatively, in one embodiment, a masking layer is applied overcompound semiconductor devices 302 and a chemical etch (e.g., wet etch or plasma etch) is used to remove the unmasked portions ofdielectric layer 402. An example, of a masking layer is an oxide layer that is patterned such that portions ofdielectric layer 402 to be removed are exposed. Exposingrelease layer 104 facilitates removal ofrelease layer 104 during a later processing step. - Once
compound semiconductor devices 302 are formed ondonor substrate 102,donor substrate 102 andcompound semiconductor devices 302 are flipped and bonded to the top of receivingstructure 602 as illustrated inFIG. 6 . Receivingstructure 602 may be made of a material other than that ofcompound semiconductor devices 302. Representatively, where compound semiconductor devices are made of a III-V semiconductor material, receivingstructure 602 may be made of silicon. Receivingstructure 602 may include receivingdevices 610 formed therein which are aligned with and bonded to respectivecompound semiconductor devices 302. Receivingdevices 610 may be silicon semiconductor devices capable of a different functionality thancompound devices 302. For example, receivingdevices 610 may be fabricated to have microelectronic functionalities whilecompound semiconductor devices 302 can be fabricated to have optoelectronic functionalities. More specifically, in one embodiment,compound semiconductor devices 302 may have the ability to absorb, generate and modulate different wavelengths of light or generate a piezoelectric response to a mechanical input while receivingdevices 610 do not have such functionalities. Adielectric layer 608 may be formed over each of receivingdevices 610 to facilitate the bonding process. - The bonding process will now be described in more detail. In one embodiment, a surface activation (plasma) process is performed on
compound semiconductor devices 302 according to recognized techniques. A surface activation process may further be performed on receivingdevices 610. After the activation,compound semiconductor devices 302 are aligned and brought into contact with receivingdevices 610. Chemical bonding betweencompound semiconductor devices 302 and receivingdevices 610 occurs through hydrogen bonding and van der Waals forces between thedielectric layer 402 oncompound semiconductor devices 302 and a dielectric layer formed over receivingdevices 610. In one embodiment, bonding occurs at room temperature. Representatively, room temperature may be considered a temperature of from about 15 to about 30 degrees Celsius, for example, from 20 to 25 degrees Celsius, or about 23 degrees Celsius. The ability to bond the devices together at room temperature is important because, in embodiments wheredielectric layer 402 oncompound semiconductor devices 302 and the dielectric layer on receivingdevices 610 are made of different materials (e.g. silicon dioxide and silicon nitride), the coefficient of thermal expansion between the dissimilar materials is not the same. Furthermore, the coefficient of thermal expansion of the donor and receiving substrates may have different coefficients of thermal expansion which can cause problems with bonding if the bonding is not done at room temperature. In addition, typical bonding procedures which occur at elevated temperatures can create stress on the device. The ability to bond at room temperature eliminates this stress. - It is recognized that for bonding to occur repeatedly and reliably, the surfaces of
compound semiconductor devices 302 and receivingdevices 610, having the dielectric layer formed thereon, should be cleaned (no particulates) and smooth (less than a few nm rms roughness). - After the room temperature bonding step, a high temperature annealing process may be used to transform the bonds between the two surfaces into covalent bonds. Representatively, the bonded
compound semiconductor devices 302 and receivingdevices 610 can be annealed by heating to a temperature between about 150 degrees Celsius and 600 degrees Celsius to strengthen the bond. - In some embodiments,
compound semiconductor devices 302 and receivingdevices 610 are clamped together under a mechanical load to facilitate the bonding step. Alternatively, no external load is applied depending on the characteristics of the material stack and coefficient of thermal expansion (CTE) mismatches betweencompound semiconductor devices 302 and receivingdevices 610. - As further illustrated in
FIG. 6 , receivingstructure 602 is attached to receivingsubstrate 604 along a surface oppositecompound semiconductor devices 302. Anoptional release layer 606 may further be formed between receivingstructure 602 and receivingsubstrate 604 to facilitate removal of receivingsubstrate 604. - In one embodiment, receiving
substrate 604 is a structured wafer that includes multiple through holes (e.g., holes 612) (not drawn to scale) that form a pattern on the top surface of receivingsubstrate 604. Each ofholes 612 extends vertically through the thickness of receivingsubstrate 604. In one embodiment, holes 612 can be formed with uniform spacing among them, with non-uniform spacing among them, or at random locations.Holes 612 can be of the same size or different sizes (e.g., a diameter in the range of 50-500 microns (μm)). In one embodiment, receivingsubstrate 604 is made of silicon or any silicon-based materials. It is appreciated that receivingsubstrate 604 can be single crystalline or polycrystalline silicon. In alternative embodiments, receivingsubstrate 604 can be made of other materials such as ceramic materials. In one embodiment, various additional layers cover the entire surface of receivingsubstrate 604. It is appreciated that the shape and dimensions of receivingsubstrate 604 will be dictated, in one embodiment, by the requirements of receivingstructure 602 adhered to receivingsubstrate 604. - Receiving
substrate 604 can be manufactured with standard semiconductor processing techniques. In one embodiment, receivingsubstrate 604 can be formed from a base wafer (e.g., a silicon wafer) with a hard mask deposited thereon. An example of the hard mask is an oxide layer that is patterned to define the size(s) and locations ofholes 612. The hard mask exposes the part of the silicon wafer whereholes 612 are to be formed. An etchant or a plasma process can then be used to etch through the silicon wafer to form holes 612. The hard mask is removed afterholes 612 are formed. A dielectric layer 614 (e.g., an oxide layer and/or a nitride layer) is formed on the entire exposed surface (including the inner surfaces ofholes 612—i.e., the surface that defines the passage or lumen) of receivingsubstrate 604, as shown inFIG. 6 . In one embodiment,dielectric layer 614 is a thin layer of silicon dioxide with a thickness in the range of 1000 Å-1 μm. It is noted that receivingsubstrate 604 is formed prior to application of receivingstructure 602. Still further, although astructured receiving substrate 604 is described and illustrated it is contemplated that receivingsubstrate 604 may be any standard, non-structured wafer suitable for processing of a receivingstructure 602 and any associated components as described herein. For example, in another embodiment, receivingsubstrate 604 is solid, without throughholes 612. - It is important to note that the features on the surfaces of
compound devices 302 and receivingdevices 610 are critical to allow the hydrogen gas that is evolving during the bonding process to escape and not cause bonding defects. In particular, during the bonding process certain gases (e.g., hydrogen) may be generated at the surface-to-surface contact (“interface”) due to chemical reactions. If the gas is left at this interface, it will migrate and can turn into gas pockets. These gas pockets can become defects, which prevent bonding of the devices. The through passages within receivingsubstrate 604 as described herein provide a route for the gas such that it can escape the interface. - Once
compound semiconductor devices 302 are bonded to receivingdevices 610,release layer 104 is removed so thatdonor substrate 102 can be separated fromcompound semiconductor devices 302 as illustrated inFIG. 7 . In one embodiment, a chemical etching process (e.g., wet etch or plasma etch) is used to removerelease layer 104. In one embodiment, HCl or XeF2 can be used as an etchant. Since receivingdevices 610 andcompound semiconductor devices 302 are coated all around their surfaces withdielectric layers layer 104 is exposed to the etchant and will be etched away. The presence of the exposed surfaces betweencompound semiconductor devices 302 allows the etchant to reachrelease layer 104. It is further contemplated, that in some embodiments, to accelerate the release process,donor substrate 402 may have a structure similar to receivingsubstrate 604 such that there are holes through which the etchant can pass to reachrelease layer 104 from its bottom surface. It is also contemplated that neitherdonor substrate 402 nor receivingsubstrate 604 is required to have through holes through which the etchant can pass to accomplish the etching - It should be understood that the choice of chemical composition of the
release layer 104 is selected so that etching of therelease layer 104 does not substantially attack or damage any other layers, particularly,dielectric layers release layer 104 may be made of aluminum indium phosphide (AlInP) and etched using hydrogen chloride (HCl). Alternatively,release layer 104 may be made of silicon (Si) and removed with xenon difluoride (XeF2). Both HCl and XeF2 are selective etchants in that they will not remove the silicon nitride or oxidedielectric layers - In still further embodiments,
release layer 104 can be made of spin-on glass, amorphous-Si or porous silicon anddielectric layer 402 can be made of oxide. In other embodiments,release layer 104 is made of oxide anddielectric layer 402 can be made of amorphous-Si or Si-nitrite. - In one embodiment, after
compound semiconductor devices 302 are released,donor substrate 102 can be cleaned for reuse.Compound semiconductor devices 302 remain attached to receivingdevices 610 as illustrated inFIG. 8 with abottom surface 802 exposed. Afurther dielectric layer 902 is then applied over each ofcompound semiconductor devices 302 and receivingstructure 602 as illustrated inFIG. 9 .Dielectric layer 902 may be substantially the same asdielectric layer 402 and applied in a similar manner.Dielectric layer 902 covers exposedsurface 802 ofcompound semiconductor devices 302 such that all surfaces ofcompound semiconductor devices 302 are covered. Additionally,dielectric layer 902 acts to mechanically attachcompound semiconductor devices 302 to receivingdevices 610 to further reinforce the bonding between the two structures. In this aspect, the initial bonding strength betweencompound semiconductor devices 302 and receivingdevices 610 does not need to be extremely high since a mechanical bonding step, through the encapsulation bydielectric layer 902, is also performed. Although the dielectric encapsulation is not a necessary part of the invention for bond strength or utility of the bonded structures. - A second set of
compound semiconductor devices 1002 may also be bonded to the first set ofcompound semiconductor devices 302 and covered with afurther dielectric layer 1004 as illustrated inFIG. 10 .Compound semiconductor devices 1002 may be formed and bonded to compoundsemiconductor devices 302 using substantially the same process steps previously discussed with reference toFIGS. 1-9 . A representative process flow for forming the cell stack shown inFIG. 10 is illustrated inFIG. 16 . Representatively,process 1600 may include forming the first plurality of devices (e.g., compound semiconductor devices 302) on a first donor substrate (e.g., substrate 102)(block 1602). The first plurality of devices can then be attached to a receiving structure (e.g., structure 602) as previously discussed (block 1604). The receiving structure may include receiving devices which are aligned with the first plurality of devices. The first donor substrate can then be removed from the first plurality of devices as previously discussed to expose a surface of the first plurality of devices (block 1606). The second plurality of devices are formed on a second donor substrate (block 1608) and then attached to the exposed surface of the first plurality of devices (block 1610). The second plurality of devices can be attached to the first plurality of devices using the chemical and/or mechanical bonding steps previously discussed in reference toFIGS. 8-9 . Once the first plurality of devices and the second plurality of devices are bonded together, the second donor substrate is removed (block 1612). Further processing may then be performed on the resulting device stack (e.g.,compound semiconductor devices 302,devices 1002 and devices 610) to provide the desired functionality (block 1614). - The second set of
compound semiconductor devices 1002 may be made of the same material or a different material thancompound semiconductor devices 302. Representatively, in one embodiment,compound semiconductor devices 302 andcompound semiconductor devices 1002 may be made of the same or different III-V semiconductor materials. For example,compound semiconductor devices 302 may be made of gallium arsenide (GaAs) andcompound semiconductor devices 1002 may be made of indium gallium phosphide (InGaP). Alternatively, one ofcompound semiconductor devices 302 orcompound semiconductor devices 1002 may be made of a group IV material (e.g. germanium or silicon) while the other is made of a compound group III-V material. Alternatively, both may be made of the same or a different group IV material. - Once the desired number of compound semiconductor devices are stacked and bonded to receiving
structure 602,compound semiconductor devices compound semiconductor devices - For example, in one embodiment illustrated in
FIG. 11 ,metal contacts 1102 are deposited and patterned ontocompound semiconductor devices compound semiconductor devices compound semiconductor devices receiving handle substrate 1302, as shown inFIG. 13 .Handle substrate 1302 can be a temporary handle (e.g., a tape) or a final assembly substrate. - Prior to attaching
devices substrate 1302, portions of receivingstructure 602 between receivingdevices 610 are removed to formtrenches 1202 as illustrated inFIG. 12 . These portions may be removed through any of the previously discussed etching processes (e.g., a chemical etch). - At the end of device processing, receiving
substrate 604 is removed to release the resulting devices 1402 (i.e., receivingdevices 610,compound semiconductor devices 302 and compound semiconductor devices 1002), as shown inFIG. 14 . In one embodiment, a chemical etching process (e.g., wet etch or plasma etch) is used to removerelease layer 606. In one embodiment, xenon difluoride (XeF2) can be used as an etchant. Since each ofdevices dielectric layers layer 606 is exposed to the etchant and will be etched away. The presence ofholes 612 allows the etchant to reachrelease layer 606 from its bottom surface, in addition to its exposed side and/or edge surfaces. As a result, the release process can be accelerated. In another embodiment, receivingsubstrate 604 is solid, without throughholes 612, and the release etchant etches the release layer from the side and/or edge surfaces only. - After
devices 1402 are released from receivingsubstrate 604 withhandle substrate 1302,devices 1402 can be separated and re-assembled for a specific configuration, without needing dicing or sawing of the parts. - In some embodiments, after release of the processed
devices 1402, receivingsubstrate 604 can be made available for further reuse. Reusing receivingsubstrate 604 reduces fabrication and materials costs. This is in contrast to a conventional wafer, which is consumed by the process of device fabrication and cannot be reused. - The resulting
devices 1402 are integrally formed devices that are made of different materials having different functionalities. Representatively,devices 1402 can be devices having microelectronic functionalities typically associated with silicon semiconductor devices as well as optoelectronic functionalities typically associated with compound semiconductor devices. For example,devices 1402 may have the functionality of detectors, sensors, photovoltaic (PV) cells, integrated circuits (ICs), micro-machine parts, micro-mechanical parts or electronic components in combination with the light emitting and/or detecting functionalities typically associated with compound semiconductor devices. -
FIG. 15 schematically illustrates a cross-sectional view of another embodiment for forming a device in which compound devices are bonded to receiving structure positioned along opposing sides of a receiving substrate. Representatively, each of the process steps and components described in references toFIGS. 1-10 , which were performed on afirst side 1502 of receivingsubstrate 604, may be duplicated and performed onsecond side 1504 of receivingsubstrate 604. In this aspect, in addition to the previously discussed components formed onfirst side 1502,second side 1504 may have formed thereonrelease layer 1506, receivingdevice 1508 having receivingdevices 1510 and a stack ofcompound devices devices 1510. Each of receivingdevices 1510 andcompound devices device stack 1501 formed onfirst side 1502 anddevice stack 1503 formed onsecond side 1504 may be formed simultaneously or one formed followed by formation of the other. The further processing steps described in reference toFIGS. 11-14 may also be performed ondevice stack 1503 to form devices similar todevices 1402. - While certain embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that the invention is not limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those of ordinary skill in the art. For example, although various process steps are described in a particular order, it is contemplated that one or more of the steps may be performed in a different order. The description is thus to be regarded as illustrative instead of limiting.
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Also Published As
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US20140084450A1 (en) | 2014-03-27 |
US8946052B2 (en) | 2015-02-03 |
WO2014105233A3 (en) | 2014-08-21 |
WO2014105233A2 (en) | 2014-07-03 |
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