CN110534473B - Heterogeneous integration method and heterogeneous integration device for compound semiconductor and silicon-based complementary metal oxide semiconductor wafer - Google Patents
Heterogeneous integration method and heterogeneous integration device for compound semiconductor and silicon-based complementary metal oxide semiconductor wafer Download PDFInfo
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- CN110534473B CN110534473B CN201910691211.7A CN201910691211A CN110534473B CN 110534473 B CN110534473 B CN 110534473B CN 201910691211 A CN201910691211 A CN 201910691211A CN 110534473 B CN110534473 B CN 110534473B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Abstract
The invention relates to the field of semiconductor materials, in particular to a heterogeneous integration method of a compound semiconductor and a silicon-based complementary metal oxide semiconductor wafer, which comprises the following steps: selectively etching the compound semiconductor epitaxial layer to form an etching groove on the compound semiconductor; forming a bonding dielectric layer on the etching surface of the epitaxial layer and the inner groove wall of the etching groove; coating a thermosetting adhesive layer on a silicon-based substrate; bonding the compound semiconductor and the silicon-based complementary metal oxide semiconductor wafer; and etching the substrate of the compound semiconductor, and forming a part of the bonding dielectric layer and the glue layer. According to the invention, the corrosion groove formed by selective etching is beneficial to discharging bubbles in the thermosetting adhesive layer, the bonding dielectric layer is formed on the compound semiconductor, the surface of the compound semiconductor is protected, and the good bonding of the epitaxial layer of the compound semiconductor and the silicon-based complementary metal oxide semiconductor wafer is realized through the bonding of the thermosetting adhesive layer and the bonding dielectric layer.
Description
Technical Field
The invention relates to the field of semiconductor materials, in particular to a heterogeneous integration method and a heterogeneous integration device for a compound semiconductor and a silicon-based complementary metal oxide semiconductor wafer.
Background
Modern integrated circuits based on silicon-based CMOS technology are continuously advancing in integration level, power consumption and device characteristics as the feature size of CMOS devices is continuously shrinking. On the other hand, compound semiconductor devices and integrated circuits have been developed in the fields of ultra-high-speed circuits, microwave circuits, terahertz circuits, optoelectronic integrated circuits, and the like. Because the silicon-based semiconductor CMOS chip and the compound semiconductor chip are difficult to produce in the same wafer factory and can not realize process compatibility, if the silicon-based semiconductor CMOS chip and the compound semiconductor chip are organically combined, the problems that the device selection is limited in the field of integrated circuit design and devices made of different materials can not be mixed and integrated are solved, and the design and the performance of the integrated circuit are certainly greatly improved.
In summary, a method for heterogeneous integration of a compound semiconductor and a silicon-based cmos wafer is provided.
Disclosure of Invention
The invention aims to provide a heterogeneous integration method of a compound semiconductor and a silicon-based complementary metal oxide semiconductor wafer, which is characterized in that selective etching is carried out on an epitaxial layer of the compound semiconductor to form a corrosion groove, so that bubbles in a thermosetting adhesive layer can be discharged, the integration level is improved, a bonding medium layer is formed on the compound semiconductor, and the surface of the compound semiconductor is protected; and then, the good bonding of the epitaxial layer of the compound semiconductor and the base complementary metal oxide semiconductor wafer is realized through the bonding of the thermosetting adhesive layer and the bonding dielectric layer.
The second purpose of the invention is to provide a heterogeneous integrated device, which has high quality and greatly improved performance.
In order to achieve the above purpose, the invention provides the following technical scheme:
a heterogeneous integration method of a compound semiconductor and a silicon-based complementary metal oxide semiconductor wafer comprises the following steps:
selectively etching the compound semiconductor epitaxial layer until the surface of the compound semiconductor substrate is exposed so as to form an etching groove on the compound semiconductor;
forming a bonding medium layer on the etching surface of the epitaxial layer and the inner groove wall of the etching groove for later use;
coating a thermosetting adhesive layer on a silicon-based substrate of a silicon-based complementary metal oxide semiconductor wafer for later use;
aligning and bonding the spare compound semiconductor and silicon-based complementary metal oxide semiconductor wafers to ensure that part of the thermosetting adhesive layer is extruded into the corrosion groove and then bonding is carried out;
and etching the substrate of the compound semiconductor, the part of the bonding dielectric layer formed on the substrate of the compound semiconductor and the glue layer positioned in the corrosion groove until the silicon-based substrate of the silicon-based complementary metal oxide semiconductor wafer is exposed.
The method can achieve the following technical effects:
selective etching is carried out on an epitaxial layer of the compound semiconductor, so that the area selectivity of heterogeneous integration is increased, and the device manufacturing efficiency and the integrated circuit interconnection efficiency are improved. Meanwhile, the corrosion groove formed by selective etching is beneficial to discharging bubbles in the thermosetting adhesive layer and improving the integration level, in addition, a bonding dielectric layer is formed on the compound semiconductor, the surface of the compound semiconductor is protected, and the good bonding of the epitaxial layer of the compound semiconductor and the silicon-based complementary metal oxide semiconductor wafer is realized through the bonding of the thermosetting adhesive layer and the bonding dielectric layer.
In addition, the heterogeneous integration method of the compound semiconductor and the silicon-based complementary metal oxide semiconductor wafer according to the invention can also have the following additional technical characteristics:
preferably, the bonding medium layer is formed by means of plasma vapor deposition.
Preferably, the thickness of the dielectric layer is 50-200 nm, and the material of the bonding dielectric layer is preferably selected from silicon dioxide.
Preferably, the thickness of the thermosetting glue layer is 2-5 microns.
Preferably, the material of the thermosetting adhesive layer is selected from siloxane polymers or benzocyclobutene polymers.
Preferably, the bonding temperature is 250-400 ℃ and the bonding time is 6-8 hours.
Preferably, the step of etching the compound semiconductor epitaxial layer specifically includes:
and etching is carried out along the longitudinal direction and the transverse direction of the compound semiconductor epitaxial layer.
Preferably, the etching step uses a table type reactive ion etching apparatus, and the etching gas is CF4 gas.
Preferably, the compound semiconductor is indium phosphide or gallium arsenide.
In summary, compared with the prior art, the invention achieves the following technical effects:
(1) the manufacturing efficiency of heterogeneous integrated devices and the interconnection efficiency of integrated circuits are improved;
(2) the heterogeneous integrated device has high integration level, few defects and excellent quality;
(3) the process is simple and convenient for automatic application.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
FIG. 1 is a cross-sectional view of a compound semiconductor epitaxial layer of embodiment 1 after selective etching;
FIG. 2 is a cross-sectional view of FIG. 1 after forming a layer of bonding dielectric;
FIG. 3 is a cross-sectional view of a silicon-based CMOS wafer coated with a thermosetting adhesive layer according to example 1;
FIG. 4 is a cross-sectional view of a compound semiconductor, silicon-based CMOS wafer after aligned bonding and bonding according to embodiment 1 of the present invention;
FIG. 5 is a cross-sectional view of FIG. 4 with the compound semiconductor substrate etched away;
fig. 6 is a cross-sectional view of fig. 5 with portions of the bonding dielectric layer and the glue layer (i.e., heterogeneous integrated device) in the etch trench etched away.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
Example 1
As shown in fig. 1 to 6, the present embodiment provides a heterogeneous integration method of a compound semiconductor and a silicon-based complementary metal oxide semiconductor wafer, wherein the compound semiconductor may specifically be an indium phosphide wafer, and includes a compound semiconductor substrate 101 and an epitaxial layer 102 deposited on a surface of the compound semiconductor substrate 101, and the silicon-based complementary metal oxide semiconductor wafer is a silicon-based wafer processed by a CMOS process, and includes the following steps:
selectively etching the compound semiconductor epitaxial layer 102, specifically, etching along the longitudinal direction and the transverse direction of the compound semiconductor epitaxial layer 102 until the surface of the compound semiconductor substrate 101 is exposed, so as to form criss-cross etching grooves on the compound semiconductor;
forming a bonding medium layer 103 on the etching surface of the epitaxial layer 102 and the inner groove wall of the etching groove for later use; specifically, the material of the bonding dielectric layer is selected from silicon dioxide, the thickness of which is 50 nanometers, and further, the bonding dielectric layer 103 is formed by means of Plasma Enhanced Chemical Vapor Deposition (PECVD).
Coating a thermosetting adhesive layer 202 on a silicon-based substrate 201 of a silicon-based complementary metal oxide semiconductor wafer for later use; in particular, the thickness of the thermosetting glue layer is 2 microns, and in practical operation, the material of the thermosetting glue layer may be selected from siloxane Polymer (PDMS) or benzocyclobutene polymer (BCB). The liquid-state adhesive is used for filling, adsorbing, curing and forming, removing a substrate and transferring chips by utilizing the characteristics of low curing temperature, high bonding strength, good chemical stability, low water absorption, good air tightness and the like of the liquid-state adhesive at room temperature.
Aligning and bonding the spare compound semiconductor and silicon-based complementary metal oxide semiconductor wafer, specifically, aligning and bonding the compound semiconductor epitaxial layer 102 and the thermosetting adhesive layer 202 on the silicon-based complementary metal oxide semiconductor wafer, so that part of the thermosetting adhesive layer 202 is extruded into the corrosion groove and then bonded; it should be noted that the bonding step needs to be completed when the thermosetting adhesive layer 202 is in a softened state, specifically, the bonding temperature is 250 degrees, and the bonding time is 6 hours.
And etching the compound semiconductor substrate 101, the part of the bonding dielectric layer 103 formed on the compound semiconductor substrate 101 and the glue layer positioned in the etching groove until the silicon-based substrate 201 of the silicon-based complementary metal oxide semiconductor wafer is exposed.
It is worth mentioning that the etching step adopts a table type reactive ion etching device, and the etching gas is CF4 gas.
Example 2
The embodiment provides a heterogeneous integration method of a compound semiconductor and a silicon-based complementary metal oxide semiconductor wafer, wherein the compound semiconductor can be a gallium arsenide wafer, the compound semiconductor comprises a compound semiconductor substrate and an epitaxial layer deposited on the surface of the compound semiconductor substrate, the silicon-based complementary metal oxide semiconductor wafer is a silicon-based wafer processed by a CMOS process, and the heterogeneous integration method comprises the following steps:
selectively etching the compound semiconductor epitaxial layer, specifically, etching along the longitudinal direction and the transverse direction of the compound semiconductor epitaxial layer until the surface of the compound semiconductor substrate is exposed so as to form criss-cross corrosion grooves on the compound semiconductor;
forming a bonding medium layer on the etching surface of the epitaxial layer and the inner groove wall of the etching groove for later use; specifically, the material of the bonding dielectric layer is selected from silicon dioxide, the thickness of the silicon dioxide is 100 nanometers, and further, the bonding dielectric layer is formed by means of plasma vapor deposition.
Coating a thermosetting adhesive layer on a silicon-based substrate of a silicon-based complementary metal oxide semiconductor wafer for later use; in particular, the thickness of the thermosetting glue layer is 3 microns, and in practical operation, the material of the thermosetting glue layer may be selected from siloxane Polymer (PDMS) or benzocyclobutene polymer (BCB). The liquid-state adhesive is used for filling, adsorbing, curing and forming, removing a substrate and transferring chips by utilizing the characteristics of low curing temperature, high bonding strength, good chemical stability, low water absorption, good air tightness and the like of the liquid-state adhesive at room temperature.
Aligning and bonding the spare compound semiconductor and silicon-based complementary metal oxide semiconductor wafer, specifically, aligning and bonding a compound semiconductor epitaxial layer and a thermosetting adhesive layer on the silicon-based complementary metal oxide semiconductor wafer, so that part of the thermosetting adhesive layer is extruded into a corrosion groove, and then bonding; specifically, the bonding temperature was 350 degrees and the bonding time was 7 hours.
And etching the compound semiconductor substrate, the part of the bonding dielectric layer formed on the compound semiconductor substrate and the glue layer positioned in the corrosion groove until the silicon-based substrate of the silicon-based complementary metal oxide semiconductor wafer is exposed.
It is worth mentioning that the etching step adopts a table type reactive ion etching device, and the etching gas is CF4 gas.
Example 3
The embodiment provides a heterogeneous integration method of a compound semiconductor and a silicon-based complementary metal oxide semiconductor wafer, wherein the compound semiconductor can be a gallium arsenide wafer, the compound semiconductor comprises a compound semiconductor substrate and an epitaxial layer deposited on the surface of the compound semiconductor substrate, the silicon-based complementary metal oxide semiconductor wafer is a silicon-based wafer processed by a CMOS process, and the heterogeneous integration method comprises the following steps:
selectively etching the compound semiconductor epitaxial layer, specifically, etching along the longitudinal direction and the transverse direction of the compound semiconductor epitaxial layer until the surface of the compound semiconductor substrate is exposed so as to form criss-cross corrosion grooves on the compound semiconductor;
forming a bonding medium layer on the etching surface of the epitaxial layer and the inner groove wall of the etching groove for later use; specifically, the material of the bonding medium layer is selected from silicon dioxide, the thickness of the silicon dioxide is 200 nanometers, and further, the bonding medium layer is formed by means of plasma vapor deposition.
Coating a thermosetting adhesive layer on a silicon-based substrate of a silicon-based complementary metal oxide semiconductor wafer for later use; in particular, the thickness of the thermosetting glue layer is 5 microns, and in practical operation, the material of the thermosetting glue layer may be selected from siloxane Polymer (PDMS) or benzocyclobutene polymer (BCB). The liquid-state adhesive is used for filling, adsorbing, curing and forming, removing a substrate and transferring chips by utilizing the characteristics of low curing temperature, high bonding strength, good chemical stability, low water absorption, good air tightness and the like of the liquid-state adhesive at room temperature.
Aligning and bonding the spare compound semiconductor and silicon-based complementary metal oxide semiconductor wafer, specifically, aligning and bonding a compound semiconductor epitaxial layer and a thermosetting adhesive layer on the silicon-based complementary metal oxide semiconductor wafer, so that part of the thermosetting adhesive layer is extruded into a corrosion groove, and then bonding; specifically, the bonding temperature was 400 degrees and the bonding time was 8 hours.
And etching the compound semiconductor substrate, the part of the bonding dielectric layer formed on the compound semiconductor substrate and the glue layer positioned in the corrosion groove until the silicon-based substrate of the silicon-based complementary metal oxide semiconductor wafer is exposed.
It is worth mentioning that the etching step adopts a table type reactive ion etching device, and the etching gas is CF4 gas.
Through detection, the heterogeneous integrated device prepared by the embodiment has better quality and greatly improved performance.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A heterogeneous integration method of a compound semiconductor and a silicon-based complementary metal oxide semiconductor wafer is characterized by comprising the following steps:
selectively etching the compound semiconductor epitaxial layer until the surface of the compound semiconductor substrate is exposed so as to form an etching groove on the compound semiconductor;
forming a bonding medium layer on the etching surface of the epitaxial layer and the inner groove wall of the etching groove for later use;
coating a thermosetting adhesive layer on a silicon-based substrate of a silicon-based complementary metal oxide semiconductor wafer for later use;
aligning and bonding the spare compound semiconductor and silicon-based complementary metal oxide semiconductor wafers, and bonding, wherein the bonding step is completed when the thermosetting adhesive layer is in a softened state, and the bonding temperature is 250-400 ℃;
and etching the substrate of the compound semiconductor, the part of the bonding dielectric layer formed on the substrate of the compound semiconductor and the glue layer positioned in the corrosion groove until the silicon-based substrate of the silicon-based complementary metal oxide semiconductor wafer is exposed.
2. The method of claim 1, wherein the bonding dielectric layer is formed by plasma vapor deposition.
3. The method of claim 2, wherein the thickness of the bonding dielectric layer is 50-200 nm, and the material of the bonding dielectric layer is selected from silicon dioxide.
4. The method of claim 1, wherein the thickness of the layer of thermosetting glue is 2-5 microns.
5. The method of claim 1, wherein the thermosetting adhesive layer is made of a material selected from the group consisting of a siloxane polymer and a benzocyclobutene polymer.
6. The method of claim 4, wherein the bonding time is 6-8 hours.
7. The method according to claim 1, wherein the step of etching the compound semiconductor epitaxial layer specifically comprises:
and etching is carried out along the longitudinal direction and the transverse direction of the compound semiconductor epitaxial layer.
8. The method of claim 1, wherein the etching step uses a bench-top reactive ion etching apparatus and the etching gas is CF4 gas.
9. The method according to claim 1, wherein the compound semiconductor is indium phosphide or gallium arsenide.
10. A heterogeneous integrated device, characterized in that it is obtained by the method according to any one of claims 1 to 9.
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| CN1688014A (en) * | 2005-05-11 | 2005-10-26 | 华东师范大学 | Preparing method and application of heterobonded wafer |
| US20140084450A1 (en) * | 2012-09-26 | 2014-03-27 | Sandia Corporation | Processes for multi-layer devices utilizing layer transfer |
| CN107408603A (en) * | 2015-01-06 | 2017-11-28 | 苹果公司 | The LED structure compound for reducing non-radiative side wall |
| US20190088480A1 (en) * | 2017-09-20 | 2019-03-21 | International Business Machines Corporation | Chip handling and electronic component integration |
| KR20190076690A (en) * | 2017-12-22 | 2019-07-02 | (재)한국나노기술원 | Transfer Method using Deformable Film |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1688014A (en) * | 2005-05-11 | 2005-10-26 | 华东师范大学 | Preparing method and application of heterobonded wafer |
| US20140084450A1 (en) * | 2012-09-26 | 2014-03-27 | Sandia Corporation | Processes for multi-layer devices utilizing layer transfer |
| CN107408603A (en) * | 2015-01-06 | 2017-11-28 | 苹果公司 | The LED structure compound for reducing non-radiative side wall |
| US20190088480A1 (en) * | 2017-09-20 | 2019-03-21 | International Business Machines Corporation | Chip handling and electronic component integration |
| KR20190076690A (en) * | 2017-12-22 | 2019-07-02 | (재)한국나노기술원 | Transfer Method using Deformable Film |
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