JP2009088052A - Semiconductor element and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element which operates stably against voltage variation. <P>SOLUTION: Multilayered wiring 12 is formed on a semiconductor substrate 2 where a MOS transistor 4 is formed, and an electrode electrically connected to power supply wiring in the multilayered wiring 12 is formed extending from the side of a surface of the semiconductor substrate 2 where the multilayered wiring 12 is formed to the side of its reverse surface. When capacity becomes necessary to suppress an influence of the voltage variation, the reverse surface side of the semiconductor substrate 2 is subjected to back grind processing to expose the electrode 15, and a capacitance element such as a decoupling capacitor is connected thereto. Consequently, sufficient capacity can be secured without making the semiconductor element 1 large-sized even after the semiconductor element 1 is formed, and the semiconductor element 1 is enabled to stably operate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor element and a semiconductor device, and more particularly to a semiconductor element and a semiconductor device provided with a capacitor for stabilizing circuit operation.

  With the increase in density and scale of semiconductor devices, the operating voltage and power consumption increase, and the power supply voltage drop and power supply noise on the mounted circuit board, such as the package board, are likely to occur. It is in. Therefore, the circuit operation is stabilized by adding a capacitance to the inside of the semiconductor element or the package substrate and suppressing the influence of power supply noise or the like.

FIG. 28 is an explanatory diagram of an example of a form in which a capacitor is added inside the semiconductor element, and FIG. 29 is an explanatory diagram of an example of a form in which a capacitor is added to the package substrate.
First, a semiconductor element 200 shown in FIG. 28 has an n-channel MOS (Metal Oxide Semiconductor) transistor (nMOS transistor) 220 and a p-type semiconductor element in an element region defined by an STI (Shallow Trench Isolation) 202 of a p-type semiconductor substrate 201. A channel type MOS transistor (pMOS transistor) 230 is formed. The nMOS transistor 220 and the pMOS transistor 230 include p-type and n-type wells 221 and 231, n-type and p-type source / drain regions 222 and 232, gate insulating films 223 and 233, gate electrodes 224 and 234, and sidewalls, respectively. 225, 235. The source / drain regions 222 and 232 and the gate electrodes 224 and 234 are connected to predetermined wirings 205 a to 205 f through plugs 204 a to 204 f in the interlayer insulating film 203.

  Here, an n-type impurity diffusion region 206 is provided in the same semiconductor substrate 201 where the nMOS transistor 220 and the pMOS transistor 230 are formed, and an insulating film 207 and an electrode 208 are partially formed thereon. The capacitor cells 211 are formed by sequentially stacking the electrodes 208 and connecting the wirings 210a and 210b to the portions of the impurity diffusion regions 206 not covered with the insulating film 207 via plugs 209a and 209b, respectively. .

  In the semiconductor device 300 shown in FIG. 29, the semiconductor element 310 is flip-chip mounted on the package substrate 320 using the bump 311, and the bump 321 for external connection is attached to the surface opposite to the mounting surface. An external decoupling capacitor 330 is mounted on the mounting surface side of the semiconductor element 310.

Various forms of semiconductor devices are known.For example, after a semiconductor element is flip-chip mounted on a circuit board provided with wiring, the mounting surface side is covered with an insulating film and planarized, There has been proposed a plug in which a plug reaching a predetermined wiring of the circuit board is formed in the insulating film region to enable electrical connection with the outside (see, for example, Patent Document 1).
JP 2005-109419 A

However, when a capacitor is added to the inside of the semiconductor element or the package substrate for the purpose of stabilizing the circuit operation as described above, there are the following problems.
For example, when a capacitor cell is to be formed inside a semiconductor element, the capacitor cell must be formed in an empty region where a transistor or the like for realizing an operation necessary for the semiconductor element is not formed. However, with the progress of miniaturization and high integration, the area of the empty area where the capacity cells can be formed is limited, and the number of capacity cells is limited. In order to increase the capacity cell, it is sometimes necessary to increase the size of the semiconductor element.

  Further, when a decoupling capacitor is mounted on a package substrate of a semiconductor device, the wiring path in the package substrate that connects between the semiconductor element and the decoupling capacitor becomes long, and the inductance (equivalent series inductance (ESL)) of the package substrate becomes long. ) May cause problems in the operation of the semiconductor element. That is, when the inductance of the package substrate is large, when the semiconductor element instantaneously consumes current (charge) due to abrupt operation, the decoupling capacitor can supply the consumed charge to the semiconductor element. Disappear.

FIG. 30 is a diagram illustrating an example of a voltage waveform inside the semiconductor element.
When the shortage of charge supply as described above occurs, as shown by a solid line in FIG. 30, a power supply voltage drop occurs in the semiconductor element. Further, due to the influence, current supply to the semiconductor element in the semiconductor device and the decoupling capacitor Charge / discharge becomes unstable, and resonance of the power supply voltage also occurs in the semiconductor element.

  Such an influence of the inductance of the package substrate can be suppressed to some extent as shown by a dotted line in FIG. 30 by changing the capacitance of the decoupling capacitor mounted on the package substrate. However, depending on the magnitude of the inductance, such a voltage drop or resonance phenomenon may not be avoided. Further, the voltage drop due to the target operating voltage value and the voltage fluctuation range due to the resonance phenomenon are expected to be further improved in terms of performance and reliability.

It is also considered to deal with such problems by reviewing the design of the package substrate and changing the mounting position and number of decoupling capacitors.
31 and 32 are diagrams showing an example of mounting a decoupling capacitor.

  For example, as shown in FIG. 31, in a semiconductor device 400 in which a semiconductor element 410 is mounted on a package substrate 420, a decoupling capacitor 430 is mounted on the side opposite to the mounting surface of the semiconductor element 410 and directly below the semiconductor element 410. To do. Thereby, the wiring path between the semiconductor element 410 and the decoupling capacitor 430 is shortened, and the influence of the inductance of the package substrate 420 can be suppressed. However, at present, technical and cost problems remain in the production of the package substrate 420 applicable to such a configuration.

  Further, as in the semiconductor device 500 shown in FIG. 32, a plurality of decoupling capacitors 530 are distributed around the semiconductor element 510 on the package substrate 520 to disperse the charges as indicated by dotted lines and arrows in the figure. By doing so, the inductance can be reduced by utilizing the parallel effect. However, depending on the wiring structure of the package substrate 520, there is a case where the inductance is not drastically reduced and no significant improvement is observed.

  As described above, in the method of forming a capacity cell inside the semiconductor element, there is a limit to the increase in the capacity, and in the method of mounting a decoupling capacitor on the package substrate, it is mounted due to the influence of the inductance of the package substrate. It is not always possible to suppress the voltage drop and resonance phenomenon of the semiconductor device. In particular, in recent semiconductor devices in which low voltage, high power, large scale, and high frequency are advanced, even if those methods are used, when a sudden voltage fluctuation occurs in the semiconductor device, It has become difficult to stably operate a semiconductor element mounted on the semiconductor element.

  The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor element and a semiconductor device that can be stably operated against voltage fluctuations.

  In order to solve the above problems, the present invention includes a semiconductor substrate having a transistor formed on one main surface side, and a wiring provided on the one main surface side and electrically connected to the transistor. A semiconductor element comprising: a wiring layer; and an electrode that is electrically connected to the wiring and is disposed on the semiconductor substrate so as to extend from the one main surface side toward the other main surface side. Provided.

  According to such a semiconductor element, the electrode electrically connected to the wiring in the wiring layer formed on one main surface side of the semiconductor substrate is connected from one main surface side to the other main surface side of the semiconductor substrate. It is arranged toward. If this electrode is used, a capacitive element such as a decoupling capacitor can be connected to the other main surface side of the semiconductor substrate of the semiconductor element.

  In the present invention, in order to solve the above-described problem, a semiconductor substrate having a transistor formed on one main surface side and a wiring provided on the one main surface side and electrically connected to the transistor are provided. A semiconductor element comprising: a wiring layer provided; and an electrode electrically connected to the wiring and disposed on the semiconductor substrate so as to extend from the one main surface side toward the other main surface side, and the semiconductor There is provided a semiconductor device comprising: a circuit board on which an element is mounted using a terminal provided on the wiring layer side.

  According to such a semiconductor device, it becomes possible to connect a capacitive element such as a decoupling capacitor to the other main surface side of the semiconductor substrate of the semiconductor element.

  In the present invention, the electrode electrically connected to the wiring in the wiring layer formed on one main surface side of the semiconductor substrate is arranged on the semiconductor substrate from the one main surface side toward the other main surface side. Made the configuration. As a result, a capacitive element such as a decoupling capacitor can be connected to the other main surface side of the semiconductor substrate using the electrode, which is sufficient even after the formation of the semiconductor element without increasing the size of the semiconductor element. Capacity can be secured. Therefore, it is possible to realize a semiconductor element that stably operates against voltage fluctuations and a semiconductor device mounted with such a semiconductor element.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the configuration principle of the semiconductor element will be described.
FIG. 1 is an explanatory diagram of the configuration principle of a semiconductor element.

  In the semiconductor element 1, a predetermined channel type MOS transistor 4 is formed in an element region defined by an STI 3 formed on a semiconductor substrate 2 such as a silicon substrate. The MOS transistor 4 includes a well 5 of a predetermined conductivity type formed in its element region, a gate electrode 7 formed on the semiconductor substrate 2 via a gate insulating film 6, and a side wall formed on the side wall of the gate electrode 7. 8 and a source region 9 a and a drain region 9 b formed in the semiconductor substrate 2 on both sides of the gate electrode 7.

  On the semiconductor substrate 2 on which such a MOS transistor 4 is formed, a multilayer wiring 12 including a wiring 10 formed in a predetermined pattern in a plurality of layers and a plug 11 for connecting the predetermined wiring 10 is laminated. Has been.

  A part of the wiring 10 and the plug 11 is electrically connected to the source region 9a of the MOS transistor 4, and a power supply terminal provided on the surface side for supplying current (charge) to the semiconductor element 1 13 (VDD / GND) and its source region 9a are electrically connected. Another part of the wiring 10 and the plug 11 is electrically connected to the drain region 9b of the MOS transistor 4, and a signal provided on the surface side for outputting the signal of the semiconductor element 1 to the outside. The terminal 14 and the drain region 9b are formed so as to be electrically connected. The semiconductor element 1 can be flip-chip mounted with the surface side on which the power supply terminals 13 and the signal terminals 14 are formed facing a circuit board (not shown) such as a package board.

  Further, the semiconductor element 1 includes a wiring 10 in the multilayer wiring 12 electrically connected to the power supply terminal 13 and an electrode 15 formed so as to be electrically connected to the plug 11 (power supply wiring). Yes. The electrode 15 is formed so as to extend from the formation surface side of the multilayer wiring 12 of the semiconductor substrate 2 on which the MOS transistor 4 is formed to the back surface side of the semiconductor substrate 2. One end of the electrode 15 is connected to the power supply wiring in the multilayer wiring 12, and the other end is embedded in the semiconductor substrate 2. The portion of the electrode 15 formed in the semiconductor substrate 2 is formed so that the periphery thereof is covered with the insulating film 16 and the electrode 15 and the semiconductor substrate 2 are insulated.

  In the semiconductor element 1 having such a configuration, the semiconductor substrate 2 is back-grinded so that the electrode 15 can be exposed on the back surface side of the semiconductor substrate 2. The electrode 15 exposed on the back side can be used as a terminal for mounting a capacitive element such as a decoupling capacitor on the semiconductor element 1 when the semiconductor element 1 is flip-chip mounted on a circuit board. The back grinding process of the semiconductor substrate 2 can be performed at any stage before and after mounting on the circuit board.

  Therefore, even if there is no space in the semiconductor element 1 for forming a capacity cell sufficient to fill the capacity, the back grinding process is performed after the semiconductor element 1 is completed, and a capacitor element such as a decoupling capacitor is externally attached. Therefore, the capacity necessary for the semiconductor element 1 can be ensured.

  For example, a capacity cell can be formed inside the semiconductor element 1 without increasing the size, and the shortage can be compensated by a capacitor element connected using the electrode 15 exposed as described above. . Alternatively, when a shortage of capacity occurs after the completion of the semiconductor element 1 due to the occurrence of a defect or a change in use, a capacity element can be added to compensate for the shortage. . Therefore, it is possible to cope with defects and application changes without changing the wiring structure of the semiconductor element 1, and it is possible to reduce the manufacturing cost of the semiconductor element after the design change or the design change.

  As described above, since the capacitor element can be mounted on the back surface side of the semiconductor element 1, it is possible to prevent the semiconductor element 1 from being planarly enlarged due to securing the capacity. When a capacitive element is mounted on the semiconductor element 1, a sufficient capacity can be ensured to suppress the influence of power supply voltage fluctuations and power supply noise, thereby stabilizing the operation of the semiconductor element 1. Further, when a capacitive element is mounted on the semiconductor element 1, the capacitive element mounted on the circuit board for the same purpose can be reduced or eliminated, so that the circuit board on which the semiconductor element 1 is mounted can be eliminated. It can also contribute to miniaturization and ease of design.

  The electrode 15 exposed on the back side can also be used as a terminal for testing the electrical characteristics of the semiconductor element 1. For example, when testing whether or not necessary electrical characteristics can be obtained after completion of the semiconductor element 1 or performing a test for investigating the cause when a failure occurs, an external signal input is used. It can be used as a terminal. As a result, the test can be facilitated and the accuracy can be improved, and an appropriate cause of the occurrence of the defect can be investigated.

  In order to form the semiconductor element 1 having such an electrode 15, first, in the design stage, a circuit block that may cause power supply voltage fluctuation or power supply noise is extracted in advance. The wiring path for connecting 15 and the position for forming the electrode 15 are set. Further, at that time, the shape of the electrode 15 is set according to the form of the capacitive element that may be mounted via the electrode 15.

  Here, the case where the electrode 15 is connected to the power supply wiring electrically connected to the power supply terminal 13 has been described. However, the type of element to be mounted using the electrode 15 and the test performed after the semiconductor element 1 is completed. The electrode 15 can be connected to the wiring 10 and the plug 11 (signal wiring) that are electrically connected to the signal terminal 14 depending on the type or the like.

  Next, a method of forming an electrode that can be exposed by the back grinding process of the semiconductor substrate as described above will be described. Note that here, an example of a method for forming an exposed electrode included in a semiconductor element using a copper wiring will be described with reference to FIGS.

FIG. 2 is a schematic cross-sectional view of an essential part of a MOS transistor forming process.
First, an STI 21 which is an element isolation region is formed on the silicon substrate 20, and a well 22 is formed by ion implantation of a predetermined conductivity type impurity in the element region defined by the STI 21. Next, an insulating film such as a silicon oxide film and polysilicon are stacked, and gate processing is performed to form the gate insulating film 23 and the gate electrode 24. Thereafter, an insulating film is deposited on the entire surface, etched back to form sidewalls 25, and ions of a predetermined conductivity type are implanted to form source regions 26a and drain regions 26b. Thereby, the MOS transistor 27 is formed. After the formation of the MOS transistor 27, a cover film 28 using silicon nitride or the like and an interlayer insulating film 29 such as a silicon oxide film or a low-k film are formed on the entire surface.

FIG. 3 is a schematic sectional view showing an important part of the plug forming process.
After the formation of the interlayer insulating film 29, first, a resist pattern is formed, and the interlayer insulating film 29 and the cover film 28 are etched using the resist pattern as a mask, and contact holes reaching the gate electrode 24, the source region 26a, and the drain region 26b. Form. Then, after depositing a conductive material such as tungsten on the entire surface, planarization by CMP is performed to form the plug 30.

FIG. 4 is a schematic sectional view showing an important part of the first interlayer insulating film forming step.
After the plug 30 is formed, a stopper film 31 such as a silicon nitride film and an interlayer insulating film 32 such as a low-k film are formed on the entire surface.

FIG. 5 is a schematic cross-sectional view of an essential part of the wiring forming process.
After the stopper film 31 and the interlayer insulating film 32 are formed, a first-layer wiring 33 is formed by a damascene process. That is, first, a resist pattern formation, an interlayer insulating film 32 and a stopper film 31 are sequentially etched to form a wiring formation groove. Then, a barrier metal 33a and a seed copper layer are formed on the entire surface by sputtering or the like, then a copper layer is formed by plating, flattened by CMP, and a first layer connected to each plug 30 The wiring 33 is formed.

After the first layer wiring 33 is formed in this way, the above-described electrode that can be exposed is formed.
FIG. 6 is a schematic cross-sectional view of the main part of the first resist pattern forming process, FIG. 7 is a schematic cross-sectional view of the main part of the first etching process, and FIG. 8 is a schematic cross-sectional view of the main part of the resist removing process.

  First, as shown in FIG. 6, after a stopper film 34 is formed on the interlayer insulating film 32 on which the wiring 33 is formed, a resist pattern having an opening at an electrode forming position is formed. Here, a multilayer resist process is used in which a lower resist 35, a film thickness control layer 36, an antireflection film 37, and an upper resist 38 are sequentially stacked on the stopper film 34.

  In that case, first, a predetermined opening pattern is formed in the upper resist 38, and the antireflection film 37 and the film thickness control layer 36 are etched using the mask as a mask to transfer the opening pattern to the film thickness control layer 36. The opening pattern is transferred to the underlying resist 35 using the film thickness control layer 36 as a mask. Then, using the film thickness control layer 36 and the underlying resist 35 as a mask, the stopper film 34, the interlayer insulating film 32, and the stopper film 31 thereunder are etched to form an opening 39 as shown in FIG. After the opening 39 is formed, the film thickness control layer 36 and the underlying resist 35 are removed to obtain a state as shown in FIG.

FIG. 9 is a schematic cross-sectional view of the relevant part in the second resist pattern forming step, and FIG. 10 is a schematic cross-sectional view of the relevant part in the second etching step.
After the opening 39 is formed, as shown in FIG. 9, the lowermost interlayer insulating film 29 is etched using the multilayer resist process similar to the above, using the film thickness control layer 40 and the resist 41 to which the opening pattern is transferred as a mask. Then, an opening 39a reaching the cover film 28 as shown in FIG. 10 is formed. After the opening 39a is formed, the film thickness control layer 40 and the resist 41 are removed. By forming the opening 39a after forming the resist 41 and the like in this way, etching damage to a region other than the region where the opening 39a is formed can be suppressed.

FIG. 11 is a schematic cross-sectional view of an essential part of a third resist pattern forming step, and FIG. 12 is a schematic cross-sectional view of an essential part of a third etching step and a spacer film forming step.
After the formation of the opening 39a, as shown in FIG. 11, a film thickness control layer 42 and resists 43 and 44 are formed using a multilayer resist process. In that case, by appropriately controlling the forming conditions (coating conditions), a thin resist 43 is formed in the opening 39a, and a thick resist 44 is formed on the surface around the opening 39a. .

  Then, by performing etching from the side of the resists 43 and 44 thus formed, a deeper opening 39b reaching the inside of the silicon substrate 20 is formed as shown in FIG. In this etching, the disappearance of the resists 43 and 44 shown in FIG. 11 progresses before the etching of the silicon substrate 20, but the thin resist 43 disappears first, and the remaining resist 44 that has been formed thick is used as a mask. Thus, the opening 39b is formed before the resist 44 disappears.

  Therefore, the film thicknesses of the resists 43 and 44 are set based on the depth of the opening 39b to be formed. Further, from the viewpoint of the aspect ratio that can be formed, the deeper the opening 39b is formed, the more the openings 39 and 39a having a larger opening area need to be formed in advance. A resist pattern (opening pattern) is formed on the basis of the planar shape.

After the opening 39b is formed, a spacer film 45 is formed on the exposed surface of the silicon substrate 20 with a silicon nitride film or the like.
13 is a schematic cross-sectional view of an essential part of a barrier metal and seed copper layer forming step, FIG. 14 is a schematic cross-sectional view of an essential part of a copper embedding process, and FIG. 15 is a schematic cross-sectional view of an essential part of a CMP process.

  After the formation of the opening 39b and the spacer film 45, first, as shown in FIG. 13, a barrier metal 46 and a seed copper layer 47 are formed on the entire surface by sputtering or the like, and then, as shown in FIG. The copper layer 48 is formed using In FIG. 14, the copper layer 48 is shown including the seed copper layer 47 of FIG. Then, planarization by CMP is performed up to the interlayer insulating film 32, and the excess copper layer 48, barrier metal 46, and stopper film 34 are removed, thereby forming an electrode 49 as shown in FIG. 15 in the opening 39b.

FIG. 16 is a schematic sectional view showing an important part of a second interlayer insulating film forming step.
After the electrode 49 is formed, a stopper film 50 such as a silicon nitride film and an interlayer insulating film 51 such as a low-k film are newly formed on the entire surface. Thereafter, in the same manner as shown in FIGS. 2 to 5, the plug and the second and subsequent layers should be formed so that the electrode 49 is connected to a predetermined power supply line or signal line. That's fine. Of course, it is possible to form the second and subsequent wirings using a dual damascene process.

  The electrode 49 formed as described above can be exposed by back-grinding the back surface of the silicon substrate 20, and the exposed end surface of the electrode 49 is connected to a capacitor element or an external connection for conducting an electrical characteristic test. It is used as a terminal. In forming the electrode 49, the planar shape is set based on the type of capacitive element to be connected and the type of test. For example, when a capacitive element is connected to the exposed electrode 49, the capacitive element can be connected directly to the exposed end face, or an appropriate pad can be formed on the exposed end face and connected via the pad. Next, the planar shape of the electrode 49 is set.

  Here, the case where copper wiring is formed has been described as an example, but aluminum wiring can also be formed. Although the electrode 49 is made of copper here, it can be made of one or two or more metals having conductivity in addition to copper.

  Hereinafter, a configuration example of a semiconductor device in which a semiconductor element to which the above principle is applied is mounted on a package substrate will be described with reference to FIGS. In FIG. 17 to FIG. 27, the inside of the semiconductor element and the package substrate is schematically shown by simplifying the wiring structure including the plug. Further, the positions and connection relations of the wiring of the semiconductor element and the package substrate, the structure of the MOS transistor of the semiconductor element and the formation position thereof are merely examples, and are not limited thereto. Moreover, in the following description, the same code | symbol is attached | subjected about the same element.

First, the first configuration example will be described.
17 and 18 are schematic cross-sectional views of the first configuration example of the semiconductor device, and FIG. 19 is a schematic plan view of the semiconductor element in the first configuration example.

  In the semiconductor device 60 shown in FIG. 17, a semiconductor element 70 is flip-chip mounted on a package substrate 80 via bumps 71, and the package substrate 80 is connected to another circuit such as a mother board via bumps 81 provided thereon. It can be connected to the board. The semiconductor element 70 is configured to be supplied with current (charge) from the package substrate 80 side and to output a generated signal to the package substrate 80 side.

  In the semiconductor element 70, a MOS transistor 73 is formed using a semiconductor substrate 72, and a multilayer wiring 74 having a wiring structure 74a in which plugs and wirings are formed in a predetermined connection relation over a plurality of layers is formed on the semiconductor substrate 72. Has been. Further, the semiconductor element 70 has a plurality of electrodes 75 connected to the wiring structure 74 a in the multilayer wiring 74 and extending from there to the semiconductor substrate 72. One end of each electrode 75 is connected to power supply wiring (power supply wiring (VDD / GND) electrically connected to power supply wiring (VDD / GND) of the package substrate 80) in the wiring structure 74a in the multilayer wiring 74. It is assumed that the other end is embedded in the semiconductor substrate 72 in an insulated state.

  The package substrate 80 is a so-called build-up substrate, and has a wiring structure 80a in which plugs and wirings are formed in a predetermined connection relation over a plurality of layers. Here, a plurality of decoupling capacitors 83 are mounted on the pads 82 provided on the mounting surface side of the semiconductor element 70. Each of these decoupling capacitors 83 accumulates the charge supplied to the package substrate 80 and supplies the accumulated charge to the semiconductor element 70 as necessary, so that the package substrate 80 and the semiconductor element 70 can be supplied. Is electrically connected.

  The semiconductor element 70 of such a semiconductor device 60 has a sufficient capacity secured by a capacity cell (not shown) formed inside or a decoupling capacitor 83 mounted on the package substrate 80. As shown in FIG. 17, the electrode 75 can be used without being exposed.

  On the other hand, the capacity cell built in the semiconductor element 70 or the decoupling capacitor 83 mounted on the package substrate 80 does not have sufficient capacity, such as when voltage fluctuations occur in the semiconductor element 70 due to defects or application changes. In such a case, the semiconductor element 70 is subjected to back-grinding processing on the semiconductor substrate 72 (the dotted line portion of the semiconductor substrate 72 in FIG. 17 is removed), and the electrode 75 is exposed to be decoupled therein. Capacitance elements such as capacitors can be mounted. Here, as shown in FIG. 18, a plurality of decoupling capacitors 76 can be mounted on the exposed electrode 75, and each of these decoupling capacitors 76 has a charge supplied to the semiconductor element 70. The accumulated charge can be supplied to the semiconductor element 70 via the electrode 75 connected to the power supply wiring as necessary. The exposure of the electrode 75 by the back grinding process can be performed before or after the semiconductor element 70 is mounted on the package substrate 80.

  The semiconductor element 70 has an electrode 75 formed therein in advance so that the structure shown in FIG. 18 can be obtained. For example, as shown in FIG. 19, a maximum of four decoupling capacitors 76 (shown by dotted lines in the figure) that can perform the above function when exposed can be mounted, and the decoupling capacitors 76 to be mounted can be mounted. The electrode 75 is formed in a planar shape corresponding to the size and electrode shape.

  The decoupling capacitor 76 can be mounted after the pad 77 is formed after the electrode 75 is exposed, but the decoupling capacitor 76 can also be directly mounted on the exposed electrode 75. It is. Further, each capacitance of the decoupling capacitor 76 mounted on the semiconductor element 70 and each capacitance of the decoupling capacitor 83 mounted on the package substrate 80 may be the same or different.

  Here, a plurality of decoupling capacitors 83 are mounted on the package substrate 80, but the number thereof is not limited, and may be omitted if unnecessary. When a plurality of decoupling capacitors 83 are mounted, it is preferable to disperse them on the package substrate 80, for example, as shown in FIG.

FIG. 20 is a schematic plan view of the semiconductor device of the first configuration example.
As shown in FIG. 20, if the decoupling capacitors 83 on the package substrate 80 are dispersedly arranged around the semiconductor element 70, the parallel effect thereof reduces the inductance in the package substrate 80 and reduces the voltage drop. And the resonance phenomenon can be effectively suppressed.

  Further, here, the configuration in which the decoupling capacitor 76 is connected to the exposed electrode 75 has been described, but this electrode 75 is used as a terminal for testing electrical characteristics instead of connecting the decoupling capacitor 76. You can also In the case where the electrode 75 is provided for such a test terminal, in consideration of knowledge at the design stage, for example, in which circuit block power voltage fluctuation or power noise may occur, The electrode 75 may be electrically connected to a signal wiring other than the power supply wiring.

Next, a second configuration example will be described.
FIG. 21 is a schematic cross-sectional view of a second configuration example of the semiconductor device, and FIG. 22 is a schematic plan view of a semiconductor element in the second configuration example. FIG. 23 is a diagram showing a circuit configuration of the capacitor array chip.

  A semiconductor device 60a shown in FIG. 21 has a configuration in which a capacitor array chip 90 is mounted on a semiconductor element 70a from which an electrode 75a is exposed by backgrinding a semiconductor substrate 72. The capacitor array chip 90 includes an MIM (Metal-Insulator-Metal) in which an impurity diffusion region is formed on a semiconductor substrate and an insulating film and an electrode film are stacked thereon, and an insulating film is provided between metals. ) It has a configuration in which a plurality of capacitors and the like are formed inside. The capacitor array chip 90 is provided with external connection terminals electrically connected to the respective capacitors, and these external connection terminals are electrically connected to the electrodes 75a of the semiconductor element 70a.

  Here, the capacitor array chip 90 and the semiconductor element 70a are connected through the pads 91 and 77 and the bumps 92, and an underfill material 93 is interposed between the capacitor array chip 90 and the semiconductor element 70a. Filled.

In the semiconductor element 70a, for example, as shown in FIG. 22, an electrode 75a is formed in advance so that the capacitor array chip 90 can be mounted when the electrode 75a is exposed. Further, for example, as shown in FIG. 23, the capacitor array chip 90 is configured to form a circuit including a plurality of capacitors C _{1 to} C _n and a fuse F, and the capacity is increased by cutting the fuse F. Can do.

Such a semiconductor device 60a can also stabilize the operation of the semiconductor element 70a.
Next, a third configuration example will be described.

FIG. 24 is a schematic cross-sectional view of a third configuration example of the semiconductor device.
In the semiconductor device 60b shown in FIG. 24, an interposer 101 is connected via a bump 100 to a semiconductor element 70b from which an electrode 75b is exposed by backgrinding a semiconductor substrate 72, and a plurality of decoupling capacitors 102 are connected to the interposer 101. Is mounted.

  The interposer 101 includes a predetermined wiring structure 101a therein, and a plurality of decoupling capacitors 102 are electrically connected to the wiring structure 101a. Each of these decoupling capacitors 102 accumulates the charge supplied to the semiconductor element 70b via the electrode 75b and the interposer 101, and stores the accumulated charge via the interposer 101 and the electrode 75b as necessary. Can be supplied to.

  The interposer 101 can have a circuit configuration in which more decoupling capacitors 102 can be mounted compared to the semiconductor element 70b having a complicated circuit configuration. Therefore, if the electrode 75b is formed inside so as to be connectable to the interposer 101, a large number of decoupling capacitors 102 can be mounted to stabilize the operation.

Next, a fourth configuration example will be described.
FIG. 25 is a schematic cross-sectional view of a fourth configuration example of the semiconductor device.
In the semiconductor device 60c shown in FIG. 25, the first metal member 110, the dielectric layer 111, and the second metal member 112 are laminated on the semiconductor element 70c from which the electrode 75c is exposed by the back grinding process of the semiconductor substrate 72. The two metal members 112 are connected to the package substrate 80. The first metal member 110 is connected to the electrode 75c electrically connected to the VDD wiring of the semiconductor element 70c, and the second metal member 112 arranged via the dielectric layer 111 is the VSS wiring of the package substrate 80. It is designed to be connected electrically.

  The first metal member 110 can be constituted by, for example, a metal plating layer, and the second metal member 112 is constituted by using, for example, a metal radiating fin or cover provided so as to cover the semiconductor element 70c. can do.

  In such a semiconductor device 60c, the first metal member 110, the dielectric layer 111, and the second metal member 112 form a capacitance, thereby causing the semiconductor element 70c to operate stably even when voltage fluctuation occurs. be able to.

Next, a fifth configuration example will be described.
FIG. 26 is a schematic cross-sectional view of a fifth configuration example of the semiconductor device.
In the semiconductor device 60d shown in FIG. 26, an impurity diffusion region (well tap) 78 connected to a power supply wiring (VDD / GND) is formed in a semiconductor element 70d in which a MOS transistor (not shown) is formed. The electrode 75d is formed from the well tap 78.

  In this case, the electrode 75d is formed by forming a contact hole reaching the well tap 78 from the back surface side of the semiconductor element 70d before or after the semiconductor element 70d is mounted on the package substrate 80, and then embedding the material of the electrode 75d therein. Formed by. A decoupling capacitor 76 is electrically connected to the electrode 75d formed in this manner, thereby forming a semiconductor device 60d.

Such a semiconductor device 60d can also stabilize the operation of the semiconductor element 70d.
A capacitor array chip 90 as shown in FIG. 21 or an interposer 101 on which a decoupling capacitor 102 as shown in FIG. 24 is mounted is connected to the electrode 75d of the semiconductor element 70d. It is also possible to do.

Next, a sixth configuration example will be described.
FIG. 27 is a schematic cross-sectional view of a sixth configuration example of the semiconductor device.
A semiconductor device 60e shown in FIG. 27 has a capacitance in which a dielectric layer 86 is sandwiched between a plate-like wiring 84 connected to VDD and a plate-like wiring 85 connected to GND in a wiring structure 80a in a package substrate 80e. Is formed. The wirings 84 and 85 are electrically connected to predetermined bumps 71 of the semiconductor element 70. The package substrate 80e is a build-up substrate, and the wirings 84 and 85 can be formed in a predetermined layer like the other wirings, and the dielectric layer 86 is a wiring 84 made of the substrate material of the package substrate 80e. , 85 can be used as they are.

  Here, a decoupling capacitor 76 is connected to the semiconductor element 70 mounted on the package substrate 80e through an electrode 75. Such a semiconductor device 60e can also stabilize the operation of the semiconductor element 70.

Such a package substrate 80e can be used in place of the package substrate 80 of the semiconductor devices 60a, 60b, 60c, and 60d shown in FIGS.
(Appendix 1) a semiconductor substrate having a transistor formed on one main surface side;
A wiring layer provided on the one main surface side and provided with a wiring electrically connected to the transistor;
An electrode that is electrically connected to the wiring and that extends from the one main surface side toward the other main surface side of the semiconductor substrate;
A semiconductor device comprising:

(Additional remark 2) The end surface of the said electrode has exposed to the said other main surface, The semiconductor element of Additional remark 1 characterized by the above-mentioned.
(Additional remark 3) The semiconductor element of Additional remark 2 characterized by the above-mentioned. The capacitive element arrange | positioned at the said other main surface side is electrically connected to the said electrode.

(Supplementary Note 4) A semiconductor substrate having a transistor formed on one main surface side, a wiring layer provided on the one main surface side and provided with a wiring electrically connected to the transistor, and an electrical connection to the wiring Connected to the semiconductor substrate, an electrode extending from the one main surface side toward the other main surface side, and a semiconductor element,
A circuit board on which the semiconductor element is mounted using a terminal provided on the wiring layer side;
A semiconductor device comprising:

(Supplementary Note 5) A first metal member formed on the other main surface and electrically connected to the electrode, a dielectric layer formed on the first metal member, and on the dielectric layer A second metal member formed,
The first metal member is electrically connected to the electrode to which a high voltage is applied, and the second metal member is electrically connected to a wiring to which a low voltage is applied to the circuit board. The semiconductor device according to appendix 4, which is characterized.

  (Additional remark 6) The semiconductor device of Additional remark 4 or 5 characterized by the several capacitive element disperse | distributing and arrange | positioning around the said semiconductor element on the mounting surface side of the said semiconductor element of the said circuit board.

  (Additional remark 7) It has the capacity | capacitance comprised by the wiring and board | substrate material which opposes in the said circuit board, and was electrically connected to the said semiconductor element. The semiconductor device described.

It is explanatory drawing of the structure principle of a semiconductor element. It is a principal part cross-sectional schematic diagram of a MOS transistor formation process. It is a principal part cross-sectional schematic diagram of a plug formation process. It is a principal part cross-sectional schematic diagram of a 1st interlayer insulation film formation process. It is a principal part cross-sectional schematic diagram of a wiring formation process. It is a principal part cross-sectional schematic diagram of a 1st resist pattern formation process. It is a principal part cross-sectional schematic diagram of a 1st etching process. It is a principal part cross-sectional schematic diagram of a resist removal process. It is a principal part cross-sectional schematic diagram of a 2nd resist pattern formation process. It is a principal part cross-sectional schematic diagram of a 2nd etching process. It is a principal part cross-sectional schematic diagram of a 3rd resist pattern formation process. It is a principal part cross-sectional schematic diagram of a 3rd etching process and a spacer film formation process. It is a principal part cross-sectional schematic diagram of a barrier metal and seed copper layer formation process. It is a principal part cross-sectional schematic diagram of a copper embedding process. It is a principal part cross-sectional schematic diagram of a CMP process. It is a principal part cross-sectional schematic diagram of a 2nd interlayer insulation film formation process. It is a cross-sectional schematic diagram of the first structural example of the semiconductor device (part 1). FIG. 3 is a schematic cross-sectional view (part 2) of the first configuration example of the semiconductor device. It is a plane schematic diagram of the semiconductor element in the first configuration example. It is a plane schematic diagram of the semiconductor device of the first configuration example. It is a cross-sectional schematic diagram of the 2nd structural example of a semiconductor device. It is a plane schematic diagram of the semiconductor element in the 2nd example of composition. It is a figure which shows the circuit structure of a capacity | capacitance array chip. It is a cross-sectional schematic diagram of the 3rd structural example of a semiconductor device. It is a cross-sectional schematic diagram of the 4th structural example of a semiconductor device. It is a cross-sectional schematic diagram of the 5th structural example of a semiconductor device. It is a cross-sectional schematic diagram of the 6th structural example of a semiconductor device. It is explanatory drawing of an example of the form which added the capacity | capacitance inside the semiconductor element. It is explanatory drawing of an example of the form which added the capacity | capacitance to the package board | substrate. It is a figure which shows an example of the voltage waveform inside a semiconductor element. It is FIG. (1) which shows the example of mounting of a decoupling capacitor. It is FIG. (2) which shows the example of mounting of a decoupling capacitor.

Explanation of symbols

1,70,70a, 70b, 70c, 70d Semiconductor element 2,72 Semiconductor substrate 3,21 STI
4, 27, 73 MOS transistor 5, 22 well 6, 23 Gate insulating film 7, 24 Gate electrode 8, 25 Side wall 9a, 26a Source region 9b, 26b Drain region 10, 33, 84, 85 Wiring 11, 30 Plug 12 , 74 Multi-layer wiring 13 Power terminal 14 Signal terminal 15, 49, 75, 75a, 75b, 75c, 75d Electrode 16 Insulating film 20 Silicon substrate 28 Cover film 29, 32, 51 Interlayer insulating film 31, 34, 50 Stopper film 33a, 46 Barrier metal 35, 38, 41, 43, 44 Resist 36, 40, 42 Film thickness control layer 37 Antireflection film 39, 39a, 39b Opening 45 Spacer film 47 Seed copper layer 48 Copper layer 60, 60a, 60b, 60c , 60d, 60e Semiconductor device 71, 81, 92, 100 Bump 74 , 80a, 101a Wiring structure 76, 83, 102 Decoupling capacitor 77, 82, 91 Pad 78 Well tap 80, 80e Package substrate 86, 111 Dielectric layer 90 Capacitance array chip 93 Underfill material 101 Interposer 110 First metal member 112 Second metal member

Claims (5)

A semiconductor substrate having a transistor formed on one main surface side;
A wiring layer provided on the one main surface side and provided with a wiring electrically connected to the transistor;
An electrode that is electrically connected to the wiring and that extends from the one main surface side toward the other main surface side of the semiconductor substrate;
A semiconductor device comprising:   The semiconductor element according to claim 1, wherein an end face of the electrode is exposed on the other main surface.   The semiconductor element according to claim 2, wherein a capacitive element disposed on the other main surface side is electrically connected to the electrode. A semiconductor substrate having a transistor formed on one main surface side, a wiring layer provided on the one main surface side and provided with a wiring electrically connected to the transistor, and electrically connected to the wiring A semiconductor element having, on the semiconductor substrate, an electrode extending from the one main surface side toward the other main surface side, and
A circuit board on which the semiconductor element is mounted using a terminal provided on the wiring layer side;
A semiconductor device comprising:   5. The semiconductor device according to claim 4, wherein a plurality of capacitive elements are distributed and arranged around the semiconductor element on the mounting surface side of the semiconductor element of the circuit board.

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