JP2008186976A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid an operational malfunction while eliminating an increase in parasitic capacitance even if a short circuit takes place due to a step on the upper surface of an interlayer insulating film formed between a memory region and a logic region. <P>SOLUTION: A semiconductor device comprises a memory circuit region M having a bit line 2A and a dummy bit line 2D, and a semiconductor substrate having a peripheral circuit region L adjacent to the memory circuit region M formed thereon. The memory circuit region M has a dummy cell region D in a region adjacent to the peripheral circuit region L. The dummy bit line 2D, a cell plate 4 formed under the dummy bit line 2D, and a conductive plate contact 6 for electrically connecting the cell plate 4 and the dummy bit line 2D are formed in the dummy cell region D. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a memory unit having a so-called CUB (Capacitor Under Bit-line) structure in which a capacitor is provided below a bit line and a manufacturing method thereof.

  In recent years, there has been an increasing demand for processing large amounts of data centered on images at high speed. For example, a DRAM-embedded LSI (Large Scale Integrated) circuit with a built-in DRAM (Dynamic Random Access Memory) can widen the data bus width between the memory unit and the logic unit, and is good at high-speed and large-volume data processing. To do. Furthermore, unlike when a packaged memory part is added (externally attached) to the logic part, the load capacity and load resistance between the packages are extremely small, and low power consumption can be achieved. It is expected as a solution to the demand for processing.

  Hereinafter, a conventional DRAM device having a CUB structure will be described with reference to the drawings.

  5 to 8 are cross-sectional views showing a manufacturing process of a DRAM-embedded semiconductor device having a CUB structure according to a first conventional example (see, for example, Non-Patent Document 1).

  In FIG. 5, a DRAM cell transistor 130 and a capacitor (storage capacitor) 140 are formed in the DRAM region 120 of the semiconductor substrate 101 partitioned into the DRAM region 120 and the logic region 121 by the semiconductor element isolation region 102. The logic region 121 shows a state in which a logic transistor 131 is formed. The DRAM cell transistor 130 includes a source / drain diffusion layer 104 and a gate electrode 106, and the logic transistor 131 includes a source / drain diffusion layer 103 and a gate electrode 105.

  A first interlayer insulating film 107 and a second interlayer insulating film 111 are sequentially formed on the DRAM cell transistor 130 and the logic transistor 131. Contact plugs 109 and 110 connected to the source / drain diffusion layer 104 are provided in the DRAM region 120 of the first interlayer insulating film 107, respectively. Further, contact plugs 108 connected to the source / drain diffusion layer 103 are provided in the logic region 121 of the first interlayer insulating film 107.

  The capacitor 140 formed in the DRAM region 120 includes a storage electrode 112, a capacitor insulating film 113, and a plate electrode 117. Specifically, the storage electrode 112 is formed in the second interlayer insulating film 111 so as to cover the bottom surface and the wall surface of the opening 111a that penetrates in the direction perpendicular to the substrate surface and exposes the contact plug 109. Yes. The capacitor insulating film 113 is formed over the entire surface of the second interlayer insulating film 111 including the storage electrode 112 formed in the opening 111a, and the plate electrode 117 made of titanium nitride (TiN) is formed on the capacitor insulating film 113. Formed on the entire surface.

  As shown in FIG. 5, by using the first resist pattern 114 formed by lithography as a mask, the plate electrode 117 and the capacitor insulating film 113 are patterned to be included in the DRAM region 120 in the plate electrode 117 and the capacitor insulating film 113. A first opening 117a for forming a bit line contact is formed in the portion to be formed. At the same time, a second opening 117b is formed in a portion of the plate electrode 117 and the capacitor insulating film 113 included in the logic region 121.

  Next, as shown in FIG. 6, after removing the first resist pattern 114, a third interlayer insulating film 119 is deposited on the second interlayer insulating film 111 and the plate electrode 117. Subsequently, the upper surface of the deposited third interlayer insulating film 119 is planarized by a chemical mechanical polishing (CMP) method. Thereafter, a second resist pattern 122 for forming a contact plug is formed on the third interlayer insulating film 119.

  Next, as shown in FIG. 7, by etching the third interlayer insulating film 119 using the second resist pattern 122 as a mask, the first through hole 119 a reaching the plate electrode 117 is formed in the DRAM region 120. Form. The third interlayer insulating film 119 included in the first opening 117a and the second opening 117b and the second interlayer insulating film 111 below the second interlayer insulating film 111 are in contact with the contact plug 110. A third through hole 119c that contacts the hole 119b and the contact plug 105 is formed. Thereafter, a metal film is embedded in each of the through holes 119a to 119c, thereby forming a plate contact plug 136, a bit line contact plug 137, and a logic part contact plug 138, respectively. Subsequently, metal wirings 123 that are in contact with the contact plugs 136 to 138 are selectively formed on the third interlayer insulating film 119.

  However, in the method of manufacturing the DRAM-embedded semiconductor device according to the first conventional example, when the third interlayer insulating film 119 is planarized by CMP in the step shown in FIG. The upper surface of the DRAM region 120 is higher than the upper surface of the logic region 121. For this reason, in the third interlayer insulating film 119, the CMP polishing rate in the portion of the DRAM region 120 adjacent to the logic region 121 becomes larger than the polishing rate of the logic region 121. That is, as shown in FIG. 8, a situation occurs in which part of the plate electrode 117 is exposed from the third interlayer insulating film 119 in the DRAM region 120. If the metal wiring 123 shown in FIG. 8 is formed in such a state, the metal wiring 123 and the plate electrode 117 are short-circuited, resulting in a malfunction in the operation of the semiconductor device.

  Next, a DRAM device as a second conventional example having a so-called COB (Capacitor Over Bit-line) structure in which a capacitor (storage capacitor) is formed above a bit line will be described with reference to the drawings.

  9 and 10 are cross-sectional views showing a manufacturing process of a DRAM-embedded semiconductor device having a COB structure according to a second conventional example (see, for example, Patent Document 1).

  In FIG. 9, the DRAM cell transistor 200 and the capacitor 210 are formed in the DRAM region 190 of the semiconductor substrate 151 divided into the DRAM region 190 and the logic region 191 by the element isolation region 152, and the logic region 191 of the semiconductor substrate 151 is formed in the logic region 191. A state in which the logic transistor 201 is formed is shown. The DRAM cell transistor 200 includes a source / drain diffusion layer 154 and a gate electrode 156, and the logic transistor 201 includes a source / drain diffusion layer 153 and a gate electrode 155.

  On the DRAM cell transistor 200 and the logic transistor 201, a first interlayer insulating film 157, a second interlayer insulating film 163, and a third interlayer insulating film 165 are sequentially formed. Contact plugs 159 and 160 connected to the source / drain diffusion layer 154 are formed in the DRAM region 190 of the first interlayer insulating film 157, respectively. Further, contact plugs 158 connected to the source / drain diffusion layers 153 are formed in the logic region 191 of the first interlayer insulating film 157, respectively.

  A contact pad 161 is formed on each contact plug 158, 159 of the first interlayer insulating film 157, and a bit line 162 is formed on the contact plug 160.

  The capacitor 210 formed in the DRAM region 190 includes a storage electrode 166, a capacitor insulating film 167, and a plate electrode 175. Specifically, the storage electrode 166 is formed to cover the bottom surface and the wall surface of the opening 165a penetrating in the direction perpendicular to the substrate surface in the third interlayer insulating film 165. The capacitor insulating film 167 is formed over the entire surface of the third interlayer insulating film 165 including the storage electrode 166 formed in the opening 165a, and the plate electrode 175 is formed over the entire surface of the capacitor insulating film 167.

  A storage electrode contact 164 is formed between the contact pad 161 in the second interlayer insulating film 163 and the bottom of the storage electrode 166.

  As shown in FIG. 9, by using the resist pattern 171 formed by the lithography method as a mask, the TiN film for forming the plate electrode and the capacitor insulating film 167 are patterned, so that the plate electrode 175 made of TiN is formed in the DRAM region 190. Form. At the same time, a dummy plate 176 made of TiN is formed in the logic region 191 so that an opening 176a is formed in the upper portion of each contact pad 161.

  Next, as shown in FIG. 10, after removing the resist pattern 171, a fourth interlayer insulating film 177 is deposited on the third interlayer insulating film 165 including the plate electrode 175 and the dummy plate 176. Thereafter, a plate contact hole 177 a exposing the plate electrode 175 is formed in the DRAM region 190. At the same time, in the logic region 191, contact holes reaching the contact pads 161 through the fourth interlayer insulating film 177, the third interlayer insulating film 165, and the second interlayer insulating film 163 in the opening 176 a. 177b is formed. Thereafter, a plate contact plug 180 and a logic part contact plug 179 are formed by embedding metal in the plate contact hole 177a and the contact hole 177b, respectively. Subsequently, a metal wiring 182 is selectively formed on the fourth interlayer insulating film 177 so as to be in contact with the plate contact plug 180 and the logic part contact plug 179, respectively.

As described above, in the method of manufacturing the DRAM-embedded semiconductor device according to the second conventional example, since the dummy plate 176 made of the same material as the plate electrode 175 is formed in the logic region 191, the DRAM region 190 and the logic region 191 are formed. The step due to the film thickness of the plate electrode 175 does not occur. For this reason, when the fourth interlayer insulating film 177 is planarized by CMP, a difference in polishing rate between the DRAM region 190 and the logic region 191 can be reduced.
JP 2003-31690 A VLSI Symp. Tech. Dig., P. 29, 2001 (M. Takeuchi et al.)

  However, the DRAM-embedded semiconductor device manufacturing method according to the second conventional example has a problem that the parasitic capacitance caused by the dummy plate 176 formed in the logic region 191 increases. In particular, it is a fatal injury for a request for ultra-high speed for a DRAM device as a memory device replacing an SRAM (Static Random Access Memory) device. Therefore, it is extremely difficult to adopt a configuration in which the dummy plate 176 is formed in the logic region 191 when it is necessary to satisfy the requirement for ultra high speed.

  In view of the above-described conventional problems, the present invention operates without increasing parasitic capacitance even if a short circuit occurs due to a step on the upper surface of an interlayer insulating film formed between a memory region and a logic region. The purpose is to prevent problems.

  To achieve the above object, according to the present invention, a dummy bit line is connected to a plate contact connected to a cell plate in a dummy cell region adjacent to a peripheral circuit (logic circuit) region in a memory circuit region. The structure is such that it is not connected to the semiconductor substrate, that is, the source and drain of the transistor.

  Specifically, a semiconductor device according to the present invention is directed to a semiconductor device including a semiconductor substrate having a memory circuit region having a bit line and a dummy bit line and a peripheral circuit region adjacent to the memory circuit region. The circuit area has a dummy cell area adjacent to the peripheral circuit area. The dummy cell area includes a dummy bit line, a cell plate formed below the dummy bit line, the cell plate and the dummy bit line. And a plate contact having electrical conductivity for electrically connecting the two.

  According to the semiconductor device of the present invention, the dummy cell region has a dummy bit line, a cell plate formed below the dummy bit line, and conductivity for electrically connecting the cell plate and the dummy bit line. A plate contact is formed. That is, since the potential of the dummy bit line formed in the peripheral portion of the memory circuit region is the same as that of the cell plate, a step is generated between the memory circuit region and the peripheral path region, and the cell is different due to the difference in CMP rate. Even when the plate is exposed and the dummy bit line and the cell plate are short-circuited, there is no problem in the operation in the memory circuit area. As a result, the manufacturing yield can be improved. Unlike the second conventional example, the semiconductor device of the present invention does not have a dummy cell plate remaining in the peripheral circuit region, so that a problem caused by parasitic capacitance does not occur.

  In the semiconductor device of the present invention, the dummy cell region has a capacitor insulating film formed in contact with the lower side of the cell plate and a storage electrode formed in contact with the lower side of the capacitor insulating film. preferable.

  In the semiconductor device of the present invention, in the memory circuit region, the storage electrode, the capacitor insulating film, and the cell plate constitute a capacitor, and the capacitor is preferably provided below the bit line and the dummy bit line.

  Preferably, the semiconductor device of the present invention further includes an interlayer insulating film formed on the semiconductor substrate, and the storage electrode is formed so as to cover the wall surface and bottom surface of the recess formed in the interlayer insulating film.

  In the semiconductor device of the present invention, a bit line contact for electrically connecting the bit line and the semiconductor substrate is formed in the memory circuit region excluding the dummy cell region. In the memory circuit region, the bit line contact and the plate contact are formed. Are preferably arranged periodically.

  In the case where the semiconductor device of the present invention includes an interlayer insulating film formed on a semiconductor substrate, a plurality of storage electrodes are formed in the memory circuit region, and each storage electrode is formed on the interlayer insulating film. It is preferable that the storage electrode wirings are connected to each other.

  In this case, the plate contact preferably penetrates the cell plate and the capacitor insulating film and is in contact with the storage electrode wiring. In this way, even if the capacitance insulating film formed between the storage electrode and the cell plate causes a dielectric breakdown in the dummy cell region, the storage electrode and the cell plate are held at the same potential by the storage electrode wiring. As a result, the transient current does not flow. For this reason, the potential of the cell plate is stabilized, and malfunctions occurring in the memory circuit can be prevented.

  In the method of manufacturing a semiconductor device according to the present invention, a first interlayer insulating film having a plurality of recesses is formed on a semiconductor substrate partitioned into a memory circuit region and a peripheral circuit region adjacent to each other. A step of forming a storage electrode on a wall surface and a bottom surface of each recess in the first interlayer insulating film, a step of forming a storage electrode wiring on the upper surface of the first interlayer insulating film, and the storage electrode and the storage electrode Forming a capacitor insulating film on the wiring; forming a cell plate on the capacitor insulating film; forming a second interlayer insulating film on the cell plate; and a peripheral circuit in the memory circuit region In the dummy cell region adjacent to the region, a conductive pre-process is formed so as to penetrate the second interlayer insulating film, the cell plate, and the capacitor insulating film and be in contact with the storage electrode wiring. Forming bets contacts, on the second interlayer insulating film in the dummy cell region, characterized in that it comprises a step of forming a dummy bit line in contact with the plate contact.

  According to the method for manufacturing a semiconductor device of the present invention, a dummy bit line, a cell plate formed below the dummy bit line in the dummy cell region, and the electrical connection between the cell plate and the dummy bit line are electrically connected. And a plate contact having. As a result, the potential of the dummy bit line formed at the periphery of the memory circuit region is the same as that of the cell plate. For this reason, even if a step occurs between the memory circuit area and the peripheral path area and the cell plate is exposed due to the difference in CMP rate and the dummy bit line and the cell plate are short-circuited, the memory circuit area There is no problem in the operation of As a result, the manufacturing yield can be improved. In addition, in the dummy cell region, the storage electrode and the cell plate are held at the same potential by the storage electrode wiring even if the capacitance insulating film formed between the storage electrode and the cell plate causes dielectric breakdown. As a result, since a transient current does not flow, the potential of the cell plate is stabilized, and the malfunction of the operation of the memory circuit is less likely to occur.

  The method for manufacturing a semiconductor device of the present invention further includes a step of removing a portion included in the peripheral circuit region in the cell plate between the step of forming the cell plate and the step of forming the second interlayer insulating film. Preferably it is. In this way, since the dummy cell plate does not remain in the peripheral circuit region, there is no problem caused by the parasitic capacitance.

  In the method for manufacturing a semiconductor device of the present invention, in the step of forming the storage electrode wiring, the storage electrode wiring in the dummy cell region is preferably formed so as to connect the storage electrodes to each other.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to prevent problems caused by the wiring adjacent to the peripheral circuit region coming into contact with the cell plate, so that the processing margin is increased and the yield can be improved.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a planar configuration of a DRAM-embedded semiconductor device according to the first embodiment of the present invention, and FIG. 2 shows a cross-sectional configuration taken along line II-II in FIG.

  As shown in FIGS. 1 and 2, a semiconductor substrate 11 made of, for example, P-type silicon includes a memory circuit region M and a logic circuit adjacent to the memory circuit region M by an element isolation region (STI: Shallow Trench Isolation) 12. It is partitioned into a peripheral circuit region L including it.

  The memory circuit region M includes a memory cell region A in which memory cells that actually operate are arranged, and a region sandwiched between the memory cell region A and the peripheral circuit region L, that is, a dummy cell region D that is a terminal portion of the memory cell array. It is divided into and.

  As shown in FIG. 1, in the dummy cell region D, a dummy pattern (dummy storage electrode) 1D of a storage electrode (lower electrode) constituting a capacitor is disposed, and a dummy bit line 2D is disposed above the dummy storage electrode 1D. Is formed. In the memory cell region A, a plurality of storage electrodes 1A each constituting a capacitor are arranged in an array, and a plurality of bit lines 2A are formed on the storage electrodes 1A.

  In the memory circuit region M, a cell plate (upper electrode) 4 is formed so as to cover the dummy storage electrode 1D and the storage electrode 1A.

  As shown in FIGS. 1 and 2, in the memory cell region A, a bit for electrically connecting the bit line 2 </ b> A and the semiconductor substrate 11 (source / drain diffusion layer 14) through an opening formed in the cell plate 4. A line contact 5 is formed.

  As a feature of the first embodiment, no opening is formed in the cell plate 4 below the dummy bit line 2D, and the dummy bit line 2D and the cell plate 4 have a plate contact 6 instead of the bit line contact 5. Are electrically connected.

  Here, a cross-sectional configuration will be described with reference to FIG.

  As shown in FIG. 2, a source / drain diffusion layer 14 is formed in the memory cell region A of the semiconductor substrate 11, and a dummy diffusion layer 14 </ b> D is formed in the dummy cell region D. A source / drain diffusion layer 13 is formed in the peripheral circuit region L of the semiconductor substrate 11, and a logic transistor 28 is formed by the gate electrode 15 formed on the semiconductor substrate 11.

  A first interlayer insulating film 17 made of, for example, silicon oxide is formed on the entire surface of the semiconductor substrate 11, and a memory cell transistor (not shown) is formed in the memory cell region A of the first interlayer insulating film 17. The storage portion contact plug 19 connected to the source / drain diffusion layer 14 is formed. A dummy contact plug 19D connected to the dummy diffusion layer 14D is formed in the dummy cell region D of the first interlayer insulating film 17. Logic portion contact plugs 18 connected to the source / drain diffusion layers 13 are formed in the peripheral circuit region L of the first interlayer insulating film 17, respectively.

  A second interlayer insulating film 21 is formed on the first interlayer insulating film 17, and a cell plate 4 is formed in the memory circuit region M on the second interlayer insulating film 21. . Here, the cell plate 4 is not formed in the peripheral circuit region L.

  A third interlayer insulating film 27 is formed on the second interlayer insulating film 21 including the cell plate 4, and the memory cell region A of the third interlayer insulating film 27 and the second interlayer insulating film 21 is formed. The bit line contact 5 is formed so as to be connected to the storage unit contact plug 19. A plate contact 6 is formed in the dummy cell region D of the third interlayer insulating film 27 so as to be connected to the cell plate 4. Further, in the peripheral circuit region L of the third interlayer insulating film 27 and the second interlayer insulating film 21, the logic part contact 31 is formed so as to be connected to the logic part contact plug 18.

  According to the first embodiment, when the bit line contact 5 and the plate contact 6 are formed, even if the film thickness of the dummy cell region D in the third interlayer insulating film 27 is relatively large, the plate contact 6 has a smaller aspect ratio than the bit line contact 5, the height of the stepped portion formed between the dummy cell region D and the peripheral circuit region L of the second interlayer insulating film 21 is not more than the height of the capacitor. For example, etching by CMP or the like is not insufficient.

  On the contrary, when the film thickness of the third interlayer insulating film 27 and the second interlayer insulating film 21 is extremely thin in the dummy cell region D, the plate contact 6 is excessively overetched. Even if the bit line 2D comes into contact with the dummy contact plug 19D, the potential of the dummy bit line 2D and the potential of the cell plate 4 (plate potential) are the same potential, so no particular problem occurs.

  Even if the dummy bit line 2D and the cell plate 4 are in contact with each other, the memory circuit (DRAM) operates normally because they have the same potential.

  In addition, according to the first embodiment, normally, the dummy bit line 2D and the bit line contact wiring provided individually can be used together, so that the area of the memory circuit region M can be reduced.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  3 and 4 show cross-sectional structures in the order of steps of a method for manufacturing a DRAM-embedded semiconductor device according to the second embodiment of the present invention. 3 and 4, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals. Here, a main part including a dummy cell region D including a capacitor and a peripheral circuit region L adjacent to the dummy cell region D is illustrated.

  First, as shown in FIG. 3, an element isolation region (STI) 12 is selectively formed in a P-type semiconductor substrate 11, and a gate insulating film 15 a is formed in a region surrounded by the element isolation region 12 on the semiconductor substrate 11. And the gate electrode 16 with the gate insulating film 16a interposed therebetween, respectively. Thereafter, source / drain diffusion layers 13 and 14 are formed on the semiconductor substrate 11 using the gate electrodes 15 and 16 as masks. As a result, a memory cell transistor is formed in the dummy cell region D, and a logic transistor is formed in the peripheral circuit region L.

  Subsequently, a first interlayer insulating film 17 is deposited on the semiconductor substrate 11 so as to cover the gate electrodes 15 and 16 by chemical vapor deposition (CVD). After that, each through hole is formed in the first interlayer insulating film 17 by lithography and etching, and the logic portion contact plug reaching the source / drain diffusion layer 13 of the logic transistor so as to fill each formed through hole. 18 and a storage portion contact plug 19 reaching the source / drain diffusion layer 14 of the memory cell transistor are formed.

  Subsequently, a second interlayer insulating film 21 is deposited on the first interlayer insulating film 17, and the deposited second interlayer insulating film 21 is in contact with each storage unit contact plug 19 and has a depth of 500 nm. The opening 21a is formed as a recess.

  Subsequently, a first conductive film made of titanium nitride (TiN) having a thickness of 20 nm is deposited on the second interlayer insulating film 21 by the CVD method so as to cover the bottom surface and the wall surface of the opening 21a. Thereafter, a resist pattern (not shown) is formed by lithography to cover the inside of the opening 21a and the dummy bit line formation region in the first conductive film, and the first conductive film is formed using the formed resist pattern as a mask. By etching back, the storage electrode 22 made of TiN is formed on the bottom surface and the wall surface of the opening 21a. At the same time, the storage electrode wiring 23 that electrically connects the storage electrodes 22 is formed on the second interlayer insulating film 21. Note that the storage electrode 22 and the storage electrode wiring 23 may not be formed in one step but may be formed in separate steps.

Subsequently, a capacitor insulating film 24 made of hafnium oxide (HfO ₂ ) having a thickness of 8 nm is deposited on the storage electrode 22 and the storage electrode wiring 23 by a CVD method or a sputtering method, and then again by the CVD method. A second conductive film made of TiN having a thickness of 50 nm is formed on the capacitor insulating film 24. Subsequently, the second conductive film, the capacitor insulating film 24, and the storage electrode wiring 23 deposited in the peripheral circuit region L are removed by etching. Thereby, the cell plate 25 made of TiN is selectively formed in the dummy cell region D and the memory cell region A (not shown).

  Next, as shown in FIG. 4, a third interlayer insulating film 27 is formed on the second interlayer insulating film 21 and the cell plate 25. Subsequently, a plate contact hole 27 a is formed in the dummy cell region D of the third interlayer insulating film 27, and a logic part contact hole 27 b is formed in the peripheral circuit region L of the third interlayer insulating film 27. Here, the plate contact hole 27 a is formed so as to penetrate the cell plate 25 and to be connected to at least the storage electrode wiring 23.

  Subsequently, a metal film made of tungsten (W) or the like is embedded in each contact hole 27a, 27b by CVD or sputtering, thereby providing a logic part contact 31 having a depth of 700 nm and a plate contact having a depth of 150 nm. 30. Thereafter, a dummy bit line 2D and a metal wiring 32 are selectively formed on the third interlayer insulating film 27 so as to be in contact with the contact plugs 30 and 31.

  As described above, according to the second embodiment, in the dummy cell region D of the memory circuit region M, the storage electrode 22 and the cell plate are held at the same potential. For this reason, even if dielectric breakdown occurs between the storage electrode 22 and the cell plate 25 in the dummy cell region D due to processing defects in the dummy cell region D, which is the terminal portion of the memory cell array, a transient occurs from the cell plate 25 to the storage electrode 22. Current does not flow. For this reason, since the cell plate 25 can maintain a stable potential, it is possible to prevent a characteristic failure in the memory circuit (DRAM).

  The semiconductor device and the manufacturing method thereof according to the present invention can prevent a problem caused by a wiring adjacent to the peripheral circuit region coming into contact with the cell plate, and particularly includes a memory unit having a CUB structure in which a capacitor is provided below the bit line. It is useful for semiconductor devices and manufacturing methods thereof.

1 is a plan view showing a DRAM-embedded semiconductor device according to a first embodiment of the present invention. It is sectional drawing in the II-II line of FIG. It is sectional drawing which shows 1 process of the manufacturing method of the DRAM embedded type semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the DRAM embedded type semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows 1 process of the manufacturing method of the DRAM mixed type | mold semiconductor device which has a CUB structure based on a 1st prior art example. It is sectional drawing which shows 1 process of the manufacturing method of the DRAM mixed type | mold semiconductor device which has a CUB structure based on a 1st prior art example. It is sectional drawing which shows 1 process of the manufacturing method of the DRAM mixed type | mold semiconductor device which has a CUB structure based on a 1st prior art example. FIG. 6 is a schematic cross-sectional view showing a defect in a DRAM-embedded semiconductor device according to a first conventional example. It is sectional drawing which shows 1 process of the manufacturing method of the DRAM embedded type semiconductor device which has the COB structure concerning a 2nd prior art example. It is sectional drawing which shows 1 process of the manufacturing method of the DRAM embedded type semiconductor device which has the COB structure concerning a 2nd prior art example.

Explanation of symbols

M memory circuit region A memory cell region D dummy cell region L peripheral circuit region 1A storage electrode 1D dummy storage electrode 2A bit line 2D dummy bit line 4 cell plate 5 bit line contact 6 plate contact 11 semiconductor substrate 12 element isolation region (STI)
13 Source / drain diffusion layer 14 Source / drain diffusion layer 14D Dummy diffusion layer 15 Gate electrode 15a Gate insulating film 16 Gate electrode 16a Gate insulating film 17 First interlayer insulating film 18 Logic portion contact plug 19 Storage portion contact plug 19D Dummy contact plug 21 Second interlayer insulating film 21a Opening 22 Storage electrode 23 Storage electrode wiring 24 Capacitor insulating film 25 Cell plate 27 Third interlayer insulating film 27a Plate contact hole 27b Logic part contact hole 30 Plate contact 31 Logic part contact 32 Metal wiring

Claims (10)

A memory circuit area having a bit line and a dummy bit line;
A semiconductor device comprising a semiconductor substrate having a memory circuit region and a peripheral circuit region adjacent thereto,
The memory circuit area has a dummy cell area in an area adjacent to the peripheral circuit area,
In the dummy cell region, the dummy bit line, a cell plate formed below the dummy bit line, and a conductive plate contact for electrically connecting the cell plate and the dummy bit line are formed. A semiconductor device which is characterized by being made.   The dummy cell region includes a capacitor insulating film formed in contact with the lower side of the cell plate, and a storage electrode formed in contact with the lower side of the capacitor insulating film. 2. The semiconductor device according to 1. In the memory circuit region, the storage electrode, the capacitive insulating film, and the cell plate constitute a capacitor,
The semiconductor device according to claim 2, wherein the capacitor is provided below the bit line and the dummy bit line. Further comprising an interlayer insulating film formed on the semiconductor substrate,
The semiconductor device according to claim 2, wherein the storage electrode is formed so as to cover a wall surface and a bottom surface of a recess formed in the interlayer insulating film. A bit line contact for electrically connecting the bit line and the semiconductor substrate is formed in the memory circuit area excluding the dummy cell area,
5. The semiconductor device according to claim 1, wherein the bit line contact and the plate contact are periodically arranged in the memory circuit region. 6. In the memory circuit region, a plurality of the storage electrodes are formed,
6. The semiconductor device according to claim 4, wherein the storage electrodes are connected to each other by a storage electrode wiring formed on the interlayer insulating film.   The semiconductor device according to claim 6, wherein the plate contact penetrates the cell plate and the capacitor insulating film and is in contact with the storage electrode wiring. Forming a first interlayer insulating film on the semiconductor substrate partitioned into a memory circuit region and a peripheral circuit region adjacent to each other and having a plurality of recesses in the memory circuit region;
Forming a storage electrode on a wall surface and a bottom surface of each recess in the first interlayer insulating film;
Forming a storage electrode wiring on the upper surface of the first interlayer insulating film;
Forming a capacitive insulating film on the storage electrode and the storage electrode wiring;
Forming a cell plate on the capacitive insulating film;
Forming a second interlayer insulating film on the cell plate;
In the dummy cell region adjacent to the peripheral circuit region in the memory circuit region, a conductive plate contact is provided so as to penetrate the second interlayer insulating film, the cell plate, and the capacitor insulating film and to be in contact with the storage electrode wiring. Forming, and
Forming a dummy bit line on the second interlayer insulating film in the dummy cell region so as to be in contact with the plate contact. Between the step of forming the cell plate and the step of forming the second interlayer insulating film,
9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of removing a portion included in the peripheral circuit region in the cell plate.   10. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the storage electrode wiring, the storage electrode wiring in the dummy cell region is formed so as to connect the storage electrodes to each other. .

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