JP2009087181A - Analog function block design system and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve efficiency in designing an analog function block from the viewpoint of analog layout. <P>SOLUTION: A design object circuit is represented by a from-to list format 301 on the basis of netlist information of the circuit to be designed. In the from-to list format 301, the layout for each MOS transistor is represented by adding a symbol "s" or "d" indicating a source or drain, respectively, on the left side of transistor type names A and B. EACH transistor can be connected with each other through the sources s and drains d. The from-to list format 301 is converted into a corresponding symbol figure format layout 302 by use of a model library 304. In the symbol figure format layout 302, the transistors and the wirings are arranged in meshes for device arrangement and wiring. The data is edited in the form of the symbol figure format layout 302 and output in the form of a layout 303 such as a GDS format or the like. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a system for designing an analog functional block in a semiconductor integrated circuit such as an LSI (Large Scale Integrated Circuit). Here, the analog functional block is not only a functional block having an external analog signal interface represented by an operational amplifier, an analog digital (AD) converter, or a digital analog (DA) converter, but also an external digital signal interface such as an inverter or a flip-flop. Even if it has, the internal operation is analog, and the functional block design includes those that require analog function design or analog circuit simulation.

  Conventionally, when designing an analog functional block represented by an operational amplifier or an AD / DA converter, a transistor circuit diagram netlist is first created, a simulation check is performed with an analog circuit simulator, and then a transistor circuit is displayed with an LSI pattern editor. After that, the resistance and the capacitance are extracted and then returned to the analog circuit simulator to perform the final confirmation circuit simulation.

Here, even if a certain circuit configuration is determined as an analog function in the design process, the effective W of the local MOS transistor (a parameter corresponding to the transistor driving capability and the transistor pattern width) is frequently generated. It is a performance change or adjustment according to the expansion request.
This is because even if it is logically one MOS transistor on the circuit diagram, it is necessary to expand the transistor in parallel according to the performance requirement, effectively increase W, improve the driving capability, and adjust the performance. It depends on what happens.

  There are two types of parallel development of this type, parameter “F” and parameter “M”. F is an abbreviation of “Finger”, and is a parallel parameter for sharing a plurality of transistors and sharing a gate by wiring, and represents the number of gate divisions. As a result, the effective W is F times. M is an abbreviation of “Multiple”, and is a general parallel parameter in which a plurality of transistors are independently paralleled, and then the source, drain, and gate are shared by wiring, and represents the number of divided transistors. The effective W is M times.

  The target of the parameter M is a transistor group having W multiplied by F, and the parameters F and M can be combined. As a result, the effective W is F × M times. The method of specifying the increase in effective W by parameters F and M is general and effective in the analog circuit simulation stage at the initial stage of design, and F and M parameters can be normally set in a commercially available analog circuit simulator. is there.

  In particular, the parameter F has a model generation function in the circuit simulator because it is different in model from M that parallelizes a single transistor in order to share diffusion, and a very accurate simulation is performed by specifying the parameter F. A model is generated. That is, F is in a situation where model generation must be handled on the circuit simulator side. However, since it is necessary to perform a design including a two-dimensional spatial degree of freedom at the layout stage, the linkage between the F and M parameters and the layout is not obvious, and there are numerous combinations thereof.

  Here, since the layout related to F is diffusion sharing, there is not much freedom and it is uniquely determined to some extent. However, since M is a spatial combination of independent transistor groups, its layout flexibility is enormous. As a method for dealing with the layout of F and M, a processing method for realizing a layout in a programming language has been proposed. This is successful to some extent for F with a low degree of freedom, and at present, the layout generation of transistor groups related to F is often handled by language.

However, the parameter M has a large degree of freedom in space, and it is not easy to describe the spatial topology information including the wiring in the language, and there is a visualization problem that the topology cannot be understood even if other people see the program. Not accepted.
In addition, an operation of setting a parameter for a transistor on a transistor circuit diagram is very generally performed. However, as shown in Patent Document 1, it is usually a parameter setting for a single transistor or an operation, and is linked to a layout. It does not describe complicated parallel layout operations concerning F and M, especially M.

  A conventional layout editor in analog design is a pattern editor for manipulating data types (path, rectangle, boundary) shown in a standard format such as so-called GDS or OASYS. In this case, there is a problem that the design efficiency of an analog functional block that is increased in scale is not improved.

FIG. 35 is a diagram for explaining processing of a conventional analog functional block design system.
When designing an analog function block by a conventional analog function block design system, for example, if parameters F and M are designated from the operation unit on the circuit diagram of the MOS transistor 341 in FIG. Corresponding transistor circuit diagrams and layout diagrams (FIGS. 35B to 35D) are generated. As described above, F means a configuration of a transistor group whose gates are shared by diffusion sharing, M means a configuration of a transistor group obtained by parallelizing the group, and the processing result is developed as an internal model and is an analog circuit. Simulated with a simulator.

  Here, as a development of F, a large error occurs in accuracy when it is considered as a model in which single transistors 342a to 342f as shown in FIG. In other words, since the diffusion is shared, the numerical values such as capacity are not simply connected to the unit model. Therefore, the F development model has a built-in function in the circuit simulator, and as shown in FIG. 35 (c), an original transistor group (connected circuit of MOS transistors 343a and 343b equivalent to F = 3) model is displayed on the spot. It is more accurate to think that it is generated by

M is an independent parallelization of the F-expanded transistor group, which is also automatically expanded by the circuit simulator for simulation. These automatic deployment functions of F and M are functions that are usually provided in current commercially available analog circuit simulators, and there is no difference in interpretation.
However, at the stage where the layout as shown in FIG. 35 (d) is implemented, there is a problem due to the high degree of freedom especially with respect to M.

That is, in the case of F, since diffusion sharing is performed, the source and drain may be shared by arranging them in parallel in a one-dimensional manner like MOS transistors 344a to 344c and MOS transistors 344d to 344f, but in the case of M, transistors 344a to 344 may be shared. The 344c and the transistors 344d to 344f may be arranged in the X direction and connected by the wiring 345, or may be arranged in the Y direction and connected by the wiring 345.
Accordingly, in the case of M, since the degree of spatial freedom is large in layout, more detailed design control is required. In addition, the layout editor does not increase the work efficiency only by the function of operating a standard format such as the conventional GDS or OASYS. A symbolic layout editor that recognizes transistors is desired.

On the other hand, F is usually made into a library from a situation where the degree of freedom is limited. That is, a standard format pattern library such as GDS or OASYS with F = 1, 2, 3,... Is prepared for a certain transistor type, or a description for generating such patterns is often prepared. This is called a transistor library (including F expansion) and is distinguished from a library having a larger function.
Thus, there is a problem that the design efficiency of the analog function block is poor.

JP 2003-86705 A

An object of the present invention is to improve the efficiency of analog design from the viewpoint of analog layout in the design process of an analog functional block.
Another object of the present invention is to provide a program suitable for constructing an analog functional block design system using a computer.

  According to the present invention, storage means for storing array list data representing device arrays as characters, symbol graphic data representing the devices as symbol graphics, input means for inputting netlist information of the circuit to be designed, Display means for displaying at least a dialog window and a symbolic layout window; and an array list corresponding to the netlist information using the array list data stored in the storage means, and symbol graphic data stored in the storage means A symbol graphic format layout corresponding to the array list, and a layout processing means for displaying the array list and the symbol graphic format layout in a dialog window and a symbolic layout window. Temu is provided.

  The layout processing means generates an array list corresponding to the net list information using the array list data stored in the memory means, and uses a symbol graphic data stored in the storage means in a symbol graphic format corresponding to the array list. A layout is generated, and the array list and symbol graphic format layout are displayed in a dialog window and a symbolic layout window.

  Here, the device is a MOS transistor, a bipolar transistor, a capacitor, or a resistor, and the symbolic layout window includes a first mesh that defines the arrangement position of the device and a second mesh that defines the arrangement position of the wiring. At least two types of meshes are defined, and the layout processing means is configured to display the device and the wiring arranged in the symbolic layout window so as to be aligned with the first and second meshes, respectively. May be.

The dialog window displays an array list of basic model patterns corresponding to the net list information of the circuit to be designed, and the symbolic layout window displays a layout in a symbol graphic format corresponding to the array list of the basic model patterns. May be configured to be displayed.
In addition, the layout processing means performs a first development on a predetermined parameter with respect to the basic model pattern to generate an arrangement list of the first development model pattern; and an arrangement list of the first development model pattern. A layout generation unit that generates a layout in a corresponding symbol graphic format and displays the layout in the symbolic layout window may be provided.

  Further, the expansion means further performs a second expansion on a predetermined parameter for the first expansion model pattern to generate an array list of second expansion model patterns, and the layout generation means further includes the second expansion model pattern. A symbol graphic format layout corresponding to the model pattern arrangement list may be generated and displayed in the symbolic layout window.

In the display of the device in the dialog window, at least one character is associated with the device, and when the device is a MOS transistor, the existence direction of either the source or drain terminal is represented by at least one character. You may comprise so that it may describe on the one side of the character showing the said device.
In addition, the expansion unit includes at least one of a diffusion shared expansion unit that performs expansion using diffusion sharing at the time of expansion and a packing unit that performs packing when there is a gap between the devices that are laid out. May be.

Further, the circuit to be designed may have a bias circuit or a switch circuit whose function can be configured by at least one MOS transistor, and the layout processing means may be configured to parallelize the MOS transistors.
The circuit to be designed has a differential pair circuit, a current mirror circuit, or an inverter circuit that can be configured by at least two MOS transistors, and the layout processing means parallels the MOS transistors. It may be configured.

When the layout processing means displays an array list of basic model patterns corresponding to the net list information of the design target circuit, the layout information of the basic model patterns in the library and the net list of the design target circuit are displayed. You may comprise so that the arrangement | sequence list | wrist which matches with information may be displayed.
Further, it may be configured to include conversion means for converting circuit graphic data in GDS or OASYS format into layout data in a corresponding symbol graphic format.

According to the present invention, there is provided a program that causes a computer to function as any one of the analog functional block design systems.
The computer functions as any one of the analog functional block design systems by executing the program.

According to the analog functional block design system of the present invention, it is possible to improve the efficiency of analog design from the viewpoint of analog layout in the analog functional block design process.
The program according to the present invention can construct the analog functional block design system using a computer.

Hereinafter, an analog functional block design system and program according to embodiments of the present invention will be described with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals.
First, the outline of the embodiment of the present invention will be described. In the present embodiment, the following three processing functions are mainly provided in the analog function block design process in order to improve the efficiency of analog design from the viewpoint of analog layout. ing.

  First, instead of using a conventional pattern editor for manipulating data shown in standard formats such as GDS or OASYS, a symbolic layout editor that handles the abstraction of transistors is constructed to improve the efficiency of analog layout work. To do.

Next, as a second point, for the transistor parameters F and M already established in the circuit simulation world, a design mechanism linked with the symbolic layout editor is built to improve the efficiency of analog design work. For this purpose, a dialog window is introduced for the purpose of layout control, and the control of F and M, especially M, is addressed.
Finally, as a third point, in order to improve analog design efficiency, we will establish a design mechanism that actively reuses analog function blocks that have already been designed as a library.

  The first symbolic layout editor employs a method of abstracting device elements suitable for analog design and assigning the device elements to the first arrangement mesh. Since the wiring is naturally smaller in size than the transistor device, the second wiring mesh having a more finely spaced interval is assigned to the first arrangement mesh.

  As a result, a doubled symbolic mesh structure “duplex structure mesh” is established in which device element placement is handled in units of first placement meshes and wiring is handled in finer second wiring mesh units. . As a result, the handling of each transistor is standardized, so that handling of the transistor, that is, correction and modification, becomes extremely easy. According to the present invention, when a large-scale drivability transistor (that is, large-scale W) is required, it is easily deployed, and the large-scale W is constructed in basic units, so that standardization is easy. .

  The processing function for transmitting the second circuit parameters such as F and M to the symbolic layout editor is extremely important for improving the efficiency of analog design. In order to realize this, in this embodiment, M is a combination of X (the number of repetitions in the X direction), Y (the number of repetitions in the Y direction perpendicular to X), and Flip (inversion) on the dialog window. It is made to embody. In addition, in this embodiment, a mechanism that can specify X, Y, and Flip designation twice independently is realized.

  This is because the layout is performed in two dimensions, X and Y, so that it is versatile to enable X-direction expansion, Y-direction expansion, and two-stage expansion independently, as well as differential pairs and currents. This is because it is easy to deploy while maintaining the objectivity like a mirror, and it is possible to cope with a large-scale analog function block. Here, since F is diffusion sharing, diffusion is usually shared only by expansion in the X direction, so that it is handled only by expansion in the first stage. In other words, since F is one-dimensional, the degree of freedom is not so much, and the solution is determined almost uniquely (the degree of control in which the direction of the gate terminal is raised or lowered).

  On the other hand, since M is a parallel arrangement of independent transistors or transistor groups, the degree of freedom is extremely high. Even if M = 4 is designated, a total of four types of arrangements are possible from 4 parallels in the X direction to 4 parallels in the Y direction. For this reason, M can be designated and controlled independently twice in the first stage and the second stage. In addition, in order to control this degree of freedom in detail, the arrangement arrangement is designated in the dialog window and transmitted to the symbolic layout window.

  The reuse of the already-designed analog macro of the third point is not only analog but is generally said in LSI design, and is a so-called library. The library is normally incorporated by designating by the designer, but this embodiment realizes a better reuse method.

  Note that what is called a library here is not just a transistor-type library, but a larger function. That is, the present embodiment has means for automatically collating between a designated circuit and an existing library group and displaying a library that has been collated and matched as a target to be incorporated. Here, in the automatic collation, the instance name is not used as a collation key.

  As a result, in the specified circuit, the designer freely sets the instance name of the transistor in advance, performs initial circuit design verification by analog circuit simulation, and then automatically collates with the already designed analog library in this system. It is possible to select a matching candidate. As a result, the initial design stage and the analog library design stage premised on library matching can proceed independently and in parallel, and the design efficiency is greatly improved.

  In addition, as an additional function, for the purpose of more effectively using existing design assets, in the present invention, a symbolic double-structured mesh that is data of a symbolic layout editor from standard format layout data such as GDS or OASYS at a function macroblock level is used. It also realizes the function of converting to format and converting the converted Debye element mesh data to the layout control data used in the dialog window.

FIG. 2 shows an outline of the design scale output by this embodiment as a direct circuit simulation target. However, FIG. 2 only gives an example of the processing target of this embodiment, and is not limited to these ranges.
Since this embodiment has a functional block that performs an analog operation as a design target, the number of transistors directly handled is on the order of several hundreds (mesh portion in FIG. 2) as a guide for one processing unit. This is a limitation that comes from the scale that analog circuit simulation can handle.

  However, even if the data is directly manipulated for the purpose of simulation, even if it is a unit of several hundreds of transistors, the method of proceeding the design by dividing it into a plurality of functional blocks is taken. Can use a hierarchization technique to advance larger designs. Actually, this embodiment can be applied to a case where an LSI is advanced by placing a huge core such as a processor while designing an operational amplifier, an analog-digital (AD) / digital-analog (DA) converter, or the like.

  Analog circuits are often required in the peripheral area, and a symbolic layout editor needs to be able to handle huge amounts of data. Therefore, the most common design object range for the purpose of circuit simulation verification after layout in this embodiment is an operational amplifier, AD / DA converter, current mirror, differential pair, bias in a functional block having an analog signal interface. In a functional block having a digital signal interface, such as FF, NAND, NOR, EOR, latch, inverter, transfer gate, and the like. The switch and the transfer gate have the same function.

  In addition, when these functional blocks are a part of the functions of the LSI, there is a form in which a desired functional block is corrected and edited while displaying the whole in a symbolic layout editor. This is particularly noticeable in digital large-scale functional blocks having an analog signal interface.

FIG. 1 is a diagram showing an outline of processing of an analog functional block design system and a program according to the present embodiment.
Data input to the system is netlist information 101 corresponding to a transistor circuit diagram. The net list information 101 is data including at least a net list of the circuit to be designed. In the present embodiment, the netlist information 101 is a transistor level netlist in which parameters such as parameters F and M are specified, and a general format such as a Spice format or an EDIF format can be used. The interface may be in the form of a binary database of circuit diagram data.

  As the most common MOS transistor parameters, there are four parameters of F, M, L, and W. Here, F and M are as described above, L is a gate length, and W is a gate width. For the numerical values of these parameters, a net list verified in advance by an analog circuit simulator is input. Since this system is a layout system that realizes F and M, the following description will focus on F and M. L is not changed during normal layout. W can be effectively adjusted in this system by realizing F and M.

The next input is the library. In this system, there are two types of libraries. A transistor library 102 and a model library 105 expressing model patterns.
The transistor library 102 is a single unit library of a standard format such as GDS or OASYS that defines a transistor type, and includes an F expansion format. Since it includes up to F expansion, it may be a package that is described in a programming language and generates a standard format such as GDS or OASYS (this is called a parametric cell). The transistor library 102 is used for standard format conversion such as GDS or OASYS in the present embodiment.

The model library 105 is divided into two main data contents. One is an array list data in which the arrangement of transistors to be displayed and edited in the dialog window is abstracted in the s / d / A / B format, and the other is a symbolic layout used in the symbolic layout window. This is data in a double structure mesh format.
The model library 105 is a set having these two types of data formats and connection information (data corresponding to a netlist) attached to the duplex structure mesh data. In the present system, a function macro block is generated using the model library 105. The generated function macro block can be re-libraryed for reuse.

Next, the processing outline of this system will be described along the processing of the processing function block 106 representing the processing contents of the processing device (CPU) used in this system.
1) First, a parameter F or M is designated, and a target circuit (block) to be expanded is designated on the net list. This designation may be designated in advance in the net list as input information.
2) Next, the model library 105 having the same topology as the target circuit is detected by automatic verification.
3) Next, when there is a matching model library, various parameters (especially F and M) are transmitted from the target circuit, and corresponding symbolic duplex structure mesh data is generated via the transistor array list. To do.

4) Next, edit the symbolic duplex structure mesh data.
5) Thereafter, the data is converted into predetermined format data (for example, standard format data such as GDS or OASYS), and the layout data file 107 is output.
In this system, a function for generating model library data (symbolic duplex structure mesh data, connection information, and transistor array list) 104 from standard format data 103 such as GDS or OASYS designed as a library creation utility There is also a function to convert the data format (the path is indicated by a dotted line).

FIG. 3 is a diagram showing a circuit layout 301 in a transistor array list format, a circuit layout 302 in a symbol graphic format in a duplex structure mesh format, and a circuit layout 303 in a standard format format such as GDS or OASYS.
Here, the transistor array list format is expressed in an array list format by adding the character symbol “s” indicating the source or the character symbol “d” indicating the drain to the left of the MOS transistor type name represented by one character. Thus, each transistor is configured to be mutually connectable by a source s and a drain d.

The example of FIG. 3 shows that two types of MOS transistors A and B are arranged in 2 rows and 2 columns (2 × 2) with the source s on the left side.
Here, only the type name is specified for the transistor, and the instance name corresponding to the proper noun of each device is not specified. In this system, an instance name that is a name unique to each device exists as internal data, but is not essential data. Also, capacitors (capacitances) and resistors are displayed in a list with the letters C and R.

  The symbolic double mesh structure is a symbol graphic layout, and includes at least two types of layout grids that define device or macro layouts, wiring topology that connects between them, and wiring grids that define contact positions. A data structure and display format of a symbolic editor in which a mesh structure having a grid is defined and displayed and edited.

  In the model library format, the array list format of transistors, capacitors, and resistors has a corresponding symbolic duplex structure mesh format, and the symbolic duplex structure mesh format is a GDS via a library of transistors, capacitors, and resistors. Alternatively, it is automatically converted into a standard format such as OASYS. That is, there are a MOS transistor, a capacitor C, a resistor R, and a bipolar transistor (BJT) as device types. Accordingly, the library includes not only MOS but also standard format formats such as GDS or OASYS for bipolar transistors, capacitors and resistors.

  In FIG. 3, the devices defined in the model library 304 (FIG. 3 shows MOS transistors, bipolar transistors, capacitors, and resistors) are used, and a double layout corresponding to the circuit layout 301 in the array list format is used. After generating the symbol mesh format layout 302 in the mesh form, circuit layout data in a standard format such as GDS or OASYS is generated.

FIG. 4 is a flowchart showing a basic processing procedure of analog function block design according to the present embodiment.
In FIG. 4, first, data equivalent to a transistor net list (a net list including parameters) is read as input data (step S401). The net list may be configured to be input from an external device, or may be stored in advance in storage means of the present system.

In the former case, the external device constitutes input means, and in the latter case, the storage means constitutes input means.
The net list is created by a general commercially available transistor circuit diagram entry tool 410 (displayed by a dotted box). At this time, transistor parameters F, M, L, and W are also designated and verified in advance by an analog circuit simulator.

  Next, 1) F or M is designated on the input net list, and a transistor group to be laid out in this system is designated as a block. The transistor group normally specified here includes a differential pair, a current mirror, a bias, a switch, an inverter, and the like. Next, automatic comparison / collation between the designated model library and the designated transistor group block is performed.

  Normally, the designated model library is the basic model pattern library 105, and the connection information (data equivalent to the net list) included in the corresponding symbolic duplex structure mesh data and the circuit diagram net list information of the designated transistor group block Are compared from the viewpoint of topology. If there is a matched library, it is displayed on the display unit and selected by the user (step S402).

  Next, 2) F is performed on the transistor arrangement list corresponding to the basic model pattern selected by the user from the basic model pattern list 105 on the dialog window, and then X, Y, and Flip parameters are designated and first development is performed. A transistor array list corresponding to the model pattern and symbolic duplex structure mesh data are generated. Note that X is designated when a plurality of transistors are arranged in parallel in the X direction, Y is designated when they are arranged in parallel in the Y direction, and Flip is designated when they are inverted. Subsequently, X, Y, and Flip are designated again as necessary to generate a transistor arrangement list corresponding to the second development model pattern and symbolic (symbolic) duplex structure mesh data (step S403).

Next, 3) the generated symbol graphic format duplex structure mesh data can be edited or modified by the symbolic layout editor (step S404).
After that, 4) if editing processing has been performed, the edited data is finalized as double-structured mesh data in the symbol graphic format (step S405), and the data is converted to GDS or GDS using the transistor library 102. Conversion to a standard format such as OASYS (step S406), an output process is performed, and the process ends (step S407).

The input of this system is a transistor netlist, while the output is a standard format such as GDS or OASYS. The necessary transistor level netlist 412 is obtained by converting the output standard format such as GDS or OASYS using a commercially available netlist automatic conversion tool 411 (displayed by a dotted box).
Although not shown, the layout and transistor net list created in this way are applied for final verification by a circuit simulator.

  Here, an example is described in which the parameter F or M is started from automatic matching with a basic model pattern for symbolic layout processing. However, a larger first developed model pattern or second developed model pattern may be started as a target for automatic matching. Is possible. In addition, utilities 103 and 104 for converting from a standard format such as a predesigned GDS or OASYS are also prepared as model library creation tools (paths are indicated by dotted arrows).

There are three types of model patterns: a basic model pattern, a first developed model pattern, and a second developed model pattern.
Each model pattern is composed of three types of data. It includes (1) an array list of each device displayed in sAdB, etc., (2) double-structure mesh data in a symbol graphic format corresponding to the array list, and (3) a connection between the corresponding devices. Information. Here, in the case of the corresponding symbolic double-structured mesh data of (2), there are cases where the layout information is included but the wiring information is not included. When the wiring information is included, a plurality of pattern versions can exist. Further, one piece of connection information (3) exists for one array list.

FIG. 5 is a flowchart showing details of the processing step S402 in FIG.
FIG. 5 shows an example in which the differential pair circuit 500 of the operational amplifier 510 is designated as a transistor group to be developed and automatically collated with an existing basic model pattern. Parameters F and M are designated for each transistor of the differential pair circuit 500, and the circuit simulation is completed in advance.

  In FIG. 5, the central processing is automatic verification at the topology level. Corresponding to the array list 511 (here, the basic model patterns of one type of CMOS operation type and 16 types of pair operation type are shown) and the symbolic dual structure mesh data format as the model library 105 in which the connection is completed Connection information (double mesh format and connection information) 512 exists.

First, the net list of the operational amplifier 510 is read from the storage means and inputted (step S501), and the user designates a block to be targeted on the circuit diagram displayed on the display unit by the operation means (step S502). In this example, the designated block is a differential pair circuit 500.
Next, the connection information on the model library 105 and the netlist information of the designated block are automatically collated according to the following procedure (step S503).

That is, 1) coincidence of the number of terminals considering the same potential terminal of both circuits, 2) coincidence of the number of transistors and transistor types subsequently formed, and 3) finally coincidence of the topologies according to the graph matching algorithm.
Although the target candidates are displayed on the display unit, there may be a case where a plurality of target candidates are detected. In this case, finally, the user selects and determines the target candidates from the displayed target candidates. (Step S504).

FIG. 6 shows details of the graph matching algorithm.
First, since the processing device may possibly have both the netlist information of the target circuit A specified on the input netlist and the connection information B of the comparison target circuit on the library being parallelized, And the basic parts of the parameters F, M, X, and Y are restored (steps S601 and S602).

  That is, the contents of the parameters F and M are degenerate. F is simple because a parameter is attached to one transistor in both the net list of the target circuit A and the connection information of the comparison target circuit B in the library. Since M is expanded in parallel in X and Y in the connection information, M is degenerated if it exists.

  Next, the processing device takes a matching check after degenerating parallelization by F or M (step S603). This is because a method is adopted in which matching is determined in a circuit before F and M are expanded, and a plurality of candidates are selected from among them. That is, in the net list information of the target circuit A, F and M may be specified as a range (which numerical value is selected by the user at the time of layout), and is in a single degenerated state before development. First take a match. As a result, if the end indices of both block levels do not match, it is determined that they do not match.

If the processing device determines in step S603 that the number of terminals matches, the processing device next compares the number of nets, the number of transistors, and the transistor type (step S604). Here, the transistor type is a distinction such as PMOS or NMOS.
The processing device determines that they do not match if they do not match in step S604. When it is determined in processing step S604 that the two match, attention is paid to one netlist information of the designated target circuit A and next connection information of the comparison target circuit B on the model library (step S605).

When the next candidate connection information exists in the comparison target circuit B on the model library (step S606), the processing apparatus determines that each transistor type and gate terminal name in the net is the same as the number of terminals in the net. It is determined whether or not the power source names (VCC, GND, etc.) are matched (step S607).
In processing step S607, when the net of the target circuit A of interest matches the connection information of the selected comparison target circuit B, the processing apparatus determines that the net of the target circuit A of interest and the net of the comparison target circuit B match. (Step S609).

If there is a next net of the target circuit A, the processing device returns to the processing step S605 and repeats the processing (S609).
If all the nets in the target circuit A match the connection information of the comparison target circuit B, it can be said that they match at the module level (step S610). Here, the transistor type name, the gate terminal name, and the power supply name are the keys for collation, and the instance name, net name, source terminal name, and drain terminal name are not subject to collation keys. There is also a function for specifying the correspondence between the gate terminal name and the power supply name from the two circuits.

If the processing device determines in step S607 that they do not match, the processing device returns to processing step S605 and performs processing focusing on the next connection information of the comparison target circuit B in the model library.
If the processing apparatus determines in step S606 that there is no next candidate net in the comparison target circuit B on the model library, the number of nets, the number of transistors, and the transistor type do not match in processing step S604. If it is determined, and if it is determined in step S603 that the number of terminals does not match, the comparison target circuit connection information in the next library is input and the above process is repeated.

FIG. 7 is a diagram for explaining the details of the processing step S403 in FIG. 4, and shows the relationship between the basic pattern, the model pattern, and the arrangement pattern, and the editor.
In FIG. 7, there are the following steps to create a transistor array list developed from the basic model pattern 703 and symbolic duplex structure mesh data. They are a basic model pattern, a first developed model pattern, and a second developed model pattern.
The basic model pattern 704 is a development element composed of at least one transistor. A very large number of basic model patterns can be defined.

  Although details will be described later, in this system, one type of MOS basic operation type composed of one transistor, one type of CMOS basic operation type composed of two transistors, more complicated differential pair circuits, In consideration of parallel development of the current mirror circuit, 16 types of pair operation types corresponding to main array lists including repetitions composed of a minimum of 2 and a maximum of 4 transistors are used (see FIG. 14).

  Almost all of the circuits constituting the function based on at least two transistors, such as a differential pair circuit and a current mirror circuit, can be supported by the 16 types of arrangement lists in FIG. A circuit configuration that can express a function using at least one transistor such as a bias circuit or a switch circuit can also be constructed from one type of MOS basic operation type.

  Symbolic duplex structure mesh data corresponding to the transistor array list of the basic model pattern is made into a model library including wiring. Here, first, when F is designated, F is executed. The execution of F is not reflected in the sA type array list. Even if F is executed, the symbolic double-structured mesh data is not expanded in parallel. Even if F is executed, it is only displayed as one F = n type device element. This is because F is a content reflected in the transistor model itself, because independent transistors are not parallelized and because abstraction is being advanced.

Next, the process of M is specified in detail by X and Y. X and Y are expanded again by the transistor group unit expanded by F. At this time, Flip designation is possible for X and Y. In this way, a corresponding transistor arrangement list is first generated in the first development model pattern.
Since both F and M are developed in parallel, the connection information after the expansion is automatically generated, and symbolic 2 in the first model pattern is generated from the symbolic duplex structure mesh data of the already wired basic model pattern and the automatically generated connection information. The wiring of the overlapped mesh data can be automatically processed (the wiring can be completed by manual wiring here).

In this way, both the arrangement list of the first development model pattern and the symbolic duplex structure mesh data are completed. Since F is diffusion shared, it is expanded in the X direction in one dimension, and the M expansion in the first expansion stage is often expanded to X and Y in the target circuit like a differential pair or a current mirror.
After that, a circuit that needs to maintain such objectivity can be developed while maintaining the balance in the X direction and the Y direction again in the second development. Further, at the time of the first expansion, it is possible to specify diffusion sharing in the M expansion. That is, the source or drain that is parallel when M parallel is expanded is designated in common.

Subsequently, the second development can be performed with the first development model pattern as a group based on the designation of X, Y and Flip again. In this way, the transistor arrangement list of the second development model pattern and the symbolic duplex structure mesh data are completed including the wiring data.
Processing related to F cannot be performed at the stage of creating the second development model pattern. It must be done at the stage of creating the first development model pattern.

  In this example, sAdB / dBsA (“/” means a line feed) is selected as the basic model pattern 704 in the transistor array list format, and F = 4 and M = 4 are set as parameters 705 for both A and B. M = 2 is flip-expanded in the X direction in the first expansion to generate the first expansion model pattern 706, and M = 2 designated as the parameter 707 is expanded in the Y direction in the second expansion. An example of generating a two-deployment model pattern 708 is given. In the first development model pattern 706, each transistor of sAsB is F-expanded inside, and the F-expansion is not displayed in the array list.

The duplex structure mesh editor 701 constitutes a layout processing means as a function of the processing unit (CPU) 2 described later, and includes a transistor array list of the basic model pattern 704 and placement and routing result information of the basic model pattern 703, 2 Edit processing is performed using the symbolic library of the overlapped mesh format. The first development model pattern 706 and the second development model pattern 708 are automatically generated by the placement and routing data automatic generation unit 702, displayed on the display unit, and edited by the duplex structure mesh editor 701.
As shown in the parameter 707, at the time of the second expansion, the space for the transistor group at the time of the first expansion, which is an element to be expanded, can be designated in the X and Y directions. This is effective for securing a future power wiring area.

FIG. 8 is a flowchart showing processing for shifting from symbolic duplex structure mesh data corresponding to each model pattern stage to standard format conversion such as GDS or OASYS at the final stage.
In FIG. 8, the basic model pattern arrangement list is laid out only with basic transistors (step S801), duplex structure mesh arrangement and wiring data is generated (step S806), and conversion processing to a format such as GDS is performed in the subsequent stage. Is called.

  When F, M, and Flip with parameters designated for the basic model pattern array list are executed (step S802), a first expanded model pattern array list is generated (step S803), and the double structure of the first expanded model pattern Mesh placement and routing data is generated (step S806), and conversion processing to a format such as GDS is performed in the subsequent stage.

When M and Flip with parameters designated for the first development model pattern are executed (step S804), a second development model pattern arrangement list is generated (step S805), and the double structure mesh arrangement of the second development model pattern is generated. Wiring data is generated (step S806), and conversion processing to a format such as GDS is performed at a later stage.
As described above, in the processing according to the present embodiment, it is possible to output a standard format such as GDS or OASYS at any stage from the basic model pattern to the second development model pattern, and a small-scale analog circuit To large-scale analog circuits can be handled with a single concept.

FIG. 9 is an explanatory diagram showing details of the latter half of the processing step S403 and the processing step S404 of FIG. 4, and shows the relationship among device placement automatic generation, wiring automatic generation, and functional block output. Note that the data in FIG. 9 is not linked to FIG. The symbolic dual structure mesh editor can intervene at any stage and can be corrected manually.
In the example of FIG. 9, one type of MOS basic type sA is designated as the basic model pattern, and this is passed through in the first development. As shown in the second development model pattern 901 in the array list format, M = 2 and the space P in the X direction are designated in the second development, and the data converted into the standard format such as GDS or OASYS is finally obtained as sAsA. This is an example to be created.
Note that it is also possible to make the standard format such as GDS or OASYS by spreading and sharing in the first development to be sAdA and passing the second development.

  When converting to a standard format such as GDS or OASYS, a transistor library 202 having a programming description for generating a standard format library such as GDS or OASYS for a transistor to be incorporated or a standard format library such as GDS or OASYS for a transistor that implements F (Ie, a parametric cell) and a rule file 905 for determining the line width and contact shape are input, and the format conversion unit 906 uses the input and the symbol graphic layout from the duplex structure mesh editor 701 to input the rule file 905. The format is changed to a GDS format functional block 907 (an example of which is shown as a functional block 908).

  The symbolic duplex structure mesh data 902 of each development level generated in this way can be incorporated into the higher-order analog function block 903 as a partial circuit element 904, which is also the symbolic duplex structure. Designed with a mesh editor. The partial circuit element 904 is edited by the placement and routing data editing unit 909.

FIG. 10 and FIG. 11 are diagrams showing an outline of processing of a utility (a library utility) for converting a standard model format such as GDS or OASYS into a library set of a basic model pattern or a first developed model pattern desired by the user.
In FIG. 10, as a processing procedure, first, a circuit layout 303 in a standard format such as GDS or OASYS is converted into a symbol figure format layout (symbolic duplex structure mesh data) 302 and then converted into an array list format 301. become.

  In this example, the array list format 301 is sA. At this time, F (D = 5 in this example) which is diffusion sharing is recognized and degenerated (parallelization is unified). Here, an example in which a single device symbol is associated with F is shown. The user can select whether to recognize and degenerate the parallelization of M. When registering with M parallelism remaining, registration is basically performed as a first development model pattern.

  11 is the same as the processing in FIG. 10 except that F = 1, that is, F is not specified. That is, first, a circuit layout 303 in a standard format such as GDS or OASYS is converted into a symbol graphic format layout (symbolic duplex structure mesh data) 302 and then converted into an array list format 301. The sequence list format 301 is sAsB / sCsD. When registering with M parallelism remaining, registration is basically performed as a first development model pattern.

FIG. 12 is a flowchart showing the processing procedure of the library making utility that performs the processing of FIGS. 10 and 11.
First, the processing apparatus inputs design target circuit diagram data 121 in a standard format such as GDS or OASYS, and recognizes and extracts the netlist information of the circuit (step S122).
Subsequently, the processing apparatus recognizes diffusion sharing, degenerates the number of transistors, recognizes F, and extracts (step S123).

  Next, the processor recognizes the parallelization of the independent transistors, and recognizes and extracts M (in this case, automatically X and Y) (step S124). At this time, the presence or absence of the flip is also recognized in the processing step S124. However, whether or not to degenerate M including the flip can be selected by selection by the operation means. In this way, the numerical values M in the F, X, and Y directions and the data 129 of presence / absence of the flip are extracted by the processing of the processing steps S123 and S124.

Subsequently, the processing apparatus performs region division by horizontal lines, and then performs division by vertical lines (step S125). At this time, since the data generally swells, it is impossible to completely restore a standard format such as GDS or OASYS (an example is shown in FIG. 33).
The transistor netlist information 130 finally degenerated in this way, the values of F and M (for both X and Y) related thereto, and the symbolic double mesh format divided by horizontal and vertical lines Data (symbol graphic format layout data) 126 is obtained.

The processing device converts the symbol graphic format layout data 126 into an array list format (step S127), and generates array list format data 128.
When M is degenerated, restoration of wiring data is not guaranteed in the symbolic double mesh format. This is because the degenerated transistor netlist information is generated, and it is sufficient that only the arrangement data is restored as symbolic data.
When it is desired to save the wiring data, the M degeneration is not performed. When the M degeneration is not performed, that is, when the M expansion is maintained, the first expansion model library is created, and the second expansion is possible.

FIG. 13 is a block diagram of the analog functional block design system according to the embodiment of the present invention.
In FIG. 13, an analog functional block design system includes a processing unit (CPU) 2, an input unit 3 constituted by a keyboard 7 and a mouse 8, etc., a display unit 1 constituted by a liquid crystal display, a magnetic disk device and a semiconductor memory. The memory | storage part 4 comprised by these is provided. As described above, this system includes at least the CPU 2, the storage unit 4, the input unit 3, and the display unit 1.

The storage unit 4 stores a program executed by the CPU 2. The storage unit 4 includes a data storage unit 9 for storing input data to the system, output data to be output from the system to the outside, intermediate data generated during processing, and rule files and libraries that define design rules and the like. A file storage unit 10 for storing files is provided.
At least a dialog window 5 and a symbolic layout window 6 are displayed on the screen of the display unit 1.

  In the dialog window 5, the basic model pattern is displayed in a selectable manner, the instruction for expansion and the display of the first expansion model pattern obtained by expansion, the instruction for re-expansion and the second expansion obtained by expansion. Model patterns are displayed in an array list format. The symbolic layout window 6 displays a symbol graphic format circuit layout (circuit layout having a symbolic double structure mesh structure) and the like.

  The CPU 2 includes 1) means for inputting information equivalent to a transistor circuit diagram netlist (connection information), and 2) processing for performing array control using transistors as elements on the dialog window 5 (for example, display of a basic model pattern). And selection processing, designation and generation processing of the first development model pattern, designation and generation processing of the second development model pattern), 3) arrangement on the mesh (arrangement mesh) having transistors as elements on the symbolic layout window 6 An interactive editing process that symbolically displays and edits a data format having a symbolic double mesh structure in which wiring is performed in a mesh format on an interval mesh (wiring mesh) obtained by further subdividing the arrangement mesh. 4) Symbolic Standards such as GDS or OASYS for duplex mesh data Converted into formats performs processing for outputting.

  In addition to the above processing, the CPU 2 uses 5) circuit data input in a standard format such as GDS or OASYS as a basic model or first development model library (wiring list, duplex structure mesh data, connection information). The system is configured to have a utility function for creating the basic model or the first development model on the user side by using this system.

  Further, the library file stored in the file storage unit 10 includes 1) describing the transistor type in a standard format format such as GDS or OASYS, or F-development in which programming is described to generate a standard format format such as GDS or OASYS. There are a transistor library, 2) an array list belonging to various basic model patterns, symbolic duplex structure mesh data, and accompanying connection information. The basic model pattern can be increased by the user. It is also possible to make the first development model into a library and make it an object of automatic collation. As a rule file, there are definitions regarding 3) transistor types, lines, contacts, terminals, etc. in a symbolic double structure mesh.

Here, the display unit 1 constitutes a display unit, the input unit 3 and the storage unit 4 constitute an input unit, and the storage unit 4 constitutes a storage unit.
The input unit 3 and the CPU 2 constitute a layout processing unit, a development unit, a layout generation unit, a diffusion shared development unit, a packing unit, and a conversion unit.

The storage means can store array list data representing device arrays in characters and symbol graphic data representing the devices in symbol graphics.
The input means can input netlist information of the circuit to be designed.
The display means can display at least a dialog window and a symbolic layout window. The symbolic layout window can define at least two types of meshes: a first mesh that defines the arrangement position of the device and a second mesh that defines the arrangement position of the wiring.

  The dialog window displays a basic model pattern array list corresponding to the net list information of the circuit to be designed, and the symbolic layout window displays a symbol graphic layout corresponding to the basic model pattern array list. be able to. In the display of the device in the dialog window, at least one character corresponds to the device, and when the device is a MOS transistor, the presence direction of either the source or drain terminal is represented by at least one character. It can be written on one side of the character representing.

  The layout processing means generates an array list corresponding to the net list information using the array list data stored in the storage means, and uses the symbol graphic data stored in the storage means to generate symbols corresponding to the array list. A graphic format layout can be generated, and the array list and symbol graphic format layout can be displayed in a dialog window and a symbolic layout window. In addition, the layout processing means can arrange and display the device and the wiring in the symbolic layout window so that they are aligned with the first and second meshes, respectively.

  The layout processing means corresponds to the expansion means for generating a first expansion model pattern arrangement list by performing a first expansion on the basic model pattern with respect to a predetermined parameter, and the first expansion model pattern arrangement list. Layout generating means for generating a symbol graphic format layout to be displayed in the symbolic layout window.

  The expansion means further performs a second expansion on the first expansion model pattern with respect to a predetermined parameter to generate an array list of second expansion model patterns, and the layout generation means further includes the second expansion model pattern. A symbol graphic layout corresponding to the arrangement list of the above can be generated and displayed in the symbolic layout window. Further, the expansion means can include at least one of a diffusion shared expansion means for performing expansion using diffusion sharing at the time of expansion and a packing means for packing when there is a gap between the laid out devices.

  Further, the layout processing means can parallelize the MOS transistors when the circuit to be designed has a bias circuit or a switch circuit whose function can be configured by at least one MOS transistor. Further, the layout processing means can parallelize the MOS transistors when the circuit to be designed has a differential pair circuit, a current mirror circuit or an inverter circuit whose function can be configured by at least two MOS transistors.

The layout processing means displays the basic model pattern connection information in the library and the design target circuit net list information when displaying the arrangement list of the basic model pattern corresponding to the net list information of the design target circuit. And a matching sequence list can be displayed.
The converting means can convert the circuit graphic data in the GDS or OASYS format into the corresponding layout data in the symbol graphic format.

  FIG. 14 shows a MOS basic operation type 1 (sA), a CMOS basic operation type 1 (sA / sB), and a pair operation type 16 types (10 types of general types of pair operation type, pair operation) in this system. The transistor arrangement list 141 includes a total of 18 basic model patterns. Of course, other basic models can be defined.

The MOS type basic operation type is:
sA. . .
The basic CMOS operation type is:
sA / sB. . .

Common forms of pair operation are:
dAsB. . . ,
sAdB. . . ,
dAsB / dCsD, sAdB / sCdD,
dAsBdAsB. . . AdBsAsB. . . , DAsAdBsB. . . , SAdAsBdB. . . ,
dAsB / dAsB. . . ,
sAdB / sAdB. . . ,

Symmetric forms include:
dAsB / dBsA,
sAdB / sBdA,
dAsBdBsA / dBsAdAsBs,
AdBsBdA / sBdAsAdB,
dAsB / dDsC. . . ,
sAdB / sDdC. . . ,
Etc. Here, the symbol “...” Means that it can be repeated, and the symbol “/” means a line feed.

Each basic model pattern array list corresponds to a plurality of symbolic duplex structure mesh data including wiring and connection information 142.
The basic pattern of the basic operation type of MOS and CMOS does not go beyond the mere material. However, if there is symbolic double-structured mesh data including wiring corresponding to this array list, F or M (X, Y) is applied to a basic circuit including at least two transistors such as a differential pair and a current mirror. Can be easily developed in parallel including Flip and Flip, and is extremely effective for a circuit of pair type operation.

In addition, it is of course possible to design a large-scale analog functional block such as an operational amplifier by adding a differential pair etc. developed in parallel to other circuit blocks in a symbolic dual structure mesh editor and modifying and editing them. is there.
Further, a plurality of symbolic duplex structure mesh data 142 and 143 belonging to one basic model array list shown in FIG. 14 may exist. However, there is one connection information in the basic model pattern.

FIG. 15 is a diagram showing the contents of the dialog window 5 in the present embodiment.
1) First, a box 151 in which target circuits on the selected input netlist are listed is displayed in the dialog window 5 (FIG. 15A). Here, various transistor parameters of transistor type, F, M, W, and L are displayed. In FIG. 15A, transistor types A and B are set. An initial circuit simulation was performed under these parameter conditions.

2) As a result of automatic comparison of the target model with the model library specified next, here 16 types of basic model patterns (and user added patterns), a candidate array list 152 is displayed (FIG. 15B). )). Here, if there are a plurality of candidates, they are selected by the input unit 3.
3) When the selection operation by the input unit 3 is performed, the selected candidate is displayed as the sequence list 153, or when there is only one candidate, the candidate is displayed as the sequence list 153 (FIG. 15C). ). Although not the dialog window 5, the corresponding symbolic duplex structure mesh data (symbol figure format layout) 154 is also displayed on the symbolic window 6 (FIG. 15D).

  Here, when a plurality of symbolic duplex structure mesh data 154 exists corresponding to one sequence list candidate, the user operates the input unit 3 to generate one symbolic duplex structure mesh data. 154 is selected on the symbolic window 6. As a result, the basic model pattern (array list and symbolic duplex structure mesh data set) shown in 3) is determined to correspond to the target circuit shown in 1).

  4) Next, the input unit 3 is operated to specify the first development for generating the first development model pattern from the development designation box 155 of the dialog window 5 (FIG. 15E). Since F can be expanded only in the first time, F and M are expanded using X and Y here. It is possible to select whether or not diffusion sharing is performed for X expansion of M. In X and Y, a flip can be specified. Normally, the first expansion is performed with F and X expansion.

  5) Subsequently, the second development designation is performed to generate the second development model pattern (FIG. 15 (f)). In this case, the second expansion for M is performed with X and Y from the expansion instruction box 156 of the dialog window 5. Of course, there is also a flip specification. Here, an instruction to leave a space between elements in the X direction and the Y direction can be given. Usually, the second development is a Y-direction development. As a result, a parallelized circuit expanded in two dimensions X and Y and having an increased effective W is created.

FIG. 16 is a diagram showing a double mesh structure by the symbolic layout editor according to the present embodiment, and shows the display of the symbolic layout window 6.
The first mesh 161 having a large interval is a device placement mesh. Here, the device includes a MOS transistor, a capacitor C, a resistor R, a bipolar transistor BJT, and the like. The devices are arranged so as to align with the first mesh 161 (for example, the outer periphery of the device overlaps the first mesh 161), and are displayed in the symbolic layout window 6 of the display unit 1 in that state.

  The second mesh 162 having a smaller interval than the first arrangement mesh 161 is a wiring arrangement mesh, and contacts and terminals can be arranged in addition to the wiring. Here, the interval between the first meshes 161 is an integral multiple of the interval between the second meshes 162. The wiring, contacts, and terminals are arranged so as to be aligned with the second mesh 162 (for example, the center of the wiring or the like overlaps the second mesh 162), and are displayed on the display unit 1 in that state.

FIG. 16 shows an example in which a symbol graphic format circuit layout 302 in a double mesh format corresponding to an array list format circuit layout is generated using a device defined in the model library 304.
In the model library 304, a MOS transistor 163, a bipolar transistor 164, a resistor 165, and a capacitor 166 are defined.

Further, a symbol graphic format circuit layout 302 in which four MOS transistors defined in the model library 304 are connected by wiring 167 is displayed as the symbol graphic format circuit layout.
The model library 304 and the symbol graphic format circuit layout 302 are displayed in a symbolic layout window.

FIG. 17 is a diagram illustrating an example of development from the basic model pattern to the first development model pattern.
The basic model pattern 170 is represented by an array list “sAsB” in which two transistors A and B are arranged side by side as shown in FIG. 17A, and the symbol figure format layout corresponding thereto is the gate of the transistors A and B. Are connected by a wiring 171. F and M are assigned to each of the transistors A and B, and F = 1 and M = 4, respectively.

  When the first development (M = 2 in the X direction, Flip = ON: M = 2 in the Y direction, Flip = OFF) is executed on the basic model pattern 170, the array list “sAdBsBdA / sAdBsBdA” of the first development model pattern Is obtained. As shown in FIG. 17B, the symbol figure format layout of the first development model pattern corresponding to the array list includes two basic model patterns 170 and 170 and two model patterns (inverted). Inverted model pattern) 174 is arranged 2 × 2 and connected by wiring 175.

  On the other hand, FIG. 17C is an example in which another basic development (M = 4 in the X direction, Flip = ON) is performed on the basic model pattern 170. The meaning of Flip is applied to the model immediately after expansion. As can be seen from this example, repeating the flip results in repeating “Filp” and “returning to the original”. The origin of repetition is in the lower left corner (indicated by a dotted box).

  When another first expansion (M = 4 in the X direction, Flip = ON) is performed on the basic model pattern 170, an array list “sAdBsBdAsAdBsBdA” of the first expansion model pattern is obtained. As shown in FIG. 17C, the symbol graphic format layout of the first development model pattern corresponding to the array list includes a basic model pattern 170, an inverted model pattern 174 of the basic model pattern 170, and an inverted model of the inverted model pattern 174. A pattern (that is, the basic model pattern 170) and an inverted model pattern 174 of the basic model pattern 170 are sequentially arranged in the X direction, and the gates are connected by the wiring 175.

  18 and 19 are examples of development from the first development model patterns 181 and 191 to the second development model patterns 182 and 192, respectively. Although X = 2 (M = 2 in the X direction) and Y = 2 (M = 2 in the Y direction) are executed for both of the first development model patterns 181 and 191, FIG. 18 shows Flip = ON (X FIG. 19 shows an example of Flip = OFF (Flip = OFF in both X and Y directions).

  In the order of expansion with respect to X and Y, expansion is first performed in the X direction, and then expansion is performed in the Y direction. The interpretation of the flip regarding X and Y is the same. When the flip is specified for both X and Y, the flip is first repeated in the X direction. Therefore, when the number of flips of 3 or more is specified, the same pattern appears alternately on the left and right. Subsequently, flip development in the Y direction is performed on the entire pattern developed in the X direction. Therefore, the same pattern appears alternately in the top and bottom.

  As can be seen from FIGS. 17 to 19, in this system, the same result as the second development pattern can be obtained by the first development pattern. This is because there are cases where the expansion is not required twice when the expansion is simple. However, what is deployed in each deployment varies depending on the user. This system is necessary and sufficient if it provides two deployment functions, and more than that, and it is desirable to prepare two deployment functions from the two-dimensionality of LSI design. These functions are provided.

FIG. 20 shows a device in which a second expansion model pattern 2002 is generated by performing the second expansion on the first expansion model pattern 2001 by specifying X, Y, and flip, and packing processing is performed on the result. This is an example in which the gaps 2003 are filled.
The packing process can be performed in two stages after the first development and after the second development. Although not shown, in the packing process after the first expansion, the packing process can be performed by spreading and sharing, and it can be specified whether or not the sharing is performed. After the second expansion, the packing process is not performed by spreading and sharing. Diffusion sharing, including F expansion, is a processing content that is performed only during the first expansion. Further, whether or not to perform packing processing can be designated from the input unit 3, and when the packing processing is set, packing processing is performed to close the gap.

  FIG. 21 is an example of developing symbolic double-structured mesh format data determined by the first development model pattern into the second development model pattern, and is an example of development including wiring. As can be seen from this example, the wiring data described by the symbolic duplex structure mesh data is also subject to flipping in the X direction and the Y direction.

In FIG. 21, the second development (M = 2 in the X direction, Flip in the X direction = OFF: Y direction) for the first development model pattern (the array list 211, the duplex structure mesh data 212 corresponding to the array list 211). The second development model pattern 213 is generated by performing (M = 2, Y-direction Flip = OFF).
Further, by performing another second development (M = 2 in the X direction, Flip = ON in the X direction: M = 2 in the Y direction, Flip = ON in the Y direction) for the first development model pattern, the second development is performed. A development model pattern 214 is generated.

FIG. 22 shows an example of a CMOS basic model pattern, which is an example of sA / sB symbolic duplex structure mesh data to which a gate G is connected.
FIG. 22A is a circuit configuration diagram of a CMOS transistor, in which both gates of one polarity MOS transistor 221 and the other polarity MOS transistor 222 are connected by a wiring 223.
The CMOS transistor of FIG. 22A is represented as a CMOS basic model pattern “sA / sB” in an array list format (FIG. 22B).
Further, the CMOS transistor of FIG. 22A is represented as a model pattern of a symbolic figure format layout as shown in FIG.

  FIG. 23 shows the symbolic double-structured mesh data “sA / sB” shown in FIG. 22 in the X direction by passing the first development from the basic model pattern “sA / sB” (ie, without generating the first development model pattern). This is an example in which a second development model pattern “sA dA / sB dB” is created with a space specified and Flip = ON in the X direction and M = 2 in the X direction (blank indicates a space). FIG. 23A shows a second development model pattern in an array list format, and FIG. 23B shows a second development model pattern in a symbolic graphic format layout. In FIG. 23B, reference numeral 231 denotes a space.

FIG. 24 is an example of basic model duplex structure mesh data including wiring. FIG. 24A shows array list data “sAsB”, and FIG. 24B shows duplex structure mesh data corresponding thereto, in which MOS transistors A and B are connected by a wiring 241.
In the symbolic double-structured mesh data of the basic model pattern “sAsB” including the wiring, two devices A and B are defined as one first mesh for device placement, and the wiring is drawn to the external terminal position. It is an example.

  The method of defining the two devices A and B in one mesh is a method often adopted in analog design using thin film transistors of a liquid crystal display device. The method of drawing out wiring is suitable for an analog engineer who prefers manual wiring, and has a function of automatically deleting branch wiring that has become redundant after placement and routing. In addition, it is possible to select “do / do not” to delete the redundant branch wiring itself as a processing target in order to balance the characteristics.

  The symbolic dual-structure mesh editor is also equipped with an automatic wiring function, and a user who prefers automatic wiring may perform shared wiring only for the normal gates manually and apply automatic wiring to other wirings. Analog design often requires delicate wiring balance, and the system that automates anything is not acceptable to users. As shown as an example of the present system, there is also a demand for a system in which an automatic function is prepared and in which fine control can be performed manually by operating the input unit 3.

  25, the basic model pattern “sAsB” for user registration shown in FIG. 24 is passed through the first development at M = 4 (X = 2, Y = 2), and the space is designated by the second development. This is an example of performing M development. The generated second expansion model pattern in the array list format is “sAsB sAsB // sAsB sAsB” as shown in FIG. Here, a blank indicates a space, and “//” indicates that a space is inserted after a line feed.

FIG. 25B shows a symbol graphic format layout corresponding to the array list format data. An X direction space 251 and a Y direction space 252 are formed between devices.
When the expansion of X and Y is instructed, it is performed in the order of X to Y, that is, (X = 2, Flip = OFF), (Y = 2, Flip = OFF). This reserved space is used for power supply wiring.

FIG. 26 shows an example of a switch circuit. As shown in FIG. 26A, the technology is a single MOS (for example, NMOS) transistor, and is an example in which M expansion is performed using one basic model pattern of a MOS basic operation type.
Here, it is assumed that 12 is designated as the parameter M when the initial netlist is input. Then, the “sAdB” basic model pattern is adopted for the MOS transistor type A = B (FIG. 26B), and the first expansion in the X direction is performed six times so that M = 12 (FIG. 26C). Then, the second expansion is performed 13 times and the total is equivalent to M = 156 (FIG. 26 (d)). Since the development is performed in a plurality of times, the development process can be performed in a short time even when M is large.

  When A = B, the sources and drains of the MOS transistors A and B are not distinguished from each other, and therefore may be arranged as “sAsA”. In addition, when the initial designation M is exceeded, a warning is displayed on the display unit 1, but it is basically developed at the user's responsibility. In this way, it is possible to create various switches by adjusting the effective W during layout. If the gate terminal is connected to the source, a bias circuit is formed. All parallel circuits are configured.

  These differences between the switch circuit and the bias circuit are all reflected as differences in symbolic double-structured mesh data. That is, even in the same sAsA, the connection information in the symbolic duplex structure mesh data is that the source terminal and the drain terminal are floating, the source terminal is connected to VCC (or GND), and the drain terminal is connected to GND (or VCC). There are various types of mesh data, such as those that are connected and those whose gate terminals are connected to the source terminals, and are sorted at the stage of automated verification.

  FIG. 27 shows an example of the differential pair circuit 271 in the operational amplifier (FIG. 27A). The technology is a single MOS (eg NMOS) transistor. The parameter specified by the MOS transistor A (F = 4, M = 2) and the MOS transistor B (F = 4, M = 2) is set to the first parameter F from “sAdB / dBsA” in the basic model pattern array list 301. It is generated by expanding (FIG. 27B). Thereafter, a symbol graphic format layout 302 corresponding to the array list data 301 is generated (FIG. 27C), and a standard format such as GDS or OASYS corresponding to the symbol graphic format layout 302 (in other words, the array list data 301) is generated. A layout 303 is generated (FIG. 27D).

In this example, since M = 2 of each transistor group has already been realized in the basic model pattern, only the F expansion is executed when the first expansion model is generated. b) and (c) the first development model can be expanded again while maintaining the second development (M development in both the X and Y directions) again, and such a symmetrical circuit can be obtained. This is a very useful function for deployment. This is because it is necessary to always develop the symmetrical circuit while maintaining the symmetry. The basic structure is developed in the first development shown in FIG. 27, and then the center of gravity (balance) is made easier in the second development. It is because it becomes possible to control.
Similarly, as shown in FIG. 28, a current mirror circuit which is a symmetric circuit having MOS transistors 304 and 305 can be constructed.

29 to 31 are examples of latch circuits having a plurality of transistor pairs a to h. The technology is CMOS. In a circuit having a digital signal interface, this system is often used when it is desired to increase the effective W of the inverter buffer at the final stage. This is not limited to the latch, but is applied to the final stage of a general gate circuit such as an AND gate or an OR gate.
In the transistor circuit diagram of FIG. 29, it is assumed that M = 2 is designated for the buffer h of the output terminal OUT.

FIG. 30 shows symbolic double-structured mesh data corresponding to the transistor circuit diagram of FIG. 29, which is data before M = 2, and the CMOS transistor pairs a to h of FIGS. 29 and 30 correspond to each other. is doing.
FIG. 31 shows symbolic double structure mesh data obtained as a result of performing M = 2 on the CMOS transistor pair h. A CMOS transistor pair i is formed in parallel to the output stage CMOS transistor pair h.

If such a circuit is made into a library of transistor circuit diagrams and symbolic double-structured mesh data, it is possible to easily parallelize buffers in the output stage with M designation. This is an example of creating a library as the first expansion model.
Design and provide a cell with increased W on demand if a flip-flop circuit (FF) in a digital circuit such as an ASIC or a cell library such as NAND or NOR is registered as the first development library in this system. It shows what you can do. FIG. 30 shows an example of spreading and sharing independently of parallelization. The symbolic editor also has a function of making a connection by sharing a diffusion pattern without using a wiring pattern according to an instruction.

  FIG. 32 shows a large-scale IP (for example, a processor), which is not an object of analog design, but in the case where an analog function block such as an AD / DA converter exists in the peripheral portion, F, M of this embodiment This is an example of a design technique in which a large-scale IP is placed on a symbolic dual structure mesh editor (although not modified) as a data object when designing an AD / DA converter or the like using the development function of (See 903 and 904 in FIG. 9).

Although this is a hierarchical design in a so-called layout, this symbolic dual structure mesh editor can design a peripheral analog functional block of a large-scale digital circuit including a digital circuit.
In FIG. 32, a fixed hardware macro 322 such as a processor and an analog function block 321 are arranged so as to align with a first mesh 323 for device arrangement. The analog function block 321 is, for example, a differential circuit ABBA of an operational amplifier and is a circuit to be designed, and processing such as change is performed by the processing described above.

33 and 34 are diagrams showing an example of conversion from a standard format such as GDS or OASYS to symbolic duplex structure mesh data. The conversion process is performed as described above (see FIGS. 10 to 12).
33A shows the original GDS format layout data, FIG. 33B shows F recognition and division processing by the horizontal line 332, and FIG. 33C shows division processing by the vertical line 333 with respect to FIG. 33B. . F = 4 is recognized from the four MOS transistors 331 whose gates are commonly connected. Further, each MOS transistor is divided by a horizontal line 332 and a vertical line 333, and a mesh region in which these MOS transistors are arranged is determined.

  FIG. 34 shows a symbol graphic format layout corresponding to FIG. The four transistors 331 are represented by a single symbol MOS transistor 334 with F = 4, and each MOS transistor is arranged in alignment with the first mesh for device arrangement. Each wiring is arranged in alignment with the second mesh for wiring.

As can be seen from this example, when converting from a standard format such as GDS or OASYS to symbolic duplex structure mesh data, it is abstracted horizontally and vertically, so it may not be completely consistent. Many. Even so, the effect of reusing the circuit including the wiring as a library (particularly the first development model library) is great.
The circuit specified by the user and the first expansion model library can be automatically collated without using the instance name as a key, and then the second expansion can be performed or corrected with a symbolic dual structure mesh editor. Some are very effective in terms of reusing existing data.

  If only considering the library registration, it is possible to register the array list and symbolic duplex structure mesh data before reaching the standard format such as GDS or OASYS, but output the standard format such as GDS or OASYS. Based on the idea of creating a library of data whose operation has been confirmed by a later circuit simulator, it is preferable to create a route from a standard format such as GDS or OASYS for library registration of the basic model and the first development model.

    As described above, in the analog functional block design system according to the embodiment of the present invention, the design target circuit is represented in the wiring list format 301 based on the net list information of the design target circuit. In the array list format 301, the layout of each MOS transistor is represented by adding a symbol “s” indicating a source or a symbol “d” indicating a drain to the left of the transistor type names A and B. Each transistor has a source s and a drain d. Are configured to be mutually connectable. The wiring list format 301 is converted into a corresponding symbol graphic format layout 302 using the symbol graphic of the model library 304.

  In the symbol graphic format layout 302, transistors and wirings are arranged in alignment with a device placement mesh and a wiring placement mesh. After editing in the state of the symbol graphic format layout 302, it is converted into a layout 303 such as GDS format and output. Thereby, in the design process of the analog functional block, the efficiency of the analog design is improved from the viewpoint of the analog layout.

  In the analog functional block design system according to the embodiment of the present invention, a symbolic layout editor having a symbolic double mesh structure of a device placement mesh and a subdivided wiring placement mesh, and F and M parameters Design function of analog function block, especially differential pair circuit and current mirror circuit, effectively linked with development control by dialog window which develops specified transistor circuit in 2D plane, preferably divided into 2 stages at maximum The ease of design is enhanced when deploying while maintaining the objectivity as seen in the above.

  Also, displaying the array list format on the dialog window and performing the expansion control divided into two stages promotes data abstraction and expands while maintaining the objectivity suitable for LSI two-dimensional plane design operations. A versatile design control means including cases is provided.

  In addition, the model library that matches the target circuit specified in the transistor netlist is automatically searched by comparing and collating topologically without using the instance name as a key. This function includes a circuit scale of the level specified by the F and M parameters. Applicable to analog function macroblock. First, for the specified M, an array list is prepared as a basic model pattern, including symbolic double-structured mesh data and connection information, and is specified by automatic verification. Is possible. In addition, since automatic matching is possible not only in the basic model pattern but also in the first development model pattern, the value of library assetization is high.

Further, the symbolic layout editor used in the present embodiment is not only effective for F and M parameter operations but also extremely effective for the design of analog function macroblocks thereafter.
Since symbolic data representation is used in this way, it is possible to respond flexibly to changes in technology and increase the value of making it a library and capitalizing it.

From the viewpoint of capitalization, the means for automatically converting the standard format such as GDS or OASYS provided by the present invention into a model library of symbolic duplex structure mesh data is also an effective tool, not only the basic model pattern. Further, it is possible to create a library of a more complicated first development model pattern, and the asset utilization value at a place where it can be used for the subsequent second development is high.
According to the embodiment of the present invention, the analog functional block design system is constructed by causing a computer having an input means such as a keyboard and a mouse, a storage means such as a magnetic disk device, a display means and a CPU to execute. A program can be provided.

In the above-described embodiment, an example in which development is performed in two stages at the maximum has been described. However, it may be configured so as to be developed in a plurality of stages as required.
Moreover, although the example of the MOS transistor was mainly given as a device, it can process similarly about devices, such as a resistor and a capacitor | condenser.
In addition, parameters specified when developing a model pattern are not limited to F, M, and the like, and various parameters can be specified according to applications and purposes.

  In the above-described embodiment, the analog functional block design system is configured by using one computer, but may be configured by using a plurality of computers.

A semiconductor integrated circuit that performs analog operations even if it has external digital signal interfaces such as inverters and flip-flops, as well as analog functional blocks that have external analog signal interfaces such as operational amplifiers, AD converters, and DA converters It can be used in a system for designing an analog functional block of a circuit.
Further, the present invention can be used for a program that causes a computer to function as a system for designing the analog functional block.

It is a figure which shows the analog functional block design system which concerns on embodiment of this invention, and the process outline | summary of a program. It is a figure which shows the outline | summary of the design scale which the analog functional block design system which concerns on embodiment of this invention processes. It is explanatory drawing explaining the process in embodiment of this invention, and is a response | compatibility figure of an arrangement | sequence list format, a symbol figure format layout, and a standard format format layout. It is a flowchart which shows the basic process sequence of the analog functional block design system which concerns on embodiment of this invention. It is a flowchart which shows the detail of the one part processing procedure of the analog functional block design system which concerns on embodiment of this invention. It is a flowchart which shows the detail of the one part processing procedure of the analog functional block design system which concerns on embodiment of this invention. It is explanatory drawing which shows the detail of the one part processing procedure of the analog functional block design system which concerns on embodiment of this invention. It is a flowchart which shows the detail of the one part processing procedure of the analog functional block design system which concerns on embodiment of this invention. It is explanatory drawing which shows the detail of the one part processing procedure of the analog functional block design system which concerns on embodiment of this invention. It is explanatory drawing which shows the data conversion processing function of the analog functional block design system which concerns on embodiment of this invention. It is explanatory drawing which shows the data conversion processing function of the analog functional block design system which concerns on embodiment of this invention. It is a flowchart which shows the detail of the process sequence of the analog functional block design system which concerns on embodiment of this invention. 1 is a block diagram of an analog functional block design system according to an embodiment of the present invention. It is a figure which shows the basic model pattern used in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the content of the dialog window in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the display of the symbolic layout window in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of expansion | deployment from a basic model pattern to a 1st expansion | deployment model pattern in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of expansion | deployment from a 1st expansion | deployment model pattern to a 2nd expansion | deployment model pattern in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of expansion | deployment from a 1st expansion | deployment model pattern to a 2nd expansion | deployment model pattern in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of expansion | deployment from a 1st expansion | deployment model pattern to a 2nd expansion | deployment model pattern in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of expansion | deployment from a 1st expansion | deployment model pattern to a 2nd expansion | deployment model pattern in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of the basic model pattern used in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of expansion | deployment from a basic model pattern to a 2nd expansion | deployment model pattern in the analog functional block design system which concerns on embodiment of this invention. It is an example of the basic model symbol figure format layout containing the wiring used in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of expansion | deployment from a basic model pattern to a 2nd expansion | deployment model pattern in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of expansion | deployment of the switch circuit in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the development example of the differential pair circuit in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the current mirror circuit developed in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the expansion example of the latch circuit in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the development example of the latch circuit in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the development example of the latch circuit in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the example of a mode of the change process in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the format conversion process in the analog functional block design system which concerns on embodiment of this invention. It is a figure which shows the format conversion process in the analog functional block design system which concerns on embodiment of this invention. It is a figure explaining the process of the conventional analog functional block design system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display part 2 ... CPU
DESCRIPTION OF SYMBOLS 3 ... Input part 4 ... Storage part 5 ... Dialog window 6 ... Symbolic layout window 7 ... Keyboard 8 ... Mouse 9 ... Data storage part 10 ... File storage part

Claims (12)

Storage means for storing array list data representing device arrays as characters and symbol graphic data representing the devices as symbol graphics;
An input means for inputting netlist information of the circuit to be designed;
Display means for displaying at least a dialog window and a symbolic layout window;
An array list corresponding to the net list information is generated using the array list data stored in the storage means, and a symbol graphic format layout corresponding to the array list is generated using the symbol graphic data stored in the storage means. An analog functional block design system comprising: layout processing means for generating and displaying the array list and the symbol graphic format layout in a dialog window and a symbolic layout window. The device is a MOS transistor, a bipolar transistor, a capacitor, or a resistor, and the symbolic layout window has at least two types of a first mesh that defines an arrangement position of the device and a second mesh that defines an arrangement position of wiring. Is defined and consists of
2. The analog functional block design according to claim 1, wherein the layout processing means arranges and displays the device and the wiring in the symbolic layout window so as to be aligned with the first and second meshes, respectively. system.   The dialog window displays an array list of basic model patterns corresponding to the net list information of the circuit to be designed, and the symbolic layout window displays a layout in a symbol graphic format corresponding to the array list of the basic model patterns. The analog functional block design system according to claim 2, wherein:   The layout processing means corresponds to the expansion means for generating a first expansion model pattern arrangement list by performing a first expansion on the basic model pattern with respect to a predetermined parameter, and the first expansion model pattern arrangement list. 4. The analog functional block design system according to claim 3, further comprising layout generation means for generating a symbol graphic layout and displaying it in the symbolic layout window.   The expansion means further performs a second expansion on the first expansion model pattern with respect to a predetermined parameter to generate an array list of second expansion model patterns, and the layout generation means further includes the second expansion model pattern. 5. The analog functional block design system according to claim 4, wherein a layout in a symbol graphic format corresponding to the array list is generated and displayed in the symbolic layout window.   In the display of the device in the dialog window, at least one character corresponds to the device, and when the device is a MOS transistor, the presence direction of either the source or drain terminal is represented by at least one character. The analog functional block design system according to claim 1, wherein the system is described on one side of a character representing the character.   The expansion unit includes at least one of a diffusion shared expansion unit that performs expansion using diffusion sharing at the time of expansion and a packing unit that performs packing when there is a gap between the devices that are laid out. Item 6. The analog functional block design system according to Item 4 or 5.   8. The design object circuit includes a bias circuit or a switch circuit whose function can be configured by at least one MOS transistor, and the layout processing means parallelizes the MOS transistors. An analog functional block design system according to any one of the above.   The circuit to be designed has a differential pair circuit, a current mirror circuit, or an inverter circuit that can be configured by at least two MOS transistors, and the layout processing means parallelizes the MOS transistors. The analog functional block design system according to any one of claims 1 to 7.   When the layout processing means displays an array list of basic model patterns corresponding to the net list information of the circuit to be designed, the connection information of the basic model pattern and the net list information of the circuit to be designed, which are made into a library, The analog function block design system according to any one of claims 3 to 5, wherein the matching sequence list is displayed by collating.   11. The analog functional block design system according to claim 1, further comprising conversion means for converting circuit graphic data in GDS or OASYS format into layout data in a corresponding symbol graphic format.   A program for causing a computer to function as the analog functional block design system according to any one of claims 1 to 11.

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