JP2009086252A - Image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the increase of a leak current caused by threshold voltage shift of a switching element in an image display apparatus. <P>SOLUTION: The image display apparatus includes: an organic light emitting device OLED; a driving transistor Td for controlling light emission of the organic light emitting device OLED; a capacity Cs connected to the driving transistor Td; a power line 10 for supplying a power source voltage to the organic light emitting device OLED; an image signal line 14 for outputting image data corresponding to emission luminance of the organic light emitting device OLED; a switching transistor Ts for controlling timing when image data are supplied to the capacity Cs; a switching transistor Ts_dum inserted in series between the image signal line 14 and the switching transistor Ts; and a scan line 13 for controlling conduction of the switching transistor Ts and the switching transistor Ts_dum. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image display device such as an organic EL display device.

  Conventionally, there has been proposed an image display device using an organic EL (Electroluminescence) element having a function of generating light by recombination of holes and electrons injected into a light emitting layer.

  In this type of image display device, for example, a thin film transistor (hereinafter referred to as “TFT”) formed of amorphous silicon, polycrystalline silicon, or the like, or an organic light emitting diode (Organic Light Emitting Diode): (Hereinafter referred to as “OLED”) constitutes each pixel, and each pixel is arranged in a matrix. Then, by setting an appropriate current value for each pixel, the luminance of each pixel is controlled, and a desired image is displayed (for example, Non-Patent Document 1).

S. Ono, et al. (2003). Pixel Circuit for a-Si AM-OLED. Proceedings of IDW '03, pp. 255-258.

  By the way, in a TFT (particularly in the case of amorphous silicon) used in this type of image display device, the threshold voltage for determining the on-voltage of the TFT when a high voltage negative bias is continuously applied between the gate and the source. The inventors of the present application have found that the phenomenon that the value voltage shifts to the negative side occurs.

  For example, when the threshold voltage of the TFT that controls the supply of the image data potential according to the light emission luminance of the OLED shifts in the negative direction, the off-current (leakage current) in the TFT increases. As a result, the light emission current flowing through the OLED fluctuates, and there is a problem in that the contrast ratio may be reduced or uneven brightness may occur.

  The present invention has been made in view of the above, and an object of the present invention is to provide an image display device capable of suppressing an increase in leakage current due to a threshold voltage shift of a TFT.

  In order to solve the above-described problems and achieve the object, an image display device according to the present invention includes a light-emitting element, a drive element that controls light emission of the light-emitting element, a capacitive element connected to the drive element, A power supply line for supplying a power supply voltage to the light emitting element, an image signal line for outputting image data corresponding to the light emission luminance of the light emitting element, and a first switching element for controlling timing for supplying the image data to the capacitor element; A second switching element inserted in series between the image signal line and the first switching element; and a scanning line for controlling conduction of the first switching element and the second switching element. It is characterized by.

  The image display apparatus according to the next invention is the image display device according to the above invention, wherein one end is connected to a connection end between the first switching element and the second switching element, and the other end is connected to the scanning line. It further comprises a capacitive element.

  In the image display device according to the next invention, in the above invention, one end is connected to a connection end between the first switching element and the second switching element, and the other end is connected to the first capacitance element. And a third capacitor element connected to a potential line that maintains a substantially constant potential during the period in which the voltage is held.

In the image display device according to the next invention, in the above invention, the power supply voltage when the light emitting element emits light is VDD, and the control voltage when the first switching element and the second switching element are on-controlled. VgH and a control voltage when VgL is controlled to be VgL, the capacitance value C2 of the second capacitance element and the capacitance value C3 of the third capacitance element satisfy the condition of the following equation: To do.
C2 / (C2 + C3) ≦ VDD / (VgH−VgL)

In the image display device according to the next invention, in the above invention, when at least one of the second capacitor element and the third capacitor element is used as a parasitic capacitor, the power source for causing the light emitting element to emit light is used. The voltage VDD, the control voltage VgH when the first switching element and the second switching element are on-controlled, and the control voltage VgL when the off-control are satisfied satisfy the condition of the following expression.
VDD / (VgH−VgL)> C2 / (C2 + C3)

  According to the image display device of the present invention, the negative voltage stress received by the first switching element is reduced by the second switching element inserted in series between the image signal line and the first switching element. There is an effect that an increase in leakage current due to a threshold voltage shift of one switching element can be suppressed.

  Hereinafter, an image display device according to a preferred embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

(Configuration of pixel circuit for solving the problem of the present application)
First, a configuration of a suitable pixel circuit for solving the problem of the present application will be described. FIG. 1 is a diagram showing a configuration of a pixel circuit constituting one pixel of an image display device according to a preferred embodiment of the present invention. As shown in the figure, this pixel circuit is connected in series so as to control the electrical connection between the organic light emitting element OLED, the drive transistor Td, the storage capacitor Cs (capacitance element), and the storage capacitor Cs and the image signal line 14. Switching transistors Ts and Ts_dum, and an additional capacitor Csel (second capacitor element) and an additional capacitor Cz (third capacitor element) added to the connection end of the switching transistor Ts and the switching transistor Ts_dum. Yes.

In FIG. 1, a drive transistor Td is a drive element for controlling the amount of current flowing through the organic light emitting element OLED in accordance with the potential difference applied between the gate electrode and the source electrode. The organic light emitting device OLED has a structure including at least an anode layer, a cathode layer, and a light emitting layer that is interposed between the anode layer and the cathode layer and made of an organic material. As the material for the anode layer and the cathode layer, Al or an alloy of Al and Nd, other Al alloys, Cu, ITO (Indium Tin Oxide), Mg, Ca, Al, IZO, and other metal materials are used. Al is used as the anode layer, and a laminate of Mg and Ca is used as the cathode layer. As the material for the light emitting layer, organic materials such as phthalocyanine, trisaluminum complex, benzoquinolinolato, and beryllium complex are used. Such an organic light emitting device OLED has a function of generating light by recombination of holes and electrons injected into the light emitting layer.

  The drive transistor Td and the switching transistors Ts and Ts_dum are configured by, for example, thin film transistors (TFTs). The switching transistor Ts corresponds to the first switching element in the present invention, and the switching transistor Ts_dum corresponds to the second switching element in the present invention. As for the channel (N-type or P-type) of each thin film transistor, either N-type or P-type may be used, but in this embodiment, the case of using the N-type is shown as an example.

  The power line 10 supplies a predetermined voltage to one end of the drive transistor Td and the storage capacitor Cs. The scanning line 13 supplies a control signal for controlling the switching transistors Ts and Ts_dum. The image signal line 14 supplies an image signal (image data) corresponding to the light emission luminance of the organic light emitting element OLED. The storage capacitor Cs is a capacitive element that holds the image data potential supplied from the image signal line 14. For example, one end of the storage capacitor Cs is connected to the power supply line 10 and the other end (forms a connection end A in the figure). Is connected to the gate electrode of the driving transistor Td (also the drain electrode of the switching transistor Ts).

  The switching transistor Ts_dum and the additional capacitors Csel and Cz are TFTs and capacitor elements added to reduce excessive stress (“negative voltage stress” described later) that the switching transistor Ts receives. The drain electrode forming one end of the switching transistor Ts_dum is connected to the source electrode of the switching transistor Ts, and the source electrode forming the other end is connected to the image signal line 14. One end of the additional capacitor Csel is connected to a connection end (connection end B in the drawing) of the switching transistor Ts and the switching transistor Ts_dum, and the other end is connected to the scanning line 13. On the other hand, one end of the additional capacitor Cz is connected to the connection terminal B in the same manner as the additional capacitor Csel, and the other end is connected to the control line 15.

  In the configuration of FIG. 1, the anode side of the organic light emitting element OLED is connected to the ground line, and the cathode electrode side is connected to the power line 10. However, the anode side of the organic light emitting element OLED is connected to the power line 10. In addition, the cathode electrode side may be connected to the ground line, or power supply lines may be connected to both sides of the organic light emitting element OLED to vary the potentials of both power supply lines.

  In the configuration of FIG. 1, the anode common configuration is such that the cathode electrode of the organic light emitting element OLED and the drain electrode of the driving transistor Td are connected. However, the source electrode of the driving transistor Td and the anode electrode of the organic light emitting element OLED are used. It is good also as a structure of the cathode common which connects to.

  In the configuration of FIG. 1, a configuration in which the other end of the additional capacitor Cz is connected to the control line 15 is shown, but the configuration is not limited to this configuration. The control line 15 only needs to have a function of supplying a constant potential in a writing period to be described later. Therefore, in the configuration of FIG. 1, for example, the power supply line 10 can be selected as the connection destination of the other end of the additional capacitor Cz. As an alternative to the power supply line 10, not only a power supply line in its own pixel circuit but also a power supply line of another pixel circuit may be used.

(Operation of basic pixel circuit)
Before describing the operation of the pixel circuit of FIG. 1 according to the present embodiment, a pixel circuit in which the switching transistor Ts_dum and the additional capacitors Csel and Cz are omitted from the configuration of FIG. 1 (hereinafter referred to as “basic pixel circuit”). ) Will be described with reference to FIGS.

  FIG. 2 is a diagram showing the configuration of the basic pixel circuit defined here, and FIG. 3 is a sequence diagram for explaining the operation of the pixel circuit of FIG. Note that the pixel circuit of FIG. 2 is generally divided into three operation periods such as a duty adjustment period, a writing period, and a light emission period as shown in FIG. In these operation periods, the duty adjustment period and the writing period are positioned as a preparation period (non-light emission period) for light emission control, and a frame operation in which the non-light emission period and the light emission period are one frame is performed by the image display device. It is repeatedly executed in each pixel circuit, and a desired image is displayed on a display panel of an image display device (not shown).

  In FIG. 3, in the non-light emitting period, the power supply line 10 is set to GND, and the image data potential (Vdata ′) of the previous frame stored / held in the holding capacitor Cs is changed to a new image data potential (Vdata). For this purpose, that is, a process for changing the light emission luminance is executed. Note that the light emission luminance changing process is executed by changing the potential of the image signal line 14 from VdL to Vdata in the writing period. On the other hand, in the light emission period, the power line 10 is set to −VDD (<GND), and the image data potential stored / held in the storage capacitor Cs is applied between the gate and source of the drive transistor Td. The organic light emitting element OLED is controlled to emit light.

Next, changes in the bias voltage (hereinafter referred to as “Vgs”) applied between the gate and the source of the switching transistor Ts during the light emission period and the non-light emission period will be described with reference to FIGS. 4 and 5. Here, FIG. 4 is a diagram showing a potential and a potential difference generated in the main part of the basic pixel circuit during the light emission period, and FIG. 5 is a main part of the basic pixel circuit in the non-light emission period (Duty adjustment period). It is a figure which shows the electric potential and electric potential difference which arise in this. In the following description, the source refers to the low potential side of the current path flowing through the transistor, and the drain refers to the high potential side of the current path flowing through the transistor. Therefore, the name of a transistor terminal may be changed depending on the magnitude relationship between the potentials of the source and the drain.

In FIG. 4, during the light emission period, the power supply line 10 is set to −VDD, and the scanning line 13 is set to VgL. Further, since the voltage Vdata is stored / held in the storage capacitor Cs, the potential Va at the connection end A during the light emission period is expressed by the following equation.
Va = Vdata−VDD (1)

Therefore, Vgs of the switching transistor Ts during the light emission period (hereinafter referred to as “Vgs_emit”) is expressed by the following equation.
Vgs_emit = VgL−Va = VgL− (Vdata−VDD) (2)

On the other hand, in FIG. 5, the power supply line 10 is set to GND and the scanning line 13 is set to VgL during the non-light emitting period. The storage capacitor Cs stores / holds the voltage of Vdata (actually, the image data potential Vdata ′ in the previous frame is held, but Vdata ′ = Vdata from the viewpoint of ease of explanation). Therefore, the potential Va at the connection end A during the non-light emitting period is expressed by the following equation.
Va = Vdata (3)

Therefore, Vgs of the switching transistor Ts during the non-light-emitting period (hereinafter referred to as “Vgs_vanish”) is expressed by the following equation.
Vgs_vanish = VgL−Va = VgL−Vdata (4)

  As shown in the sequence diagram of FIG. 3, the switching transistor Ts is controlled to be off during the light emission period and the non-light emission period (except for the writing period (only when data is written to itself)).

Here, the gate-source voltage necessary for controlling the switching transistor Ts to be off is represented by Vgs_off. Then, in the light emission period, it is necessary to satisfy the following conditional expression as a condition necessary for circuit operation.
Vgs_emit = VgL− (Vdata−VDD) ≦ Vgs_off (5)
Note that “Vgs_off” in the above equation is a constant set based on the VI characteristics of the switching transistor Ts, the specifications of the image display device, and the like.

When the above equation (5) is transformed,
VgL ≦ (Vdata−VDD) + Vgs_off (6)
It becomes.

Vdata is an image data potential supplied from the image signal line 14 corresponding to the gradation, and normally takes the lowest potential during the lowest gradation display and takes the highest potential during the highest gradation display. Now, assuming that the minimum potential is VdL, the conditional expression to be satisfied by VgL is expressed by the following expression by substituting VdL into Vdata in the above expression (6).
VgL ≦ (VdL−VDD) + Vgs_off (7)
That is, in order to control the switching transistor Ts to be turned off during the light emission period, “VgL” may be set to “VdL−VDD + Vgs_off” or less.

Note that the above equation (5) is a conditional equation calculated by paying attention only to Vgs (that is, Vgs_emit) during the light emission period, but this conditional equation is automatically satisfied even during the non-light emission period. Because from the relational expression (4) and (5) above,
Vgs_vanish <Vgs_emit (8)
Therefore, “VgL” that satisfies the equation (7) is automatically Vgs_vanish <Vgs_off (9)
It is because it will satisfy.

(Stress received by the switching transistor Ts)
Next, the stress received by the switching transistor Ts will be described. This stress is caused by continuous application of an excessive negative voltage between the gate and the source of the switching transistor Ts as described later, and is hereinafter referred to as “negative voltage stress”.

Here, the relationship between the above three members Vgs_vanish, Vgs_emit, and Vgs_off is organized.
First, from the above equations (5) and (8), there is an inequality relationship shown in the following equation.
Vgs_vanish <Vgs_emit ≦ Vgs_off (10)
Further, from the above equations (2) and (4), the relationship of the following equation is also established.
Vgs_vanish = Vgs_emit−VDD (11)

  Therefore, when VgL that satisfies the above expressions (10) and (11) is set, a gate potential lower than that when the switching transistor Ts is set to OFF is applied during the non-light emitting period. Become. That is, excessive negative voltage stress is applied during the non-light emitting period. In particular, when high gradation display is performed in the previous frame, since a high potential is set for Vdata, the negative voltage stress received by the switching transistor Ts increases.

Of Vdata stored / held in the storage capacitor Cs, when the highest gradation display is VdH and the lowest gradation display is VdL, the most severe conditional expression representing the negative voltage stress applied to the switching transistor Ts is ( 4) Next, set Vdata = VdH, and in equation (6), set Vdata = VdL,
Vgs_vanish = VgL−VdH (12)
VgL = VdL−VDD + Vgs_off (13)
And by substituting equation (13) into equation (12),
Vgs_vanish = (VdL−VDD + Vgs_off) −VdH
= (VdL-VdH) -VDD + Vgs_off (14)
Is obtained.

  For example, when VdL = 0 [V], VdH = 10 [V], VDD = 15 [V], and Vgs_off = −5 [V] are used as typical values, VgL = (VdL−VDD) Since + Vgs_off = 0− (15) −5 = −20, it is necessary to set VgL to about −20 [V].

  In this case, Vgs_vanish = VgL−Vdata = −20−Vdata, but Vdata has a relationship of VdL ≦ Vdata ≦ VdH. Therefore, assuming the most severe case, Vgs_vanish = −20−VdH = −20−10 = −30, and the negative voltage stress on the switching transistor Ts reaches −30 [V].

(Characteristic change due to negative voltage stress)
FIG. 6 is a diagram illustrating a change in characteristics of the switching transistor Ts to which a negative voltage stress is applied. More specifically, under an environment of 60 ° C., an initial state IV characteristic (waveform K1) and a voltage pulse simulating a driving time between the gate and the source of the switching transistor Ts were continuously applied for 24 hours. The IV characteristics (waveform K1 ′) immediately after are plotted. Although detailed calculations are omitted, the threshold voltage in the waveform in the initial state is “0.06 V”, whereas the threshold voltage in the waveform after 24 hours is “−2.61 V”. It is. Therefore, a threshold voltage shift of “−2.67 V” occurs in the waveform after 24 hours compared to the waveform in the initial state.

  Due to this threshold voltage shift, even when the lowest gradation is displayed, the switching transistor Ts cannot sufficiently turn off the connection between the image signal line 14 and the storage capacitor Cs. A leak current from the image signal line 14 toward the storage capacitor Cs flows as shown in FIG.

  Here, it is estimated from the example shown in FIG. 6 how much value the magnitude of the leakage current takes. In FIG. 6, a thick solid line N1 is a straight line drawn parallel to the vertical axis at a position of Vgs = −5 V where the switching transistor Ts is turned off. Therefore, the intersection M1 between the waveform K1 and the straight line N1 represents the leakage current in the initial state, and the intersection M1 'between the waveform K1' and the straight line N1 represents the leakage current after 24 hours. As shown in the figure, the current value at the intersection M1 'is increased by one digit or more as compared with the current value at the intersection M1.

  The leakage current as described above flows into the storage capacitor Cs and raises the potential of the connection end A. As a result, the current flowing through the organic light emitting element OLED increases and the luminance of the pixel circuit emits light brighter than intended, which may cause a display abnormality such as a decrease in contrast ratio and occurrence of luminance unevenness.

(Problem solving method according to the present invention)
Next, a method for solving the above-described problem according to the present invention, that is, a technique for suppressing an increase in leakage current due to a threshold voltage shift of the TFT will be described.

  In the above, the characteristic change of the switching transistor Ts has been described as a cause of display abnormality in the image display apparatus. This characteristic change is largely caused by an increase in the leakage current of the switching transistor Ts, and is a phenomenon caused mainly by excessive negative voltage stress on the switching transistor Ts. That is, in order to improve the display abnormality that occurs in the image display device, it is only necessary to reduce the negative voltage stress (particularly, the negative voltage stress during the non-light emitting period) that the switching transistor Ts receives.

  Therefore, in this embodiment, the switching transistor Ts_dum, the additional capacitor Csel, and the additional capacitor Cz shown in FIG. 1 are provided. These configurations produce the following effects.

(1) Two connection ends are formed between the image signal line 14 and the storage capacitor Cs. That is, the connection end A to which the switching transistor Ts and the storage capacitor Cs are connected and the connection end B to which the switching transistor Ts and the switching transistor Ts_dum are connected are formed.
(2) The potential Vb at the connection end B is adjusted by the additional capacitance Csel provided between the connection end B and the scanning line 13 and the additional capacitance Cz provided between the connection end B and the control line 15. Thus, the negative voltage stress on the switching transistor Ts is reduced. These additional capacitors Csel and Cz have an effect of reducing negative voltage stress on the switching transistor Ts_dum.

(Negative voltage stress received by the switching transistors Ts and Ts_dum)
Next, in the pixel circuit according to the present embodiment, the negative voltage stress received by the switching transistors Ts and Ts_dum will be described by distinguishing between a light emitting period and a non-light emitting period.

(Negative voltage stress during the light emission period)
Now, when the potentials of the connection terminals A and B during the light emission period are set as “Va_emit” and “Vb_emit”, the respective sizes can be expressed by the following equations.
Va_emit = Vdata−VDD (15)
Vb_emit = Vdata−Csel / (Csel + Cz) × (VgH−VgL) (16)

In the above equation, VgL is Va_emit during the light emission period VgL−Va_emit ≦ Vgs_off (17)
The voltage is set so as to satisfy.

However, Va_emit and Vb_emit are
Va_emit> Vb_emit (18)
When taking the value
Vgs_emit = VgL−Va_emit <Vgs_off (19)
VgL-Vb_emit> VgL-Va_emit (20)
From the relationship between the two,
VgL-Vb_emit> Vgs_off (21)
In other cases, the source of the switching transistor Ts is changed from the point A to the point B, and a leakage current from the connection end A toward the connection end B flows. To prevent this leakage current,
Va_emit <Vb_emit (22)
It is preferable to design Csel and Cz so as to satisfy the above.
Specifically, from the above equations (15) and (16),
VDD <(Csel / (Csel + Cz)) × (VgH−VgL) (23)
Csel and Cz may be designed so as to satisfy the relationship.

As can be understood from the equations (15) and (16),
VDD = (Csel / (Csel + Cz)) × (VgH−VgL) (24)
In this case, the negative voltage stress received by the switching transistors Ts and Ts_dum during the light emission period is theoretically equal.

(Negative voltage stress during non-emission period)
Further, when the potentials of the connection terminals A and B during the non-light emitting period are set as “Va_vanish” and “Vb_vanish”, the respective sizes can be expressed by the following equations.
Va_vanish = Vdata (25)
Vb_vanish = Vdata−Csel / (Csel + Cz) × (VgH−VgL)
... (26)

By the way, the negative voltage stress received by the switching transistor Ts is larger in the non-light emitting period than in the light emitting period, and is highest when high gradation display is performed in the previous frame during the non-light emitting period. This is as described above. On the other hand, in the pixel circuit of this embodiment, as is clear from the relationship between the above expressions (25) and (26),
Va_vanish> Vb_vanish (27)
The inequality is established.
Therefore, the source of the switching transistor Ts is changed from the connection end A to the connection end B, and the sources of the switching transistors Ts and Ts_dum coincide at the same connection end B. In this case, as apparent from a comparison between the above formulas (15) and (26), Vb_emit in the light emission period and Vb_vanish in the non-light emission period coincide. Therefore, the negative voltage stress received by the switching transistors Ts and Ts_dum is equal to the negative voltage stress received by the switching transistor Ts_dum during the light emission period.

(Calculation of negative voltage stress)
Next, the negative voltage stress in the pixel circuit of the present embodiment is calculated using the same conditions as in the basic pixel circuit. As in the case of the basic pixel circuit, the values of VdL = 0 [V], VdH = 10 [V], VDD = 15 [V], Vgs_off = −5 [V], and VgL = −20 [V] are used. Use. Further, the gate potential when turning on the switching transistors Ts and Ts_dum is VgH, and a value of VgH = 15 [V] is used.

(Calculation of negative voltage stress-during light emission period)
Substituting VDD = -15, VgH = 15, and VgL = -20 in the above formulas (15) and (16), the following formula is obtained.
Va_emit = Vdata-15 (28)
Vb_emit = Vdata−Csel / (Csel + Cz) × (15 − (− 20)) =
Vdata-Csel / (Csel + Cz) × 35 (29)
Now, considering the most severe negative voltage stress, substituting Vdata = VdH = 10 in both the above equations,
In the switching transistor Ts, Vgs_emit = VgL−Va_emit = −20− (10−15) = − 15 [V].
In the switching transistor Ts_dum, Vgs_emit = VgL−Vb_emit = −20− {10−Csel / (Csel + Cz) × 35 = −30 + Csel /
(Csel + Cz) × 35 [V].
Note that, under the above conditions, Csel and Cz are designed as Csel: Cz = 3: 4, so that the negative voltage stresses on the switching transistor Ts and the switching transistor Ts_dum theoretically match.

(Calculation of negative voltage stress-during non-luminous period)
Substituting VgH = 15 and VgL = −20 in the above formulas (25) and (26), the following formula is obtained.
Va_vanish = Vdata (30)
Vb_vanish = Vdata−Csel / (Csel + Cz) × {15 − (− 20)
) = Vdata−Csel / (Csel + Cz) × 35 (31)
As described above, in the non-light emitting period, the source of the switching transistor Ts moves to the connection terminal B, so that the negative voltage stresses on the switching transistor Ts and the switching transistor Ts_dum match. Therefore, substituting Vdata = VdH = 10 into the above equation (31),
Vgs_vanish = VgL−Vb_vanish = −20− {10−Csel / (
Csel + Cz) × 35 = −30 + Csel / (Csel + Cz) × 35 [V].

  As described above, in the pixel circuit of the present embodiment in which the switching transistor Ts_dum, the additional capacitor Csel, and the additional capacitor Cz are provided, the negative voltage stress received by the switching transistor Ts can be reduced. The contents described above can be divided into the basic pixel circuit and the pixel circuit of the present embodiment and arranged as follows.

(Maximum negative voltage stress-basic pixel circuit)
Here, the maximum value of the negative voltage stress received by each switching transistor is defined as the minimum value of the gate-source voltage of each switching transistor (the value is negative and the absolute value takes the maximum value). When defined in this way, the negative voltage stress (Vst) in the basic pixel circuit is maximized in the non-light emitting period, and is given by the following equation based on the above equation (12).
Vst = VgL−VdH (32)

(Maximum negative voltage stress—pixel circuit of the present embodiment—switching transistor Ts)
In the pixel circuit of the present embodiment, the maximum value of the negative voltage stress received by the switching transistor Ts becomes the maximum during the non-light emitting period, and is given by the following equation based on the above equation (26).
Vst = Vdata−Csel / (Csel + Cz) × (VgH−VgL) (33)

(Maximum negative voltage stress—pixel circuit of the present embodiment—switching transistor Ts_dum)
Further, the maximum value of the negative voltage stress received by the switching transistor Ts_dum becomes the maximum during the non-light emitting period, and is given by the following equation based on the above equation (26), as in the case of the switching transistor Ts.
Vst = Vdata−Csel / (Csel + Cz) × (VgH−VgL) (34)

(Consideration on selection of Csel and Cz)
When the configuration according to the present embodiment is adopted, it is preferable to select the additional capacitors Csel and Cz having values as shown below.

(Csel, Cz selection-light emission period)
The potentials of the connection ends A and B during the light emission period can be expressed by the above formulas (15) and (16).
Va_emit = Vdata−VDD (15) (repost)
Vb_emit = Vdata−Csel / (Csel + Cz) × (VgH−VgL) (16) (repost)
On the other hand, in order to reduce the leakage current from the connection end A side to the connection end B side during the light emission period, it is preferable to satisfy the relationship of Va_emit ≦ Vb_emit. When this condition is applied to the expressions (15) and (16), the following conditional expressions are derived.
Csel / (Csel + Cz) ≦ VDD / (VgH−VgL) (35)
Therefore, it is preferable to set the additional capacitors Csel and Cz so as to satisfy the equation (35).

(Csel, Cz selection-non-light emission period)
The potentials of the connection ends A and B during the non-light emitting period can be expressed by the above formulas (25) and (26).
Va_vanish = Vdata (25) (repost)
Vb_vanish = Vdata−Csel / (Csel + Cz) × (VgH−VgL)
... (26) (repost)
On the other hand, in order to keep both the switching transistors Ts and Ts_dum off, it is preferable that both the switching transistors Ts and Ts_dum satisfy Vgs_vanish <Vgs_off. At this time,
Vgs = VgL− (Vdata−Csel / (Csel + Cz) × (VgH−VgL)) ≦
Vgs_off (36)
As Csel and Cz satisfying this conditional expression,
Csel / (Csel + Cz) ≦ (Vgs_off−VgL + Vdata) × (VgH−VgL) (37)
Is obtained.
Here, Vdata takes a voltage value corresponding to the gradation, but in the above equation, since it is the most severe condition at the time of the lowest gradation display, “VdL” is substituted for “Vdata” in the above equation (37). By doing
Csel / (Csel + Cz) ≦ (Vgs_off−VgL + VdL) / (VgH−VgL)) (38)
Is obtained.
However, VgL is shown in the above equation (7).
VgL ≦ (VdL−VDD) + Vgs_off (7) (repost)
Therefore, in the above equation (7), when the equal sign holds, that is, by substituting “(VdL−VDD) + Vgs_off” for “VgL”, the following conditional expression is derived: .
Csel / (Csel + Cz) ≦ VDD / (VgH−VgL) (39)
This conditional expression is the same as the above expression (35). That is, the condition regarding the selection of the additional capacitors Csel, Cz is sufficient considering either the light emission period or the non-light emission period. Regarding the selection of the additional capacities Csel and Cz, in the expressions (35) and (39), the condition that the equal sign is satisfied, that is,
Csel / (Csel + Cz) = VDD / (VgH−VgL) (40)
It is more preferable to select additional capacitors Csel and Cz that satisfy the above. By selecting such additional capacitors Csel and Cz, the negative voltage stress reduction effect can be increased, and leakage current that may flow during the light emission period is prevented or reduced, and the light emission period and the non-light emission period It becomes possible to equalize the negative voltage stress in the period.

(Characteristic change due to negative voltage stress)
FIG. 8 is a diagram showing a change in characteristics of the switching transistor Ts used in the pixel circuit of the present embodiment. More specifically, under an environment of 60 ° C., an initial state IV characteristic (waveform L1: Ts, waveform L2: Ts_dum) and a voltage pulse that simulates driving at the gate-source of the switching transistor Ts. The IV characteristics (waveform L1 ′: Ts, waveform L2 ′: Ts_dum) immediately after being given continuously for 24 hours are respectively plotted.

In FIG. 8, both the switching transistors Ts and Ts_dum have a threshold voltage shift in the negative direction. As is clear from the comparison with the characteristics of FIG. 6, the threshold voltage shift amount is reduced. ing. Although detailed calculations are omitted, in the switching transistor Ts, the threshold voltages in the initial state waveform and the waveform after 24 hours are “0.43 V” and “−0.43 V”, respectively. The threshold voltage shift is “−0.86 V”. Similarly, in the switching transistor Ts_dum, the threshold voltages in the initial state waveform and the waveform after 24 hours are “0.93 V” and “−0.21 V”, respectively, and the threshold voltage shift is “−1”. .14V ". Considering that the threshold voltage shift of the switching transistor Ts in the basic pixel circuit shown in FIG. 6 is “−2.67 V”, the threshold voltage shift is improved by the pixel circuit of the present embodiment. Becomes clear.
<Plane configuration of pixel circuit>
FIG. 9 is an example of a schematic plan view of a pixel circuit in the image display apparatus according to the present embodiment. In the schematic plan view shown in FIG. 9, 4 (= 2 × 2) pixels arranged in the row and column directions are extracted from a plurality of pixel circuit groups arranged in a matrix, and the switching transistor Ts. , And a switching transistor Ts_dum and additional capacitors Csel and Cz added to the basic pixel circuit. In FIG. 1, the other end of the additional capacitor Cz is connected to the control line, but FIG. 9 shows an example in which the power supply line of the adjacent pixel circuit is used instead of the control line.

  In each pixel circuit shown in FIG. 9, gate metal layers 40 to 44, amorphous silicon (hereinafter referred to as “a-Si”) layers 51 to 58, signal metal layers 61 to 74, and the like are provided on an element substrate (not shown). Is formed. Among these layers, the power line 10 is composed of gate metal layers 40 to 42, the scanning line 13 is composed of gate metal layers 43 and 44, and the image signal line 14 is composed of signal metal layers 61 and 66. Yes.

  In FIG. 1, the switching transistor Ts has a source (drain) connected to the signal metal layer 63, a drain (source) connected to the signal metal layer 62, and a gate connected to the gate metal layer 43. On the other hand, the switching transistor Ts_dum has a source connected to the signal metal layer 62, a drain connected to the signal metal layer 61, and a gate connected to the gate metal layer 43. The additional capacitor Csel has one end connected to the signal metal layer 62 and the other end connected to the gate metal layer 43. The additional capacitor Cz has one end connected to the signal metal layer 62 and the other end connected to the gate metal layer 40. That is, in this pixel circuit, the other end of the additional capacitor Cz is connected to the power supply line of the adjacent pixel circuit, thereby simplifying the wiring structure.

  In the above description, the switching transistor Ts_dum and the additional capacitors Csel and Cz are newly added to the basic pixel circuit shown in FIG. 2, but the pixel circuit is added to the additional capacitors Csel and Cz. You may make it utilize the parasitic capacitance which arises inevitably in forming. By utilizing the parasitic capacitance, an effect that the circuit area can be reduced can be obtained.

In addition, when using the parasitic capacitance, the additional capacitance Csel may be used as the parasitic capacitance and only the additional capacitance Cz may be added. Conversely, the additional capacitance Cz is used as the parasitic capacitance and only the additional capacitance Csel is added. It is good also as composition to do. Further, both the additional capacitors Csel and Cz may be configured as parasitic capacitors. The parasitic capacitance is generated in the process, and it is difficult to control the size of the parasitic capacitance very accurately. For this reason, it is preferable to design the additional capacitors Csel and Cz by selecting a capacitance value having a certain margin within a range that satisfies the above equation (39). That is, when at least one of the additional capacitors Csel and Cz is used as a parasitic capacitor, the power supply line voltage “VDD” and the switching transistors Ts, It is preferable to determine a difference “VgH−VgL” between the gate voltage (VgH) when Ts_dum is turned on and the gate voltage (VgL) when turned off.
VDD / (VgH−VgL)> Csel / (Csel + Cz) (41)

<Application Example to Other Pixel Circuit (Circuit Example 1)>
FIG. 10 is a diagram illustrating a configuration example of another basic pixel circuit different from FIG. The basic pixel circuit shown in FIG. 10 has a control transistor Tth for detecting the threshold voltage of the drive transistor Td, a capacitor Cs1 for holding the detected threshold voltage, and a control in addition to the configuration of FIG. A Tth control line 12 for controlling the transistor Tth is provided. Such a pixel circuit having three transistors has a connecting component portion constituted by a switching transistor Ts and a capacitor Cs2 indicated by a broken line portion 81. For this reason, by inserting a new switching transistor between the image signal line 14 and the switching transistor Ts as in the pixel circuit according to the present embodiment, the same effect as in the present embodiment can be obtained. . In the case of this pixel circuit, the additional capacitor Cz is unnecessary, and a parasitic capacitor may be used as the additional capacitor Csel, or a new capacitor element may be formed.

<Application Example to Other Pixel Circuit (Circuit Example 2)>
FIG. 11 is a diagram illustrating a configuration example of another pixel circuit different from those in FIGS. 2 and 10. The basic pixel circuit shown in FIG. 11 includes a control transistor Tq for changing the connection destination of one end of the capacitor Cs1 and a merge line 12 for controlling the control transistor Tq in addition to the configuration of FIG. Yes. Such a pixel circuit having four transistors also has a connection component portion constituted by the switching transistor Ts and the capacitor Cs2 indicated by the broken line portion 82. For this reason, by inserting a new switching transistor between the image signal line 14 and the switching transistor Ts as in the pixel circuit according to the present embodiment, the same effect as in the present embodiment can be obtained. . Even in the case of this pixel circuit, the additional capacitor Cz is unnecessary, and a parasitic capacitor may be used as the additional capacitor Csel, or a new capacitor element may be formed.

<Other operation examples>
FIG. 12 is a sequence diagram for explaining another operation example of the pixel circuit according to the present invention. The sequence diagram shown in FIG. 12 differs from the sequence diagram shown in FIG. 3 in the method for controlling the scanning line 13. Specifically, in the sequence diagram of FIG. 12, the off potential VgL of the switching transistor Ts is set during the light emission period (the off potential at this time is VgL1) and during the non-light emission period (the off potential at this time is VgL2). 3 is different from the sequence diagram shown in FIG. 3 in that it is divided into two stages.

As described above, in order to control the switching transistor Ts to turn off during the light emission period,
VgL1 = VdL−VDD + Vgs_off (42)
The stress on the switching transistor Ts at this time is
Vgs_emit ′ = VgL1− (Vdata−VDD) (43)
It is expressed.
On the other hand, the negative voltage stress on the switching transistor during the non-emission period is
Vgs_vanish ′ = VgL2− (Vdata−Csel / (Csel + Cz) × (VgH−VgL2)) (44)
It becomes.

Here, the negative voltage stress Vgs_vanish during the non-light emission period in the sequence diagram shown in FIG. 3 is compared with the negative voltage stress Vgs_vanish ′ during the non-light emission period in the sequence diagram shown in FIG.
The negative voltage stress Vgs_vanish during the non-light emission period in the sequence diagram shown in FIG.
Vgs_vanish = VgL1− (Vdata−Csel / (Csel + Cz) × (VgH−VgL1)) (45)
It is expressed.

On the other hand, the negative voltage stress Vgs_vanish ′ during the non-light emitting period in the sequence diagram shown in FIG.
Vgs_vanish ′ = VgL2− (Vdata−Csel / (Csel + Cz) × (VgH−VgL2)) (44) (repost)
It is expressed. Therefore, the difference between the two is
Vgs_vanish′−Vgs_vanish = (VgL2−VgL1) × (1−Cs
el / (Csel + Cz)) (46)
It becomes.

  Therefore, if the condition of “VgL2> VgL1” is satisfied, the negative voltage stress Vgs_vanish ′ during the non-light emission period in the sequence diagram shown in FIG. 12 is more negative than the negative voltage stress Vgs_vanish during the non-light emission period in the sequence diagram shown in FIG. It can be seen that the voltage stress is reduced.

  As described above, the off potential of the scanning line 13 is divided into two stages of VgL1 (during the light emission period) and VgL2 (during the non-light emission period) during the light emission period and the non-light emission period, and the condition of “VgL2> VgL1” is satisfied. By controlling in this way, the negative voltage stress of the switching transistor Ts can be further reduced.

  As described above, the image display device according to the present invention is useful as an invention capable of suppressing an increase in leakage current due to a threshold voltage shift of a TFT.

It is a figure which shows the structure of the pixel circuit which comprises 1 pixel of the image display apparatus concerning suitable embodiment of this invention. FIG. 2 is a diagram illustrating a configuration of a pixel circuit (basic pixel circuit) in which a switching transistor Ts_dum and additional capacitors Csel and Cz are omitted from the configuration of FIG. FIG. 3 is a sequence diagram for explaining the operation of the pixel circuit of FIG. 2. It is a figure which shows the electric potential and electric potential difference which arise in the basic pixel circuit principal part in the light emission period. It is a figure which shows the electric potential and electric potential difference which arise in the basic pixel circuit principal part in a non-light-emission period (Duty adjustment period). It is a figure which shows the characteristic change of the switching transistor Ts to which the negative voltage stress was applied. It is a figure which shows the leak current which flows into a basic pixel circuit. It is a figure which shows the characteristic change of the switching transistor Ts used for the pixel circuit of this Embodiment. It is a schematic plan view of the pixel circuit in the image display device according to the present embodiment. It is a figure which shows the structural example of the other basic pixel circuit different from FIG. It is a figure which shows the structural example of the other pixel circuit different from FIG. 2 and FIG. It is a sequence diagram which shows the other operation example of the pixel circuit of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Power supply line 11 Tth control line 12 Merge line 13 Scan line 14 Image signal line 15 Control line 40-44 Gate metal layer 51-58 a-Si layer 61-74 Signal metal layer Cs, Cs1, Cs2 capacity Csel, Cz Additional capacity OLED organic light emitting device Td drive transistor Ts, Ts_dum switching transistor Tth, Tq control transistor

Claims (6)

A light emitting element;
A driving element for controlling light emission of the light emitting element;
A capacitive element connected to the drive element;
A power supply line for supplying a power supply voltage to the light emitting element;
An image signal line for outputting image data corresponding to the light emission luminance of the light emitting element;
A first switching element that controls timing of supplying the image data to the capacitive element;
A second switching element inserted in series between the image signal line and the first switching element;
A scanning line for controlling conduction of the first switching element and the second switching element;
An image display device comprising:   2. The device according to claim 1, further comprising a second capacitance element having one end connected to a connection end of the first switching element and the second switching element and the other end connected to the scanning line. Image display device.   A potential line that has one end connected to a connection end between the first switching element and the second switching element and the other end maintaining a substantially constant potential during the period in which the image data is held in the first capacitor element. The image display device according to claim 2, further comprising a third capacitance element connected to the. When the power supply voltage when causing the light emitting element to emit light is VDD, the control voltage when turning on the first switching element and the second switching element is VgH, and the control voltage when performing off control is VgL,
4. The image display according to claim 1, wherein a capacitance value C <b> 2 of the second capacitive element and a capacitance value C <b> 3 of the third capacitive element satisfy a condition according to the following expression. apparatus.
C2 / (C2 + C3) ≦ VDD / (VgH−VgL) When at least one of the second capacitive element and the third capacitive element is used as a parasitic capacitance, the power supply voltage VDD when the light emitting element emits light, the first switching element, and the second switching element are turned on. The image display apparatus according to claim 1, wherein the control voltage VgH for control and the control voltage VgL for off-control satisfy a condition according to the following expression.
VDD / (VgH−VgL)> C2 / (C2 + C3) When the control voltage when the first switching element and the second switching element are turned off during the light emission period is VgL1, and the control voltage when the first switching element and the second switching element are turned off during the non-light emission period is VgL2, the condition of the following equation is satisfied. The image display device according to claim 1, wherein:
VgL1 <VgL2

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