JP2009081605A - Inverted class-f amplifying circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-sized inverted class F amplifier that has high efficiency characteristics. <P>SOLUTION: The inverted class-F amplifier is constituted to include a transistor S for outputting an output signal, containing a fundamental angular frequency ω0 element and higher harmonic elements thereof in responde to an input signal, an output terminal connected to an external load, and a load circuit, including an input node to which the output signal, is inputted and an output node connected to the output terminal. In this inverted class-F amplifying circuit, the load circuit includes a first reactance 2-terminal circuit, connected to the input node and a second reactance 2-terminal circuit connected between the other terminal of the first reactance 2-terminal circuit and the ground terminal. The first reactance 2-terminal circuit becomes open for the angular frequencies 2ω0, 4ω0, ..., 2nω0 and terminated in 3ω0, 5ω0, ..., (2m+1)ω0; while the second reactance 2-terminal circuit is formed so as to be terminated in the angular frequencies 3ω0, 5ω0, ..., (2m+1)ω0. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a power amplifier used in a wireless system or the like, and more particularly, to an improvement of an inverse class F amplifier and a harmonic processing circuit therefor.

At present, mobile terminals represented by mobile phones have been widely used, and in order to enable longer battery operation, further reduction of power consumption of components is required. Similarly, low power consumption operation is a prerequisite for satellite and space communication equipment. Among them, the power consumption of the power amplifier of the microwave transmitter occupies about several tens of the whole, and the high efficiency of this power amplifier is the key to realizing further long-time operation of the device. It is known that high efficiency of a microwave power amplifier is achieved by performing harmonic processing. In recent years, the current waveform flowing into the output side of an amplifying transistor is changed to the fundamental wave + odd harmonic component, The following is the principle of the inverse class F amplifier that makes the voltage waveform applied to the output terminal composed of fundamental wave + even harmonic components and eliminates the overlap between the current waveform and voltage waveform in the transistor and suppresses power loss. Has been.

A. Inoue, et al., "Analysis of class-F and inverse class-F amplifiers," IEEE MTT-S Int. Microwave Symp. Dig., Boston, MA Jun. 2000, pp. 775-778. Experiments adjusted to the third harmonic using an external tuner (CJ Wei, et al., “Analysis and experimental waveform study on inverse class-F mode of microwave power FETs,” IEEE MTT-S Int. Microwave Symp. Dig. , Boston, MA Jun. 2000, pp. 525-528. Report of verification experiment adjusted to 3rd harmonic by combining several distributed open-ended constant lines (YY Woo, et al., "Analysis and experiments for high-efficiency class-F and inverse class-F poweramplifiers," IEEE Trans. Micorw. Theory Tech., Vol. 54, no. 5, pp. 1969-1974, May 2006.

We also proposed a harmonic processing circuit for an inverse class F amplifier capable of high order harmonic processing (Ishikawa et al., “Proposal of a harmonic processing circuit for an inverse class F amplifier capable of processing up to an arbitrary order,” Proceedings of the 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Proposal of Harmonic Processing Circuit for Inverse Class F Amplifiers (Ishikawa et al., "Proposal of Harmonic Processing Circuit for Inverse Class F Amplifiers that can Process to Arbitrary Orders," IEICE 2007 General Conference Lecture) Collection of papers,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Proposed harmonic processing circuit for inverse class F amplifier (Ishikawa et al., "Proposal of harmonic processing circuit for inverse class F amplifier capable of processing to arbitrary order," Proceedings of the 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Proposed harmonic processing circuit (Ishikawa et al., “Proposal of harmonic processing circuit for inverse class F amplifier capable of processing up to arbitrary order,” Proceedings of the 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
(Ishikawa et al., “Proposal of Harmonic Processing Circuit for Inverse Class F Amplifiers that can Process to Arbitrary Orders,” Proceedings of the 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Et al., “Proposal of Harmonic Processing Circuit for Inverse Class F Amplifier that can Process to Arbitrary Orders,” Proceedings of the 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Proposal of Harmonic Processing Circuit for Inverse Class F Amplifier that can Process Up to, "Proceedings of the 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Proposal of harmonic processing circuit for inverse class F amplifier, “Proceedings of 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Proposal of harmonic processing circuit, “Proceedings of 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Proposal, “Proceedings of the 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Proceedings of the 2007 IEICE General Conference,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
007 General Conference Proceedings,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
Conference Proceedings,
C-2-26, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
C-2-26,
2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the 7th harmonic.
, 2007-3), succeeded in trial production of a harmonic processing circuit capable of processing up to the seventh harmonic.
3), succeeded in trial production of a harmonic processing circuit capable of processing up to the 7th harmonic.
We have succeeded in making a prototype of a harmonic processing circuit that can process waves.
Has succeeded in making a prototype of a harmonic processing circuit.
The road has been successfully prototyped.
is doing.

The present invention relates to a power amplifier used in a radio system or the like, and more particularly to an amplifier circuit that realizes an inverse class F amplifier more efficiently and in a small size, and an improvement of a harmonic processing circuit therefor.

In order to obtain the above voltage waveform, the load impedance for odd harmonics should be zero at the output terminal of the amplifying transistor. Similarly, to obtain the current waveform, the load impedance for even harmonics can be obtained. Should be infinite. As a problem when realizing this with our proposed method (Reference 4), the present method, which uses the properties of standing waves in a distributed constant line, has a large structure in the low microwave band. This is to prevent downsizing of the class F amplifier circuit. Accordingly, it is desirable to provide a technique for reducing the area required for mounting the inverse class F amplifier circuit on the substrate.
Accordingly, an object of the present invention is to provide an inverse class F amplifier circuit that can be reduced in size with respect to an inverse class F amplifier cited as a high efficiency power amplifier.

According to the present invention, it is possible to provide a small inverse class F amplifier having high efficiency characteristics, and it is possible to directly calculate the element value by a calculation formula when processing higher harmonics. A possible reverse class F load circuit can be provided.

(1) First Embodiment As shown in FIG. 1, an inverse class F amplifier circuit according to an embodiment of the present invention is an amplifier circuit that operates at a basic angular frequency ω ₀ . The inverse class F amplifier circuit includes an input terminal, a DC blocking coupling capacitor C ₀₁ , an input side impedance matching circuit, an amplification transistor S (bipolar transistor in the figure), a base bias inductor L _b, and a collector bias. A choke inductor _Lc , a harmonic processing circuit, an output side fundamental wave impedance matching circuit, a DC blocking coupling capacitor _C02, and an output terminal. The input terminal is a terminal to which an input signal having a basic angular frequency ω ₀ is supplied, and the output terminal is a terminal to which the output signal of the inverse class F amplifier circuit is output to the load _Ro .

The input side fundamental wave impedance matching circuit is used to match the input impedance of the inverse class F amplifier circuit at the fundamental angular frequency ω _{0 with} the output impedance of the signal source connected to the input terminal. The coupling capacitor C ₀₁ is used to block the DC signal. The input-side fundamental wave impedance matching circuit includes an inductor L _i interposed between the coupling capacitor C ₀₂ and the base terminal of the amplifying transistor S, a connection point between the inductor L _i and the coupling capacitor C ₀₁ , and a ground. The capacitor C _i is interposed between the terminals.

The connection point between the coupling capacitor C ₀₁ and the input side impedance matching inductor L _i, a DC voltage is supplied V _bb through the choke inductor L _b for a base bias. The amplifying transistor S outputs an output signal having a fundamental angular frequency ω ₀ from its collector in response to an input signal input from the input terminal. The output signal includes a harmonic component having a fundamental angular frequency ω ₀ . The emitter of the amplifying transistor S is grounded, The collector DC voltage V _cc is supplied through the choke inductor L _c for collector bias. The collector of the amplifying transistor S is connected to a harmonic processing circuit.

  The harmonic processing circuit includes a first reactance two-terminal circuit interposed between the input node and the output node, and a second reactance two-terminal circuit interposed between the output node and the ground terminal. Yes. Here, the input node is a node connected to the collector of the amplifying transistor S, and the output node is a node connected to the output-side fundamental impedance matching circuit.

The first two-terminal reactance circuit, the angular frequency 2ω _0, 4ω _0, ..., becomes open at 2Enuomega _0, and, 3 [omega] _0, 5 [omega] _0, ..., and is configured to be short-circuited in the (2m + 1) ω ₀ . However, n is a natural number of 1 or more, and m is 1 when n is 1 and n is one of n or n-1 when n is 2 or more. The second reactance two-terminal circuit is configured to be short-circuited at angular frequencies 3ω ₀ , 5ω ₀ ,..., (2m + 1) ω ₀ . Here, the reactance two-terminal circuit means a two-terminal circuit having only a reactance element (that is, a capacitor and an inductor) without having a resistance element. The configurations of the first reactance two-terminal circuit and the second reactance two-terminal circuit will be described in detail later.

An output node of the harmonic processing circuit, between the output terminal, and an output side fundamental impedance matching circuit, and a coupling capacitor C ₀₂ are connected in series. The output side fundamental wave impedance matching circuit is used to match the output impedance of the inverse class F amplifier circuit at the fundamental angular frequency ω ₀ with the impedance of the load _Ro . The coupling capacitor _C02 is used to block the DC signal. Output side fundamental impedance matching circuit includes an inductor L _o which is interposed between the output node and coupling capacitor C ₀₂ of the harmonic processing circuit, a connection point of the inductor L _o and the coupling capacitor C ₀₂ grounded It consists interposed by a capacitor C _o between the terminals.

Harmonic processing circuit having the above configuration, even harmonics of the angular frequency 2ω _0, 4ω _0, ..., in 2Enuomega _0, the impedance anticipation of the output terminal side from the input node to infinity, further odd harmonics wave angular frequency 3ω _0, 5ω _0, ..., in (2m + 1) ω _0, to zero impedance in anticipation output terminal side from the input node. At the angular frequencies 2ω ₀ , 4ω ₀ ,..., 2nω _{0 of} even-order harmonics, the first reactance two-terminal circuit is opened, and therefore the impedance expected from the input node to the output terminal is infinite. On the other hand, at the angular frequencies 3ω ₀ , 5ω ₀ ,..., (2m + 1) ω _{0 of} the odd-order harmonics, both the first reactance two-terminal circuit and the second reactance two-terminal circuit are short-circuited. Impedance expecting the output terminal side becomes zero. As described above, it is important to increase the efficiency of power amplification that the harmonic processing circuit of the inverse class F amplifier circuit has such characteristics.
Furthermore, a harmonic processing circuit composed of reactance circuits can be realized with a lumped constant circuit that can be mounted in a small area without using a distributed constant circuit such as a transmission line. Can do.

(2) Second embodiment

FIG. 2 shows an inverse class F amplifier circuit according to the second embodiment of the present invention. In the second embodiment, the second reactance two-terminal circuit interposed between the output node and the ground terminal is changed to the second reactance two-terminal circuit interposed between the input node and the ground terminal. Has been replaced.
The second reactance two-terminal circuit is not only configured to be short-circuited at the angular frequencies 3ω ₀ , 5ω ₀ ,..., (2m + 1) ω ₀ of the odd harmonics, but also the angular frequency 2ω of the even harmonics. ₀ , 4ω ₀ ,..., 2nω ₀ are configured to be open. Here, n is a natural number of 1 or more, and m is 1 when n is 1 or n or n-1 when n is 2 or more.

Again, the harmonic processing circuit, the angular frequency 2 [omega ₀ of even harmonics, 4ω _0, ..., in 2Enuomega _0, the impedance anticipation of the output terminal side from the input node to infinity, further odd harmonics of angular frequency 3ω _0, 5ω _0, ..., in (2m + 1) ω _0, to zero impedance in anticipation output terminal side from the input node. At the angular frequencies 2ω ₀ , 4ω ₀ ,..., 2nω _{0 of} even-order harmonics, both the first reactance two-terminal circuit and the second reactance two-terminal circuit are opened, and therefore the output terminal side is expected from the input node. Impedance becomes infinite. On the other hand, at the angular frequencies 3ω ₀ , 5ω ₀ ,..., (2m + 1) ω _{0 of} odd-order harmonics, the second reactance two-terminal circuit is short-circuited, so that the impedance expected from the input node to the output terminal side is zero. Become.

Similar to the harmonic processing circuit shown in FIG. 1, the harmonic processing circuit of this embodiment is realized by a lumped constant circuit that can be mounted in a small area without using a distributed constant circuit such as a transmission line. Since it is possible, the area can be reduced.
1 and 2, the amplifying transistor S is an HBT (Hetero-junction) that has excellent high frequency characteristics among bipolar transistors.
Bipolar transistors) are preferably used. Furthermore, heterojunction FETs and HEMTs (High Electron Mobility)
Transistor) can be used. If the FET is used, a drain connected to the input node, a source connected to the ground terminal, its gate is connected to the inductor L _i for input matching.

(3) Configuration of reactance two-terminal circuit The impedance characteristics of all reactance two-terminal circuits are classified into the four equations shown in the upper part of Table 1. In the above-described two embodiments, the first reactance two-terminal circuit and the second reactance two-terminal circuit are the first Foster method for performing the equivalent circuit by partially expanding the four equations from the impedance equation or the admittance equation. According to the second method (Table 1), any one of the eight types of circuit configurations listed below is preferable.

(Foster's first method)
1. The first to kLC parallel circuits (where k is a natural number equal to or greater than n) are connected in series between the terminals of the reactance two-terminal circuit (equivalent circuit (1) in Table 1), angular frequencies 2ω ₀ , 4ω ₀ , ..., it becomes a very in 2nω _0, the angular frequency 3ω _0, 5ω _0, ..., is designed to be the zero point in the (2m + 1) ω _0. However, in the second reactance two-terminal circuit in the former form (FIG. 1), it is not necessary to satisfy the pole angular frequency condition.

2. First to kLC parallel circuits (where k is a natural number greater than or equal to n) and one inductor are connected in series between terminals of the reactance two-terminal circuit (equivalent circuit (2) in Table 1) frequency 2ω _0, 4ω _0, ..., become a very in 2nω _0, the angular frequency 3ω _0, 5ω _0, ..., is designed to be the zero point in the (2m + 1) ω _0. However, in the second reactance two-terminal circuit in the former form (FIG. 1), it is not necessary to satisfy the pole angular frequency condition.

3. A first to kLC parallel circuit (where k is a natural number equal to or greater than n) and one capacitor are connected in series between the terminals of the reactance two-terminal circuit (equivalent circuit (3) in Table 1), frequency 2ω _0, 4ω _0, ..., become a very in 2nω _0, the angular frequency 3ω _0, 5ω _0, ..., is designed to be the zero point in the (2m + 1) ω _0. However, in the second reactance two-terminal circuit in the former form (FIG. 1), it is not necessary to satisfy the pole angular frequency condition.

4). The first to kLC parallel circuits (where k is a natural number equal to or greater than n), one inductor, and one capacitor are connected in series between the terminals of the reactance two-terminal circuit (the equivalent circuit in Table 1) 4)), the angular frequency 2ω _0, 4ω _0, ..., becomes extremely in 2Enuomega _0, the angular frequency 3 [omega] _0, 5 [omega] _0, ..., are designed to be zero at the (2m + 1) ω _0. However, in the second reactance two-terminal circuit in the former form (FIG. 1), it is not necessary to satisfy the pole angular frequency condition.

(Foster's second method)
5). A first to (k-1) LC series circuit (where k is a natural number greater than or equal to n), one inductor, and one capacitor are connected in parallel between the terminals of the reactance two-terminal circuit (Table 1). equivalent circuit of the internal (5)), the angular frequency 2ω _0, 4ω _0, ..., becomes extremely in 2Enuomega _0, the angular frequency 3 [omega] _0, 5 [omega] _0, ..., are designed to be zero at the (2m + 1) ω _0. However, in the second reactance two-terminal circuit from the former viewpoint (FIG. 1), it is not necessary to satisfy the pole angular frequency condition.

6). A first to kLC series circuit (where k is a natural number greater than or equal to n) and one inductor are connected in parallel between the terminals of the reactance two-terminal circuit (equivalent circuit (6) in Table 1). frequency 2ω _0, 4ω _0, ..., become a very in 2nω _0, the angular frequency 3ω _0, 5ω _0, ..., is designed to be the zero point in the (2m + 1) ω _0. However, in the second reactance two-terminal circuit from the former viewpoint (FIG. 1), it is not necessary to satisfy the pole angular frequency condition.

7). The first to kLC series circuits (where k is a natural number equal to or greater than n) and one capacitor are connected in parallel between the terminals of the reactance two-terminal circuit (equivalent circuit (7) in Table 1). frequency 2ω _0, 4ω _0, ..., become a very in 2nω _0, the angular frequency 3ω _0, 5ω _0, ..., is designed to be the zero point in the (2m + 1) ω _0. However, in the second reactance two-terminal circuit from the former viewpoint (FIG. 1), it is not necessary to satisfy the pole angular frequency condition.

8). First to (k + 1) LC series circuits (where k is a natural number greater than or equal to n) are connected in parallel between the terminals of the reactance two-terminal circuit (equivalent circuit (8) in Table 1), angular frequency 2ω ₀ , 4ω _0, ..., become a very in 2nω _0, the angular frequency 3ω _0, 5ω _0, ..., is designed to be the zero point in the (2m + 1) ω _0. However, in the second reactance two-terminal circuit from the former viewpoint (FIG. 1), it is not necessary to satisfy the pole angular frequency condition.

The reactance two-terminal circuit derives the element values of each inductor and each capacitor by giving the frequency values of the poles and zeros of the above conditions to the calculation formulas according to the first and second methods of Foster shown in Table 1. Is done.

(1) First Embodiment FIG. 3 shows an inverse class F amplifier circuit according to a first embodiment of the present invention. As the first reactance two-terminal circuit of the harmonic processing circuit, the reactance two-terminal circuit shown in the equivalent circuit (1) in Table 1 is used. The reactance two-terminal circuit 1 includes three LC parallel circuits connected in series.

The capacitances C _{11 to} C ₁₃ of the capacitors constituting the LC parallel circuit and the inductances L _{11 to} L ₁₃ of the inductors are:
Than,
C ₁₁ = 1 / (0.2734M),
C ₁₂ = 1 / (0.2625M),
C ₁₃ = 1 / (0.4641M),
L ₁₁ = 0.2734 M / (2ω ₀ ) ² ,
L ₁₂ = 0.2625 M / (4ω ₀ ) ² ,
L ₁₃ = 0.4641 M / (6ω ₀ ) ² ,
And given. However, M is an arbitrary constant.
When the fundamental frequency f ₀ (= ω ₀ / 2π) is 1 GHz, by setting M to 4 × 10 ¹² ,
C ₁₁ = 0.914 (pF),
C ₁₂ = 0.952 (pF),
C ₁₃ = 0.539 (pF),
L ₁₁ = 6.925 (nH),
L ₁₂ = 1.661 (nH),
L ₁₃ = 1.306 (nH),
Get.

As the second reactance two-terminal circuit, the reactance two-terminal circuit shown in the equivalent circuit (7) in Table 1 is used. The reactance two-terminal circuit includes an LC series circuit and a capacitor connected in parallel.
The capacitances C _{21 to} C ₂₃ of the capacitors constituting the LC series circuit, the inductances L _{21 to} L _{23 of} the inductors, and the capacitor C are as follows:
Than,
C ₂₁ = 10.221ω ₀ ² /M′/(0.1ω ₀
) ² = 1022.1 / M ′,
C ₂₂ = 6.570ω ₀ ² / M ′ / (3ω ₀
² = 0.7300 / M ',
C ₂₃ = 5.200ω ₀ ² / M ′ / (5ω ₀
) ² = 0.2080 / M ',
C = 1 / M ′,
L ₂₁ = M ′ / (10.221ω ₀ ² ),
L ₂₂ = M ′ / (6.570ω ₀ ² ),
L ₂₃ = M ′ / (5.200ω ₀ ² ),
And given. However, M ′ is an arbitrary constant. Also, ω ₁ = 0.1ω ₀ is set so as not to short-circuit at the fundamental wave angular frequency ω ₀ .
When the fundamental frequency f ₀ (= ω ₀ / 2π) is 1 GHz, by setting M ′ to 4 × 10 ¹¹ ,
C ₂₁ = 2.555 (nF),
C ₂₂ = 1.825 (pF),
C ₂₃ = 0.520 (pF),
C = 2. pF5 (pF),
L ₂₁ = 0.991 (nH),
L ₂₂ = 1.542 (nH),
L ₂₃ = 1.948 (nH),
Get.

FIG. 4 shows the impedance frequency characteristics of the harmonic processing circuit in which the capacitances C _{11 to} C ₁₃ , C _{21 to} C ₂₃ , C and the inductor inductances L _{11 to} L ₁₃ and L _{21 to} L ₂₃ are determined. Is shown. The impedance of the harmonic processing circuit viewed from the input node is the even harmonic frequency 2f _0.
, 4f ₀ , 6f ₀ , and becomes infinite at odd-order harmonic frequencies 3f ₀ , 5f ₀ .

FIG. 5 shows the simulation results of the voltage waveform and current waveform at the collector terminal of the amplifying transistor S. As the amplifying transistor S, the saturation collector current at the time of class A bias (collector bias voltage 3.4 V, base bias voltage 1.35 V) is 15 mA, the maximum transmission frequency f _max is 51 GHz, and the current gain cutoff frequency f _T is 34 GHz. HBT is used. In the simulation, a class B bias is applied (collector bias voltage 3.4 V, base bias voltage 1.2 V). As shown in FIG. 5, the instantaneous voltage and the instantaneous current hardly overlap each other. This indicates that the inverse class F amplifier circuit of this embodiment realizes an operation close to an ideal inverse class F operation.

FIG. 6 shows the power added efficiency (PAE) of the inverse class F amplifier circuit of the first embodiment.
Shows Added Efficiency) and output power _{P out.} As shown in FIG. 6, the inverse class F amplifier circuit of the first embodiment can achieve a PAE of 80% or more.

(2) Second Embodiment FIG. 7 shows an inverse class F amplifier circuit according to a second embodiment of the present invention. As the first reactance two-terminal circuit of the harmonic processing circuit, the reactance two-terminal circuit shown in the equivalent circuit (2) in Table 1 is used. The reactance two-terminal circuit 1 includes three LC parallel circuits and an inductor connected in series.

Capacitances C _{11 to} C ₁₃ of the capacitors constituting the LC parallel circuit, inductances L _{11 to} L _{13 of} the inductors, and inductor L are:
Than,
C ₁₁ = 1 / (12.3047 Mω ₀ ² ),
C ₁₂ = 1 / (8.6625 Mω ₀ ² ),
C ₁₃ = 1 / (6.0328 Mω ₀ ² ),
L ₁₁ = 12.3047 Mω ₀ ² / (2ω ₀
) ² = 3.0762M,
L ₁₂ = 8.6625 Mω ₀ ² / (4ω ₀
) ² = 0.5414M,
L ₁₃ = 6.0328 Mω ₀ ² / (6ω ₀
) ² = 0.1676M,
L = M,
And given. However, M is an arbitrary constant.
When the fundamental frequency f ₀ (= ω ₀ / 2π) is 1 GHz, by setting M to 6 × 10 ⁻⁹ ,
C ₁₁ = 0.343 (pF),
C ₁₂ = 0.487 (pF),
C ₁₃ = 0.700 (pF),
L ₁₁ = 18.46 (nH),
L ₁₂ = 3.248 (nH),
L ₁₃ = 1.006 (nH),
L = 6 (nH),
Get.

As the second reactance two-terminal circuit, the reactance two-terminal circuit shown in the equivalent circuit (7) in Table 1 is used. The reactance two-terminal circuit is composed of LC series circuits connected in parallel.
The capacitances C _{21 to} C ₂₄ of the capacitors constituting the LC series circuit and the inductances L _{21 to} L ₂₄ of the inductors are:
Than,

C ₂₁ = 0.2086 / M ′ / (0.1ω ₀ ) ² ,
C ₂₂ = 0.1642 / M ′ / (3ω ₀ ) ² ,
C ₂₃ = 0.2166 / M ′ / (5ω ₀ ) ² ,
C ₂₄ = 0.4105 / M ′ / (7ω ₀ ) ² ,
L ₂₁ = M ′ / (0.2086),
L ₂₂ = M ′ / (0.1642),
L ₂₃ = M ′ / (0.2166),
L ₂₄ = M ′ / (0.4105),
And given. However, M ′ is an arbitrary constant. Also, ω ₁ = 0.1ω ₀ is set so as not to short-circuit at the fundamental wave angular frequency ω ₀ .
When the fundamental frequency f ₀ (= ω ₀ / 2π) is 1 GHz, by setting M ′ to 5 × 10 ⁻¹⁰ ,
C ₂₁ = 1.057 (nF),
C ₂₂ = 0.924 (pF),
C ₂₃ = 0.439 (pF),
C ₂₄ = 0.424 (pF),
L ₂₁ = 2.397 (nH),
L ₂₂ = 3.045 (nH),
L ₂₃ = 2.308 (nH),
L ₂₄ = 1.218 (nH),
Get.

FIG. 8 shows impedance frequency characteristics of the harmonic processing circuit in which the capacitances C _{11 to} C ₁₃ and C _{21 to} C ₂₄ and the inductances L _{11 to} L ₁₃ , L _{21 to} L ₂₄ , and L of the inductor are determined. Show. The impedance of the harmonic processing circuit viewed from the input node is the even harmonic frequency 2f _0.
, 4f ₀ , 6f ₀ , and becomes infinite at odd-numbered harmonic frequencies 3f ₀ , 5f ₀ , 7f ₀ .

FIG. 9 shows the simulation results of the voltage waveform and the current waveform at the collector terminal of the amplifying transistor S. As the amplifying transistor S, the saturation collector current at the time of class A bias (collector bias voltage 3.4 V, base bias voltage 1.35 V) is 15 mA, the maximum transmission frequency f _max is 51 GHz, and the current gain cutoff frequency f _T is 34 GHz. HBT is used. In the simulation, a class B bias is applied (collector bias voltage 3.4 V, base bias voltage 1.2 V). As shown in FIG. 9, the instantaneous voltage and the instantaneous current hardly overlap each other. This indicates that the inverse class F amplifier circuit of this embodiment realizes an operation close to an ideal inverse class F operation.

FIG. 10 shows the power added efficiency (PAE: Power Added) of the inverse class F amplifier circuit of the second embodiment.
Efficiency) and shows the output power _{P out.} As shown in FIG. 6, the inverse class F amplifier circuit of the second embodiment can achieve a PAE of 80% or more.

FIG. 1 is a circuit diagram showing an embodiment of an inverse class F amplifier circuit according to the present invention. FIG. 2 is a circuit diagram showing another embodiment of the inverse class F amplifier circuit according to the present invention. FIG. 3 is a circuit diagram showing a first embodiment of an inverse class F amplifier circuit according to the present invention. FIG. 4 shows the impedance frequency characteristics of the harmonic processing circuit of the first embodiment. FIG. 5 shows a voltage waveform and a current waveform at the collector terminal of the amplifying transistor S. FIG. 6 shows power added efficiency (PAE) and output power P _out of the inverse class F amplifier circuit of the first embodiment. FIG. 7 is a circuit diagram showing a second embodiment of the inverse class F amplifier circuit according to the present invention. FIG. 8 shows the impedance frequency characteristics of the harmonic processing circuit of the second embodiment. FIG. 9 shows a voltage waveform and a current waveform at the collector terminal of the amplifying transistor S. FIG. 10 shows the power added efficiency and output power of the inverse class F amplifier circuit of the second embodiment. This is a first method for making an equivalent circuit of a reactance two-terminal circuit using the Foster method. This is a second technique related to an equivalent circuit of a reactance two-terminal circuit using the Foster method.

Claims (29)

A transistor that outputs an output signal including a component of the fundamental angular frequency ω0 and its harmonic component in response to the input signal;
An output terminal connected to an external load;
A load circuit having an input node to which the output signal is input and an output node connected to the output terminal;
The load circuit is:
A first reactance two-terminal circuit connected between the input node and the output node;
A second reactance two-terminal circuit connected between the output node and a ground terminal;
The first reactance two-terminal circuit is configured to be open at angular frequencies 2ω0, 4ω0,..., 2nω0, and to be short-circuited at 3ω0, 5ω0, ..., (2m + 1) ω0 (where n is 1 or more). M is 1 when n is 1 and n is 1 or 2 when n is 2 or more),
The second reactance two-terminal circuit is an inverse class F amplifier circuit configured to be short-circuited at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. A transistor that outputs an output signal including a component of the fundamental angular frequency ω0 and its harmonic component in response to the input signal;
An output terminal connected to an external load;
A load circuit having an input node to which the output signal is input and an output node connected to the output terminal;
The load circuit is:
A first reactance two-terminal circuit connected between the input node and the output node;
A second reactance two-terminal circuit connected between the input node and a ground terminal;
The first reactance two-terminal circuit is configured to be open at angular frequencies 2ω0, 4ω0,..., 2nω0, and to be short-circuited at 3ω0, 5ω0, ..., (2m + 1) ω0 (where n is 1 or more). M is 1 when n is 1 and n is 1 or 2 when n is 2 or more),
The second reactance two-terminal circuit is an inverse class F amplifier circuit configured to be open at angular frequencies 2ω0, 4ω0,..., 2nω0 and short-circuited at 3ω0, 5ω0,. In the inverse class F amplifier circuit according to claim 1 or 2,
The first reactance two-terminal circuit is:
1st to kth parallel circuit (where k is a natural number greater than or equal to n)
With
The first to kLC parallel circuits are connected in series between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,... (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1 or 2,
The first reactance two-terminal circuit is:
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
An inductor,
The first to kLC parallel circuits and the inductor are connected in series between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1 or 2,
The first reactance two-terminal circuit is:
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
A capacitor,
The first to kLC parallel circuits and the capacitor are connected in series between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1 or 2,
The first reactance two-terminal circuit is:
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
An inductor,
A capacitor,
The first to kLC parallel circuits, the inductor, and the capacitor are connected in series between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1 or 2,
The first reactance two-terminal circuit is:
First to (k-1) LC series circuits (where k is a natural number greater than or equal to n),
An inductor,
A capacitor,
The first to (k-1) LC series circuits, the inductor, and the capacitor are connected in parallel between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1 or 2,
The first reactance two-terminal circuit is:
First to kLC series circuits (where k is a natural number greater than or equal to n),
An inductor,
The first to kLC series circuits and the inductor are connected in parallel between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1 or 2,
The first reactance two-terminal circuit is:
First to kLC series circuits (where k is a natural number greater than or equal to n),
A capacitor,
The first to kLC series circuits and the capacitor are connected in parallel between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1 or 2,
The first reactance two-terminal circuit is:
1st to (k + 1) LC series circuit (where k is a natural number greater than or equal to n)
With
The first to (k + 1) th LC series circuits are connected in parallel between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1,
The second reactance two-terminal circuit is
1st to kth parallel circuit (where k is a natural number greater than or equal to n)
With
The first to kLC parallel circuits are connected in series between terminals of a reactance two-terminal circuit;
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1,
The second reactance two-terminal circuit is
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
An inductor,
The first to kLC parallel circuits and the inductor are connected in series between terminals of a reactance two-terminal circuit;
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1,
The second reactance two-terminal circuit is
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
A capacitor,
The first to kLC parallel circuits and the capacitor are connected in series between terminals of a reactance two-terminal circuit;
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1,
The second reactance two-terminal circuit is
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
An inductor,
A capacitor,
The first to kLC parallel circuits, the inductor, and the capacitor are connected in series between terminals of a reactance two-terminal circuit;
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1,
The second reactance two-terminal circuit is
First to (k-1) LC series circuits (where k is a natural number greater than or equal to n),
An inductor,
A capacitor,
The first to (k-1) LC series circuits, the inductor, and the capacitor are connected in parallel between terminals of a reactance two-terminal circuit;
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1,
The second reactance two-terminal circuit is
First to kLC series circuits (where k is a natural number greater than or equal to n),
An inductor,
The first to kLC series circuits and the inductor are connected in parallel between terminals of a reactance two-terminal circuit;
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1,
The second reactance two-terminal circuit is
First to kLC series circuits (where k is a natural number greater than or equal to n),
A capacitor,
The first to kLC series circuits and the capacitor are connected in parallel between terminals of a reactance two-terminal circuit;
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,... (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 1,
The second reactance two-terminal circuit is
1st to (k + 1) LC series circuit (where k is a natural number greater than or equal to n)
With
The first to (k + 1) th LC series circuits are connected in parallel between terminals of a reactance two-terminal circuit;
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 2,
The second reactance two-terminal circuit is
1st to kth parallel circuit (where k is a natural number greater than or equal to n)
With
The first to kLC parallel circuits are connected in series between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 2,
The second reactance two-terminal circuit is
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
An inductor,
The first to kLC parallel circuits and the inductor are connected in series between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 2,
The second reactance two-terminal circuit is
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
A capacitor,
The first to kLC parallel circuits and the capacitor are connected in series between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,... (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 2,
The second reactance two-terminal circuit is
First to kLC parallel circuits (where k is a natural number greater than or equal to n),
An inductor,
A capacitor,
The first to kLC parallel circuits, the inductor, and the capacitor are connected in series between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,... (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 2,
The second reactance two-terminal circuit is
First to (k-1) LC series circuits (where k is a natural number greater than or equal to n),
An inductor,
A capacitor,
The first to (k-1) LC series circuits, the inductor, and the capacitor are connected in parallel between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 2,
The second reactance two-terminal circuit is
First to kLC series circuits (where k is a natural number greater than or equal to n),
An inductor,
The first to kLC series circuits and the inductor are connected in parallel between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 2,
The second reactance two-terminal circuit is
First to kLC series circuits (where k is a natural number greater than or equal to n),
A capacitor,
The first to kLC series circuits and the capacitor are connected in parallel between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to claim 2,
The second reactance two-terminal circuit is
1st to (k + 1) LC series circuit (where k is a natural number greater than or equal to n)
With
The first to (k + 1) th LC series circuits are connected in parallel between terminals of a reactance two-terminal circuit;
It becomes a pole at angular frequencies 2ω0, 4ω0, ..., 2nω0,
An inverse class F amplifier circuit having a characteristic of having a zero point at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. In the inverse class F amplifier circuit according to any one of claims 1 to 26,
In addition,
An inverse class F amplifier circuit including an impedance matching circuit between the output terminal and the output node. A first reactance two-terminal circuit interposed between an input node receiving an output signal including a component of a fundamental angular frequency ω0 and its harmonic component from a transistor and an output node connected to a load;
A second reactance two-terminal circuit interposed between the output node and the ground terminal;
The first reactance two-terminal circuit is configured to be open at the angular frequencies 2ω0, 4ω0,..., 2nω0, and to be short-circuited at the angular frequencies 3ω0, 5ω0, ..., (2m + 1) ω0 (where n is A natural number of 1 or more, and m is 1 when n is 1 and one of n or n-1 when n is 2),
The second reactance two-terminal circuit is an inverse class F amplifier load circuit configured to be short-circuited at angular frequencies 3ω0, 5ω0,..., (2m + 1) ω0. A first reactance two-terminal circuit interposed between an input node receiving an output signal including a component of a fundamental angular frequency ω0 and its harmonic component from a transistor and an output node connected to a load;
A second reactance two-terminal circuit interposed between the output node and the ground terminal;
The first reactance two-terminal circuit is configured to be open at the angular frequencies 2ω0, 4ω0,..., 2nω0, and to be short-circuited at the angular frequencies 3ω0, 5ω0, ..., (2m + 1) ω0 (where n is A natural number of 1 or more, and m is 1 when n is 1 and one of n or n-1 when n is 2),
The second reactance two-terminal circuit is configured to be open at angular frequencies 2ω0, 4ω0,..., 2nω0 and to be short-circuited at angular frequencies 3ω0, 5ω0,. Load circuit.