JP2009077239A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit which has a large loop gain and makes better phase noise during lock even when the loop gain is not increased. <P>SOLUTION: The PLL circuit is provided, wherein a reference frequency from an input terminal 1 is divided by first and third frequency dividers 2 and 9, an output from a VCO 8 and an output from an oscillator 13 are combined by a mixer 14, and a frequency is selected by an MCF 15a and divided by second and fourth frequency dividers 3 and 10. Outputs from the first and second frequency dividers 2 and 3 are phase-compared by a phase comparator 4 and smoothed by a low-pass filter (LPF) 5, outputs from the third and fourth frequency dividers 9 and 10 are detected in phase advancement or phase delay by a phase advancement/delay detector 11, and integrated by an integrator 12, and a voltage is output. The output from the LPF 5 and the output from the integrator 12 are added by an adder 6 and output to a VCO 8, an output from the MCF 15a is amplified by an amplifier 16 and output to an output terminal 17, and a frequency in the oscillator 13 is adjusted for the reference frequency. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit, and in particular, using an existing oscillator and an inexpensive AT-CUT crystal resonator, even when the loop gain does not increase, the phase noise when locked It is related with the PLL circuit which can improve.

In general, the phase comparison frequency of the PLL uses the same frequency in order to make the phase position at the time of locking constant.
However, if the reference frequency and the frequency of the voltage controlled oscillator are different, it is necessary to divide both frequencies so that the phase comparison frequencies match.

  For example, when the reference frequency is 5.0 MHz and the frequency of the voltage controlled oscillator is 7.68 MHz, the coincidence frequency of both frequencies is 40 kHz. That is, the phase comparison frequency of the reference frequency = reference frequency / 125, and the phase comparison frequency of the frequency of the voltage controlled oscillator = frequency of the voltage controlled oscillator / 192.

When a general PLL loop gain K [rad], a phase comparison sensitivity Kd [V / rad], a voltage-controlled oscillator control sensitivity Kv [rad / V], and an amplifier amplification degree G [times], the loop gain K is represented by the following equation.
K = Kd * Kv * G

Here, as a specific example, the loop gain K is calculated with the design conditions set forth below.
As design conditions, power supply voltage Vcc: 3.3 V, reference frequency fref: 5.0 MHz, output frequency fout: 7.68 MHz, control sensitivity of voltage controlled oscillator: 7.68 MHz ± 150 ppm / 1.65 V ± 1.5 V, The sensitivity Kd of the phase comparator (PFD: Phase Frequency Detector) is 4π [V / rad], and the phase comparison frequency is 40 kHz.

From the above conditions, the loop gain K is
K = Kd * Kv * G
= (3.3V / 4π) * (2π * 40kHz * 150ppm / 1.5V) * G
Depending on the phase comparison frequency, the phase noise of the output frequency of the PLL approaches the reference frequency when the loop gain is large, and approaches the oscillation frequency of the voltage controlled oscillator when the loop gain is small.

  Therefore, when the phase noise at the reference frequency is better than the output frequency, the loop gain is increased. However, in the above design example, the loop gain cannot be increased except by increasing the value of G. There was a problem that the design could not be given a degree of freedom.

  The phase noise of the frequency changes by “20 log frequency ratio” due to frequency division and multiplication, and is improved by frequency division and worsened by multiplication. That is, 20 log (5 MHz / 40 kHz) = 41.9 dbc should be improved with reference to the phase noise of the phase comparison frequency, but if the phase noise of the reference frequency is originally good, for example, -95 dbc / Hz. , − (95 + 41.9) = − 136.9 dbc / Hz, but in actuality, it may be affected by noise from the power supply or the ground or clock skew at the time of frequency division. I don't know.

  Conversely, 7.68 MHz on the output frequency side with the phase noise of the phase comparison frequency as a reference, 20 log (40 kHz / 7.68 MHz) = − 45.6 dbc / Hz will deteriorate, but in reality, the phase comparison frequency Since the phase noise itself has deteriorated, there has been a problem of further deterioration.

[Prior Art 1: FIG. 9]
In order to reduce the room temperature phase error in the phase synchronization circuit, there is a “phase synchronization circuit” described in Japanese Patent Publication No. 63-19094 (Patent Document 1).
As shown in FIG. 9, the configuration includes two phase comparators (PCs) 31 and 32, an integrator (INT) 33, a low pass filter (LPF) 34, and an adder ( ADD) 35, voltage controlled oscillator (VCO) 36, and 1 / N frequency divider (DV) 37.
FIG. 9 is a block diagram of a conventional phase synchronization circuit.

  In the phase synchronization circuit of FIG. 9, the two phase comparators 31 and 32 input the input signal (IN) and the frequency-divided signal from the 1 / N frequency divider 37, and output the phase comparison result. The output of one phase comparator 31 is integrated by an integrator 33 to correct the stationary phase error, and the output of the other phase comparator 32 is smoothed by the LPF 34, and the output from the integrator 33 and the LPF 32. Are added by the adder 35, and the addition result becomes the control voltage of the VCO 36. The VCO 36 oscillates and is output to the output terminal (OUT). Further, the output of the VCO 36 is branched and input to the 1 / N frequency divider 37, and 1 / N frequency is divided and output to the phase comparators 31 and 32.

[Prior Art 2: FIG. 10]
Further, in a PLL circuit, there is JP-A-10-75175 “PLL circuit” in order to prevent a loop gain from being lowered and a phase noise to be deteriorated when a frequency division ratio is large (Patent Document 2).
As shown in FIG. 10, the configuration includes a VCO 41, a frequency converter 42, a main counter 43, a phase comparator 44, a reference oscillator (TCXO: Temperature Compensated Crystal Oscillator) 45, and a reference. A counter 46, a charge pump 47, and an LPF 48 are provided.
FIG. 10 is a configuration block diagram of a conventional PLL circuit.

  The PLL circuit of FIG. 10 converts the oscillation frequency generated by the VCO 41 into a frequency of 7/8 by the frequency converter 42, divides the frequency by 1/85 by the main counter 43, and references the reference frequency generated by the TCXO 45. The counter 46 divides the frequency by 1/8. The frequency divided by both counters is input to the phase comparator 44 and input as the control voltage of the VCO 41 via the charge pump 47 and the LPF 48.

Japanese Patent Publication No. 63-19094 JP-A-10-75175

  However, in order to provide a highly stable PLL circuit according to the customer's request, the conventional phase noise reduction technique cannot sufficiently cope with this, and therefore, using an expensive SC-CUT crystal resonator, There is a problem that the OCXO according to the request must be developed each time, resulting in high costs.

  The SC-CUT (Stress Compensation-cut) crystal unit is a double-rotation crystal unit, and SC stands for a stress correction type, which corrects the planar stress effect and the characteristics caused by thermal transients. It is. Its excellent frequency and temperature characteristics are optimal for incorporation into OCXO.

  In the above conventional PLL circuit, when the phase comparison frequency between the reference input and the subordinate signal that feeds back the output signal becomes too low and the loop gain does not increase, the phase noise at the time of locking is sufficiently improved. There is a problem that it cannot be performed, and there is a problem that the pull-in range with respect to temperature changes.

  The present invention has been made in view of the above circumstances, and can increase the loop gain, maintain the lock according to the advance / delay of the phase, and even when the loop gain does not increase, the phase noise at the time of lock An object of the present invention is to provide a PLL circuit that can improve the above.

  The present invention for solving the problems of the above-described conventional example includes, in a PLL circuit, an input terminal that inputs a reference frequency, a voltage-controlled oscillator that outputs a frequency according to the input voltage, and a first that amplifies the input voltage. An amplifier, a first frequency divider that divides the reference frequency, a second frequency divider that divides the output from the voltage controlled oscillator, an output from the first frequency divider, and a second frequency divider Oscillates a specific frequency, a phase comparator that inputs the output from the comparator, performs phase comparison, a low-pass filter that smoothes the output from the phase comparator, a third divider that divides the reference frequency A first synthesizer that combines the output from the voltage controlled oscillator and the output from the oscillator, a first filter that band-limits the output from the first synthesizer, and an output from the first filter A fourth frequency divider, and an output from the third frequency divider, A phase advance / delay detector for detecting the phase advance or delay, an integrator for integrating the output from the phase advance / delay detector, and outputting a voltage; An adder for adding the output from the filter and the output from the integrator; and a second amplifier for amplifying the output from the first filter and outputting the amplified output to the output terminal. And the output of the fourth frequency divider are set to divide by each frequency divider until the same frequency is obtained, and the value obtained by dividing the reference frequency by the first frequency divider is output from the first filter. The specific frequency oscillated by the oscillator is adjusted so that the frequency obtained by dividing the frequency by the second frequency divider becomes equal.

  The present invention has a second filter for branching and inputting the output from the first synthesizer in the PLL circuit and band-limiting the second amplifier, and the second amplifier inputs the output from the first filter. Instead, the output from the second filter is inputted and amplified.

  According to the present invention, in the PLL circuit, the output from the oscillator is branched and input, the second synthesizer for combining with the output from the first filter, and the output from the second synthesizer is band-limited. The second amplifier does not input the output from the first filter but amplifies the output from the second filter, and the characteristics of the first filter and the first filter The characteristics of the two filters are different.

  The present invention is characterized in that, in the PLL circuit, the temperature characteristic of a specific frequency oscillated from the oscillator is set to be the same as the temperature characteristic of the frequency output from the voltage controlled oscillator.

  The present invention includes a crystal oscillator with a thermostat that oscillates a specific reference frequency in place of the oscillator in the PLL circuit, and the reference frequency from the crystal oscillator with a thermostat is input to the input terminal and the first synthesizer. It is characterized by being.

  According to the present invention, in the PLL circuit, the output from the third frequency divider and the output from the fourth frequency divider are input instead of the phase advance / delay detector to detect the phase advance or delay. A phase frequency detector for outputting the detection result in three values, and having a second low-pass filter for smoothing the output from the phase frequency detector and outputting a voltage instead of the integrator. To do.

  According to the present invention, an input terminal for inputting a reference frequency, a voltage controlled oscillator for outputting a frequency according to the input voltage, a first amplifier for amplifying the input voltage, and a first divider for dividing the reference frequency. Phase that performs phase comparison by inputting the frequency divider, the second frequency divider that divides the output from the voltage controlled oscillator, and the output from the first frequency divider and the output from the second frequency divider A comparator, a low-pass filter that smoothes the output from the phase comparator, a third frequency divider that divides the reference frequency, an oscillator that oscillates a specific frequency, an output from the voltage controlled oscillator, and an oscillator A first synthesizer that synthesizes the output of the first synthesizer, a first filter that band-limits the output from the first synthesizer, a fourth divider that divides the output from the first filter, The output from the frequency divider 3 and the output from the fourth frequency divider are input, and the phase advance or delay is input. A phase lead / lag detector for detecting the output, an integrator for integrating the output from the phase lead / lag detector, outputting a voltage, an adder for adding the output from the low-pass filter and the output from the integrator, A second amplifier that amplifies the output from the first filter and outputs it to the output terminal, and the output of the third divider and the output of the fourth divider are each set to the same frequency. A frequency divider is set to divide, and a value obtained by dividing the reference frequency by the first divider and a value obtained by dividing the frequency output from the first filter by the second divider are: Since the PLL circuit adjusts the specific frequency oscillated by the oscillator to be equal, the loop gain can be increased, the phase noise can be improved, and the lock can be maintained according to the phase advance / delay. is there.

  According to the present invention, the output from the first synthesizer is branched and input, and the second filter that limits the band is provided, and the second amplifier does not input the output from the first filter. Since the PLL circuit that receives and amplifies the output from the second filter is used, the PLL dependent frequency signal and the output signal to the output terminal can be made independent, and the effect of reducing the mutual influence can be obtained. is there.

  According to the present invention, the output from the oscillator is branched and input, the second combiner that combines the output from the first filter, and the second filter that limits the band of the output from the second combiner. The second amplifier does not input the output from the first filter, but inputs and amplifies the output from the second filter, and the characteristics of the first filter and the second filter Since the PLL circuit having different characteristics is used, the output of the voltage controlled oscillator can be output from the output terminal.

  According to the present invention, since the PLL circuit in which the temperature characteristic of the specific frequency oscillated from the oscillator is set to be the same as the temperature characteristic of the frequency output from the voltage-controlled oscillator, the temperature variation can be canceled. There is.

  According to the present invention, instead of the oscillator, the crystal oscillator with a thermostatic chamber that oscillates a specific reference frequency is provided, and the reference frequency from the crystal oscillator with a thermostatic chamber is input to the input terminal and the first combiner. Since the PLL circuit is used, there is an effect that the frequency of the input signal and the dependent frequency can be stabilized.

  According to the present invention, instead of the phase advance / delay detector, the output from the third frequency divider and the output from the fourth frequency divider are input, the phase advance or delay is detected, and the detection result Since the PLL circuit has the second low-pass filter that outputs the voltage by smoothing the output from the phase frequency detector instead of the integrator, The loop gain can be increased, the phase noise can be improved, the constant value of the second low-pass filter is not increased, the phase noise characteristics can be improved, and the lock can be maintained according to the phase advance / delay. is there.

[Outline of the embodiment]
The PLL circuit according to the embodiment of the present invention divides the reference frequency from the input terminal by the first and third frequency dividers, and outputs from the voltage controlled oscillator (VCO) and the output from the oscillator. Is synthesized with a mixer, the frequency is selected with a crystal filter, the frequency is divided with second and fourth frequency dividers, and the output from the first frequency divider and the second frequency divider is phase-shifted with a phase comparator. The phase comparison result is smoothed by a low-pass filter, the output from the third frequency divider and the fourth frequency divider is detected by the phase advance / delay detector, and the phase advance or delay is detected. The integrator integrates the voltage and outputs the voltage. The adder adds the output from the low-pass filter and the integrator to output to the VCO. The output from the crystal filter is amplified by the second amplifier and output. Is output to the terminal, and the loop gain can be increased. The output of the third divider and the output of the fourth divider are divided by each divider until the same frequency is obtained, and the reference frequency is divided by the first divider. Since the specific frequency oscillated by the oscillator is adjusted so that the value and the frequency output from the first filter are equalized by the second divider, the phase advance / delay is adjusted. Therefore, even when the loop gain does not increase, the phase noise at the time of locking can be improved.

Note that the reference frequency serving as the phase comparison frequency is set to a frequency division number at which the phase noise does not fall below −125 dbc / Hz or no frequency division. The phase comparison frequency after frequency division of the voltage controlled oscillator is not the same, and is a combination of frequencies for which the greatest common divisor is required between the phase comparison frequencies.
The phase comparator uses an EX-OR (Exclusive OR) or RS (Reset Set Flip-Flop) equation to smooth the output using an LPF (Low Pass Filter).

[First Embodiment: FIG. 1]
A PLL circuit (first PLL circuit) according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram of the first PLL circuit.
As shown in FIG. 1, the first PLL circuit includes an input terminal 1, a first frequency divider 2, a second frequency divider 3, a phase comparator (PC) 4, an LPF 5, and an addition A first amplifier 7, a VCO 8, a third frequency divider 9, a fourth frequency divider 10, a phase advance / lag detector 11, an integrator 12, an oscillator 13, It comprises a mixer (MIX) 14, a crystal filter (MCF) 15, a second amplifier 16, and an output terminal 17.

[Each part of the first PLL circuit]
Hereinafter, each part of the first PLL circuit will be described.
The input terminal 1 is a terminal for inputting a reference frequency. Here, the reference frequency is Fr.
The first frequency divider 2 is a frequency divider that receives a reference frequency signal from the input terminal 1 and divides the frequency. Here, the frequency division number of the first frequency divider 2 is N1.
The second frequency divider 3 is a frequency divider that divides and inputs a signal from the MCF 11 and divides the frequency. Here, the frequency division number of the second frequency divider 3 is N2.

  Here, the output frequencies of the first frequency divider 2 and the second frequency divider 3 do not have to be the same if the greatest common divisor is present, and are higher than the frequency obtained by the greatest common divisor. is there. Thereby, the loop gain can be increased and the phase noise can be brought closer to the reference frequency.

The phase comparator 4 is a phase comparator that receives the output from the first frequency divider 2 and the output from the second frequency divider 3, compares the phases of the two, and outputs a comparison result.
The LPF 5 inputs an output from the phase comparator 4 and passes a low-frequency band frequency signal, and is a voltage proportional to the phase difference between the first frequency divider 2 and the second frequency divider 3. Is generated and output.

The adder 6 adds the output from the LPF 5 and the output from the integrator 12.
The first amplifier 7 amplifies the output from the adder 6 and outputs the control voltage of the VCO 8.

The VCO 8 is a voltage controlled oscillator including an inexpensive AT-CUT crystal resonator, and operates so as to maintain the lock as a PLL by the control voltage from the first amplifier 7.
Here, the output frequency of the VCO 8 is assumed to be Fo.
The AT-CUT quartz crystal resonator uses a crystal piece whose main surface is parallel to the X axis and tilted by about 35 ° from the Z axis and about -3 ° from the r plane.

The third frequency divider 9 is a frequency divider that performs frequency division by inputting a reference frequency from the input terminal 1. Here, the frequency division number of the third frequency divider 9 is N3.
The fourth frequency divider 10 is a frequency divider that divides and inputs the output of the MCF 11 and performs frequency division. Here, the frequency dividing number of the fourth frequency divider 10 is N4.
Note that the output of the third frequency divider and the output of the fourth frequency divider are set to perform frequency division until they have the same frequency.

The phase advance / delay detector 11 outputs a logic low level if the rising phase position of the fourth frequency divider 10 is advanced from the rise of the third frequency divider 9, and if it is delayed. This is a logic circuit that outputs a logic high level. Therefore, the circuit configuration of the phase lead / lag detector 11 can be realized by a simple logic circuit.
The integrator 12 is a circuit that integrates the output of the phase lead / lag detector 11 and outputs a constant voltage.

  Even if the output frequency of the VCO 8 fluctuates due to a temperature change, the output frequency of the oscillator 9 also fluctuates in the same manner so that the oscillator 9 has the same temperature characteristics, so that the lock is maintained. The input phase position to the phase comparator 4 changes appropriately.

  The output of the integrator 12 prevents the phase from being shifted at the time of locking, and keeps the phase position constant. The third divider 9 and the output of the integrator 12 correspond to the fluctuation amount / second of the reference frequency. If the output frequency from the frequency divider 10 of 4 and the integration amount of the integrator 12 are determined, the return time to the original phase position can be minimized when the phase position fluctuates. Further, the phase noise characteristic also affects the output of the integrator 12, but it can be improved by adjusting the integration time regardless of the loop gain.

That is, if the integration amount or integration time of the integrator 12 is reduced, the return time can be shortened, but stability is sacrificed, and if the integration amount or integration time is increased, the return time is stabilized. Although phase noise can be improved, the return time cannot be shortened.
Ideally, it is better to increase the integration amount or integration time to make it heavy, but the integration amount or integration time is set in consideration of the return time.

The oscillator 13 is a fixed oscillator and outputs an oscillation frequency to the MIX 14.
Here, the output frequency is Ff.
The MIX 14 inputs the output frequency from the VCO 8 and the output frequency from the oscillator 13 and synthesizes both frequencies.
The output from the MIX 14 is Fo ± Ff.

The MCF 15 is a crystal filter, and removes the + Ff frequency component from the output from the MIX 14 (in this case, the MCF is a low-pass filter) or removes the −Ff frequency component (in this case, the MCF is This is a high-pass filter) and is output to the second amplifier 16 and the second frequency divider 3.
Here, the MCF 15 is used as a low-pass filter, the frequency component of + Ff is removed, and the frequency of Fo−Ff is output.
The second amplifier 16 branches and inputs the output from the MCF 15, amplifies it, and outputs it to the output terminal 17.

  Therefore, a value of Ff that satisfies Fr / N1 = (Fo-Ff) / N2 is selected to cause the oscillator 13 to oscillate the frequency Ff. As a result, if the phase comparison frequency does not match unless the phase comparison frequency is lowered, the reference input signal (reference frequency Fo) for increasing the phase comparison frequency and (dependent frequency [output frequency Fr of VCO 8] −third frequency [frequency component] Ff]), the phase frequency is matched, that is, the reference frequency is divided by the phase frequency, and the loop gain is increased to improve the phase noise.

Here, if Ff having the same temperature characteristic as the temperature characteristic of Fo is selected, (Fo-Ff) becomes constant, and there is an effect that the temperature variation can be canceled.
Further, the selectivity of the frequency combination is increased, the selectivity of the second amplifier 16 is increased, and there is an effect that the circuit design can be afforded.

[Second Embodiment: FIG. 2]
Next, a PLL circuit (second PLL circuit) according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a configuration block diagram of the second PLL circuit.
As shown in FIG. 2, the second PLL circuit is substantially the same as the first PLL circuit, except that a first MCF 15a and a second MCF 15b are provided.
Specifically, the output from the MIX 14 is branched and output to the first MCF 15a and the second MCF 15b, and the output from the first MCF 15a is supplied to the second frequency divider 3 and the fourth frequency divider 10. The output from the second MCF 15 b is output to the second amplifier 16.

As described above, one MCF 15 is used in the first PLL circuit, but the characteristics can be changed by using two MCFs in the second PLL circuit.
For example, since the output frequency from the MIX 14 is Fo ± Ff, the first MCF 15a is a low-pass filter, passes the Fo-Ff frequency, the second MCF 15b is a high-pass filter, and passes the Fo + Ff frequency.
As a result, the PLL dependent frequency signal and the output signal to the output terminal 17 can be made independent, and there is an effect that the mutual influence can be reduced.

[Third Embodiment: FIG. 3]
Next, a PLL circuit (third PLL circuit) according to a third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a configuration block diagram of the third PLL circuit.
As shown in FIG. 3, the third PLL circuit is substantially the same as the first PLL circuit, except that the first MIX 14a, the second MIX 14b, the first MCF 15a, 2 MCFs 15b.

Specifically, the output from the oscillator 13 is branched and output to the first MIX 14a and the second MIX 14b, and the first MIX 14a combines the signal from the VCO 8 and the signal from the oscillator 13 to generate the first MIX 14a and the second MIX 14b. The signal is output to the MCF 15a, and the second MIX 14b combines the signal from the oscillator 13 and the signal from the first MCF 15a and outputs the resultant signal to the second MCF 15b.
Further, the first MCF 15a band-limits the signal from the first MIX 14a and outputs it to the second frequency divider 3 and the fourth frequency divider 10, and the second MCF 15b receives the signal from the second MIX 14b. Is band-limited and output to the second amplifier 16.

Here, the first MCF 15a and the second MCF 15b have different characteristics as in the second PLL circuit.
That is, since the output frequency of the VCO 8 is Fo and the output frequency Ff of the oscillator 13, the output frequency from the first MIX 14a is Fo ± Ff.
When the first MCF 15a is a low-pass filter, the output frequency of the first MCF 15a is Fo-Ff, and when the frequency component Ff is synthesized by the second MIX 14b, the output frequency is (Fo-Ff) ± Ff. If the second MCF 15b is a high-pass filter, the frequency component (Fo−Ff) + Ff remains, and the frequency Fo is input from the second MCF 15b to the second amplifier 16.

When the first MCF 15a is a high-pass filter, the output frequency of the first MCF 15a is Fo + Ff, and when the frequency component Ff is synthesized by the second MIX 14b, the output frequency is (Fo + Ff) ± Ff. If the second MCF 15b is a low-pass filter, the frequency component (Fo + Ff) −Ff remains and the frequency Fo is input from the second MCF 15b to the second amplifier 16.
As a result, the output frequency from the second MCF 15 b can be obtained from the output terminal 17 as the same as the output frequency Fo of the VCO 8.

[Fourth Embodiment: FIG. 4]
Next, a PLL circuit (fourth PLL circuit) according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of the fourth PLL circuit.
As shown in FIG. 4, the fourth PLL circuit is substantially the same as the first PLL circuit, except that the oscillator 13 is removed and an OCXO (Oven Controlled Crystal Oscillator) is used instead. ) 20, and the OCXO 20 reference signal is input to the input terminal 1 and the MIX 14.
As a result, the frequency of the input signal and the dependent frequency can be stabilized.
The OCXO 20 may be applied to the second and third PLL circuits shown in FIGS.

[Application example]
Next, an application example using a phase frequency detector (PFD) and a low-pass filter (LPF) in place of the phase lead / lag detector 11 and the integrator 12 in the first to fourth PLL circuits will be described.

  The phase frequency detector (PFD) detects a phase difference between the output signal and the output signal from the fourth frequency divider 10 at the rising edge of the output signal from the third frequency divider 9. Then, the phase advance / delay is output in three values.

The LPF smoothes the phase difference from the PFD and outputs it to the adder 6.
Since the phase advance / delay result is output in three values from the PFD, the constant value of the LPF does not increase.
The phase noise characteristics can be improved by lowering the input frequency to the PFD.
By adjusting the time constant in the LPF, the balance between stability and reactivity can be achieved in the same manner as the integration amount or integration time in the integrator 12 is adjusted.

  The specific circuit of each of the above parts is realized by using a flip-flop or a program counter as a frequency divider, a phase comparator, an LPF, an adder, a phase advance / lag detector, and an integrator as an integrator.

[Configuration of LPF: FIGS. 5 and 6]
For example, the specific configuration of the LPF is as shown in FIG. FIG. 5 is a circuit diagram of an LPF, and FIG. 6 is a circuit diagram of an LPF using an operational amplifier.

[Configuration and time chart of PFD: FIGS. 7 and 8]
The specific configuration of the PFD 21 is as shown in FIG. FIG. 7 is a circuit diagram of the PFD. The output from the third frequency divider 9 is inputted to the input R of the IC of the PFD, and the ternary value from the fourth frequency divider 10 as shown in FIG. 8 is inputted to the input Oi-3 of the IC. (O1-3) is input. FIG. 8 is a diagram showing a time chart of input to the IC.

[Effect of the embodiment]
According to the first to third PLL circuits, the loop gain can be increased, the lock can be maintained according to the phase advance / delay, and the phase noise can be improved.

  Further, according to the second PLL circuit, since the second amplifier 16 inputs and amplifies the output from the second MCF 15b, the signal of the dependent frequency of the PLL and the output signal to the output terminal Can be made independent of each other, and the influence of each other can be reduced.

  Further, according to the third PLL circuit, the second amplifier 16 inputs and amplifies the output from the second MCF 15b so that the characteristics of the first MCF 15a and the characteristics of the second MCF 15b are different. Therefore, the output of the voltage controlled oscillator can be output from the output terminal.

  Further, according to the fourth PLL circuit, since the reference signal of the OCXO 20 is input to the input terminal 1 and the MIX 14, there is an effect that the frequency of the input signal and the dependent frequency can be stabilized.

  Further, according to the PLL circuit of the application example, since the PFD and the LPF (second LPF) are used instead of the phase lead / lag detector 11 and the integrator 12, if the constant value of the second LPF is large. The phase noise characteristics can be improved.

  The present invention is suitable for a PLL circuit that can increase the loop gain, maintain the lock according to the advance / delay of the phase, and improve the phase noise at the time of the lock even when the loop gain does not increase.

It is a block diagram of the configuration of the first PLL circuit. It is a block diagram of the configuration of the second PLL circuit. It is a block diagram of the configuration of the third PLL circuit. It is a block diagram of the configuration of a fourth PLL circuit. It is a circuit diagram of LPF. It is a circuit diagram of LPF using an operational amplifier. It is a circuit diagram of PFD. It is a figure which shows the time chart of the input to IC. It is a block diagram of the conventional phase locked loop. It is a configuration block diagram of a conventional PLL circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... 1st frequency divider, 3 ... 2nd frequency divider, 4 ... Phase comparator, 5 ... LPF, 6 ... Adder, 7 ... 1st amplifier, 8 ... VCXO, 9 DESCRIPTION OF SYMBOLS 3rd frequency divider, 10 ... 4th frequency divider, 11 ... Phase advance / lag detector, 12 ... Integrator, 13 ... Oscillator, 14 ... Mixer (MIX), 15 ... Crystal filter (MCF), 16 ... second amplifier, 17 ... output terminal, 20 ... OCXO

Claims (6)

An input terminal for inputting a reference frequency;
A voltage controlled oscillator that outputs a frequency according to an input voltage;
A first amplifier for amplifying the input voltage;
A first divider for dividing the reference frequency;
A second divider for dividing the output from the voltage controlled oscillator;
A phase comparator that receives the output from the first frequency divider and the output from the second frequency divider and performs phase comparison;
A low pass filter for smoothing the output from the phase comparator;
A third divider for dividing the reference frequency;
An oscillator that oscillates a specific frequency;
A first combiner that combines the output from the voltage controlled oscillator and the output from the oscillator;
A first filter for band limiting the output from the first combiner;
A fourth divider for dividing the output from the first filter;
A phase advance / delay detector for inputting an output from the third frequency divider and an output from the fourth frequency divider, and detecting a phase advance or delay;
An integrator that integrates the output from the phase advance / lag detector and outputs a voltage;
An adder for adding the output from the low-pass filter and the output from the integrator;
A second amplifier for amplifying the output from the first filter and outputting it to the output terminal;
The output of the third divider and the output of the fourth divider are set to divide by each divider until the same frequency is reached,
The oscillator oscillates so that a value obtained by dividing the reference frequency by the first divider is equal to a value obtained by dividing the frequency output from the first filter by the second divider. A PLL circuit characterized by adjusting a specific frequency. A second filter for branching and inputting the output from the first synthesizer to limit the bandwidth;
2. The PLL circuit according to claim 1, wherein the second amplifier does not input the output from the first filter but amplifies the input from the second filter. A second synthesizer for branching and inputting the output from the oscillator and synthesizing with the output from the first filter; and a second filter for band-limiting the output from the second synthesizer;
The second amplifier does not input the output from the first filter, but inputs and amplifies the output from the second filter, and the characteristics of the first filter and the characteristics of the second filter 2. The PLL circuit according to claim 1, wherein the two are different from each other.   4. The PLL circuit according to claim 1, wherein a temperature characteristic of a specific frequency oscillated from the oscillator is set to be the same as a temperature characteristic of a frequency output from the voltage controlled oscillator. Instead of an oscillator, it has a crystal oscillator with a thermostatic chamber that oscillates a specific reference frequency,
4. The PLL circuit according to claim 1, wherein a reference frequency from the crystal oscillator with a thermostatic bath is input to an input terminal and the first synthesizer. 5. Instead of the phase advance / delay detector, the output from the third frequency divider and the output from the fourth frequency divider are input, the phase advance or delay is detected, and the detection result is output as a ternary value. Having a phase frequency detector;
6. The PLL circuit according to claim 1, further comprising a second low-pass filter that smoothes the output from the phase frequency detector and outputs a voltage instead of the integrator.

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