JP2009076822A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2009076822A
JP2009076822A JP2007246798A JP2007246798A JP2009076822A JP 2009076822 A JP2009076822 A JP 2009076822A JP 2007246798 A JP2007246798 A JP 2007246798A JP 2007246798 A JP2007246798 A JP 2007246798A JP 2009076822 A JP2009076822 A JP 2009076822A
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electrode
semiconductor chip
semiconductor device
conductive member
thin film
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Hiroshi Kimura
浩 木村
Hiroyuki Fujioka
寛行 藤岡
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Torex Semiconductor Ltd
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Torex Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing an insulation failure. <P>SOLUTION: A semiconductor chip 2 is mounted on a lead frame 1. A wire 4B is connected between an electrode 22B of the semiconductor chip 2 and the lead frame 1. On the back surface of the semiconductor chip 2, an insulation layer 6 is formed. The lead frame 1 is formed of, for instance, Cu, and a Au or Pd thin-film layer 14 allowing wire bonding and hardly causing migration is formed on the surface thereof. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置に係り、特に、導電部材と、表面側に電極が設けられると共に裏面側が前記導電部材の表面と対向するように前記導電部材上に搭載されるチップ部品と、前記チップ部品の電極と前記導電部材との間にワイヤボンダされたワイヤと、前記チップ部品の裏面と前記導電部材の表面との間に設けられた絶縁層と、前記導電部材の表面に設けられたワイヤボンダ可能な薄膜層と、を備えた半導体装置に関するものである。   The present invention relates to a semiconductor device, and in particular, a conductive member, a chip component that is provided on the conductive member such that an electrode is provided on the front surface side and a back surface is opposed to the front surface of the conductive member, and the chip component A wire bonded between the electrode and the conductive member, an insulating layer provided between the back surface of the chip component and the surface of the conductive member, and a wire bonder provided on the surface of the conductive member And a thin film layer.

上述した従来の半導体装置について、図１及び図７を参照して以下説明する。同図に示すように、半導体装置は、導電部材としての銅（Ｃｕ）から構成されたリードフレーム１と、半導体チップ２（チップ部品）と、封止部材３と、ワイヤ４Ａ、４Ｂ、４Ｃと、を備えている。リードフレーム１は、外部接続用の例えば３つのリード１１Ａ、１１Ｂ、１１Ｃと、半導体チップ２を搭載する搭載部１２と、が設けられている。搭載部１２は、リード１１Ａと一体に設けられている。また、リードフレーム１は、後述するワイヤボンダが行えるように表面側に銀（Ａｇ）から構成されるＡｇ薄膜層１３（図７）が設けられている。   The conventional semiconductor device described above will be described below with reference to FIGS. As shown in the figure, the semiconductor device includes a lead frame 1 made of copper (Cu) as a conductive member, a semiconductor chip 2 (chip component), a sealing member 3, and wires 4A, 4B, and 4C. It is equipped with. The lead frame 1 is provided with, for example, three leads 11A, 11B, and 11C for external connection, and a mounting portion 12 on which the semiconductor chip 2 is mounted. The mounting portion 12 is provided integrally with the lead 11A. Further, the lead frame 1 is provided with an Ag thin film layer 13 (FIG. 7) made of silver (Ag) on the surface side so that a wire bonder described later can be performed.

半導体チップ２は、表面に例えば３つの電極２２Ａ、２２Ｂ、２２Ｃが設けられている。半導体チップ２は、裏面がリードフレーム１の表面と対向するようにリードフレーム１上に搭載されている。封止部材３は、樹脂などから構成され、リード１１Ａ、１１Ｂ、１１Ｃの先端を外部に露出させた状態でリードフレーム１、半導体チップ２及びワイヤ４Ａ、４Ｂ、４Ｃを封止する。   The semiconductor chip 2 is provided with, for example, three electrodes 22A, 22B, and 22C on the surface. The semiconductor chip 2 is mounted on the lead frame 1 so that the back surface faces the surface of the lead frame 1. The sealing member 3 is made of resin or the like, and seals the lead frame 1, the semiconductor chip 2, and the wires 4A, 4B, and 4C with the tips of the leads 11A, 11B, and 11C exposed to the outside.

また、半導体装置は、半導体チップ２の電極２２Ａ、２２Ｂ、２２Ｃとリードフレーム１の表面とにワイヤボンダされ、半導体チップ２とリードフレーム１とを電気的に接続する金属製のワイヤ４Ａ、４Ｂ、４Ｃを備えている。ワイヤ４Ａは、リード１１Ａと電極２２Ａとを接続している。ワイヤ４Ｂは、リード１１Ｂと電極２２Ｂとを接続している。ワイヤ４Ｃは、リード１１Ｃと電極２２Ｃとを接続している。   In addition, the semiconductor device is wire bonded to the electrodes 22A, 22B, 22C of the semiconductor chip 2 and the surface of the lead frame 1, and metal wires 4A, 4B, 4C that electrically connect the semiconductor chip 2 and the lead frame 1 to each other. It has. The wire 4A connects the lead 11A and the electrode 22A. The wire 4B connects the lead 11B and the electrode 22B. The wire 4C connects the lead 11C and the electrode 22C.

上述したように図１に示すように、搭載部１２がリード１１Ａと一体に設けられている。このため、搭載部１２の電位は、リード１１Ａに接続されている電極２２Ａの電位（例えば電源電圧）と等しくなる。一方、半導体チップ２の裏面の電位は、電極２２Ｂの電位（例えば接地電位）と等しくなることがある。このため、半導体チップ２の裏面をリードフレーム１の搭載部１２上に直接、載せるとショートが発生してしまう。そこで、図７に示すように、リードフレーム１と半導体チップ２との間に絶縁シート５を設けていた。しかしながら、上述した半導体装置は、絶縁不良が多い、という問題点があった。   As described above, as shown in FIG. 1, the mounting portion 12 is provided integrally with the lead 11A. For this reason, the potential of the mounting portion 12 becomes equal to the potential (for example, power supply voltage) of the electrode 22A connected to the lead 11A. On the other hand, the potential of the back surface of the semiconductor chip 2 may be equal to the potential of the electrode 22B (for example, ground potential). For this reason, when the back surface of the semiconductor chip 2 is placed directly on the mounting portion 12 of the lead frame 1, a short circuit occurs. Therefore, as shown in FIG. 7, an insulating sheet 5 is provided between the lead frame 1 and the semiconductor chip 2. However, the above-described semiconductor device has a problem that there are many insulation defects.

そこで、本発明は、上記のような問題点に着目し、絶縁不良を防止した半導体装置を提供することを課題とする。   In view of the above, an object of the present invention is to provide a semiconductor device in which an insulation failure is prevented by paying attention to the above problems.

本発明者らは、上述した絶縁不良の原因を鋭意探求したところ、図７中のＸ部に示すように、半導体チップ２に電流を流すとこの半導体チップ２に生じる電界によってＡｇ薄膜層４が引っ張られてＡｇ薄膜層４が半導体チップ２の側面に沿って上方に移動するマイグレーションが発生し、このマイグレーションが絶縁シート５を超えて移動することにより、リードフレーム１と半導体チップ２とがショートして絶縁不良が生じる、ということを見出した。そこで、本発明者らは、このようなマイグレーションの発生を防止するため種々の金属で構成した薄膜層を形成して試験したところ、金又はパラジウムで構成した薄膜層がマイグレーションを発生しにくいことを見出し、本発明を完成するに至った。   The present inventors diligently searched for the cause of the above-described insulation failure. As shown in the X part in FIG. 7, when an electric current is passed through the semiconductor chip 2, the Ag thin film layer 4 is formed by the electric field generated in the semiconductor chip 2. Pulling causes a migration in which the Ag thin film layer 4 moves upward along the side surface of the semiconductor chip 2, and the migration moves beyond the insulating sheet 5, whereby the lead frame 1 and the semiconductor chip 2 are short-circuited. And found that insulation failure occurs. Therefore, the present inventors formed and tested a thin film layer composed of various metals in order to prevent the occurrence of such migration, and found that the thin film layer composed of gold or palladium hardly generates migration. The headline and the present invention were completed.

即ち、請求項１に記載した本発明は、導電部材と、表面側に電極が設けられると共に裏面側が前記導電部材の表面と対向するように前記導電部材上に搭載されるチップ部品と、前記チップ部品の電極と前記導電部材との間にワイヤボンダされたワイヤと、前記チップ部品の裏面と前記導電部材の表面との間に設けられた絶縁層と、前記導電部材の表面に設けられたワイヤボンダ可能な薄膜層と、を備えた半導体装置において、前記薄膜層が、金又はパラジウムから構成されていることを特徴とする半導体装置に存する。   That is, the present invention described in claim 1 includes a conductive member, a chip component mounted on the conductive member such that an electrode is provided on the front side and a back side faces the surface of the conductive member, and the chip A wire bonded between the electrode of the component and the conductive member, an insulating layer provided between the back surface of the chip component and the surface of the conductive member, and a wire bonder provided on the surface of the conductive member A thin film layer, wherein the thin film layer is made of gold or palladium.

請求項２記載の発明は、前記導電部材が、外部接続用のリードが設けられたリードフレームから構成されていることを特徴とする請求項１に記載の半導体装置に存する。   A second aspect of the present invention resides in the semiconductor device according to the first aspect, wherein the conductive member comprises a lead frame provided with a lead for external connection.

請求項３記載の発明は、前記導電部材が、互いに独立した複数の電極層、又は、前記電極層の表面側に席相された導電パターン層、から構成されていることを特徴とする請求項１に記載の半導体装置に存する。   The invention according to claim 3 is characterized in that the conductive member is composed of a plurality of electrode layers independent of each other or a conductive pattern layer phased on the surface side of the electrode layer. 1 in the semiconductor device.

以上説明したように請求項１〜３記載の発明によれば、導電部材の表面にマイグレーションを発生させない金又はパラジウムから成る薄膜層を設けているので、マイグレーションに起因する絶縁不良を防止することができる。   As described above, according to the first to third aspects of the invention, since the thin film layer made of gold or palladium that does not cause migration is provided on the surface of the conductive member, it is possible to prevent insulation failure caused by migration. it can.

第１実施形態
以下、第１実施形態における本発明の半導体装置について、図１及び図２を参照して説明する。図１は、第１実施形態における本発明の半導体装置を示す表面図である。図２は、図１の半導体装置のＩ−Ｉ線断面図である。同図に示すように、半導体装置は、リードフレーム１（導電部材）と、半導体チップ２（チップ部品）と、封止部材３と、ワイヤ４Ａ、４Ｂ、４Ｃと、を備えている。リードフレーム１は、外部接続用の例えば３つのリード１１Ａ、１１Ｂ、１１Ｃと、半導体チップ２を搭載する搭載部１２と、が設けられている。 First Embodiment Hereinafter, a semiconductor device of the present invention in a first embodiment will be described with reference to FIGS. FIG. 1 is a surface view showing the semiconductor device of the present invention in the first embodiment. 2 is a cross-sectional view taken along the line II of the semiconductor device of FIG. As shown in the figure, the semiconductor device includes a lead frame 1 (conductive member), a semiconductor chip 2 (chip component), a sealing member 3, and wires 4A, 4B, and 4C. The lead frame 1 is provided with, for example, three leads 11A, 11B, and 11C for external connection, and a mounting portion 12 on which the semiconductor chip 2 is mounted.

搭載部１２は、リード１１Ａと一体に設けられている。また、リードフレーム１は、銅（Ｃｕ）合金などから構成されていて、その表面１３に金（Ａｕ）又はパラジウム（Ｐｄ）からなる薄膜層としてのＡｕ又はＰｄ薄膜層１４（図２）が形成されている。Ａｕ又はＰｄは、ワイヤ４Ａ、４Ｂ、４Ｃとのワイヤボンダが可能であり、かつ、マイグレーションが発生しにくい材料である。   The mounting portion 12 is provided integrally with the lead 11A. The lead frame 1 is made of a copper (Cu) alloy or the like, and an Au or Pd thin film layer 14 (FIG. 2) is formed on the surface 13 as a thin film layer made of gold (Au) or palladium (Pd). Has been. Au or Pd is a material that can be wire-bonded with the wires 4A, 4B, and 4C, and is less prone to migration.

半導体チップ２は、表面に例えば３つの電極２２Ａ、２２Ｂ、２２Ｃが設けられている。半導体チップ２は、その裏面がリードフレーム１の表面と対向するように、リードフレーム１上に搭載されている。封止部材３は、樹脂などから構成され、リード１１Ａ、１１Ｂ、１１Ｃの先端を外部に露出させた状態でリードフレーム１、半導体チップ２及びワイヤ４Ａ、４Ｂ、４Ｃを封止する。   The semiconductor chip 2 is provided with, for example, three electrodes 22A, 22B, and 22C on the surface. The semiconductor chip 2 is mounted on the lead frame 1 such that the back surface thereof faces the front surface of the lead frame 1. The sealing member 3 is made of resin or the like, and seals the lead frame 1, the semiconductor chip 2, and the wires 4A, 4B, and 4C with the tips of the leads 11A, 11B, and 11C exposed to the outside.

ワイヤ４Ａ、４Ｂ、４Ｃは、半導体チップ２の電極２２Ａ、２２Ｂ、２２Ｃとリードフレーム１の表面とにワイヤボンダされ、半導体チップ２とリードフレーム１とを電気的に接続する金属製の部材である。ワイヤ４Ａは、リード１１Ａと電極２２Ａとを接続している。ワイヤ４Ｂは、リード１１Ｂと電極２２Ｂとを接続している。ワイヤ４Ｃは、リード１１Ｃと電極２２Ｃとを接続している。ワイヤ４Ａ、４Ｂ、４Ｃは、超音波ボンディングなどによって接続される。   The wires 4A, 4B, and 4C are metal members that are wire-bonded to the electrodes 22A, 22B, and 22C of the semiconductor chip 2 and the surface of the lead frame 1, and electrically connect the semiconductor chip 2 and the lead frame 1. The wire 4A connects the lead 11A and the electrode 22A. The wire 4B connects the lead 11B and the electrode 22B. The wire 4C connects the lead 11C and the electrode 22C. The wires 4A, 4B, and 4C are connected by ultrasonic bonding or the like.

また、半導体装置は、半導体チップ２とリードフレーム１との間に絶縁層６（図２）が設けられている。なお、絶縁層６の材料としては、感光性ポリイミド、非感光性ポリイミド、感光性ポリベンゾオキサザール、非感光性ポリベンゾオキサザール或いは非導電性ポジレジストなどを用いる。絶縁層６は、半導体チップ２とリードフレーム１との絶縁を確保できる厚さに設けられている。そして、絶縁層６は、その厚さが１０μｍ以内と薄く設けられている。   In the semiconductor device, an insulating layer 6 (FIG. 2) is provided between the semiconductor chip 2 and the lead frame 1. As a material for the insulating layer 6, photosensitive polyimide, non-photosensitive polyimide, photosensitive polybenzoxazal, non-photosensitive polybenzoxazal, non-conductive positive resist, or the like is used. The insulating layer 6 is provided with a thickness that can ensure insulation between the semiconductor chip 2 and the lead frame 1. The insulating layer 6 is provided with a thickness as thin as 10 μm or less.

このように、絶縁層６が、その厚さが１０μｍ以内、例えば３μｍとなるように設けているので、ワイヤ４Ａ、４Ｂ、４Ｃをワイヤボンダの際に半導体チップ２の上下移動を１０μｍ以内と小さくすることができ、ワイヤ４Ａ、４Ｂ、４Ｃのダメージを防ぐことができる。   Thus, since the insulating layer 6 is provided so that the thickness thereof is within 10 μm, for example, 3 μm, the vertical movement of the semiconductor chip 2 is reduced to within 10 μm when the wires 4A, 4B, 4C are wire bonded. And damage to the wires 4A, 4B, 4C can be prevented.

上述した半導体装置によれば、リードフレーム１の表面１３にＡｕ又はＰｄから成るＡｕ又はＰｄ薄膜層１４が設けられている。Ａｕ又はＰｄ薄膜層１４は、半導体チップ２に生じる電界によって半導体チップ２の側面に沿って移動するマイグレーションが生じにくい。このため、ワイヤ４Ａ、４Ｂ、４Ｃのダメージを防ぐために絶縁層６を１０μｍ以内と非常に薄く設けても、リードフレーム１の表面１３に設けられたＡｕ又はＰｄ薄膜層１４のマイグレーションに起因して半導体チップ２とリードフレーム１とがショートする絶縁不良を防止することができる。   According to the semiconductor device described above, the Au or Pd thin film layer 14 made of Au or Pd is provided on the surface 13 of the lead frame 1. The Au or Pd thin film layer 14 is unlikely to undergo migration that moves along the side surface of the semiconductor chip 2 due to the electric field generated in the semiconductor chip 2. For this reason, even if the insulating layer 6 is provided as thin as 10 μm or less in order to prevent damage to the wires 4A, 4B, and 4C, it is caused by the migration of the Au or Pd thin film layer 14 provided on the surface 13 of the lead frame 1. It is possible to prevent insulation failure in which the semiconductor chip 2 and the lead frame 1 are short-circuited.

第２実施形態
次に、第２実施形態における本発明の半導体装置について、図３及び図４を参照して説明する。図３は、第２実施形態における本発明の半導体装置を示す断面図である。図４（Ａ）は図３に示す電極パッケージ７の表面図であり、図４（Ｂ）は図３に示す電極パッケージ７の裏面図であり、図４（Ｃ）は図４（Ａ）のＩＩ−ＩＩ線断面図である。なお、同図において、図１及び図２について上述した第１実施形態の半導体装置と同等の部分には同一符号を付してその詳細な説明を省略する。なお、図３は複数の半導体装置を一体形成した状態であり、切断線Ｓに沿って切断して個々の半導体装置を切り出す。 Second Embodiment Next, a semiconductor device of the present invention in a second embodiment will be described with reference to FIGS. FIG. 3 is a cross-sectional view showing the semiconductor device of the present invention in the second embodiment. 4A is a front view of the electrode package 7 shown in FIG. 3, FIG. 4B is a back view of the electrode package 7 shown in FIG. 3, and FIG. 4C is a view of FIG. It is II-II sectional view taken on the line. In the figure, the same parts as those of the semiconductor device of the first embodiment described above with reference to FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. FIG. 3 shows a state in which a plurality of semiconductor devices are integrally formed, and each semiconductor device is cut out along the cutting line S.

同図に示すように、半導体装置は、電極パッケージ７と、半導体チップ２と、封止部材３と、ワイヤ４と、を備えている。電極パッケージ７は、図４に示すように、板状樹脂７１を有している。この板状樹脂７１内には、同一形状の複数の独立した導電部材としての電極層７２がマトリクス状に並べて、樹脂封止されている。また、この電極層７２は、板状樹脂７１の両板面である表面及び裏面から露出するように、樹脂封止されている。さらに、電極層７２は、板状樹脂７１の表面から裏面に向かうに従って、断面積が大きくなるように形成されている。   As shown in the figure, the semiconductor device includes an electrode package 7, a semiconductor chip 2, a sealing member 3, and a wire 4. The electrode package 7 has a plate-like resin 71 as shown in FIG. In the plate-like resin 71, a plurality of independent conductive members 72 having the same shape are arranged in a matrix and sealed with resin. In addition, the electrode layer 72 is resin-sealed so as to be exposed from the front and back surfaces of both plate surfaces of the plate-like resin 71. Furthermore, the electrode layer 72 is formed so that the cross-sectional area increases as it goes from the front surface to the back surface of the plate-like resin 71.

電極層７２は、図３及び図４（Ｃ）に示すように、ニッケル（Ｎｉ）、ニッケル・コバルト（Ｎｉ・Ｃｏ）又はＣｕ合金を電着した導電層７２Ａと、導電層７２Ａの裏面に形成された半田乗りの良いＡｕ又は錫（Ｓｎ）から成るＡｕ又はＳｎ薄膜層７２Ｂと、表面側に形成されたＡｕ又はＰｄから成る薄膜層としてのＡｕ又はＰｄ薄膜層７２Ｃと、から構成されている。上記Ａｕ又はＰｄはワイヤ４とのワイヤボンダが可能であり、かつ、マイグレーションが生じにくい材料である。上記Ａｕ又はＳｎ薄膜層７２Ｂには、図３に示すように、半田などの導電材料を付着して、ボール状の導電端子７３が設けられている。   As shown in FIGS. 3 and 4C, the electrode layer 72 is formed on a conductive layer 72A electrodeposited with nickel (Ni), nickel-cobalt (Ni.Co), or Cu alloy, and on the back surface of the conductive layer 72A. The Au or Sn thin film layer 72B made of Au or tin (Sn) with good soldering and the Au or Pd thin film layer 72C as a thin film layer made of Au or Pd formed on the surface side is constituted. . Au or Pd is a material that can be bonded to the wire 4 and is less likely to cause migration. As shown in FIG. 3, a ball-shaped conductive terminal 73 is provided on the Au or Sn thin film layer 72B by attaching a conductive material such as solder.

半導体チップ２は、図３に示すように、表面に例えば電極２２が設けられている。半導体チップ２は、裏面が電極層７２の表面と対向するように、電極パッケージ７上に搭載されている。封止部材３は、樹脂などから構成され、電極パッケージ７の裏面を露出させた状態で電極パッケージ７、半導体チップ２及びワイヤ４を封止する。ワイヤ４は、上記電極２２と電極層７２とを接続している。また、半導体装置は、半導体チップ２と電極層７２との間に絶縁層６が設けられている。絶縁層６は、第１実施形態と同様であるため、ここでは詳細な説明を省略する。   As shown in FIG. 3, the semiconductor chip 2 is provided with, for example, an electrode 22 on the surface. The semiconductor chip 2 is mounted on the electrode package 7 so that the back surface faces the surface of the electrode layer 72. The sealing member 3 is made of resin or the like, and seals the electrode package 7, the semiconductor chip 2, and the wires 4 with the back surface of the electrode package 7 exposed. The wire 4 connects the electrode 22 and the electrode layer 72. In the semiconductor device, the insulating layer 6 is provided between the semiconductor chip 2 and the electrode layer 72. Since the insulating layer 6 is the same as that of the first embodiment, a detailed description thereof is omitted here.

上述した半導体装置によれば、電極層７２の表面にＡｕ又はＰｄから成るＡｕ又はＰｄ薄膜層７２Ｃが設けられている。Ａｕ又はＰｄ薄膜層７２Ｃは、半導体チップ２に生じる電界によって半導体チップ２の側面に沿って移動するマイグレーションが生じることがない。このため、ワイヤ４Ａ、４Ｂ、４Ｃのダメージを防ぐために絶縁層６を１０μｍ以内と非常に薄く設けても、電極層７２の表面１３に設けられたＡｕ又はＰｄ薄膜層７２Ｃのマイグレーションに起因して半導体チップ２と電極層７２とがショートする絶縁不良を防止することができる。   According to the semiconductor device described above, the Au or Pd thin film layer 72C made of Au or Pd is provided on the surface of the electrode layer 72. The Au or Pd thin film layer 72 </ b> C does not undergo migration that moves along the side surface of the semiconductor chip 2 due to the electric field generated in the semiconductor chip 2. For this reason, even if the insulating layer 6 is provided as thin as 10 μm or less in order to prevent damage to the wires 4A, 4B, and 4C, it is caused by the migration of the Au or Pd thin film layer 72C provided on the surface 13 of the electrode layer 72. It is possible to prevent insulation failure in which the semiconductor chip 2 and the electrode layer 72 are short-circuited.

第３実施形態
次に、第３実施形態における本発明の半導体装置について、図５及び図６を参照して説明する。図５（Ａ）は第３実施形態における本発明の半導体装置を示す表面図であり、図５（Ｂ）は図５（Ａ）のＩＩＩ−ＩＩＩ線断面図である。図６（Ａ）は図５に示す電極パッケージ７の表面図であり、図６（Ｂ）は図５に示す電極パッケージ７の裏面図であり、図６（Ｃ）は図６（Ａ）のＩＶ−ＩＶ線断面図である。なお、同図において、図１〜図４について上述した第１及び第２実施形態の半導体装置と同等の部分には同一符号を付してその詳細な説明を省略する。 Third Embodiment Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 5A is a surface view showing the semiconductor device of the present invention in the third embodiment, and FIG. 5B is a cross-sectional view taken along the line III-III in FIG. 6A is a front view of the electrode package 7 shown in FIG. 5, FIG. 6B is a rear view of the electrode package 7 shown in FIG. 5, and FIG. 6C is a view of FIG. It is IV-IV sectional view. In the figure, the same parts as those of the semiconductor devices of the first and second embodiments described above with reference to FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted.

同図に示すように、半導体装置は、電極パッケージ７と、半導体チップ２と、封止部材３と、ワイヤ４と、を備えている。電極パッケージ７は、図６に示すように、半導体チップ２が搭載されると共に半導体チップ２と電気的に接続される導電部材としての導電パターン層７４と、この導電パターン層７４の裏面側に積層して設けられ、同一形状の複数の独立した電極材からなる電極層７２とを備えている。この導電パターン層７４及び電極層７２とは板状樹脂７１内に封止され、この板状樹脂７１の表面から導電パターン層７４が露出し、この板状樹脂７１の裏面から電極層７２が露出している。   As shown in the figure, the semiconductor device includes an electrode package 7, a semiconductor chip 2, a sealing member 3, and a wire 4. As shown in FIG. 6, the electrode package 7 has a conductive pattern layer 74 as a conductive member on which the semiconductor chip 2 is mounted and electrically connected to the semiconductor chip 2, and is laminated on the back side of the conductive pattern layer 74. And an electrode layer 72 made of a plurality of independent electrode materials having the same shape. The conductive pattern layer 74 and the electrode layer 72 are sealed in the plate-shaped resin 71, the conductive pattern layer 74 is exposed from the surface of the plate-shaped resin 71, and the electrode layer 72 is exposed from the back surface of the plate-shaped resin 71. is doing.

導電パターン層７４は、図６（Ｃ）に示すように、Ｎｉ、Ｎｉ・Ｃｏ又はＣｕ合金を電着した導電層７４Ａと、導電層７４Ａの表面に積層されたＡｕ又はＰｄから成る薄膜層としてのＡｕ又はＰｄ薄膜層７４Ｂと、から構成される。Ａｕ又はＰｄは、ワイヤ４とのワイヤボンダが可能であり、かつ、マイグレーションが生じにくい材料である。また、電極層７２は、その裏面側に形成された半田乗りの良いＡｕ又はＳｎ薄膜層と、このＡｕ又はＳｎ薄膜層の表面側に積層して形成されたＮｉ、Ｎｉ・Ｃｏ又はＣｕ合金を電着したＮｉ、Ｎｉ・Ｃｏ又はＣｕ薄膜層とから構成される。また、電極層７２の裏面には、半田などの導電材料を付着して、ボール状の導電端子７３（図５（Ｂ））が設けられている。   As shown in FIG. 6C, the conductive pattern layer 74 includes a conductive layer 74A electrodeposited with Ni, Ni · Co or Cu alloy, and a thin film layer made of Au or Pd laminated on the surface of the conductive layer 74A. And an Au or Pd thin film layer 74B. Au or Pd is a material that can be wire-bonded with the wire 4 and hardly causes migration. The electrode layer 72 is made of a solder-mounting Au or Sn thin film layer formed on the back side thereof and a Ni, Ni · Co or Cu alloy formed by laminating on the surface side of the Au or Sn thin film layer. It is composed of an electrodeposited Ni, Ni · Co or Cu thin film layer. In addition, a conductive material 73 such as solder is attached to the back surface of the electrode layer 72 to provide a ball-shaped conductive terminal 73 (FIG. 5B).

半導体チップ２は、第２実施形態と同様に、表面に例えば電極２２が設けられている。半導体チップ２は、その裏面が導電パターン層７４の表面と対向するように、電極パッケージ７上に搭載されている。封止部材３は、樹脂などから構成され、電極パッケージ７の裏面を露出させた状態で電極パッケージ７、半導体チップ２及びワイヤ４を封止する。ワイヤ４は、導電パターン層７４と電極２２とを接続している。また、半導体装置は、半導体チップ２と電極パッケージ７との間に絶縁層６が設けられている。絶縁層６は、第１及び第２実施形態と同様なため、ここではその詳細な説明は省略する。   As in the second embodiment, the semiconductor chip 2 is provided with, for example, an electrode 22 on the surface. The semiconductor chip 2 is mounted on the electrode package 7 so that the back surface thereof faces the surface of the conductive pattern layer 74. The sealing member 3 is made of resin or the like, and seals the electrode package 7, the semiconductor chip 2, and the wires 4 with the back surface of the electrode package 7 exposed. The wire 4 connects the conductive pattern layer 74 and the electrode 22. In the semiconductor device, an insulating layer 6 is provided between the semiconductor chip 2 and the electrode package 7. Since the insulating layer 6 is the same as in the first and second embodiments, a detailed description thereof is omitted here.

上述した半導体装置によれば、導電パターン層７４の表面にＡｕ又はＰｄから成るＡｕ又はＰｄ薄膜層７４Ｂが設けられている。Ａｕ又はＰｄ薄膜層７４Ｂは、半導体チップ２に生じる電界によって半導体チップ２の側面に沿って移動するマイグレーションが生じることがない。このため、ワイヤ４Ａ、４Ｂ、４Ｃのダメージを防ぐために絶縁層６を１０μｍ以内と非常に薄く設けても、導電パターン層７４の表面に設けられたＡｕ又はＰｄ薄膜層７４Ｂのマイグレーションに起因して半導体チップ２と導電パターン層７４とがショートする絶縁不良を防止することができる。   According to the semiconductor device described above, the Au or Pd thin film layer 74B made of Au or Pd is provided on the surface of the conductive pattern layer 74. The Au or Pd thin film layer 74 </ b> B does not undergo migration that moves along the side surface of the semiconductor chip 2 due to the electric field generated in the semiconductor chip 2. Therefore, even if the insulating layer 6 is provided as thin as 10 μm or less in order to prevent damage to the wires 4A, 4B, and 4C, it is caused by the migration of the Au or Pd thin film layer 74B provided on the surface of the conductive pattern layer 74. It is possible to prevent an insulation failure in which the semiconductor chip 2 and the conductive pattern layer 74 are short-circuited.

また、前述した実施形態は本発明の代表的な形態を示したに過ぎず、本発明は、実施形態に限定されるものではない。即ち、本発明の骨子を逸脱しない範囲で種々変形して実施することができる。   Further, the above-described embodiments are merely representative forms of the present invention, and the present invention is not limited to the embodiments. That is, various modifications can be made without departing from the scope of the present invention.

第１実施形態における本発明の半導体装置を示す表面図である。It is a surface view showing a semiconductor device of the present invention in a 1st embodiment. 図１の半導体装置のＩ−Ｉ線断面図である。It is the II sectional view taken on the line of the semiconductor device of FIG. 第２実施形態における本発明の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of this invention in 2nd Embodiment. 図４（Ａ）は図３に示す電極パッケージの表面図であり、図４（Ｂ）は図３に示す電極パッケージの裏面図であり、図４（Ｃ）は図４（Ａ）のＩＩ−ＩＩ線断面図である。4A is a front view of the electrode package shown in FIG. 3, FIG. 4B is a back view of the electrode package shown in FIG. 3, and FIG. It is II sectional view. 図５（Ａ）は第３実施形態における本発明の半導体装置を示す表面図であり、図５（Ｂ）は図５（Ａ）のＩＩＩ−ＩＩＩ線断面図である。FIG. 5A is a surface view showing the semiconductor device of the present invention in the third embodiment, and FIG. 5B is a cross-sectional view taken along the line III-III in FIG. 図６（Ａ）は図５に示す電極パッケージの表面図であり、図６（Ｂ）は図５に示す電極パッケージの裏面図であり、図６（Ｃ）は図６（Ａ）のＩＶ−ＩＶ線断面図である。6A is a front view of the electrode package shown in FIG. 5, FIG. 6B is a back view of the electrode package shown in FIG. 5, and FIG. It is IV sectional view. 従来の半導体装置の一例を示す断面図である。It is sectional drawing which shows an example of the conventional semiconductor device.

符号の説明Explanation of symbols

１ リードフレーム（導電部材）
２ 半導体チップ（チップ部品）
４ ワイヤ
４Ａ ワイヤ
４Ｂ ワイヤ
４Ｃ ワイヤ
６ 絶縁層
１１Ａ リード
１１Ｂ リード
１１Ｃ リード
１４ Ａｕ又はＰｄ薄膜層（薄膜層）
２２ 電極
２２Ａ 電極
２２Ｂ 電極
２２Ｃ 電極
７２ 電極層（導電部材）
７２Ｃ Ａｕ又はＰｄ薄膜層（薄膜層）
７４ 導電パターン層（導電部材）
７４Ｂ Ａｕ又はＰｄ薄膜層（薄膜層） 1 Lead frame (conductive member)
2 Semiconductor chip (chip parts)
4 wire 4A wire 4B wire 4C wire 6 insulating layer 11A lead 11B lead 11C lead 14 Au or Pd thin film layer (thin film layer)
22 electrode 22A electrode 22B electrode 22C electrode 72 electrode layer (conductive member)
72C Au or Pd thin film layer (thin film layer)
74 Conductive pattern layer (conductive member)
74B Au or Pd thin film layer (thin film layer)

Claims (3)

導電部材と、表面側に電極が設けられると共に裏面側が前記導電部材の表面と対向するように前記導電部材上に搭載されるチップ部品と、前記チップ部品の電極と前記導電部材との間にワイヤボンダされたワイヤと、前記チップ部品の裏面と前記導電部材の表面との間に設けられた絶縁層と、前記導電部材の表面に設けられたワイヤボンダ可能な薄膜層と、を備えた半導体装置において、
前記薄膜層が、金又はパラジウムから構成されていることを特徴とする半導体装置。 A conductive member, a chip component mounted on the conductive member such that an electrode is provided on the front surface side and a back surface side faces the surface of the conductive member, and a wire bonder between the electrode of the chip component and the conductive member In a semiconductor device comprising: a wire formed; an insulating layer provided between a back surface of the chip component and the surface of the conductive member; and a thin film layer capable of wire bonding provided on the surface of the conductive member.
The semiconductor device, wherein the thin film layer is made of gold or palladium. 前記導電部材が、外部接続用のリードが設けられたリードフレームから構成されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductive member includes a lead frame provided with a lead for external connection. 前記導電部材が、互いに独立した複数の電極層、又は、前記電極層の表面側に席相された導電パターン層、から構成されていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the conductive member includes a plurality of electrode layers independent from each other or a conductive pattern layer arranged on the surface side of the electrode layer.
JP2007246798A 2007-09-25 2007-09-25 Semiconductor device Pending JP2009076822A (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004266109A (en) * 2003-03-03 2004-09-24 Dainippon Printing Co Ltd Circuit board for ic card, ic module and manufacturing method thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004266109A (en) * 2003-03-03 2004-09-24 Dainippon Printing Co Ltd Circuit board for ic card, ic module and manufacturing method thereof

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