JP2009071765A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output a circuit-operation stopping signal from a semiconductor integrated circuit, when at least one of two high-potential-side power supplies having respectively their different voltages is not supplied. <P>SOLUTION: The semiconductor integrated circuit 30 has an input driver portion 1, a level shifting circuit 2, and an output driver portion 3. To the semiconductor integrated circuit 30, a first high-potential-side power supply VddL, and a second high-potential-side power supply VddH whose voltage is equal to the voltage of the first high-potential-side power supply VddL or higher than the voltage of the first high-potential-side power supply VddL are supplied. When at least one of the first and second high-potential-side power supplies VddL, VddH is not supplied, a low-level circuit-operation stopping signal is outputted from the semiconductor integrated circuit 30. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit to which a plurality of high potential side power supplies having different voltages are supplied.

  With the progress of miniaturization of semiconductor elements constituting a semiconductor integrated circuit (LSI) and higher integration of semiconductor integrated circuits, it is possible to reduce the power consumption of the semiconductor integrated circuit while ensuring the reliability of the internal circuit elements. Required. In order to realize this requirement, a plurality of high potential side power supplies having different voltages are supplied to the semiconductor integrated circuit. When a plurality of high-potential side power supplies having different voltages are used, circuits having different signal levels for performing logic processing are mounted on the semiconductor integrated circuit, so that a level shift circuit for converting the signal level between them is required (for example, , See Patent Document 1).

In a semiconductor integrated circuit described in Patent Document 1 or the like, an input drive unit to which a first high potential side power source is supplied, a first high potential side power source, and a second higher voltage than the first high potential side power source. Are provided with a level shift circuit that shifts the signal level and an output drive unit that is supplied with the second high potential power. When the first high potential side power source is supplied and the second high potential side power source is not supplied, and when the first high potential side power source is not supplied and the second high potential side power source is not supplied, the output drive A low level circuit operation stop signal is output from the unit. However, when the first high potential side power source is not supplied and the second high potential side power source is supplied, the input value of the input signal input to the input drive unit immediately before the first high potential side power source is interrupted. Therefore, there is a problem that a low level circuit operation stop signal may not be output from the output drive unit. By mounting the power supply voltage detection circuit in the semiconductor integrated circuit, the problem that the low-level circuit operation stop signal may not be output from the output drive unit can be avoided, but the power consumption and high integration of the semiconductor integrated circuit are reduced. There arises a problem that it becomes difficult.
JP 2004-112666 A

  The present invention provides a semiconductor integrated circuit that outputs a circuit operation stop signal when at least one of two high-potential-side power supplies having different voltages is not supplied.

  The semiconductor integrated circuit of one embodiment of the present invention is provided between a first high-potential-side power supply and a low-potential-side power supply, and receives an input signal, and outputs an input driver that drives the input signal And the second high-potential side power source having the same voltage as the first high-potential side power source and the first high-potential side power source or a voltage higher than that of the first high-potential side power source. A level shift circuit that is connected to a potential-side power supply, receives the first signal output from the input driver unit, and outputs a second signal obtained by shifting the level of the first signal; Provided between the potential side power source and the low potential side power source, the second signal output from the level shift circuit is input, the signal driving the second signal is output, and the input signal is low Level, the first high potential side power supply When the second high potential side power supply is supplied, a low level signal is output, the input signal is high level, the first high potential side power supply is supplied, and the second high potential side power supply Outputs a high level signal when the power source is supplied, and outputs a low level signal when at least one of the first high potential side power source and the second high potential side power source is not supplied. And an output drive circuit.

  Furthermore, a semiconductor integrated circuit according to another aspect of the present invention is provided between a first high potential power source and a low potential power source, and receives an input signal and outputs a first signal that drives the input signal. Provided between the input driver unit and the second high potential side power source having the same voltage as the first high potential side power source or a voltage higher than the first high potential side power source and the low potential side power source, A level shift circuit that receives the first signal output from the input driver unit and outputs a second signal obtained by level shifting the first signal; the second high-potential side power supply; and the low-potential side Provided between the power supplies, the second signal output from the level shift circuit is input, the signal driving the second signal is output, the input signal is low level, the first high potential Side power supply, and the second high potential side A low level signal is output when the source is a supply, a high level signal is output when the input signal is a high level, the first high potential side power supply is supplied, and the second high potential side power supply is supplied And an output drive circuit that outputs a low level signal when at least one of the first high potential power source and the second high potential power source is not supplied. Features.

  According to the present invention, it is possible to provide a semiconductor integrated circuit that outputs a circuit operation stop signal when at least one of two high-potential side power supplies having different voltages is not supplied.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor integrated circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram illustrating a semiconductor integrated circuit, and FIG. 2 is a diagram illustrating a relationship between an input signal, an output signal, a first high potential side power source, and a second high potential side power source of the semiconductor integrated circuit. In this embodiment, the circuit operation stop signal is output when at least one of the two high-potential side power supplies having different voltages is not supplied.

  As shown in FIG. 1, the semiconductor integrated circuit 30 includes an input driver unit 1, a level shift circuit 2, and an output driver unit 3. The semiconductor integrated circuit 30 is mounted on, for example, an SoC (System on a chip), and has a function of level shifting the signal level and a shutdown function. The semiconductor integrated circuit 30 includes a second high potential side power source VddH having the same voltage as the first high potential side power source VddL and the first high potential side power source VddL or a voltage higher than the first high potential side power source VddL. When at least one of the first high potential power source VddL and the second high potential power source VddH is not supplied, a low level circuit operation stop signal is output from the semiconductor integrated circuit 30. Based on the low-level circuit operation stop signal, the operation of the internal circuit provided in the SoC stops (shuts down).

  The input driver unit 1 is provided with a pre-driver 11 and a first buffer BUF1. The pre-driver 11 is provided between the first high potential side power source VddL and the low potential side power source (ground potential) Vss, receives the input signal Sin, and outputs a signal that drives the input signal Sin. Here, the input signal is input via an input terminal (not shown). For example, the input signal may be generated inside the SoC and input to the pre-driver 11. The first buffer BUF1 is provided between the first high-potential-side power supply VddL and the low-potential-side power supply (ground potential) Vss. A signal output from the pre-driver 11 is input, and a signal that drives this signal is displayed. Output from node N1.

  The level shift circuit 2 includes a first inverter INV1, a second inverter INV2, Nch MOS transistors NMT1 to NMT6, and Pch MOS transistors PMT1 to PMT3. The level shift circuit 2 receives a signal output from the input driver unit 1 and generates a signal obtained by level-shifting this signal.

  Here, the MOS transistor is also referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The MIS transistor is also called a MISFET (Metal Insulator Semiconductor Field Effect Transistor). The MOS transistor and the MIS transistor are also called insulated gate field effect transistors.

  The first inverter INV1 is provided between the first high-potential-side power supply VddL and the low-potential-side power supply (ground potential) Vss, receives a signal output from the first buffer BUF1, and inverts this signal .

  The Nch MOS transistor NMT1 has a drain and a gate connected to the first high potential side power supply VddL, a source connected to the node N2, and operates as a diode. The Nch MOS transistor NMT2 has a gate connected to the node N2, a drain and a source connected to the low potential side power supply (ground potential) Vss, and the first high potential side power supply VddL supplied to the semiconductor integrated circuit 30. It accumulates electric charge and operates as a MOS capacitor. Instead of the MOS capacitor using the Nch MOS transistor NMT2, a MOS capacitor using a Pch MOS transistor, a MOS capacitor, or the like may be used. The Pch MOS transistor PMT1 has a source connected to the node N2, a gate connected to the first high potential side power supply VddL, and a drain connected to the node N3. The Nch MOS transistor NMT3 has a drain connected to the node N3, a gate connected to the first high potential side power supply VddL, and a source connected to the low potential side power supply (ground potential) Vss. The Nch MOS transistor NMT4 has a drain connected to the node N4, a gate connected to the node N3, and a source connected to the low potential side power supply (ground potential) Vss.

  The Pch MOS transistor PMT2 has a source connected to the second high potential side power source VddH having the same voltage as the first high potential side power source VddL or a voltage higher than the first high potential side power source VddL, and a gate connected to the node N5. The drain is connected to the node N4. In the Nch MOS transistor NMT5, the drain is connected to the node N4, the signal output from the inverter INV1 is input to the gate, and the source is connected to the low potential side power supply (ground potential) Vss. The Pch MOS transistor PMT3 has a source connected to the second high potential side power supply VddH, a gate connected to the node N4, and a drain connected to the node N5. The Nch MOS transistor NMT6 has a drain connected to the node N5, a gate connected to the node N1 (the output side of the first buffer BUF1), and a source connected to the low potential side power supply (ground potential) Vss. Pch MOS transistors PMT2 and PMT3 form a latch circuit.

  The second inverter INV2 is provided between the second high potential side power source VddH and the low potential side power source (ground potential) Vss, and the input side is the node N5 (the drain of the Pch MOS transistor PMT3 and the drain of the Nch MOS transistor NMT6). And a signal obtained by inverting the signal of the node N5 is output from the node N6.

  The output driver unit 3 is provided with a second buffer BUF2. The second buffer BUF2 is provided between the second high-potential-side power supply VddH and the low-potential-side power supply (ground potential) Vss, and receives a signal output from the second inverter INV2 (signal of the node N6). Then, this signal is driven to output an output signal Sout.

  As shown in FIG. 2, in the semiconductor integrated circuit 30, first, when the first high potential side power source VddL and the second high potential side power source VddH are supplied (energized state), the Nch MOS transistor NMT1 and the Nch MOS transistor The transistor NMT3 is turned “ON” and the Pch MOS transistor PMT1 is turned “OFF”. The Nch MOS transistor NMT2 which is a MOS capacitor is supplied with electric charge from the first high potential side power supply VddL and accumulates electric charge. Since the Nch MOS transistor NMT4 has the same level as the source potential connected to the low potential side power supply (ground potential) Vss, the Nch MOS transistor NMT4 is cut off. That is, the Pch MOS transistors PMT2 and PMT3 constituting the latch circuit are not affected.

  When the “Low” level input signal Sin is input, the output signal of the first inverter INV1 becomes “High” level, the output signal of the second inverter INV2 becomes “Low” level, and the output signal Sout becomes “Low”. Become a level. When the “High” level input signal Sin is input, the output signal of the first inverter INV1 becomes the “Low” level, the output signal of the second inverter INV2 becomes the “High” level obtained by level shifting, and the output signal Sout Becomes the “High” level that has been level-shifted.

  Next, when the first high potential side power supply VddL is not supplied (not supplied) and the second high potential side power supply VddH is supplied (energized), the Nch MOS transistor NMT1 and the Nch MOS transistor NMT3 are “OFF”. Then, the Pch MOS transistor PMT1 is turned “ON”. Since the electric charge accumulated in the N-channel MOS transistor NMT2 which is a MOS capacitor is supplied to the gate of the N-channel MOS transistor NMT4 via the P-channel MOS transistor PMT1, the N-channel MOS transistor NMT4 is turned on. As a result, the node N4 becomes “Low” level, the Pch MOS transistor PMT3 becomes “ON”, and the node N5 becomes the second high potential side power supply VddH voltage level (“High” level). The Pch MOS transistor PMT2 is “OFF”, the signal output from the second inverter INV2 is at the “Low” level, and the output signal Sout is a circuit operation stop signal at the “Low” level. Here, the potentials of the nodes N4 and N5 are not affected by the signal level of the input signal Sin. For this reason, the output signal Sout becomes a circuit operation stop signal of “Low” level regardless of whether the input signal Sin is “High” level or “Low” level.

  Subsequently, when the first high potential power source VddL is supplied or not supplied and the second high potential power source VddH is not supplied, the second high potential power source VddH is supplied to the level shift circuit 2 and the second buffer BUF2. Is not supplied, the output signal Sout becomes a “Low” level circuit operation stop signal regardless of the state of the input signal Sin and the first high-potential-side power supply VddL.

  Here, the first high-potential-side power supply VddL changes from the supply state to the non-supply state, and the output signal Sout becomes a “Low” level circuit operation stop signal even when the second high-potential-side power supply VddH is supplied. . This means that the semiconductor integrated circuit 30 does not hold the signal level of the input signal Sin immediately before the voltage supply of the first high potential side power supply VddL is interrupted. For this reason, in the SoC in which the semiconductor integrated circuit 30 is mounted, it is not necessary to mount a power supply voltage detection circuit.

  Normally, the power supply voltage detection circuit occupies about 5% of the chip area in SoC and system LSI, and generates a current consumption of several tens of μA to 50 μA. In addition, it is necessary to evaluate the characteristics as to whether the design value is satisfied.

  As described above, in the semiconductor integrated circuit of this embodiment, the input driver unit 1, the level shift circuit 2, and the output driver unit 3 are provided. The semiconductor integrated circuit 30 includes a second high potential side power source VddH having the same voltage as the first high potential side power source VddL and the first high potential side power source VddL or a voltage higher than the first high potential side power source VddL. Supplied. When the first high potential side power source VddL and the second high potential side power source VddH are supplied, the semiconductor integrated circuit 30 outputs the low level output signal Sout when the input signal Sin is at the low level. When the signal Sin is at a high level, the level-shifted output signal Sout is output. When at least one of the first high potential side power supply VddL and the second high potential side power supply VddH is not supplied, the low level is output. The circuit operation stop signal is output.

  For this reason, when the first high potential side power supply VddL is not supplied and the second high potential side power supply VddH is supplied, the first high potential side power supply VddL is input to the input drive unit 1 immediately before being interrupted. Since a low level circuit operation stop signal is output from the output drive unit 3 without holding the input value of the input signal Sin, there is no need to mount a power supply voltage detection circuit. Further, since the power supply detection circuit is not mounted, an increase in the chip area of the semiconductor integrated circuit 30 can be suppressed, and low power consumption and high integration can be achieved.

  In this embodiment, a MOS transistor is used for the semiconductor integrated circuit 30, but a MIS transistor (also referred to as MISFET) may be used. Further, a bipolar transistor or a junction FET (JFET) may be used instead of the MOS transistor.

  Next, a semiconductor integrated circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram showing a semiconductor integrated circuit. In this embodiment, the level shift circuit is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 3, the semiconductor integrated circuit 30a is provided with an input driver unit 1, a level shift circuit 2a, and an output driver unit 3. The semiconductor integrated circuit 30a is mounted, for example, on the SoC and has a function of shifting the signal level and a shutdown function. The semiconductor integrated circuit 30a has a first high potential side power source VddL and a second high potential side power source VddH having the same voltage as the first high potential side power source VddL or a voltage higher than the first high potential side power source VddL. When at least one of the first high potential side power supply VddL and the second high potential side power supply VddH is not supplied, a low level circuit operation stop signal is output from the semiconductor integrated circuit 30a.

  The level shift circuit 2a is provided with a first inverter INV1, a second inverter INV2, Nch MOS transistors NMT11 to 15 and Pch MOS transistors PMT11 to 15. The level shift circuit 2a receives a signal output from the input driver unit 1, and generates a signal obtained by level-shifting this signal.

  The first inverter INV1 is provided between the first high-potential-side power supply VddL and the low-potential-side power supply (ground potential) Vss, and receives a signal output from the first buffer BUF1 (signal of the node N1). Then, a signal obtained by inverting this signal is output from the node N11.

  The Nch MOS transistor NMT11 has a drain connected to the first high potential side power supply VddL, and a gate having the same voltage as the first high potential side power supply VddL or a second voltage having a higher voltage than the first high potential side power supply VddL. It is connected to the high potential side power supply VddH. The source of the Pch MOS transistor PMT11 is connected to the source of the Nch MOS transistor NMT11, the signal output from the first inverter INV1 (the signal of the node N11) is input to the gate, and the drain is connected to the node N12. In the Nch MOS transistor NMT12, the drain is connected to the node N12, the signal output from the first inverter INV1 (the signal of the node N11) is input to the gate, and the source is connected to the low potential side power supply (ground potential) Vss. The Pch MOS transistor PMT11 and Nch MOS transistor NMT12 form an inverter, and output a signal obtained by inverting the signal of node N11 from node N12.

  The Pch MOS transistor PMT12 has a source connected to the second high potential side power supply VddH and a gate connected to the node N14. Nch MOS transistor NMT13 has a drain connected to the drain of Pch MOS transistor PMT12, a gate connected to node N12, and a source connected to node N13. The Nch MOS transistor NMT14 has a drain connected to the node N13, a gate connected to the first high potential side power supply VddL, and a source connected to the node N12. The Pch MOS transistor PMT13 has a source connected to the node N13, a gate connected to the first high potential side power supply VddL, and a drain connected to the low potential side power supply (ground potential) Vss.

  The Pch MOS transistor PMT14 has a source connected to the second high potential side power supply VddH and a gate connected to the node N13 (the source of the Nch MOS transistor NMT1 and the drain of the Nch MOS transistor NMT14) and the source of the Pch MOS transistor PMT13. . Pch MOS transistor PMT15 has a source connected to the drain of Pch MOS transistor PMT14, a gate connected to the gate of Nch MOS transistor NMT13 and node N12, and a drain connected to node N14. The Nch MOS transistor NMT15 has a drain connected to the node N14, a gate connected to the gate of the Nch MOS transistor NMT13, a gate of the Pch MOS transistor PMT15, and the node N12, and a source connected to the low potential side power supply (ground potential) Vss. Is done. Pch MOS transistors PMT12 and PMT14 constitute a latch circuit.

  The second inverter INV2 is provided between the second high potential side power source VddH and the low potential side power source (ground potential) Vss, and the input side is a node N14 (the drain of the Pch MOS transistor PMT15 and the drain of the Nch MOS transistor NMT15). And outputs a signal obtained by inverting the signal of the node N14 from the node N6.

  Next, the operation of the semiconductor integrated circuit 30a will be described. First, when the first high potential side power supply VddL and the second high potential side power supply VddH are supplied (energized state), the Nch MOS transistor NMT11 and the Nch MOS transistor NMT14 are “ON”, and the Pch MOS transistor PMT13 is turned on. It will be in the “OFF” state. Since the inverter composed of the Pch MOS transistor PMT11 and the Nch MOS transistor NMT12 operates, when the input signal Sin is at “Low” level, the node N11 is at “High” level, the node N12 is at “Low” level, and the node N13 is at Low level. ", The Pch MOS transistors PMT14 and PMT15 are" ON ", and the node N14 is at the second high potential side power supply VddH voltage level (" High "level). The Pch MOS transistor PMT12 and the Nch MOS transistor NMT13 are" OFF " Then, the output signal of the second inverter INV2 becomes the “Low” level, and the output signal Sout becomes the “Low” level.

  When the input signal Sin is at the “High” level, the node N11 is at the “Low” level, the node N12 is at the first high potential side power supply VddL voltage level (“High” level), the node N13 is at the Low level, and the Nch MOS transistor The NMT 15 is turned “ON”, the node N 14 is set to the “Low” level, the output signal of the second inverter INV 2 is changed to the “High” level, and the output signal Sout is set to the “High” level.

  Next, when the first high potential side power supply VddL is not supplied (not supplied) and the second high potential side power supply VddH is supplied (energized), the Nch MOS transistor NMT13, the Nch MOS transistor NMT14, and the Nch MOS are supplied. The transistor NMT15 is turned “OFF”, and the Pch MOS transistor PMT13 and the Pch MOS transistor PMT15 are turned “ON”. At this time, since the node N13 is at the “Low” level, the Pch MOS transistor PMT14 is “ON”, and the node N14 is at the second high potential side power source VddH voltage level (“High” level). The signal output from the second inverter INV2 becomes “Low” level, and the output signal Sout becomes a “Low” level circuit operation stop signal. Here, the potentials of the nodes N13 and N14 are not affected by the signal level of the input signal Sin. For this reason, the output signal Sout becomes a circuit operation stop signal of “Low” level regardless of whether the input signal Sin is “High” level or “Low” level.

  Subsequently, when the first high potential side power supply VddL is supplied or not supplied and the second high potential side power supply VddH is not supplied, the second high potential side power supply is supplied to the level shift circuit 2a and the second buffer BUF2. Since the power supply VddH is not supplied, the output signal Sout becomes a “Low” level circuit operation stop signal regardless of the state of the input signal Sin and the first high potential side power supply VddL.

  The operation of the semiconductor integrated circuit 30a described above is the same as that of the first embodiment (FIG. 1). Here, the first high-potential-side power supply VddL changes from the supply state to the non-supply state, and the output signal Sout becomes a “Low” level circuit operation stop signal even when the second high-potential-side power supply VddH is supplied. . This means that the semiconductor integrated circuit 30a does not hold the signal level of the input signal Sin immediately before the voltage supply of the first high potential side power supply VddL is interrupted. For this reason, it is not necessary to mount a power supply voltage detection circuit in the SoC in which the semiconductor integrated circuit 30a is mounted.

  As described above, in the semiconductor integrated circuit of this embodiment, the input driver unit 1, the level shift circuit 2a, and the output driver unit 3 are provided. The semiconductor integrated circuit 30a includes a second high potential side power source VddH having the same voltage as the first high potential side power source VddL and the first high potential side power source VddL or a voltage higher than the first high potential side power source VddL. Supplied. When the first high potential side power supply VddL and the second high potential side power supply VddH are supplied, the semiconductor integrated circuit 30a outputs the low level output signal Sout when the input signal Sin is at the low level. When the signal Sin is at a high level, the level-shifted output signal Sout is output. When at least one of the first high potential side power supply VddL and the second high potential side power supply VddH is not supplied, the low level is output. The circuit operation stop signal is output.

  For this reason, when the first high potential side power supply VddL is not supplied and the second high potential side power supply VddH is supplied, the first high potential side power supply VddL is input to the input drive unit 1 immediately before being interrupted. Since a low level circuit operation stop signal is output from the output drive unit 3 without holding the input value of the input signal Sin, there is no need to mount a power supply voltage detection circuit. Further, since the power supply detection circuit is not mounted, an increase in the chip area of the semiconductor integrated circuit 30a can be suppressed, and low power consumption and high integration can be achieved.

  Next, a semiconductor integrated circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing a semiconductor integrated circuit. In this embodiment, the configuration of the level shift circuit is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 4, the semiconductor integrated circuit 30b is provided with an input driver unit 1, a level shift circuit 2b, and an output driver unit 3. The semiconductor integrated circuit 30b is mounted on, for example, an SoC (System on a chip), and has a function of shifting the signal level and a shutdown function. The semiconductor integrated circuit 30b includes a second high potential side power source VddH having the same voltage as the first high potential side power source VddL and the first high potential side power source VddL or a voltage higher than the first high potential side power source VddL. When at least one of the first high potential power source VddL and the second high potential power source VddH is not supplied, a low level circuit operation stop signal is output from the semiconductor integrated circuit 30b. Based on the low-level circuit operation stop signal, the operation of the internal circuit provided in the SoC stops (shuts down).

  The level shift circuit 2b is provided with a second inverter INV2, Nch MOS transistors NMT21 to 24, and Pch MOS transistors PMT21 to 23. The level shift circuit 2b receives a signal output from the input driver unit 1, and generates a signal obtained by level-shifting this signal.

  The Pch MOS transistor PMT21 has a source connected to the second high potential side power source VddH having the same voltage as the first high potential side power source VddL or a voltage higher than the first high potential side power source VddL, and a gate connected to the node N22. Connected. The Nch MOS transistor NMT21 has a drain connected to the drain of the Pch MOS transistor PMT21, a gate that receives a signal output from the first buffer BUF1 (a signal at the node N1), and a source that is connected to the node N21. The Nch MOS transistor NMT22 has a drain connected to the node N21 and a gate connected to the second high potential side power supply VddH. The Nch MOS transistor NMT23 has a drain connected to the gate and the source of the Nch MOS transistor NMT22, and a signal output from the first buffer BUF1 (a signal of the node N1) is input to the source, and operates as a diode.

  The Pch MOS transistor PMT22 has a source connected to the second high potential side power supply VddH and a gate connected to the node N21 (the source of the Nch MOS transistor NMT21 and the drain of the Nch MOS transistor NMT22). Pch MOS transistor PMT23 has a source connected to the drain of Pch MOS transistor PMT22, a gate connected to the gate of Nch MOS transistor NMT21 and node N1, and a drain connected to node N22. The Nch MOS transistor NMT24 has a drain connected to the node N22, a gate connected to the gate of the Nch MOS transistor NMT21, a gate of the Pch MOS transistor PMT23, and the node N1, and a source connected to the low potential side power supply (ground potential) Vss. Is done.

  The second inverter INV2 is provided between the second high potential side power source VddH and the low potential side power source (ground potential) Vss, and the input side is a node N22 (the drain of the Pch MOS transistor PMT23 and the drain of the Nch MOS transistor NMT24). And outputs a signal obtained by inverting the signal of the node N22 from the node N6.

  Next, the operation of the semiconductor integrated circuit 30b will be described. First, when the first high potential side power source VddL and the second high potential side power source VddH are supplied (energized state), the Nch MOS transistor NMT22 is in an “ON” state. When the input signal Sin is at “Low” level, the node N1 becomes “Low” level, the Pch MOS transistor PMT23 is “ON”, the Nch MOS transistors NMT21 and NMT24 are “OFF”, and the Pch MOS transistor PNT22 is “ON”. Then, the node N22 becomes the second high potential side power supply VddH voltage level ("High" level). The output signal of the second inverter INV2 becomes “Low” level, and the output signal Sout becomes “Low” level.

  When the input signal Sin is at “High” level, the node N1 is at “High” level, the Nch MOS transistor NMT21, the Nch MOS transistor NMT22, and the Nch MOS transistor NMT24 are “ON”, and the node N22 is at “Low” level. . The output signal of the second inverter INV2 is shifted to “High” level, and the output signal Sout is set to “High” level.

  Next, when the first high potential side power supply VddL is not supplied (not supplied) and the second high potential side power supply VddH is supplied (energized), the Nch MOS transistor NMT21 and the Nch MOS transistor NMT24 are “OFF”. Then, the Nch MOS transistor NMT22 and the Pch MOS transistor PMT23 are turned on. At this time, since the node N21 is at the “Low” level, the Pch MOS transistor PMT22 is “ON”, and the node N22 is at the second high potential side power supply VddH voltage level (“High” level). The signal output from the second inverter INV2 becomes “Low” level, and the output signal Sout becomes a “Low” level circuit operation stop signal. Here, the potentials of the nodes N21 and N22 are not affected by the signal level of the input signal Sin. For this reason, the output signal Sout becomes a circuit operation stop signal of “Low” level regardless of whether the input signal Sin is “High” level or “Low” level.

  Subsequently, when the first high potential side power source VddL is supplied or not supplied and the second high potential side power source VddH is not supplied, the second high potential side power source is supplied to the level shift circuit 2b and the second buffer BUF2. Since the power supply VddH is not supplied, the output signal Sout becomes a “Low” level circuit operation stop signal regardless of the state of the input signal Sin and the first high potential side power supply VddL.

  The operation of the semiconductor integrated circuit 30b described above is the same as that of the first embodiment (FIG. 1). Here, the first high-potential-side power supply VddL changes from the supply state to the non-supply state, and the output signal Sout becomes a “Low” level circuit operation stop signal even when the second high-potential-side power supply VddH is supplied. . This means that the semiconductor integrated circuit 30b does not hold the signal level of the input signal Sin immediately before the voltage supply of the first high potential side power supply VddL is interrupted. For this reason, it is not necessary to mount a power supply voltage detection circuit in the SoC in which the semiconductor integrated circuit 30b is mounted.

  As described above, in the semiconductor integrated circuit of this embodiment, the input driver unit 1, the level shift circuit 2b, and the output driver unit 3 are provided. The semiconductor integrated circuit 30b includes a second high potential side power source VddH having the same voltage as the first high potential side power source VddL and the first high potential side power source VddL or a voltage higher than the first high potential side power source VddL. Supplied. When the first high potential side power supply VddL and the second high potential side power supply VddH are supplied, the semiconductor integrated circuit 30b outputs the low level output signal Sout when the input signal Sin is at the low level. When the signal Sin is at a high level, the level-shifted output signal Sout is output. When at least one of the first high potential side power supply VddL and the second high potential side power supply VddH is not supplied, the low level is output. The circuit operation stop signal is output.

  For this reason, when the first high potential side power supply VddL is not supplied and the second high potential side power supply VddH is supplied, the first high potential side power supply VddL is input to the input drive unit 1 immediately before being interrupted. Since a low level circuit operation stop signal is output from the output drive unit 3 without holding the input value of the input signal Sin, there is no need to mount a power supply voltage detection circuit. Further, since the power supply detection circuit is not mounted, an increase in the chip area of the semiconductor integrated circuit 30b can be suppressed, and low power consumption and high integration can be achieved.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, a semiconductor integrated circuit having a level shift function and a shutdown function is mounted on the SoC, but may be mounted on a system LSI, a memory LSI, or the like. Further, although the input driver unit and the output driver unit are provided with buffers, inverters may be provided instead of the buffers. In that case, it is preferable that the inverter has an n-stage configuration (where n is an even number).

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A predriver that is provided between a first high-potential-side power supply and a low-potential-side power supply and that receives an input signal and drives the input signal; the first high-potential-side power supply and the low-potential An input driver unit having a first buffer that outputs a first signal that drives a signal output from the pre-driver, the first high-potential power supply, and the first A second high potential power source having the same voltage as that of the first high potential power source or a voltage higher than that of the first high potential power source is supplied, connected to the low potential power source, and output from the first buffer. Provided between the second high-potential power supply and the low-potential power supply, and a level shift circuit that receives the first signal and outputs a second signal obtained by level-shifting the first signal. And output from the level shift circuit A second buffer that receives the second signal and outputs a signal that drives the second signal; the input signal is at a low level; the first high-potential-side power supply is supplied; and When the second high potential side power supply is supplied, a low level signal is output, the input signal is high level, the first high potential side power supply is supplied, and the second high potential side power supply is supplied An output drive circuit that outputs a high level signal to the output terminal and outputs a low level signal when at least one of the first high potential side power supply and the second high potential side power supply is not supplied. A semiconductor integrated circuit comprising:

(Supplementary Note 2) A pre-driver that is provided between a first high-potential-side power supply and a low-potential-side power supply and that receives an input signal and drives the input signal, the first high-potential-side power supply, and the low-potential And an input driver unit having a first buffer that outputs a first signal that drives a signal output from the pre-driver, and the same voltage as the first high-potential side power source or The first signal output from the first buffer is input between a second high potential power source having a voltage higher than that of the first high potential power source and the low potential power source, A level shift circuit for outputting a second signal obtained by shifting the level of the first signal; and provided between the second high potential side power source and the low potential side power source, and output from the level shift circuit. A second signal is input, A second buffer that outputs a signal obtained by driving the second signal, the input signal is at a low level, the first high-potential-side power supply is supplied, and the second high-potential-side power supply is supplied A low level signal is output, and when the input signal is high level, the first high potential side power source is supplied, and the second high potential side power source is supplied, the high level signal is output, A semiconductor integrated circuit comprising: an output drive circuit that outputs a low level signal when at least one of one high-potential-side power supply and the second high-potential-side power supply is not supplied.

1 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 1 of the present invention. FIG. 3 is a diagram illustrating a relationship among an input signal, an output signal, a first high potential side power source, and a second high potential side power source of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 6 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 2 of the present invention. FIG. 6 is a circuit diagram showing a semiconductor integrated circuit according to Embodiment 3 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input driver part 2, 2a, 2b Level shift circuit 3 Output driver part 30, 30a, 30b Semiconductor integrated circuit BUF1, BUF2 Buffer INV1, INV2 Inverter N1-6, N11-14, N21, N22 Node NMT1-6, NMT11 15, NMT21-24 Nch MOS transistors PMT1-3, PMT11-15, PMT21-23 Pch MOS transistor Sin Input signal Sout Output signal VddL, VddH High potential side power supply Vss Low potential side power supply (ground potential)

Claims (5)

An input driver unit provided between a first high-potential-side power supply and a low-potential-side power supply, which receives an input signal and outputs a first signal that drives the input signal;
A second high-potential-side power supply having the same voltage as the first high-potential-side power supply and the first high-potential-side power supply or a voltage higher than the first high-potential-side power supply is supplied; A level shift circuit that receives the first signal output from the input driver unit and outputs a second signal obtained by level shifting the first signal;
Provided between the second high-potential-side power supply and the low-potential-side power supply, input the second signal output from the level shift circuit, and outputs a signal that drives the second signal; When the input signal is at a low level, the first high potential side power supply is supplied, and the second high potential side power supply is supplied, a low level signal is output, the input signal is at a high level, and the first When the high potential side power source is supplied and the second high potential side power source is supplied, a high level signal is output, and among the first high potential side power source and the second high potential side power source, An output drive circuit that outputs a low-level signal when at least one of them is not supplied;
A semiconductor integrated circuit comprising:   The level shift circuit includes a first Nch insulated gate field effect transistor having a drain and a gate connected to the first high potential side power supply, and one end serving as a source of the first Nch insulated gate field effect transistor. A capacitor connected at the other end to the low-potential side power supply, a source connected to the source of the first Nch insulated gate field effect transistor, and a gate connected to the first high-potential side power supply. A first Pch insulated gate field effect transistor, a drain connected to the drain of the first Pch insulated gate field effect transistor, a gate connected to the first high potential side power source, and a source connected to the low power source A second Nch insulated gate field effect transistor connected to the potential side power source, and between the first high potential side power source and the low potential side power source. A first inverter that receives the first signal output from the input driver unit and outputs a signal obtained by inverting the first signal; and a gate that has the first Pch insulated gate field effect. A third Nch insulated gate field effect transistor connected to a drain of the transistor and a drain of the second Nch insulated gate field effect transistor; a source connected to the second high potential side power supply; A second Pch insulated gate field effect transistor connected to the drain of the third Nch insulated gate field effect transistor; a drain connected to the drain of the second Pch insulated gate field effect transistor; A fourth N whose input is a signal output from the first inverter and whose source is connected to the low potential side power source. An h-insulated gate type field effect transistor, a source connected to the second high potential side power supply, a gate connected to a drain of the second Pch insulated gate field effect transistor, and a drain connected to the second Pch insulation A third Pch insulated gate field effect transistor connected to the gate of the gate type field effect transistor, a drain connected to the drain of the third Pch insulated gate field effect transistor, and an output from the input driver section to the gate The fifth Nch insulated gate field effect transistor to which the first signal to be input is input and the source is connected to the low potential side power source, and between the second high potential side power source and the low potential side power source And the input side has a drain of the third Pch insulated gate field effect transistor and the fifth Nch insulated gate. 2. The semiconductor integrated circuit according to claim 1, further comprising: a second inverter connected to a drain of the type field effect transistor and inverting the signal on the input side and outputting the second signal.   The level shift circuit is provided between the first high potential side power source and the low potential side power source, receives the first signal output from the input driver unit, and inverts the first signal. A first inverter that outputs the signal, a first Nch insulated gate field effect transistor having a drain connected to the first high potential power source and a gate connected to the second high potential power source, , A first Pch insulated gate field effect transistor having a source connected to the source of the first Nch insulated gate field effect transistor and a gate receiving a signal output from the first inverter; The first Pch insulated gate field effect transistor is connected to the drain of the first Pch insulated gate field effect transistor, the gate receives a signal output from the first inverter, and the source is the low power A second Nch insulated gate field effect transistor which is connected to a side power supply and forms an inverter with the first Pch insulated gate field effect transistor, and a source connected to the second high potential side power supply A second Pch insulated gate field effect transistor; a drain connected to the drain of the second Pch insulated gate field effect transistor; a gate connected to the drain of the first Pch insulated gate field effect transistor; A third Nch insulated gate field effect transistor connected to the drain of the Nch insulated gate field effect transistor; a drain connected to the source of the third Nch insulated gate field effect transistor; Connected to the high potential side power source of the first Pch insulated gate type field effect A fourth Nch insulated gate field effect transistor connected to the drain of the transistor and the drain of the second Nch insulated gate field effect transistor; the source is the source of the third Nch insulated gate field effect transistor; A third Pch insulated gate field effect is connected to the drain of the fourth Nch insulated gate field effect transistor, the gate is connected to the first high potential power supply, and the drain is connected to the low potential power supply. A transistor and a source are connected to the second high potential side power supply, and a gate is connected to a source of the third Nch insulated gate field effect transistor and a source of the third Pch insulated gate field effect transistor. A fourth Pch insulated gate field effect transistor and a source connected to the fourth Pch insulated gate; A gate of the third Nch insulated gate field effect transistor, a drain of the first Pch insulated gate field effect transistor, and a second Nch insulated gate type. A fifth Pch insulated gate field effect transistor connected to the drain of the field effect transistor, the drain connected to the gate of the second Pch insulated gate field effect transistor, and a drain connected to the fifth Pch insulated gate type The drain of the field effect transistor is connected to the drain of the first Pch insulated gate field effect transistor, the drain of the second Nch insulated gate field effect transistor, and the third Nch insulated gate field effect transistor. And the fifth Pch insulating gate A fifth Nch insulated gate field effect transistor connected to the gate of the G-type field effect transistor and having a source connected to the low potential side power supply, and between the second high potential side power supply and the low potential side power supply The input side is connected to the drain of the fifth Pch insulated gate field effect transistor and the drain of the fifth Nch insulated gate field effect transistor, and the second signal is inverted by inverting the signal on the input side. 2. The semiconductor integrated circuit according to claim 1, further comprising: a second inverter that outputs. An input driver unit provided between a first high-potential-side power supply and a low-potential-side power supply, which receives an input signal and outputs a first signal that drives the input signal;
Provided between the second high-potential side power source and the low-potential side power source, which are the same voltage as the first high-potential side power source or higher in voltage than the first high-potential side power source, and output from the input driver unit A level shift circuit that receives the first signal and outputs a second signal obtained by level-shifting the first signal;
Provided between the second high-potential-side power supply and the low-potential-side power supply, input the second signal output from the level shift circuit, and outputs a signal that drives the second signal; When the input signal is at a low level, the first high potential side power supply is supplied, and the second high potential side power supply is supplied, a low level signal is output, the input signal is at a high level, and the first When the high potential side power source is supplied and the second high potential side power source is supplied, a high level signal is output, and among the first high potential side power source and the second high potential side power source, An output drive circuit that outputs a low-level signal when at least one of them is not supplied;
A semiconductor integrated circuit comprising:   The level shift circuit has a source connected to the first Pch insulated gate field effect transistor whose source is connected to the second high potential side power supply, and a drain connected to the drain of the first Pch insulated gate field effect transistor. A first Nch insulated gate field effect transistor whose gate is supplied with the first signal output from the input driver unit, and a drain connected to the source of the first Nch insulated gate field effect transistor. , A second Nch insulated gate field effect transistor whose gate is connected to the second high potential side power source, and a drain connected to the gate and the source of the second Nch insulated gate field effect transistor. A third Nch insulated gate field effect transistor to which the first signal output from the input driver unit is input. A transistor and a source are connected to the second high-potential side power supply, and a gate is connected to a source of the first Nch insulated gate field effect transistor and a drain of the second Nch insulated gate field effect transistor. A second Pch insulated gate field effect transistor, a source connected to the drain of the second Pch insulated gate field effect transistor, and a gate connected to the gate of the first Nch insulated gate field effect transistor; A third Pch insulated gate field effect transistor in which the first signal output from the input driver unit is input to a gate and a drain is connected to the gate of the first Pch insulated gate field effect transistor; A drain connected to a drain of the third Pch insulated gate field effect transistor; Is connected to the gate of the first Nch insulated gate field effect transistor and the gate of the third Pch insulated gate field effect transistor, and the first signal output from the input driver section is connected to the gate. A fourth Nch insulated gate field effect transistor that is input and whose source is connected to the low-potential-side power source, and is provided between the second high-potential-side power source and the low-potential-side power source; A second inverter connected to the drain of the third Pch insulated gate field effect transistor and the drain of the fourth Nch insulated gate field effect transistor, inverting the signal on the input side and outputting the second signal; The semiconductor integrated circuit according to claim 4, further comprising:

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