JP2008228192A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a leak current, during a standby mode, of a flip-flop circuit, a latch circuit, etc. <P>SOLUTION: A flip-flop circuit 20 comprises a master latch circuit 1, a slave latch circuit 3, a clamp section 3, and a clock buffer circuit 4. The clamp section 3 is provided between a node N3 and a low potential side power source (ground potential) Vss and is constituted of an Nch MOS transistor NMT1 and a gate-grounded Nch MOS transistor NMT2. While the flip-flop circuit 20 is on standby, a standby signal STB of "Low" level is input to the gate of the Nch MOS transistor NMT1 in the clamp section 3, the Nch MOS transistor NMT1 is turned "OFF", the voltage of the node N3 is pulled up by a forward voltage (Vf) of the gate-grounded Nch MOS transistor NMT2, and the voltage of "Vdd-Vf" is applied to the master latch circuit 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a flip-flop circuit and a latch circuit used in a semiconductor integrated circuit.

In semiconductor integrated circuits, high speed and high integration progressed, and LSI as a semiconductor integrated circuit
The number of latch circuits and flip-flop circuits used in the field is increasing. As the flip-flop circuit, a master-slave type circuit in which latch circuits configured using an inverter and a transfer gate are connected in series is usually used (see, for example, Patent Document 1).

In recent years, miniaturization and low voltage operation of MOS transistors used in LSIs have progressed.
The threshold voltage (Vth) of the OS transistor is steadily decreasing. Due to the lower Vth of the MOS transistor, the subthreshold leakage current of the transistor increases, and there is a problem that the leakage current during standby of the flip-flop circuit, the latch circuit, etc. increases.
Japanese Patent Laying-Open No. 2004-187037 (page 9, FIG. 10)

  The present invention provides a semiconductor integrated circuit capable of reducing leakage current during standby.

The semiconductor integrated circuit of one embodiment of the present invention is provided on the high potential side power source side, and is provided between the master latch circuit to which an input signal is input, the high potential side power source and the low potential side power source, and the master latch A slave latch circuit that receives a signal output from the circuit and outputs an output signal, and is provided between the master latch circuit and the low-potential-side power supply, and the master latch circuit on the low-potential-side power supply side during standby And a clamp part having a pull-up voltage generating means for pulling up the voltage of the above-mentioned voltage from the low-potential-side power supply voltage.

Furthermore, a semiconductor integrated circuit according to another aspect of the present invention is provided on a low potential side power supply side, provided between a master latch circuit to which an input signal is input, a high potential side power supply, and the low potential side power supply, A slave latch circuit that receives an output signal from the master latch circuit and outputs an output signal, and is provided between the high-potential side power source and the master latch circuit, and in standby, the master on the high-potential side power source side And a clamp unit having pull-down voltage generating means for pulling down the voltage of the latch circuit from the high-potential side power supply voltage.

According to the present invention, it is possible to provide a semiconductor integrated circuit capable of reducing a leakage current during standby.

  Embodiments of the present invention will be described below with reference to the drawings.

First, a semiconductor integrated circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a flip-flop circuit as a semiconductor integrated circuit, and FIG. 2 is a circuit diagram showing a clocked inverter. In this embodiment, a clamp unit for reducing leakage current during standby is provided on the low potential side power supply side of the master latch circuit of the flip-flop circuit.

As shown in FIG. 1, the flip-flop circuit 20 includes a master latch circuit 1, a slave latch circuit 2, a clamp unit 3, and a clock buffer circuit 4. The flip-flop circuit 20 is a D-type flip-flop.

The clock buffer circuit 4 is provided with an inverter INV3 and an inverter INV4. The inverter INV3 is provided between the high-potential-side power supply Vdd and the low-potential-side power supply (ground potential) Vss, receives the clock signal CLK, and outputs an inverted clock signal CLKb obtained by inverting the clock signal CLK from the node N6. The inverter INV4 is provided between the high-potential-side power supply Vdd and the low-potential-side power supply (ground potential) Vss, receives the inverted clock signal CLKb, and has the clock signal CL in phase with the inverted clock signal CLKb.
Output K1. The clock signal CLK1 and the inverted clock signal CLKb are input to the clocked inverters CI1 and CI2 of the master latch circuit 1 and the clocked inverters CI3 and CI4 of the slave latch circuit 2.

As shown in FIG. 2A and FIG. 2B, the clocked inverters CI1 to CI4 are
Pch MOS transistor PMT11, Pch MOS transistor PMT12, Nc
h It is composed of a MOS transistor NMT11 and an Nch MOS transistor NMT12. The MOS transistor is a MOSFET (Metal Oxide Semiconductor F
ield Effect Transistor).

The clock signal CLK1 is input to the gates of the Pch MOS transistors PMT12 of the clocked inverters CI1 and CI4, and Nc of the clocked inverters CI1 and CI4 is input.
h The inverted clock signal CLKb is input to the gate of the MOS transistor NMT11.
The inverted clock signal CLKb is input to the gates of the Pch MOS transistors PMT12 of the clocked inverters CI2 and CI3, and N of the clocked inverters CI2 and CI3 is input.
The clock signal CLK1 is input to the gate of the ch MOS transistor NMT11.

The source of the Pch MOS transistor PMT11 is connected to the high potential side power supply Vdd side, the drain is connected to the source of the Pch MOS transistor PMT12, and the gate is connected to the input side. The Pch MOS transistor PMT12 has an Nch MOS drain
Connected to the drain of the transistor NMT11. Nch MOS transistor NMT1
1, the source is connected to the drain of the Nch MOS transistor NMT12. Nch
The MOS transistor NMT12 has a source connected to the low potential power supply Vss side and a gate connected to the input side. The drain of the Pch MOS transistor PMT12 and the Nch M
The drain of the OS transistor NMT11 is connected to the output side, and an output signal is output.

Here, the Pch MOS transistor PMT11, the Pch MOS transistor PMT12, and the Nch MOS transistor N constituting the clocked inverters CI1 to CI4.
The MT11 and the Nch MOS transistor NMT12 may not necessarily be designed to have the same dimensions such as the gate length Lg and the gate width Wg. In some cases, the absolute value | Vth | of the threshold voltage is not set to be the same.

The master latch circuit 1 includes a clocked inverter CI1, a clocked inverter CI
2 and an inverter INV1 are provided. The master latch circuit 1 receives the clock signal CL
When K changes from the “Low” level to the “High” level (at the rising edge of the signal), the signal level of the input signal Sin (data of the input signal) is latched by the inverter INV1 and the clocked inverter CI2.

The clocked inverter CI1 is provided between the high-potential-side power supply Vdd and the node N3, and receives the input signal Sin, the clock signal CLK1, and the inverted clock signal CLKb, and outputs an output signal from the node N1.

The inverter INV1 is provided between the high-potential-side power supply Vdd and the node N3, receives a signal output from the clocked inverter CI1, and outputs an inverted signal obtained by inverting the signal from the node N2 to the clocked inverters CI2 and CI3. To do.

The clocked inverter CI2 is provided between the high-potential-side power supply Vdd and the node N3, receives the inverted signal output from the inverter INV1, the clock signal CLK1, and the inverted clock signal CLKb, and outputs the output signal from the node N1. . Clocked inverter CI
The signal output from 2 is input to the inverter INV1 as a feedback signal.

The slave latch circuit 1 includes a clocked inverter CI3 and a clocked inverter CI.
4 and an inverter INV2. The slave latch circuit 1 receives the clock signal CL
When K changes from “High” level to “Low” level (at the falling edge of the signal), the signal level (input signal data) input to the slave latch circuit 2 is latched by the inverter INV2 and the clocked inverter CI4. To do.

The clocked inverter CI3 includes a high potential side power source Vdd and a low potential side power source (ground potential) Vs.
s, the signal of the node N2, the clock signal CLK1, and the inverted clock signal C
LKb is input and an output signal is output from the node N4.

The inverter INV2 is provided between the high-potential-side power supply Vdd and the low-potential-side power supply Vss. A signal output from the clocked inverter CI3 is input, and an inverted signal obtained by inverting the signal is supplied from the node N5 to the clocked inverter CI4. Output. Note that the signal output from the inverter INV2 is the output signal Sout of the flip-flop circuit 20.

The clocked inverter CI4 includes a high potential side power source Vdd and a low potential side power source (ground potential) Vs.
s and an inverted signal output from the inverter INV2 and the clock signal CLK1
And the inverted clock signal CLKb are input, and an output signal is output from the node N4. The signal output from the clocked inverter CI4 is input to the inverter INV2 as a feedback signal.

The clamp unit 3 is provided between the node N3 and the low potential side power supply (ground potential) Vss, and Nc
h It is composed of a MOS transistor NMT1 and an Nch MOS transistor NMT2.

The Nch MOS transistor NMT1 has a drain connected to the node N3, a source connected to the low potential power source Vss, and a standby signal STB input to the gate. When standby signal STB is at “High” level (when flip-flop circuit 20 is in operation) Nch
When the MOS transistor NMT1 is “ON” and the standby signal STB is at the “Low” level (when the flip-flop circuit 20 is on standby), the Nch MOS transistor NMT1 is “
“OFF”.

Here, the Nch MOS transistor NMT1 is an enhanced mode (also referred to as E-type) transistor. When the standby signal STB is at the “Low” level, the NM
The voltage between the source and drain of T1 is the forward voltage of the Nch MOS transistor NMT2 (V
f), the leakage current can be suppressed to a very low level.

The Nch MOS transistor NMT2 is a gate-grounded MOS diode whose gate and drain are connected to the node N3 and whose source is connected to the low potential power source Vss.

Next, the operation of the flip-flop circuit will be described with reference to FIG. FIG. 3 is a diagram for explaining the operation of the flip-flop circuit.

As shown in FIG. 3, during the operation of the flip-flop circuit 20, the “High” level standby signal STB is input to the gate of the Nch MOS transistor NMT1 of the clamp unit 3, and the Nch MOS transistor NMT1 is turned “ON”. The voltage at node N3 is Nch
Since the on-resistance of the MOS transistor NMT1 is small, a substantially low potential side power supply (ground potential) Vs
s voltage. Therefore, the master latch circuit 1 is normally operated by applying the high potential side power supply Vdd voltage.

On the other hand, when the flip-flop circuit 20 is on standby, the “Low” level standby signal ST
B is input to the gate of the Nch MOS transistor NMT1 of the clamp unit 3, and Nch
The MOS transistor NMT1 is turned “OFF”. Therefore, the voltage at the node N3 is equal to the forward voltage (VV) of the Nch MOS transistor NMT2, which is a gate-grounded MOS diode.
f) Pull-up is performed, and “Vdd−Vf” is applied to the master latch circuit 1. Therefore, the leakage current during standby can be reduced as compared with a conventional flip-flop circuit that does not have a clamp portion. The Nch MOS transistor NMT2 functions as a pull-up voltage generating unit.

Here, the back gate of the Nch MOS transistor NMT2 is connected to the low potential side power supply Vss.
However, the back gate of the Nch MOS transistor NMT2 may not be connected to the low potential side power source Vss. In this case, the voltage of the node N3 is not Vf but Nch MO
Pull up the threshold voltage of the S transistor NMT2. Note that the high potential side power supply Vdd voltage is applied to the slave latch circuit 2 regardless of whether it is in operation or standby.

As described above, in the semiconductor integrated circuit of this embodiment, the master latch circuit 1, the slave latch circuit 2, the clamp unit 3, and the clock buffer circuit 4 are provided. The clock buffer circuit 4 is provided with an inverter INV3 and an inverter INV4, and the clock signal CL
K is input, and the inverted clock signal CLKb and the clock signal CLK1 having the same phase as the clock signal CLK are output to the master latch circuit 1 and the slave latch circuit 2. Clamp part 3
Is provided between the node N3 and the low-potential-side power supply (ground potential) Vss, and includes an Nch MOS transistor NMT1 and a grounded Nch MOS transistor NMT2. During the operation of the flip-flop circuit 20, the “High” level standby signal STB is input to the gate of the Nch MOS transistor NMT 1 of the clamp unit 3, and the Nch MOS
The transistor NMT1 is turned “ON”. On the other hand, when the flip-flop circuit 20 is on standby, “L”
The standby signal STB at the “ow” level is the Nch MOS transistor N of the clamp unit 3
The signal is input to the gate of MT1, and the Nch MOS transistor NMT1 is turned “OFF”.

For this reason, the voltage of the node N3 on the low potential side power supply Vss side of the master latch circuit 1 is higher than the low potential side power supply Vss voltage during standby in the forward voltage of the diode (gate grounded Nch M
Pull up by Vf) of the OS transistor NMT2. Therefore, the leakage current during standby can be reduced as compared with the prior art. In addition, since the power supply is not shut down during standby, there is no need for a complicated sequence of temporarily saving the data prior to the power shutdown and re-reading the saved data when returning from the power shutdown, increasing system cost and processing time. Can be suppressed.

In this embodiment, one gate-grounded Nch MOS transistor NMT2 as a diode is provided in the clamp unit 3, but n (where n is an integer of 2 or more) cascade-connected gate-grounded Nch MOS transistors are connected. It may be provided. Gate grounding Nch
A diode may be used instead of the MOS transistor NMT2. Furthermore, although a Pch MOS transistor and an Nch MOS transistor using a silicon oxide film as a gate insulating film are used, a SiNxOy film obtained by nitriding a silicon oxide film, a silicon nitride film (Si ₃ N
₄ ) A Pch MIS transistor and an Nch MIS transistor using a stacked film of a silicon oxide film or a high dielectric film (High-K gate insulating film) may be used.

Next, a semiconductor integrated circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram showing a flip-flop circuit as a semiconductor integrated circuit. In this embodiment, the arrangement of the clamp portions is changed.

In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

As shown in FIG. 4, the flip-flop circuit 20a includes a master latch circuit 1a, a slave latch circuit 2, a clock buffer circuit 4, and a clamp unit 5. The flip-flop circuit 20a is a D-type flip-flop.

The master latch circuit 1a includes a clocked inverter CI1 and a clocked inverter C.
I2 and an inverter INV1 are provided. When the clock signal CLK changes from the “Low” level to the “High” level (at the rising edge of the signal), the master latch circuit 1a performs the signal level of the input signal Sin (data of the input signal) by the inverter INV1 and the clocked inverter CI2. Latch).

The clocked inverter CI1 is provided between the node N7 and the low-potential side power supply (ground potential) Vss, receives the input signal Sin, the clock signal CLK1, and the inverted clock signal CLKb, and outputs an output signal from the node N1.

The inverter INV1 is provided between the node N7 and the low-potential-side power supply (ground potential) Vss. A signal output from the clocked inverter CI1 is input, and an inverted signal obtained by inverting the signal is output from the node N2 to the clock inverter CI2. And output to CI3.

The clocked inverter CI2 is provided between the node N7 and the low-potential-side power supply (ground potential) Vss. The inverted signal output from the inverter INV1, the clock signal CLK1, and the inverted clock signal CLKb are input, and the output signal is output to the node. Output from N1. The signal output from the clocked inverter CI2 is input to the inverter INV1 as a feedback signal.

The clamp unit 5 is provided between the high-potential-side power supply Vdd and the node N7, and includes a Pch MOS transistor PMT1 and a Pch MOS transistor PMT2.

In the Pch MOS transistor NMT1, the source is connected to the high potential side power supply Vdd, the drain is connected to the node N7, and the standby signal STB1 is input to the gate. When standby signal STB1 is at "Low" level (during operation of flip-flop circuit 20a) P
The channel MOS transistor PMT1 is “ON” and the standby signal STB1 is “High”.
"Level (when the flip-flop circuit 20a is on standby) Pch MOS transistor P"
MT1 is “OFF”.

Here, the Pch MOS transistor PMT1 is an enhanced mode (also referred to as E-type) transistor, and no leakage current is generated between the source and drain when the standby signal STB1 is at "High" level.

The Pch MOS transistor PMT2 is a grounded MOS diode whose source is connected to the high potential side power supply Vdd, and whose gate and drain are connected to the node N7.

Next, the operation of the flip-flop circuit will be described with reference to FIG. FIG. 5 is a diagram for explaining the operation of the flip-flop circuit.

As shown in FIG. 5, during the operation of the flip-flop circuit 20a, the “Low” level standby signal STB1 is input to the gate of the Pch MOS transistor PMT1 of the clamp unit 5, and the Pch MOS transistor PMT1 is turned “ON”. The voltage at node N7 is Pc
h Since the on-resistance of the MOS transistor PMT1 is small, the voltage becomes substantially the high potential side power supply Vdd voltage. Therefore, the master latch circuit 1a is normally operated by applying the high potential side power supply Vdd voltage.

On the other hand, when the flip-flop circuit 20a is on standby, a “High” level standby signal STB1 is input to the gate of the Pch MOS transistor PMT1 of the clamp unit 5, and P
The channel MOS transistor PMT1 is turned “OFF”. Therefore, the voltage at the node N7 is
The voltage is pulled down by the forward voltage (Vf) of the Pch MOS transistor PMT2 which is a MOS diode with a common gate, and “Vdd−Vf” is applied to the master latch circuit 1a. Therefore, the leakage current during standby can be reduced as compared with a conventional flip-flop circuit that does not have a clamp portion. The Pch MOS transistor PMT2 functions as a pull-down voltage generating unit.

Here, the back gate of the Pch MOS transistor PMT2 is connected to the high potential side power supply Vdd.
However, the back gate of the Pch MOS transistor PMT2 may not be connected to the high potential side power source Vdd. In this case, the voltage at the node N7 is not Vf but Pch MO
Pull down the threshold voltage of the absolute value of the S transistor PMT2.

As described above, in the semiconductor integrated circuit of this embodiment, the master latch circuit 1a, the slave latch circuit 2, the clamp unit 5, and the clock buffer circuit 4 are provided. The clock buffer circuit 4 is provided with an inverter INV3 and an inverter INV4, and a clock signal C
LK is input, and the inverted clock signal CLKb and the clock signal CLK1 having the same phase as the clock signal CLK are output to the master latch circuit 1a and the slave latch circuit 2. The clamp unit 5 is provided between the high-potential-side power supply Vdd and the node N7, and includes a Pch MOS transistor PMT1 and a grounded Pch MOS transistor PMT2. During the operation of the flip-flop circuit 20a, the “Low” level standby signal STB1 is input to the gate of the Pch MOS transistor PMT1 of the clamp unit 5, and the Pch MOS transistor NMT1 is turned “ON”. On the other hand, when the flip-flop circuit 20a is on standby,
The h ”level standby signal STB1 is applied to the Pch MOS transistor P of the clamp unit 5.
The signal is input to the gate of MT1, and the Pch MOS transistor PMT1 is turned “OFF”.

For this reason, the voltage of the node N7 on the high potential side power supply Vdd side of the master latch circuit 1a is higher than the high potential side power supply Vdd voltage during standby.
Pull down by Vf) of the MOS transistor PMT2. Therefore, the leakage current during standby can be reduced as compared with the prior art. In addition, since the power supply is not shut down during standby, there is no need for a complicated sequence of temporarily saving the data prior to the power shutdown and re-reading the saved data when returning from the power shutdown, increasing system cost and processing time. Can be suppressed.

In this embodiment, the clamp unit 5 is provided with one gate-grounded Pch MOS transistor PMT2 as a diode. However, n (where n is an integer of 2 or more) cascade-connected gate-grounded Pch MOS transistors are provided. It may be provided.

Next, a semiconductor integrated circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing a flip-flop circuit as a semiconductor integrated circuit. In this embodiment, two clamp portions are provided.

In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

As shown in FIG. 6, the flip-flop circuit 20b includes a master latch circuit 1b, a slave latch circuit 2, a clamp unit 3, a clock buffer circuit 4, and a clamp unit 5. The flip-flop circuit 20b is a D-type flip-flop.

The master latch circuit 1b includes a clocked inverter CI1, a clocked inverter C
I2 and an inverter INV1 are provided. When the clock signal CLK changes from “Low” level to “High” level (at the rising edge of the signal), the master latch circuit 1b receives the signal level of the input signal Sin (data of the input signal) by the inverter INV1 and the clocked inverter CI2. Latch).

The clocked inverter CI1 is provided between the node N7 and the node N3, and the input signal S
in, the clock signal CLK1, and the inverted clock signal CLKb are input, and an output signal is output from the node N1.

The inverter INV1 is provided between the node N7 and the node N3, receives a signal output from the clocked inverter CI1, and outputs an inverted signal obtained by inverting the signal from the node N2 to the clocked inverters CI2 and CI3.

The clocked inverter CI2 is provided between the node N7 and the node N3. The inverted signal output from the inverter INV1, the clock signal CLK1, and the inverted clock signal CLK
b is input and an output signal is output from the node N1. The signal output from the clocked inverter CI2 is input to the inverter INV1 as a feedback signal.

The Nch MOS transistor NMT1 has a drain connected to the node N3, a source connected to the low potential power supply (ground potential) Vss, and a standby signal STB input to the gate. When the standby signal STB is at “High” level (when the flip-flop circuit 20b is operating), the Nch MOS transistor NMT1 is “ON” and the standby signal STB is “
At the “Low” level (when the flip-flop circuit 20b is on standby), the Nch MOS transistor NMT1 is turned “OFF”.

In the Pch MOS transistor NMT1, the source is connected to the high potential side power supply Vdd, the drain is connected to the node N7, and the standby signal STB1 that is an inverted signal of the standby signal STB is input to the gate. When the standby signal STB1 is at "Low" level (when the flip-flop circuit 20b is operating), the Pch MOS transistor PMT1 is "ON", and when the standby signal STB1 is at "High" level (when the flip-flop circuit 20b is waiting), Pch MOS The transistor PMT1 is turned “OFF”.

Next, the operation of the flip-flop circuit will be described with reference to FIG. FIG. 7 is a diagram for explaining the operation of the flip-flop circuit.

As shown in FIG. 7, during the operation of the flip-flop circuit 20b, the “High” level standby signal STB is input to the gate of the Nch MOS transistor NMT1 of the clamp unit 3, the Nch MOS transistor NMT1 is turned “ON”, and “Low” "Level standby signal STB1 is input to the Pch MOS transistor PMT1 of the clamp unit 5, and Pc
h The MOS transistor PMT1 is turned “ON”.

The voltage of the node N3 is substantially the low potential side power supply (ground potential) Vss voltage because the on-resistance of the Nch MOS transistor NMT1 is small. On the other hand, the voltage at the node N7 is substantially the high potential side power supply Vdd. Therefore, the master latch circuit 1b is normally operated by being applied with the substantially high potential side power supply Vdd voltage.

On the other hand, when the flip-flop circuit 20b is on standby, the “Low” level standby signal S
TB is input to the gate of the Nch MOS transistor NMT1 of the clamp unit 3, and Nch
The MOS transistor NMT1 is “OFF” and the “High” level standby current S
TB1 is input to the gate of the Pch MOS transistor PMT1 of the clamp unit 5. Therefore, the voltage at the node N3 is pulled up by the forward voltage (Vf) of the Nch MOS transistor NMT2, which is a gate-grounded MOS diode, and the voltage at the node N7 is a Pch MOS transistor, which is a gate-grounded MOS diode. PMT2 forward voltage (V
f) Pull down by minutes. “Vdd−2Vf” is applied to the master latch circuit 1b.
Therefore, the leakage current during standby can be reduced as compared with a conventional flip-flop circuit that does not have a clamp portion. The Nch MOS transistor NMT2 functions as a pull-up voltage generating unit, and the Pch MOS transistor PMT2 functions as a pull-down voltage generating unit.

As described above, in the semiconductor integrated circuit of this embodiment, the master latch circuit 1b, the slave latch circuit 2, the clamp unit 3, the clock buffer circuit 4, and the clamp unit 5 are provided. The clock buffer circuit 4 is provided with an inverter INV3 and an inverter INV4.
The clock signal CLK is input, and the inverted clock signal CLKb and the clock signal CLK1 having the same phase as the clock signal CLK are output to the master latch circuit 1b and the slave latch circuit 2. The clamp unit 3 is provided between the node N3 and the low potential side power supply (ground potential) Vss.
Nch MOS transistor NMT1 and grounded Nch MOS transistor NM
It is composed of T2. The clamp unit 5 is provided between the high-potential-side power supply Vdd and the node N7, and includes a Pch MOS transistor PMT1 and a grounded Pch MOS transistor P.
It is composed of MT2. During the operation of the flip-flop circuit 20b, the “High” level standby signal STB is input to the gate of the Nch MOS transistor NMT1 of the clamp unit 3, the Nch MOS transistor NMT1 is “ON”, and the “Low” level standby signal STB1 is The signal is input to the gate of the Pch MOS transistor PMT1 of the clamp unit 5, and the Pch MOS transistor PMT1 is turned “ON”. On the other hand, when the flip-flop circuit 20b is in a standby state, the “Low” level standby signal STB is applied to the Nch of the clamp unit 3.
The N-channel MOS transistor NMT is input to the gate of the MOS transistor NMT1.
1 is “OFF”, and the “High” level standby signal STB1 is
input to the gate of the ch MOS transistor PMT1, and the Pch MOS transistor P
MT1 is “OFF”.

For this reason, the voltage applied to the master latch circuit 1b is "Vdd-2Vf" during standby.
Therefore, the leakage current during standby can be reduced as compared with the first embodiment. Also, since the power supply is not shut down during standby, the data prior to power shutdown is temporarily saved, and when returning from power shutdown. A complicated sequence of re-reading the saved data is unnecessary, and an increase in system cost and processing time can be suppressed.

Next, a semiconductor integrated circuit according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram showing a flip-flop circuit as a semiconductor integrated circuit. In this embodiment, the configuration of the clamp portion is changed.

In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

As shown in FIG. 8, the flip-flop circuit 20c is provided with a master latch circuit 1c, a slave latch circuit 2, a clamp unit 3c, and a clock buffer circuit 4. The flip-flop circuit 20c is a D-type flip-flop.

The master latch circuit 1c has a low potential side power supply (ground potential) Vss side (node N3) connected to the clamp portion 3c, and the circuit configuration is the same as that of the first embodiment.

The clamp part 3c is provided between the node N3 and the low-potential side power source Vss, and the Nch MOS
A transistor NMT1 and a resistor R1 are included. The resistor R1 and the Nch MOS transistor NMT1 are connected in parallel between the node N3 and the low potential side power supply (ground potential) Vss.

During the operation of the flip-flop circuit 20c, a “High” level standby signal STB is input to the gate of the Nch MOS transistor NMT1 of the clamp unit 3, and the Nch MO
The S transistor NMT1 is turned “ON”. The voltage of the node N3 is substantially the low potential side power supply (ground potential) Vss voltage because the on-resistance of the Nch MOS transistor NMT1 is small. For this reason, the master latch circuit 1c is normally operated by applying the substantially high potential side power supply Vdd voltage.

On the other hand, when the flip-flop circuit 20c is on standby, the standby signal S at the “Low” level
TB is input to the gate of the Nch MOS transistor NMT1 of the clamp unit 3, and Nch
The MOS transistor NMT1 is turned “OFF”. Therefore, the voltage at the node N3 is pulled up by the value of the current (I _R1 ) flowing through the resistor R1 × the resistance value (R ₁ ) of the resistor R1, and “Vdd− (I _R1 × R ₁ ) is applied to the master latch circuit 1c. ) ”Is applied. Therefore, the leakage current during standby can be reduced as compared with a conventional flip-flop circuit that does not have a clamp portion. The resistor R1 functions as a pull-up voltage generating unit.

As described above, in the semiconductor integrated circuit of this embodiment, the master latch circuit 1c, the slave latch circuit 2, the clamp unit 3c, and the clock buffer circuit 4 are provided. The clock buffer circuit 4 includes an inverter INV3 and an inverter INV4. The clock signal CLK is input to the clock buffer circuit 4. The inverted clock signal CLKb and the clock signal CLK1 having the same phase as the clock signal CLK are output to the master latch circuit 1c and the slave latch circuit 2. To do. The clamp portion 3c is provided between the node N3 and the low potential side power supply (ground potential) Vss, and Nch M
It comprises an OS transistor NMT1 and a resistor R1. During the operation of the flip-flop circuit 20c, the “High” level standby signal STB is applied to the Nch MOS of the clamp unit 3c.
The N-channel MOS transistor NMT1 is input to the gate of the transistor NMT1,
On the other hand, when the flip-flop circuit 20c is in a standby state, a “Low” level standby signal STB is input to the gate of the Nch MOS transistor NMT1 of the clamp unit 3c, and the Nch MOS transistor NMT1 is turned “OFF”.

For this reason, the voltage of the node N3 on the low potential side power supply Vss side of the master latch circuit 1c is pulled up by the value of the current flowing through the resistor R1 (I _R1 ) × the resistance value of the resistor R1 (R ₁ ) during standby, “Vdd− (I _R1 × R ₁ )” is applied to the master latch circuit 1c. Therefore, the leakage current during standby can be reduced as compared with the prior art. In addition, since the power supply is not shut down during standby, there is no need for a complicated sequence of temporarily saving the data prior to the power shutdown and re-reading the saved data when returning from the power shutdown, increasing system cost and processing time. Can be suppressed.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

For example, in the embodiment, the clamp unit is provided in the master latch circuit of the flip-flop circuit, but the clamp unit may be provided in a scanned SFF (Scan Flip Flop) circuit. In this case, a clock signal, a function input signal, a scan shift signal, and a scan input signal are input to the master latch circuit, and a clock signal is input to the slave circuit. In addition, the first scan clock signal is input to the master latch circuit, and the second scan clock signal is input to the slave latch circuit.
The present invention can also be applied to a latch-circuit-based semiconductor integrated circuit designed and scanned by an e-Scan design. In this case, a function input signal, a system clock signal, and a scan input signal are further input to the master latch circuit.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A master latch circuit that is provided on the high-potential side power supply side and that receives an input signal;
A slave latch circuit that is provided between the high-potential-side power supply and the low-potential-side power supply and that receives a signal output from the master latch circuit and outputs an output signal; and during standby, the low-potential-side power supply side Pull-up voltage generating means for pulling up the voltage of the master latch circuit from the low-potential side power supply voltage, and a MOS transistor that operates in response to a standby signal input to the gate during operation include the master latch circuit and the low-potential side A semiconductor integrated circuit comprising a clamp portion connected in parallel between power supplies.

(Supplementary Note 2) A master latch circuit that is provided on the low-high-potential-side power supply side and that receives an input signal, and a signal that is provided between the high-potential-side power supply and the low-potential-side power supply and is output from the master latch circuit A slave latch circuit that outputs an output signal, a pull-down voltage generating means that pulls down the voltage of the master latch circuit on the high-potential-side power supply side from the high-potential-side power supply voltage during standby, and during operation, A semiconductor integrated circuit comprising: a clamp unit connected in parallel between the high-potential-side power supply and the master latch circuit; and a MOS transistor that operates in accordance with a standby signal input to a gate.

(Supplementary Note 3) A master latch circuit to which an input signal is input and a slave latch that is provided between a high potential side power source and a low potential side power source, and that receives a signal output from the master latch circuit and outputs an output signal A circuit, a pull-down voltage generating means for pulling down the voltage of the master latch circuit on the high-potential side power supply side from the high-potential side power supply voltage during standby, and a MOS that operates by a standby signal input to the gate during operation A first clamp unit in which a transistor is connected in parallel between the master latch circuit and the low-potential-side power supply; and a voltage of the master latch circuit on the low-potential-side power supply side during standby is the low-potential-side power supply voltage Pull-up voltage generating means that pulls up more than the MOS transistor that operates by a standby signal input to the gate during operation A semiconductor integrated circuit comprising a second clamp unit connected in parallel between the high-potential-side power source and the master latch circuit.

(Supplementary Note 4) The pull-up voltage generating means includes one or n diodes (where n is an integer of 2 or more) cascaded between the master latch circuit and the low potential side power supply, and a gate-grounded MOS transistor Or the semiconductor integrated circuit according to appendix 1 or 3, which is a resistor.

(Supplementary Note 5) The pull-down voltage generating means includes one or n diodes (where n is an integer of 2 or more) cascaded between the high-potential-side power supply and the master latch circuit, a gate-grounded MOS transistor, Alternatively, the semiconductor integrated circuit according to appendix 2 or 3, which is a resistor.

(Supplementary Note 6) A clock signal, a function input signal, a scan shift signal, and a scan input signal are input to the master latch circuit, and the clock signal is input to the slave circuit and scanned. The semiconductor integrated circuit according to any one of the above.

(Supplementary Note 7) A first scan clock signal, a function input signal, a system clock signal, and a scan input signal are also input to the master latch circuit, and a second scan clock signal is input to the slave latch circuit. -Sensitive-S
6. The semiconductor integrated circuit according to any one of appendices 1 to 5, which is a can design designed and scanned latch circuit base.

1 is a circuit diagram showing a flip-flop circuit according to Embodiment 1 of the present invention. The figure which shows the clocked inverter which concerns on Example 1 of this invention FIG. 3 is a diagram for explaining the operation of the flip-flop circuit according to the first embodiment of the invention. FIG. 6 is a diagram illustrating a flip-flop circuit according to a second embodiment of the invention. The figure explaining operation | movement of the flip-flop circuit which concerns on Example 2 of this invention. FIG. 6 is a diagram illustrating a flip-flop circuit according to a third embodiment of the invention. The figure which shows the operation | movement of the flip-flop circuit which concerns on Example 3 of this invention. FIG. 6 is a circuit diagram showing a flip-flop circuit according to Embodiment 4 of the present invention.

Explanation of symbols

1, 1a, 1b, 1c Master latch circuit 2 Slave latch circuit 3, 3c, 5 Clamp unit 4 Clock buffer circuit 20, 20a, 20b, 20c Flip-flop circuit INV1-4 Inverter CI1-4 Clocked inverter CLK, CLK1 Clock signal CLKb Inverted clock signal N1-7 Nodes NMT1, NMT2, NMT11, NMT12 Nch MOS transistors PMT1, PMT2, PMT11, PMT12 Pch MOS transistor R1 Resistor Sin Input signal Sout Output signal STB, STB1 Standby signal Vdd High potential side power supply Vss Low potential side Power supply (ground potential)

Claims (5)

A master latch circuit provided on the high-potential-side power supply side, to which an input signal is input;
A slave latch circuit that is provided between the high-potential-side power supply and the low-potential-side power supply, receives a signal output from the master latch circuit, and outputs an output signal;
Pull-up voltage generating means provided between the master latch circuit and the low-potential side power supply, and for pulling up the voltage of the master latch circuit on the low-potential side power supply side from the low-potential side power supply voltage during standby A clamp part having,
A semiconductor integrated circuit comprising: A master latch circuit provided on the low-potential-side power supply side to which an input signal is input;
A slave latch circuit that is provided between a high-potential-side power supply and the low-potential-side power supply, receives a signal output from the master latch circuit, and outputs an output signal;
Clamp provided between the high potential side power supply and the master latch circuit, and having a pull-down voltage generating means for pulling down the voltage of the master latch circuit on the high potential side power supply side from the high potential side power supply voltage during standby And
A semiconductor integrated circuit comprising: A master latch circuit to which an input signal is input;
A slave latch circuit that is provided between a high potential side power source and a low potential side power source, receives a signal output from the master latch circuit, and outputs an output signal;
A pull-down voltage generator provided between the high-potential side power supply and the master latch circuit and pulling down the voltage of the master latch circuit on the high-potential side power supply side from the high-potential side power supply voltage during standby; 1 clamp part;
Pull-up voltage generating means provided between the master latch circuit and the low-potential side power supply and pulling up the voltage of the master latch circuit on the low-potential side power supply side from the low-potential side power supply voltage during standby A second clamping portion having
A semiconductor integrated circuit comprising: The pull-up voltage generating means includes 1 between the master latch circuit and the low potential side power source.
N or n (where n is an integer of 2 or more) cascaded diodes, gate-grounded MOS
4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a transistor or a resistor. The pull-down voltage generating means has 1 between the high potential side power supply and the master latch circuit.
N or n (where n is an integer of 2 or more) cascaded diodes, gate-grounded MOS
4. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is a transistor or a resistor.

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