JP2009071459A - Semiconductor integrated circuit and air-conditioner - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly and safely limit an output during trouble by troubleshooting a D/A converter more quickly and more safely. <P>SOLUTION: When troubleshooting a D/A converter 2, digital data to be D/A converted is stored in a D/A conversion data storing buffer 11. D/A-converted analogue data is converted by an A/D converter 4, and A/D-converted digital data is stored in an A/D conversion data storing buffer 5. Whether a difference of digital data is within a tolerable error or not is always judged by a comparator 8, for controlling an output of the D/A converter 2. Thus, troubleshooting the D/A converter 2 is performed more quickly and safely, to quickly and safely limit an output during trouble. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having functions of a D / A converter and an A / D converter and having a function of diagnosing a D / A converter, and an air conditioner on which the semiconductor integrated circuit is mounted.

  In recent years, devices using motor drive control in an air conditioner system or the like are increasing. For motor drive control, the number of revolutions is controlled using a PWM, D / A converter, etc. of a microcomputer, thereby realizing more flexible software control.

  In such a control, if the microcomputer PWM or D / A converter has failed, the microcomputer cannot know the failure of the microcomputer PWM or D / A converter itself. When such a situation is reached, the microcomputer has to continue wrong control of the PWM and D / A converter. In some cases, it can cause serious problems with overcurrent.

For this reason, the conventional drive control device detects a failure of the D / A converter by performing a failure diagnosis of the D / A converter, and limits an incorrect output.
A conventional semiconductor integrated circuit equipped with a D / A converter fault diagnosis function will be described with reference to FIGS.

FIG. 9 is a diagram showing a configuration of a semiconductor integrated circuit equipped with a conventional D / A converter fault diagnosis function, and FIG. 10 is a diagram showing a conventional D / A converter fault diagnosis flow.
In FIG. 9, the CPU 1 sets a digital value corresponding to the analog value to be output to the motor in the D / A conversion data storage buffer 11, and after the D / A conversion instruction, the converted analog voltage after D / A conversion is sent to the motor. The motor is controlled by instructing output. On the other hand, it has an analog multiplexer 3 that allows the CPU 1 to switch the input from the sensor or the like and the input from the converted analog voltage of the D / A conversion data storage buffer 11. When performing failure diagnosis, the CPU 1 instructs the analog multiplexer 3 to input the analog voltage after conversion of the D / A converter 2 to the A / D converter 4. As a result, the CPU 1 issues an A / D conversion instruction to the A / D converter 4 to which the converted analog voltage is input, and performs A / D conversion. Next, the CPU 1 obtains the difference between the value of the A / D conversion data storage buffer 5 created and stored by this instruction and the value of the D / A conversion data storage buffer 11. Next, the CPU 1 can determine whether an abnormality has occurred in the converted analog voltage of the D / A converter 2 by comparing and determining the allowable error recorded in the ROM or the like in advance with a program.

When the comparison / determination result is outside the allowable error range, the CPU 1 turns off the analog SW 6 of the D / A converter 2. Thereby, the output of the D / A converter 2 with respect to the motor can be turned off (see, for example, Patent Document 1).
JP 63-33668 A

  In order to perform the above-described failure diagnosis with the prior art, the software flow is as shown in FIG. After the hardware reset, the hardware is initialized by the initialization process, and the main flow is repeated. In this main flow, there is a D / A converter failure diagnosis process. In such a flow, the failure diagnosis process performs a failure diagnosis once for one loop of the main flow. For example, when the time of one main flow loop takes 1 second, an overcurrent may flow for a maximum of 1 second after detecting a failure of the D / A converter. In other words, in the prior art, a delay time depending on the processing timing of the software occurs from the detection of the failure of the D / A converter until the output of the D / A converter is turned off, and it cannot be turned off immediately. There was a problem.

  In other words, as a mechanism for detecting the failure of the D / A converter and restricting the output, there is a need for immediacy that the output must be restricted more quickly and safely, so it depends on the processing timing of the software. Has no effect.

  Therefore, for example, when incorporating a fault diagnosis function of a conventional D / A converter into an existing product, it should be incorporated in a timing that makes the fault diagnosis cycle as short as possible, that is, a timer interrupt that can be processed at a fixed cycle. It is. However, it is practically difficult to incorporate a fault diagnosis function of the D / A converter into a process with a short execution cycle. This is because, in general, a process with a short execution cycle often has a limitation that it must be processed within a specified time limit. By incorporating a fault diagnosis function of a D / A converter, such as a conventional D / A converter fault diagnosis device, the processing time may be extended and processing may not be completed within a specified time limit. . For this reason, a process with a short execution cycle often executes only a minimum necessary process.

  As a result, the period of performing the fault diagnosis process of the D / A converter is not important, and when the fault diagnosis is performed by increasing the period, the fault of the D / A converter can be found, but the immediacy is poor. The problem of limiting the output is not achieved. That is, it is difficult to incorporate a function that achieves the original purpose of the failure diagnosis function of the D / A converter.

  An object of the semiconductor integrated circuit of the present invention is to perform failure diagnosis of a D / A converter more quickly and safely, and to limit output at the time of failure immediately and safely.

  In order to achieve the above object, a semiconductor integrated circuit according to claim 1 is a semiconductor integrated circuit that includes a CPU and controls the operation of an external device, and controls a digital signal from the CPU to control the external device. A D / A converter that converts the signal into an analog signal that is output via an analog switch, a D / A conversion data storage buffer that stores the digital signal to be D / A converted, and converts the analog signal into a digital signal An A / D converter that outputs to the CPU, and a signal from the external device is output to the A / D converter during normal operation, and an analog signal from the D / A converter is output to the A / D converter during failure diagnosis. A first multiplexer to be output to the D converter; an A / D conversion data storage buffer for storing the digital signal after conversion by the A / D converter; and the D / A conversion data storage buffer. A difference circuit for outputting a difference between the digital signal stored in the digital signal and the digital signal stored in the A / D conversion data storage buffer, and an allowable error setting means for setting an allowable error of the difference by the CPU; A comparator for determining whether the difference is within the allowable error range, and a control circuit for limiting an output from the analog switch when the determination result is out of the allowable error range. To do.

  2. The semiconductor integrated circuit according to claim 2, further comprising an interrupt control block for inputting a signal from the comparator, wherein the determination result is outside the range of the allowable error. In some cases, the interrupt control block causes the CPU to generate an interrupt signal.

  According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, the allowable error is automatically calculated from the digital signal value stored in the D / A conversion data storage buffer. And a second multiplexer for selecting either an allowable error of the allowable error setting means or an allowable error of the allowable error automatic setting circuit under the control of the CPU and outputting the selected error to the comparator It further has these.

  The semiconductor integrated circuit according to claim 4 is the semiconductor integrated circuit according to any one of claims 1 to 3, wherein a signal that is out of the allowable error range from the comparator is an arbitrary number of times set in advance. It further has a count circuit that outputs a signal for limiting the output from the analog switch to the control circuit when output.

  The semiconductor integrated circuit according to claim 5 is the semiconductor integrated circuit according to any one of claims 1 to 4, wherein a general-purpose port in which a value at which the external device becomes inactive is latched, and the general-purpose port A third multiplexer that outputs the output from the general-purpose port to the external device when a signal outside the allowable error range is input from the comparator from among the outputs or the outputs from the analog switch; It is characterized by having.

  An air conditioner according to a sixth aspect includes a fan motor and the semiconductor integrated circuit according to any one of the first to fifth aspects, wherein the fan motor is turned on when the determination result is out of the allowable error range. It is characterized by being stopped.

  As described above, the failure diagnosis of the D / A converter can be performed more quickly and safely, and the output at the time of failure can be limited immediately and safely.

  When diagnosing a failure of a D / A converter, the digital data to be D / A converted is stored in a D / A conversion data storage buffer, and the D / A converted analog data is converted by the A / D converter. A / D converted digital data is stored in an A / D converted data storage buffer, and a D / A converter is always determined by a comparator to determine whether the difference between these digital data is within an allowable error range. By controlling the output of the D / A converter, the failure diagnosis of the D / A converter can be performed more quickly and safely, and the output at the time of the failure can be limited immediately and safely.

(First embodiment)
The semiconductor integrated circuit according to the first embodiment will be described with reference to FIG.
FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit equipped with a D / A converter fault diagnosis function in the first embodiment.

  In FIG. 1, the CPU 1 sets a digital value to be input to the D / A converter 2 in order to output an analog value to be output to the motor in the D / A conversion data storage buffer 11, and after the D / A conversion instruction, The motor is controlled by giving an instruction to output the converted analog voltage after A conversion to the motor. On the other hand, it has an analog multiplexer 3 that the CPU 1 can switch so as to output either an input from a sensor or the like and an input from an analog voltage after conversion of the D / A converter 2 to the A / D converter 4. When performing failure diagnosis, the CPU 1 instructs the analog multiplexer 3 to input the analog voltage after conversion of the D / A converter 2 to the A / D converter 4. The A / D converter 4 to which the converted analog voltage is input continuously performs A / D conversion, and stores the converted digital value in the A / D conversion data storage buffer 5 after the conversion is completed. The value of the A / D conversion data storage buffer 5 created continuously is input to a difference circuit 7 that can always output a difference from the value of the D / A conversion data storage buffer 11. Further, the output of the difference circuit 7 is always compared with the allowable error set in the allowable error setting means 9 in advance and the output of the difference circuit 7 to determine whether the output of the difference circuit 7 is within the allowable error range or out of the allowable range. It is input to the comparator 8 for output. It is determined whether the difference between the input digital value stored in the D / A conversion data storage buffer 11 and the digital value after A / D conversion stored in the A / D conversion data storage buffer 5 is within an allowable error range. Thus, it can be determined whether an abnormality has occurred in the converted analog voltage of the D / A converter 2 at this time. However, the comparator 8 cannot output the result of comparison / determination unless there is an output permission instruction from the CPU 1. The output permission instruction is given when the input of the analog multiplexer 3 is switched to the converted analog voltage of the D / A converter 2. Further, the output from the comparator 8 is input to the control circuit 10 for switching on / off the analog SW 6 of the D / A converter 2. When the comparison / determination result of the comparator 8 is outside the allowable error range, the control circuit 10 turns off the analog SW 6 that controls the output of the D / A converter 2. As a result, failure diagnosis processing of the D / A converter 2 can be performed at all times, so that the failure diagnosis of the D / A converter can be performed more quickly and safely without depending on the software processing timing. It is possible to limit the output of the D / A converter 2 with respect to the motor.

  In addition, the software performs a failure diagnosis of the D / A converter 2 at the time of initialization of the semiconductor integrated circuit, as shown in the flowchart of the D / A converter failure diagnosis flow in the semiconductor integrated circuit of the present invention in FIG. If set, the present semiconductor integrated circuit of the present invention constantly diagnoses the failure of the D / A converter 2, so that the software structure is simplified. Therefore, it becomes easy to incorporate the failure diagnosis function of the D / A converter 2. Further, in a system in which failure diagnosis is conventionally performed by software, the entire responsibility for failure diagnosis processing can be transferred to the semiconductor integrated circuit, thereby improving the readability of the software.

This embodiment is a basic configuration of the present invention.
(Second Embodiment)
A semiconductor integrated circuit according to the second embodiment will be described with reference to FIG.

FIG. 2 is a diagram showing a configuration of a semiconductor integrated circuit equipped with a D / A converter fault diagnosis function in the second embodiment.
Also in the present embodiment, the mechanism for turning off the output to the terminal of the D / A converter 2 is the same as in the first embodiment. As shown in FIG. 2, in addition to the configuration of the first embodiment, the output OFF instruction for the D / A converter 2 of the comparator 8 can also be sent to the interrupt control block 31. To do. With this configuration, when a failure of the D / A converter 2 is detected, an output OFF instruction for the D / A converter 2 of the comparator 8 is sent to the interrupt control block 31, and the interrupt control block 31 interrupts the CPU 1. Can be used to turn off the output to the D / A converter 2.

This configuration is effective for a system in which a motor to which power is supplied by a power relay is controlled, an analog output of the D / A converter 2 controls the motor, and another port controls the power relay. The analog output OFF control of the D / A converter 2 to the motor is performed in the same manner as in the first embodiment, and the abnormality recovery process of the D / A converter 2 and the output destination of the D / A converter 2 are performed by interrupt processing. Can be performed at the same timing, and the failure diagnosis of the D / A converter can be performed more quickly and safely, and the D / A converter 2 for the motor at the time of the failure immediately and safely Output can be limited, and a safer motor shutdown is possible.
(Third embodiment)
A semiconductor integrated circuit according to the third embodiment will be described with reference to FIG.

FIG. 3 is a diagram showing a configuration of a semiconductor integrated circuit equipped with a D / A converter fault diagnosis function in the third embodiment.
Also in the present embodiment, the mechanism for turning off the output to the terminal of the D / A converter 2 is the same as that in the first embodiment, but as shown in FIG. For the configuration of the embodiment, the allowable error automatic setting circuit 41 that always sets the allowable error automatically by referring to the value of the D / A conversion data storage buffer 11 and the allowable error used in the failure diagnosis is allowed. A multiplexer 42 is newly added to select which one of the value set by the automatic error setting circuit 41 and the value set by the allowable error setting means 9 is used.

  By setting the CPU 1 to select the allowable error generated by the automatic tolerance setting circuit 41 as the allowable error used for the failure diagnosis of the D / A converter 2, the automatic error tolerance setting circuit 41 is set to D during the failure diagnosis. A permissible error corresponding to the value of the / A conversion data storage buffer 11 is always created, and a fault diagnosis of the D / A converter 2 is performed using this always created permissible error. Therefore, the failure diagnosis of the D / A converter can be performed more quickly and safely and more accurately, and the output of the D / A converter 2 to the motor at the time of failure can be limited immediately and safely.

  With such a semiconductor integrated circuit, the allowable error can be corrected by the voltage level output from the D / A converter 2. That is, it is possible to correct an allowable error in accordance with the characteristics of an external device such as a zero transition, a full scale transition, or a motor unique to the microcomputer. For example, this is effective when the allowable error allowed when the voltage level output from the D / A converter 2 to the motor is low and the allowable error allowed when the voltage level is high is large. Therefore, the allowable error automatic setting circuit 41 is uniquely defined by the characteristics of the external device such as a microcomputer and a motor to be used.

For example, as shown in the figure illustrating the allowable error setting means in the third embodiment of FIG. 7, the value range of the D / A conversion data storage buffer 11 can be divided into five and the allowable error can be set in each range. Like that. For example, when the range of the value of the D / A conversion data storage buffer 11 is divided into 5 with 5V as the maximum, the allowable error at 4.5V is set to 0.5V, and the allowable error at 0.5V is set to 0. Set to .05V.
(Fourth embodiment)
A semiconductor integrated circuit according to the fourth embodiment will be described with reference to FIG.

FIG. 4 is a diagram showing a configuration of a semiconductor integrated circuit equipped with a D / A converter fault diagnosis function in the fourth embodiment.
Also in the present embodiment, the mechanism for turning off the output to the terminal of the D / A converter 2 is the same as the configuration of the first embodiment.

  In the present embodiment, as shown in FIG. 4, an m clock count circuit 51 is added between the comparator 8 and the control circuit 10 in the configuration of the first to third embodiments. The CPU 1 sets an arbitrary integer value m in the m storage buffer 52 in advance. The m clock count circuit 51 counts up the internal state by 1 when it detects an output indicating that it is out of the allowable error range as a determination result of the comparator 8. A signal for turning off the analog SW 6 of the D / A converter 2 is output to the control circuit 10 for the first time when the output of the comparator 8 is detected m times continuously.

With such a semiconductor integrated circuit, the failure diagnosis of the D / A converter can be performed more quickly and safely, and the output of the D / A converter 2 to the motor at the time of failure can be immediately and safely limited. Only when abnormalities in the analog voltage after the conversion of the A / A converter 2 are continuously detected, the output of the D / A converter 2 to the motor is turned OFF so that noise is output to the output of the comparator 8 It is possible to add a noise removal function that can prevent an operation from being erroneously recognized as an abnormal operation.
(Fifth embodiment)
A semiconductor integrated circuit according to the fifth embodiment will be described with reference to FIG.

FIG. 5 is a diagram showing a configuration of a semiconductor integrated circuit equipped with a D / A converter fault diagnosis function in the fifth embodiment.
Also in the present embodiment, the mechanism for turning off the output to the terminal of the D / A converter 2 is the same as in the first embodiment.

  In the present embodiment, as shown in FIG. 5, in addition to the configurations of the first to fourth embodiments, the OFF request signal from the comparator 8 is sent to the analog output of the D / A converter 2 and the general-purpose port 61. This is effective when the analog output after conversion of the D / A converter 2 and the output of the general-purpose port 61 are assigned as dual-purpose ports.

On the other hand, for the output of the general-purpose port 61, the output of the inactive logic of the motor is latched in the port in advance. In this configuration, the multiplexer 62 that has received the output OFF instruction for the D / A converter 2 of the comparator 8 can switch from the output of the D / A converter 2 to the output of the general-purpose port 61. As a result, the failure diagnosis of the D / A converter is performed more quickly and safely, and when it is determined that the failure has occurred, by outputting the inactive logic of the motor latched in advance, immediately after the occurrence of the failure, and It is possible to safely limit the output of the D / A converter 2 for the motor at the time of failure.
(Sixth embodiment)
The air conditioner according to the sixth embodiment will be described with reference to FIG.

FIG. 6 is a diagram showing a configuration of an air conditioner provided with the semiconductor integrated circuit of the present invention.
As shown in FIG. 6, the air conditioner indoor unit 100 includes a fan motor 101 and a semiconductor integrated circuit 102 of the present invention. As shown in the figure, the semiconductor integrated circuit 102 and the fan motor 102 are connected.

  The rotation speed of the fan motor 101 is controlled by the DA output of the semiconductor integrated circuit 102. The semiconductor integrated circuit 102 automatically determines whether the DA output value, which is the output value of the D / A converter, is within an allowable error range. If the DA output value is an abnormal value, the DA output is automatically stopped. As a result, even when the DA output circuit of the semiconductor integrated circuit 102 fails, the fan motor 101 can be stopped without causing an overcurrent to flow.

  Here, an air conditioner has been described as an example, but the present invention can be used for home appliances whose operation is controlled by the output of a D / A converter.

  The present invention can perform failure diagnosis of a D / A converter more quickly and safely, can immediately and safely limit the output at the time of failure, and has functions of a D / A converter and an A / D converter. It is useful for a semiconductor integrated circuit having a failure diagnosis function of a D / A converter and an air conditioner equipped with the semiconductor integrated circuit.

The figure which shows the structure of the semiconductor integrated circuit which mounts the D / A converter fault diagnostic function in 1st Embodiment. The figure which shows the structure of the semiconductor integrated circuit which mounts the D / A converter fault diagnostic function in 2nd Embodiment. The figure which shows the structure of the semiconductor integrated circuit which mounts the D / A converter fault diagnostic function in 3rd Embodiment. The figure which shows the structure of the semiconductor integrated circuit which mounts the D / A converter failure diagnostic function in 4th Embodiment The figure which shows the structure of the semiconductor integrated circuit which mounts the D / A converter fault diagnostic function in 5th Embodiment The figure which shows the structure of an air conditioner provided with the semiconductor integrated circuit of this invention The figure which illustrates the permissible error setting means in a 3rd embodiment The figure which shows the D / A converter failure diagnosis flow in the semiconductor integrated circuit of this invention The figure which shows the structure of the semiconductor integrated circuit carrying the conventional D / A converter fault diagnostic function The figure which shows the flow of the conventional D / A converter fault diagnosis

Explanation of symbols

1 CPU
2 D / A converter 3 Analog multiplexer 4 A / D converter 5 A / D conversion data storage buffer 6 Analog SW
7 Difference circuit 9 Allowable error setting means 10 Control circuit 11 D / A conversion data storage buffer 31 Interrupt control block 41 Allowable error automatic setting circuit 42 Multiplexer 51 m Clock count circuit 52 m Storage buffer 61 General-purpose port 62 Multiplexer 100 Air conditioner outdoor unit 101 fan motor 102 semiconductor integrated circuit

Claims (6)

A semiconductor integrated circuit comprising a CPU and controlling the operation of an external device,
A D / A converter that converts a digital signal from the CPU into an analog signal that is a control signal of the external device and outputs the analog signal via an analog switch;
A D / A conversion data storage buffer for storing the digital signal to be D / A converted;
An A / D converter that converts an analog signal into a digital signal and outputs the signal to the CPU;
A first multiplexer that outputs a signal from the external device to the A / D converter during normal operation and outputs an analog signal from the D / A converter to the A / D converter during failure diagnosis;
An A / D conversion data storage buffer for storing a digital signal after conversion by the A / D converter;
A difference circuit that outputs a difference between the digital signal stored in the D / A conversion data storage buffer and the digital signal stored in the A / D conversion data storage buffer;
Tolerance setting means for setting the tolerance of the difference by the CPU;
A comparator for determining whether the difference is within the tolerance;
And a control circuit that limits an output from the analog switch when the determination result is outside the range of the allowable error.   It further has an interrupt control block for inputting a signal from the comparator, and the interrupt control block causes the CPU to generate an interrupt signal when the determination result is outside the allowable error range. The semiconductor integrated circuit according to claim 1. An allowable error automatic setting circuit for automatically setting the allowable error from the digital signal value stored in the D / A conversion data storage buffer;
And a second multiplexer that selects either the allowable error of the allowable error setting means or the allowable error of the allowable error automatic setting circuit under the control of the CPU and outputs the selected multiplexer to the comparator. The semiconductor integrated circuit according to claim 1 or 2.   A count circuit for outputting, to the control circuit, a signal for limiting the output from the analog switch when a signal outside the allowable error range is output from the comparator an arbitrary number of times set in advance; 4. The semiconductor integrated circuit according to claim 1, further comprising: A general-purpose port latched with a value at which the external device becomes inactive; and
A third output that outputs the output from the general-purpose port to the external device when a signal outside the allowable error range is input from the comparator among the output from the general-purpose port or the output from the analog switch. The semiconductor integrated circuit according to claim 1, further comprising: a multiplexer.   An air conditioner comprising a fan motor and the semiconductor integrated circuit according to any one of claims 1 to 5, wherein the fan motor is stopped when the determination result is out of the allowable error range. .

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