JP2009071184A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having trench isolation, capable of relieving the stresses on a semiconductor substrate, while suppressing increase in the cost. <P>SOLUTION: A semiconductor device 100, having a trench isolation structure, is provided with a laminated SOI substrate, consisting of a support substrate 10, a laminated oxide film 20, and an active layer 30; a trench 70 that is provided in the active layer 30 so as to expose the active layer 30; a lid member 60 that covers at least the opening of the trench 70 and is made of an insulating material; and a void that is surrounded by the surface of the trench 70 and the lid member 60. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having trench isolation.

  Conventionally, as an example of a semiconductor device having trench isolation, there is one shown in Patent Document 1.

In the semiconductor device disclosed in Patent Document 1, a trench is provided on the surface of a semiconductor substrate. A thermal oxide film is provided on the surface of the trench, and an insulating film that partially fits into the trench and extends upward is provided so that a void is formed in the trench. The diameter of the upper end of the trench is made smaller than the diameter of the insulating film. By doing so, stress is relieved.
JP 2003-158180 A

  However, in the semiconductor device disclosed in Patent Document 1 described above, there is a problem in that the number of processes and materials increases because the thermal oxide film is provided on the surface of the trench, resulting in an increase in cost.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that can relieve stress on a semiconductor substrate while suppressing an increase in cost in a semiconductor device having trench isolation. .

  In order to achieve the above object, a semiconductor device according to claim 1 is a semiconductor device having a trench isolation structure, and includes at least a semiconductor substrate, a trench provided with the semiconductor substrate exposed to the semiconductor substrate, and at least A lid member made of an insulating material that covers the opening of the trench, and a void surrounded by the surface of the trench and the lid member are provided.

  By doing in this way, the stress of a semiconductor substrate can be relieved with a void, without providing a thermal oxide film in the surface (side wall) of a trench, and a cost increase can be suppressed. Moreover, since the stress of the semiconductor substrate can be relaxed, crystal defects of the semiconductor substrate can also be suppressed.

  According to a second aspect of the present invention, the bottom of the trench may be provided with a notch that extends around the trench. By doing in this way, a proof pressure can also be improved.

  According to a third aspect of the present invention, the trench may have a bow shape. By doing in this way, since a lid member can be provided only in the opening of a trench, it can be made easy to provide a void.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

  As shown in FIG. 1, a semiconductor device 100 according to the present embodiment uses a bonded SOI substrate including a support substrate 10, a bonded oxide film 20, and an active layer 30 (for example, made of single crystal silicon). A LOCOS 40 and an oxide film 50 are formed on the surface of the SOI substrate. In the active layer 30, a trench 70 reaching the bonded oxide film 20 is formed to insulate elements (not shown) formed in the active layer 30.

  The trench 70 is provided with the active layer 30 (semiconductor substrate) exposed on the surface. A lid member 60 formed of the oxide film 50 is formed in the opening of the trench 70. Therefore, the semiconductor device 100 has a void 80 surrounded by the surface of the trench 70 and the lid member 60.

  Conventionally, a trench for insulating and isolating elements has been embedded in the entire trench with polysilicon after trench sidewall oxidation, or embedded and isolated with an insulating film of an oxide film. However, when the trench is filled with polysilicon or an oxide film system, stress may be generated in the semiconductor substrate (active layer) in a subsequent process, and crystal defects may occur. In order to prevent such crystal defects, it is conceivable to add a high-temperature heat treatment, but there is a possibility that the process becomes longer or the diffusion layer becomes too wide. The void 80 is intended to relieve stress generated by embedding such polysilicon or oxide film in the trench and suppress the generation of crystal defects.

  Here, a method for manufacturing the semiconductor device 100 in the present embodiment will be described.

  First, an oxidation process, a film forming process, a photo process, an etching process, and an impurity diffusion process are performed on a bonded SOI substrate including the support substrate 10, the bonded oxide film 20, and the active layer 30 (for example, made of single crystal silicon). Repeat to form the device. The process for forming the device is a general process and will not be described in detail.

Then, the oxide film in a portion where element isolation is desired is removed by a photoetching process. Next, a trench 70 is formed by trench etching for the active layer 30 and the like. As an example of the conditions for forming the trench 70, SF ₆ is 70 SCCM, O ₂ is 10 SCCM, the coil magnet power is 800 W, and etching is performed just before reaching the oxide film 20.

  Thereafter, etching is performed while the RF power for drawing F ions into the SOI substrate (active layer 30) is set to a time ratio of 20% (on / off ratio). When F ions reach the substrate, the separated active layer portion is charged, so that F ions are attracted and etching proceeds in the lateral direction. In order to prevent this, the RF power is turned on and off to prevent charging, and lateral etching is reduced. In this way, a trench 70 that is almost vertical as shown in FIG. 1 is formed.

Thereafter, in order to form the lid member 60 in the opening of the trench 70, O ₃ -BPSG is formed. Specifically, TEOS, TEB, TEPO, and ozone are introduced into a chamber (for example, 480 ° C.) of the CVD apparatus to form an O ₃ -BPSG film. The flow rates of TEOS, TEB, and TEPO are adjusted according to the B concentration and the P concentration. In order to improve the coverage, as an example, the film is formed at a pressure of 600 Torr, TEOS: 1200 mg / min, TEB: 38 mg / min, and TEPO: 50 mg / min. Since the rate is small, the film thickness is increased in 2nd steps under the condition that the rate is increased (for example, the pressure is lowered to 200 Torr).

Thereafter, the BPSG film is reflowed by heat treatment at about 800 ° C. to 950 ° C., and the lid member 60 is formed in the opening of the trench 70. In the present embodiment, a sidewall oxide film is not formed on the surface of the trench 70, so that even if O ₃ -BPSG is formed, it is difficult to form a BPSG film on the side surface of the trench 70. Moreover, even if it reflows, it becomes difficult to flow into the trench 70. Therefore, since semiconductor device 100 in the present embodiment does not form a sidewall oxide film in the trench, it is possible to suppress an increase in cost and increase void 80 compared to the case where the sidewall oxide film is formed in the trench. Therefore, crystal defects due to stress can be further reduced. In other words, there is an effect that the isolation breakdown voltage can be obtained.

  In addition, after filling the upper part of the trench 70, it planarizes by CMP and the photoetching for contact formation is performed. Then, a generally performed barrier metal forming process, W plug and AL wiring formation are performed, and finally a protective film is formed to complete the wafer process.

(Modification 1)
Next, the semiconductor device 110 in Modification 1 shown in FIG. 2 will be described. In Modification 1, since there are many points equivalent to the above-described embodiment, different points will be mainly described.

  As shown in FIG. 2, in the semiconductor device 110, a notch 81 extending around the trench 70 is formed at the bottom of the trench 70. The notch 81 can be formed by performing overetching by trench etching. By providing the notch 81 in this manner, the breakdown voltage can be improved even when the bottom of the trench 70 is not covered with an oxide film.

  In the case of forming the notch 81, by turning off / on the RF bias at the 2nd step (for example, time ratio 20%, etc.) under the trench etching conditions, the lateral etching is advanced and the breakdown voltage is reduced. You can also earn. In addition, by performing overetching for a long time, lateral etching can be advanced.

(Modification 2)
Next, the semiconductor device 120 in Modification 2 shown in FIG. 3 will be described. In Modification 2, since there are many points equivalent to the above-described embodiment, different points will be mainly described.

  As shown in FIG. 3, the trench 70 of the semiconductor device 120 in Modification 2 has a bow shape. That is, the trench 70 has a wider intermediate portion than the opening and the bottom. Therefore, the void 80a has a bow shape in which the intermediate portion is wider than the opening and the bottom.

In this way, when the trench 70 is bowed, it can be formed, for example, by increasing the substrate temperature from −50 ° C. or reducing the oxygen flow rate under the trench etching conditions. As the substrate temperature rises, the Si etch rate increases, and the polymer attached to the sidewalls of the trench 70 volatilizes, making it difficult to reach the sidewalls. Further, since SF ₆ gas isotropically etches Si (active layer 30), the etching proceeds in a reverse taper shape. However, when the trench 70 becomes deeper, it becomes difficult to supply F ions, so that the etching is difficult to proceed at the bottom of the trench 70, resulting in a bow shape.

  By doing in this way, since the cover member 60 can be provided only in the opening part of the trench 70, the void 80a can be easily provided.

It is sectional drawing which shows the semiconductor device in embodiment of this invention. It is sectional drawing which shows the semiconductor device in the modification 1 of this invention. It is sectional drawing which shows the semiconductor device in the modification 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Support substrate, 20 Bonding oxide film, 30 Active layer, 40 LOCOS, 50 Oxide film, 60 Lid member, 70 Trench, 80, 80a Void, 81 notch, 100, 110, 120 Semiconductor device

Claims (3)

A semiconductor device having a trench isolation structure,
A semiconductor substrate;
A trench provided in the semiconductor substrate with the semiconductor substrate exposed;
A lid member made of an insulating material covering at least the opening of the trench;
A void surrounded by the surface of the trench and the lid member;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein a notch extending around the trench is provided at a bottom of the trench.   The semiconductor device according to claim 1, wherein the trench has a bow shape.

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