JP2009071132A - Method for manufacturing multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein in a multilayer wiring board manufacturing, resist residues in unwanted parts sometimes prevent electrolytic plating formation, especially in a via hole, when the formation of an upper-layer wiring layer and the hole-filling of the via hole are performed by electrolytic plating by arranging a plating resist for upper-layer wiring, after the non-electrolytic plating of a front-end in a multilayer wiring board manufacturing method for laminating and integrating prepreg and metal foil, arranged on the upper layer of the prepreg, with an internal layer material formed by circuit, arranging the via hole by laser after patterning the metallic foil in a hole shape, and performing the formation of the upper layer wiring layer and the hole filling of the via hole by electrolytic plating. <P>SOLUTION: Plating is performed with an electrolytic filler plating liquid, after performing the non-electrolytic plating of the front-end and also before arranging the plating resist for the upper layer wiring, and then hole filling is performed in the via hole through electrolytic plating. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a multilayer wiring board. In particular, it relates to a pretreatment method for filled plating.

Conventionally, a prepreg structure with a copper foil has been proposed for manufacturing a multilayer wiring board, and it becomes possible to form fine wiring from the thin copper foil, which leads to higher wiring density, thinner film, and smaller size. Can be achieved. On the other hand, for via holes connecting upper and lower conductor wiring layers, excimer lasers and laser processing machines using third and fourth harmonics of YAG have been actively introduced, and formation of minute diameter via holes has become easier. Yes.
Then, by applying these, a prepreg and a metal foil are laminated and integrated on the inner layer material on which the circuit is formed, a via hole is provided by a laser, and after the base electroless plating, the via hole is filled by electrolytic plating The manufacturing method of a wiring board is performed actively (patent document 1).
JP 2003-318544 A

The problem to be solved is that after the prepreg and the metal foil are laminated and integrated on the inner layer material on which the circuit is formed, the metal foil is patterned into a hole shape, and then a hole for a via hole is provided, after the base electroless plating When the upper layer wiring layer is formed by electrolytic plating after the plating resist is provided for the upper layer wiring and the via hole is filled, an unnecessary portion of the plating resist residue particularly disturbs the formation of the electrolytic plating in the via hole. There is a case. An object of the present invention is to provide a method for manufacturing a multilayer wiring board that eliminates the adverse effects of plating resist residue and forms an upper wiring layer and fills the via hole by electrolytic plating.

In the present invention, a prepreg and a metal foil are laminated and integrated on an inner layer material on which a circuit is formed, the metal foil is patterned into a hole shape, holes for via holes are provided, base electroless plating is performed, and upper layer wiring is used. In the method of manufacturing a multilayer wiring board in which an upper wiring layer is formed by electrolytic plating and the via hole is filled, electrolytic plating is performed before providing the upper layer wiring plating resist after the base electroless plating. It is an object of the present invention to provide a method for manufacturing a multilayer wiring board for plating with a filled plating solution.

In the method of the present invention, a prepreg and a metal foil are laminated and integrated on an inner layer material on which a circuit is formed, and the metal foil is patterned into a hole shape. After the plating resist is provided, in the method of manufacturing the multilayer wiring board in which the upper wiring layer is formed by electrolytic plating and the via hole is filled, before the plating resist for the upper wiring is provided after the base electroless plating, the electrolytic filled plating solution Since the bottom of the hole rises and the plating resist residue does not easily remain in the hole, it is difficult to cause a defect that a via hole is not filled by electrolytic plating. Further, since the bottom surface of the hole is raised by plating with the electrolytic filled plating solution, this plating is not applied on the upper layer surface, so that it is easy to finally form the upper wiring layer by etching.

  The inner layer material described in the present invention is used for a general inner layer of a wiring board, and generally, copper, copper, on the upper surface and / or lower surface of a required number of resin-impregnated base materials obtained by impregnating a reinforcing base material with a resin composition, A metal foil made of aluminum, brass, nickel, iron or the like alone, alloy or composite foil is laminated and integrated, and the metal foil is formed by etching or the like.

  The prepreg described in the present invention is an adhesive sheet in which a reinforcing base material is impregnated with a resin composition to form a semi-cured B stage, and a prepreg used for a general wiring board can be used.

As said resin composition, the well-known and usual resin composition used as an insulating material of a printed wiring board can be used. Usually, a thermosetting resin having good heat resistance and chemical resistance is used as a base, and one kind of resin such as phenol resin, epoxy resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, fluorine resin or the like Two or more types are used in combination, and as required, inorganic powder fillers such as talc, clay, silica, alumina, calcium carbonate, aluminum hydroxide, antimony trioxide, antimony pentoxide, glass fiber, asbestos fiber, pulp fiber Further, a fiber filler such as synthetic fiber or ceramic fiber is added.
In addition, the resin composition may be blended with a thermoplastic resin in consideration of dielectric properties, impact resistance, film processability, and the like. Further, various additives and fillers such as an organic solvent, a flame retardant, a curing agent, a curing accelerator, thermoplastic particles, a colorant, an ultraviolet light impermeant, an antioxidant and a reducing agent are added as necessary.

  Examples of the reinforcing substrate include inorganic fibers such as glass and asbestos, polyester, polyamide, polyacryl, polyvinyl alcohol, polyimide, organic fibers such as fluorine resin, natural fibers such as cotton, nonwoven fabric, paper, mats, etc. Is used.

Usually, after impregnating or coating the reinforcing base so that the amount of the resin composition attached to the reinforcing base is 20 to 90% by weight in terms of the resin content of the prepreg after drying, the temperature is usually 100 to 200 ° C. And dried for 1 to 30 minutes to obtain a prepreg in a semi-cured state (B stage state). Usually, 1 to 20 sheets of this prepreg are stacked and heated and pressed in a configuration in which metal foils are arranged on both surfaces. As a molding condition, a method of a normal laminated plate can be applied. For example, a multi-stage press, a multi-stage vacuum press, continuous molding, an autoclave molding machine or the like is used, and a temperature is typically 100 to 250 ° C., a pressure is ^{2 to} 100 kg / cm ² , and heating is performed. The molding may be performed in the range of 0.1 to 5 hours, or may be performed under reduced pressure or atmospheric pressure under a lamination condition of 50 to 150 ° C. and 0.1 to 5 MPa using a vacuum laminating apparatus or the like. Although the thickness of the prepreg layer used as an insulating layer changes with uses, the thickness of 0.1-5.0 mm is good normally.

As the metal foil described in the present invention, a metal foil used for a general wiring board can be used. As for the surface roughness of the metal foil used in the present invention, the 10-point average roughness (Rz) shown in JIS B0601 is preferably 2.0 μm or less on both sides in view of electrical characteristics. Although copper foil, nickel foil, aluminum foil, etc. can be used for metal foil, copper foil is usually used. In the case of a copper sulfate bath, the production conditions of the copper foil are sulfuric acid 50-100 g / L, copper 30-100 g / L, liquid temperature 20 ° C.-80 ° C., current density 0.5-100 A / dm ² , pyrophosphoric acid In the case of a copper bath, the conditions of potassium pyrophosphate 100-700 g / L, copper 10-50 g / L, liquid temperature 30 ° C.-60 ° C., pH 8-12, current density 1-10 A / dm ² are commonly used. In some cases, various additives may be added in consideration of the physical properties and smoothness of copper.

The antirust treatment performed on the resin adhesive surface of the metal foil can be performed using any of nickel, tin, zinc, chromium, molybdenum, cobalt, or an alloy thereof. In these methods, a thin film is formed on a metal foil by sputtering, electroplating or electroless plating, but electroplating is preferable from the viewpoint of cost. The amount of the rust-proofing metal varies depending on the type of metal, but is preferably 10 to 2000 μg / dm ^{2 in} total. If the rust preventive treatment is too thick, it may cause etching inhibition and deterioration of electrical characteristics, and if it is too thin, it may cause a reduction in peel strength with the resin. Furthermore, if a chromate treatment layer is formed on the rust prevention treatment, it is useful because a reduction in peel strength with the resin can be suppressed.

  The via holes described in the present invention include interstitial via holes (IVH) that are plated holes for connecting the layers of two or more conductor layers at all connection holes that are not penetrated during plating. . In addition to those plated on the inner surface of the hole, fill vias in which the entire hole is plated are also included. A via hole having a diameter about the same as or twice the thickness of the insulating layer tends to form a fill via.

  The base electroless plating described in the present invention is an electroless plating provided on the entire surface of the substrate after the via hole is provided, and is plated on the surface of the upper layer, the side surface of the via hole, the inner layer circuit surface of the bottom surface of the via hole, and the like.

The plating resist described in the present invention prevents electrolytic plating. A dry film or a liquid resist is provided on the entire surface of the substrate, and after exposure, developed with a sodium carbonate aqueous solution or the like so as to remove the subsequent electrolytic plating portion. is there.

  The upper wiring layer described in the present invention refers to a wiring layer provided in an upper layer made of a cured prepreg provided on the surface of the inner layer material.

The plating with the electrolytic filled plating solution described in the present invention refers to plating using a conventional electrolytic filled plating solution, and the thickness of the plating layer is thicker at the bottom surface in the via hole than at the upper surface. The thickness of the upper surface is in the range of 0.5 to 3 μm, and the thickness of the bottom surface in the via hole is in the range of 2 to 10 μm.
The electrolytic filled plating solution is generally prepared by adding an inhibitor for suppressing plating growth and an accelerator for promoting plating growth to a copper sulfate plating bath.
By applying the fact that the plating inhibitor is difficult to adsorb inside the via hole and easily adsorbs to the substrate surface in accordance with the diffusion law of the substance, the plating growth rate is slowed down compared to the inside of the via hole. It is said that the inside of the via hole is filled with copper, and the surface of the substrate is smoothly electrolytically plated at a portion directly above the via hole and a portion other than the portion immediately above the via hole. As the plating inhibitor, there can be used a nitrogen-containing compound such as a polyether compound such as polyalkylene glycol, a polyvinyl imidazolium quaternized product, and a copolymer of vinyl pyrrolidone and vinyl imidazolium quaternized product.
The plating accelerator is uniformly adsorbed on the bottom, side, and substrate surface of the via hole, and then the surface area decreases with the growth of plating inside the via hole, and the distribution of the accelerator in the via hole becomes dense. Therefore, the plating speed inside the via hole becomes faster than the plating speed on the substrate surface, the inside of the via hole is filled with copper, and the substrate surface is smoothed and electroplated in the portion directly above the via hole and the portion other than the portion immediately above the via hole. It is said that there is an effect. The plating accelerator is represented by a sulfur compound represented by sodium 3-mercapto-1-propanesulfonate or sodium 2-mercaptoethanesulfonate, or bis- (3-sulfopropyl) -disulfide disodium. Sulfur compounds to be used can be used. These plating accelerators are also a kind of additive added to a copper plating solution called a brightener (brightener).
The said plating inhibitor and a plating accelerator are used 1 type or in mixture of 2 or more types. The concentration of these aqueous solutions is not particularly limited, but can be used at a concentration of several ppm to several percent.

Hereinafter, the present invention will be described based on embodiments shown in the drawings.
FIG. 1 shows a method for manufacturing a multilayer wiring board according to the present invention.

First, as shown in FIG. 1A, a prepreg 3 and a metal foil 4 for upper layer wiring are laminated and integrated on an inner layer material 2 on which an inner layer circuit 1 is formed, and the metal foil 4 for upper layer wiring is integrated. After patterning into a hole shape, a via hole 5 is provided in the patterned portion by laser.
As a method of laminating and integrating the prepreg and the metal foil on the upper layer on the inner layer material on which the circuit is formed, a method of laminating and pressing the inner layer substrate, the prepreg and the copper foil, or a method of laminating a resin with a single-sided metal foil is used. The thickness of the insulating layer is about 10 to 100 μm, preferably 20 to 60 μm, and the thickness of the metal foil is 5 to 9 μm. Resin used for the production of resin with single-sided metal foil, copper foil is the same as that for laminates, and resin varnish is applied to metal foil using a kiss coater, roll coater, comma coater, etc., or a film-like resin Is laminated to a metal foil. When the resin varnish is applied to the metal foil, it is then heated and dried, but the condition is suitably 1 to 30 minutes at a temperature of 100 to 200 ° C., and in the resin composition after heating and drying. The residual solvent amount is suitably about 0.2 to 10%. When laminating a film-like resin on a metal foil, vacuum or atmospheric pressure conditions are suitable under the conditions of 50 to 150 ° C. and 0.1 to 5 MPa.
As the laser is able to be used for forming a via hole, CO ₂ and CO, it has a solid laser gas laser or a YAG or the like of an excimer like. Since a CO ₂ laser can easily obtain a large output, it is suitable for processing IVH of φ50 μm or more. When processing a fine IVH of φ50 μm or less, a YAG laser with a shorter wavelength and good condensing property is suitable, but care must be taken not to penetrate the inner layer copper foil.

  Next, as shown in FIG. 1 (b), the thickness 4 of the metal foil for the upper layer wiring is reduced by an etching solution such as ferric chloride aqueous solution, ammonium persulfate, or sulfuric acid-hydrogen peroxide aqueous solution. Half-etch from about 1 to 3 μm. At this time, if the thickness of the metal foil 4 for the upper layer wiring is about 1 to 3 μm from the beginning, it is not necessary to further perform half etching.

Next, as shown in FIG.1 (c), after providing a catalyst nucleus on metal foil and a via hole, the electroless-plating layer 6 is formed. For example, an activator neogant (trade name, manufactured by Atotech Japan Co., Ltd.) that is a palladium ion catalyst and HS201B (trade name, manufactured by Hitachi Chemical Co., Ltd.) that is a palladium colloid catalyst are used for imparting a catalyst nucleus. . Adsorption onto a copper foil of the palladium catalyst in the present invention is in the range of 0.03~0.6μg / cm ^2, more preferably in the range of 0.05~0.3μg / cm ^2. The treatment temperature for adsorbing the palladium catalyst is preferably 10 to 40 ° C. By controlling the treatment time, the adsorption amount of the palladium catalyst on the copper foil can be controlled.
For electroless plating, commercially available electroless copper plating such as CUST2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) or CUST201 (trade name, manufactured by Hitachi Chemical Co., Ltd.) can be used. These electroless copper platings are mainly composed of copper sulfate, formalin, complexing agent and sodium hydroxide. The thickness of plating should just be the thickness which can perform the following electroplating, and is the range of 0.1-5 micrometers. However, as will be described later, in order to remove via-hole plating resist residues and other dirt adhering to the electroless plating layer by etching, the thickness is more preferably in the range of 0.5 to 3.0 μm.

  Next, as shown in FIG.1 (d), after performing electroless plating, the electrolytic plating layer 7 by an electrolytic filled plating solution is formed. The thickness of the plating layer is such that the thickness of the bottom surface in the via hole is larger than the thickness of the upper layer surface, the thickness of the upper layer surface is in the range of 0.5 to 3.0 μm, and the thickness of the bottom surface in the via hole is 2 It is provided in a range of about 10 μm.

  Next, as shown in FIG.1 (e), the plating resist 8 is formed on the plating layer 7 by an electrolytic filled plating solution. The thickness of the plating resist is preferably set to a thickness that is about the same as or thicker than the conductor to be subsequently plated. Resins that can be used for the plating resist include liquid resists such as PMER P-LA900PM (trade name, manufactured by Tokyo Ohka Co., Ltd.), HW-425 (trade name, Hitachi Chemical Co., Ltd.), RY-3025 (Hitachi Chemical). There are dry films such as Kogyo Co., Ltd. (trade name). A plating resist is not formed on the via hole and the portion to be a conductor circuit.

  Next, as shown in FIG. 1 (f), after removing the resin residue inside the via hole using an oxidizing agent such as permanganate, chromate, chromic acid, etc., ferric chloride is then used. With an etching solution such as an aqueous solution, ammonium persulfate, or a sulfuric acid-hydrogen peroxide mixed solution, the uppermost wiring layer on the upper wiring layer until the plating layer 7 by the electrolytic filled plating solution on the upper wiring layer is at least half or less. The underlying electroless plating layer 6 is removed by etching until the thickness is about half.

  Next, as shown in FIG. 1G, a fill via 9 and a circuit pattern 10 are formed by electroplating. For electroplating, copper sulfate electroplating for fill vias that is usually used for printed wiring boards can be used. The plating thickness may be used as a circuit conductor and the via hole can be filled with a conductive metal, and is preferably in the range of 1 to 100 μm, and more preferably in the range of 10 to 50 μm.

  Next, as shown in FIG. 1 (h), the plating resist 8 is stripped using an alkaline stripping solution, sulfuric acid, or a commercially available resist stripping solution, and copper other than the pattern portion is removed by etching.

Next, as shown in FIG. 1 (i), copper other than the pattern portion is preferably removed using an etching solution mainly composed of 10 to 300 g / L sulfuric acid and 10 to 200 g / L hydrogen peroxide. This completes the circuit formation. After the etching is completed, the undercut is preferably within 5 μm on one side.
A two-layer wiring board is completed by the method described above. Furthermore, when producing a multilayer board, the surface of the wiring board is roughened, and while improving the adhesion with the interlayer resin insulating layer formed on the copper pattern, a metal foil is formed on the prepreg and the upper layer. And are laminated.

Hereinafter, the present invention will be described based on examples.
First, a resin film with a single-sided metal foil having an insulating layer thickness of 30 μm and a metal foil thickness of 5 μm is vacuum-laminated on the circuit-formed inner layer material under the conditions of 120 ° C. and 2 MPa. Next, this metal foil is patterned into a hole shape having a diameter of 80 μm for a via hole. Next, a hole for a via hole is formed in a hole-shaped portion having a diameter of 80 μm with a CO ₂ laser.
Next, the thickness of the metal foil is half-etched to 2 μm with an etching solution such as ferric chloride aqueous solution, ammonium persulfate, or sulfuric acid-hydrogen peroxide mixed solution.
Next, after applying catalyst core using HS201B (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is a palladium colloid catalyst, on the metal foil and inside the via hole, CUST2000 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is used. A base electroless plating layer having a thickness of 2 μm is formed.
Next, an electrolytic plating layer is formed with an electrolytic filled plating solution having an upper layer surface thickness of 2 μm and a bottom surface inside the via hole of 6 μm.
Next, a plating resist having a thickness of 29 μm is formed using SL-1229 (Hitachi Chemical Co., Ltd., trade name) which is a dry film resist. The plating resist is removed from the via hole and the portion to be a conductor circuit.
Next, it is removed by etching with an etching solution of ammonium persulfate and sulfuric acid-hydrogen peroxide aqueous solution until the base electroless plating film thickness on the upper wiring layer becomes 1.8 μm.
Next, a circuit pattern is formed by electroplating with a thickness of 20 μm.
Next, the resist is stripped using an alkaline stripping solution, and copper other than the pattern portion is preferably removed using an etching solution mainly containing 50 g / L sulfuric acid and 50 g / L hydrogen peroxide.

1 illustrates a method for manufacturing a multilayer wiring board according to the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Inner layer circuit, 2 ... Inner layer material, 3 ... Prepreg, 4 ... Metal foil for upper layer wiring, 5 ... Hole for via hole, 6 ... Electroless plating layer, 7 ... Plating layer by electrolytic filled plating solution, 8 ... Plating Resist, 9 ... fill via, 10 ... circuit pattern.

Claims (1)

  A prepreg and a metal foil are laminated and integrated on the inner layer material on which the circuit is formed, the metal foil is patterned into a hole shape, holes for via holes are provided, base electroless plating is performed, and a plating resist is applied for upper layer wiring. In the manufacturing method of the multilayer wiring board in which the upper wiring layer is formed by electrolytic plating and the via hole is filled, after the base electroless plating, before the plating resist for the upper wiring is provided, an electrolytic filled plating solution is used. A method of manufacturing a multilayer wiring board for plating.

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