JP2009070303A - Program rewriting method in erasing reset vector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a program rewriting method in erasing a reset vector for performing the stable rewriting processing of a normal operation service program from the erasure of the reset vector to writing completion by starting a normal operation service program rewriting program, and to provide a program. <P>SOLUTION: The program rewriting method includes the erasure of the reset vector of a system including a CPU and an electrically erasable nonvolatile memory. When a reset occurs, it is discriminated whether the value of the reset vector mounted on the electrically erasable nonvolatile memory is electrically erased or not. When the reset vector is erased, the program is arranged, which is for rewriting the service program being the program to be performed in the normal operation from an address which is indicated by an erased state reset vector mounted on an in-operation unerasable area. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to rewriting of a program recorded in a memory of a system including a CPU and a memory, and more particularly to a technique of rewriting a program recorded in an electrically erasable nonvolatile memory.

  In a system including a CPU and a flash memory (an electrically erasable nonvolatile memory), the CPU reads a necessary program based on a reset vector recorded in the flash memory before starting the processing, and follows the program. Executed.

There are cases where it is necessary to rewrite the program recorded in the flash memory during the operation of such a system, and the following proposal has been made as a rewriting method.
According to Japanese Patent Laid-Open No. 2004-260, a proposal is made to efficiently modify all or part of an application program including a processing program for disk access and interface control of a disk drive device.

  According to Patent Literature 2, each EPROM is provided with a program area for storing a BOOT program, an operation program, and a spare program, and a switching flag. The microprocessor executes processing according to the program stored in the ROM, and the built-in RAM is provided with an interrupt vector that is referred to for starting the BOOT program and the operation program. The switching circuit exchanges the addresses of the operation program area and the spare program area in response to a switching control signal from the microprocessor based on the switching flag. When the latest program is downloaded, the BOOT program rewrites the interrupt vector for the BOOT program and downloads it to the spare program area and inverts the switching flag. On the other hand, during normal operation, the BOOT program rewrites the interrupt vector for the operation program. There has been a proposal that makes it possible to perform download processing while performing normal processing.

  According to Patent Document 3, the system ROM stores a plurality of bootable flash images and includes a non-programmable boot block, and status information indicating which flash image is selected by the nonvolatile RAM. Is stored. The CPU tests the integrity of the selected image, executes the image if it is complete, and selects another flash image if it is incomplete. It then tests for completeness and executes the image if it is complete. As a result, the incomplete flash image is not executed, and the system can be automatically recovered. Proposals have been made to properly recover from system errors that occur during the boot process.

  However, in Patent Document 1 and Patent Document 2, when the reset vector assigned to a part of the electrically erasable nonvolatile memory is to be rewritten, the reset is performed between the erasing of the reset vector area and the completion of the rewriting. When this occurs, there are problems that the value of the reset vector is indefinite, so that the program rewriting process cannot be performed, and the program runs out of control.

Further, in Patent Document 3, when determining the first program to be operated after a reset occurs, the value of the non-volatile RAM disappears when the power supply to the non-volatile RAM that requires power supply is interrupted, and is activated first after the reset occurs. Since the value of the information (BIOS parameter) for determining the program is not guaranteed, there is a problem that the expected program cannot be started.
International Publication No. 97/38367 Pamphlet JP 2005-332228 A Japanese Patent Laid-Open No. 11-316687

  The present invention has been made in view of the above circumstances, and a reset vector that executes stable normal operation service program rewrite processing from reset vector erase to write completion when the normal operation service program rewrite program is started. An object is to provide a program rewriting method and program at the time of erasure.

  The reset vector value mounted on the electrically erasable non-volatile memory when a reset occurs by the reset vector erasing program rewriting method of the system including the CPU and the electrically erasable non-volatile memory according to the present invention. A program that is executed during normal operation from the address indicated by the reset vector in the erased state installed in an area that cannot be erased during operation when the reset vector is erased. A program for rewriting a service program is arranged.

  Preferably, the program for rewriting the service program executed during normal operation erases the electrically erasable nonvolatile memory block having the reset vector and the service program, and writes the service program. The reset vector may be written.

  By the above method, the normal operation service program rewriting program can be restarted even when a reset occurs between the erasure of the electrically erasable nonvolatile memory including the reset vector and the completion of the reset vector rewriting. .

  Preferably, when the reset vector value is recognized to be other than an electrically erased value when a reset occurs, the first watchdog clear pattern is selected as the watchdog timer clear pattern, and when the reset occurs, When the reset vector value is recognized as an electrically erased value, a second watchdog clear pattern may be selected as the watchdog timer clear pattern.

  Preferably, the rewriting program of the service program performs read confirmation from the address indicated by the reset vector, and when the value of the reset vector is recognized to be other than an electrically erased value, the first watchdog If the watchdog timer is cleared based on the clear pattern and the reset vector value is recognized as an electrically erased value, the watchdog timer may be cleared based on the second watchdog clear pattern. Good.

  Even if the reset vector is erased by the above method, an unexpectedly remaining program operates, and even if you try to clear the watchdog timer using the first watchdog clear pattern, the watchdog timer It is not cleared. That is, the watchdog timer is prevented from erroneously recognizing that the program has been rewritten by repeating overflow.

  Preferably, the reset vector is in an erased state, and when a reset occurs during rewriting of the service program, the service program rewriting program may be activated to rewrite the service program.

  According to the present invention, when the normal operation service program rewriting program is started, it is possible to execute a stable normal operation service program rewriting process from reset vector erasing to writing completion.

(Principle explanation)
When a reset occurs, it is determined whether the value of the reset vector is an electrically erased value.
For example, in an electrically erasable non-volatile memory (such as a flash memory), whether or not the memory contents are electrically erased is determined using the fact that all the values on the memory are “1”. If it is determined that the reset vector value is the erase value when a reset occurs, a reset vector is used instead of the reset vector in the erase state, and the program start address is set in the reset vector in the erase state (in the erase state) The reset vector stores the boundary address of the electrically erasable nonvolatile memory block).

In addition, the reset vector in the erased state is mounted in a non-rewritable area (such as a register or a memory that cannot be erased during operation).
The user places a program (normal operation service program rewriting program) for rewriting a service program, which is a program executed during normal operation, at the start address indicated by the reset vector in the erase state.

  The service program (normal operation service program) periodically monitors to determine whether or not the condition for shifting to rewrite is satisfied, and jumps to the same address as the reset vector value in the erased state when the rewrite condition is satisfied. In addition, a watchdog clear pattern A (first watchdog clear pattern) is used as a clear pattern of the watchdog timer.

  When it is determined that the reset vector value is other than the erase value when a reset occurs, the watchdog clear pattern A is selected as the clear pattern of the watchdog timer.

  The normal operation service program rewrite program is a watchdog clear pattern B as a clear pattern of the watchdog timer that is valid only when the program activation factor is a reset occurrence and it is determined that the reset vector value is an erase value. (Second watchdog clear pattern) is used.

Next, the following processing is performed as the rewriting order of the normal operation service program.
Erasing an electrically erasable nonvolatile memory block including a reset vector. Thereafter, the normal operation service program is deleted. Next, the normal operation service program is written, and the reset vector is written.

  By doing so, the reset vector can be rewritten. In addition, it is possible to prevent program runaway due to an undefined program start address due to an unexpected reset vector (erase value), and falling into a program-like unrecoverable state.

When the normal operation service program rewrite program is restarted, the normal operation service program rewrite process can be executed again.
In addition, since a special circuit and jig for rewriting a program are not required, the rewriting of the program can be performed at most product handling bases, and the cost can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Constitution)
On the on-board substrate 1 shown in FIG. 1, a CPU 2 (such as a microcomputer), a flash memory 3 (an electrically erasable nonvolatile memory), a communication interface 4 and the like are mounted. The on-board substrate 1 is connected to the communication interface connection device 6 via the communication line 5.

The CPU 2 executes a normal operation service program and a normal operation service program rewriting program stored in the flash memory 3.
The flash memory 3 stores a normal operation service program, a normal operation service program rewriting program, and a reset vector. The electrically erasable non-volatile memory may be mounted on the on-board substrate 1 or may be provided in the CPU 2.

  The communication interface 4 connects the on-board substrate 1 and the communication interface connection device 6. When the normal operation service program is rewritten, the CPU 2 controls communication with the communication interface connection device 6 via the communication interface 4, acquires the normal operation service program from the communication interface connection device 6, and rewrites the flash memory 3.

The communication interface connection device 6 transmits the normal operation service program to the on-board substrate 1 via the communication line 5 when rewriting the normal operation service program.
The normal operation service program is a user application program mapped to the flash memory 3.
(Memory map)
FIG. 2 shows an example of a memory map of an electrically erasable nonvolatile memory.

  A normal operation service program is installed in the electrically erasable nonvolatile memory block # 0 to the electrically erasable nonvolatile memory block # 2 (address space 0x00400000 to 0x009FFFFF).

  A normal operation service program rewriting program is mounted in the electrically erasable nonvolatile memory block # 3 to the electrically erasable nonvolatile memory block # 4 (address space 0x00A00000 to 0x00DFFFFF).

The electrically erasable nonvolatile memory block # 5 (address space 0x00E00000 to 0x00FFFFFF) is an area including a reset vector (address space 0x00FFFFFC to 0x00FFFFFF).
In the erase state, the reset vector is used instead of the reset vector when the reset vector value in the electrically erasable nonvolatile memory block # 5 is an erase value when a reset occurs.

  The reset vector in the erase state is mounted in an area such as a non-rewritable register, and the value of the reset vector in the erase state is a value indicating the boundary of the erase unit of the electrically erasable nonvolatile memory. In FIG. 2, the value of the reset vector in the erased state is the leading address (0x00A00000) of the electrically erasable nonvolatile memory block # 3.

  Further, when the electrically erasable nonvolatile memory block # 5 is in an electrically unerased state, the head address (0x00400000) of the electrically erasable nonvolatile memory block # 0 is indicated.

When the electrically erasable nonvolatile memory block # 5 is electrically erased, all values are “1” (0xFFFFFFFF).
(Description of operation from reset generation to program start)
FIG. 3 shows the hardware operation from the occurrence of reset to the start of the program.

  In step S1, when the reset vector read reset occurs, the CPU 2 determines the program start address, so that the reset vector (in the embodiment, the electrically erasable nonvolatile memory block # 5, addresses 0x00FFFFFC to 0x00FFFFFF) is used. After reading, the process proceeds to step S2.

  In step S2, it is determined whether the reset vector value is other than the erase value (0xFFFFFFFF). If the value of the reset vector is other than the erase value, the process proceeds to step S3. If the value of the read reset vector is an erase value, the process proceeds to step S5.

  In step S3, a watchdog clear pattern A (for example, 0x5555) is selected as the watchdog clear pattern. If the reset vector is in an unerased state, the CPU 2 selects the watchdog clear pattern A as the watchdog timer clear pattern, and the process proceeds to step S4.

  In step S4, a reset vector is selected as the program start address. When the reset vector is in an unerased state, the CPU 2 selects a reset vector value (in the embodiment, an electrically erasable nonvolatile memory block # 0 (address 0x00400000)) as a program start address, and proceeds to step S7. Transition.

  In step S5, a watchdog clear pattern B (for example, 0xAAAA) is selected as the watchdog clear pattern. If the reset vector is in the erased state, the CPU 2 selects the watchdog clear pattern B as the watchdog timer clear pattern, and proceeds to step S6.

  In step S6, the reset vector in the erase state is selected as the program start address. If the reset vector is in the erased state, the CPU 2 selects the reset vector value in the erased state (in the embodiment, electrically erasable nonvolatile memory block # 3 (address 0x00400000)) as the program start address, and the step Transition to S7.

In step S7, the program jumps to the start address of the program selected according to the state of the reset vector (erased or not erased).
Here, the watchdog timer clear pattern selects either the watchdog clear pattern A or the watchdog clear pattern B as the watchdog timer clear pattern.

  In addition, if the reset vector is in the erased state, an unexpectedly remaining program operates, and if the watchdog timer can be cleared by the normally used watchdog clear pattern A, it is mistaken that the program has been rewritten. There is a possibility of recognizing. Therefore, a watchdog clear pattern B is newly provided when the reset vector is in the erased state.

If the reset vector is in an erased state, an unexpected program operates, and even if an attempt is made to clear the watchdog timer using the watchdog clear pattern A, the watchdog timer is not actually cleared. In other words, by providing the watchdog clear pattern B, it is possible to prevent the watchdog timer from erroneously recognizing that the program has been rewritten due to repeated overflow.

  In the process of rewriting the normal operation service program using the normal operation service program rewriting program, the reset is performed between the erasure of the electrically erasable nonvolatile memory including the reset vector and the completion of the reset vector rewriting. If it occurs, the reset vector value becomes indefinite and even the normal operation service program rewrite program may not be restarted.

  Therefore, a reset vector is newly provided in the erase state, and when the reset vector is an erase value, the reset vector in the erase state is used as a program start address instead of the reset vector.

In addition, by setting the reset vector value in the erase state as the start address of the normal operation service program rewrite program, the period between the erasure of the electrically erasable nonvolatile memory including the reset vector and the completion of the reset vector rewrite Even if a reset occurs, the normal operation service program rewriting program can be restarted.
(Explanation of normal operation service program rewriting)
4A to 4G are diagrams showing the normal operation service program rewriting flow of the normal operation service program rewriting program.

  The normal operation service program rewrite program is started when either a reset occurs in the reset vector erase state and it starts from the reset vector in the erase state, or when the program rewrite mode condition of the normal operation service program is detected. The

  In FIG. 2, the normal operation service program rewrite program is mounted in the area of electrically erasable nonvolatile memory block # 3 to electrically erasable nonvolatile memory block # 4 (address space 0x00A00000 to 0x00DFFFFF). .

  Initial setting is performed in step S01 of FIG. 4A. When the normal operation service program rewrite program is started, the initial setting is first performed to disable interrupts and set the communication interface.

  Interrupt disable initial setting is the operation of the normal operation service program rewrite program when the interrupt vector value used for the normal operation service program remains in the electrically erasable nonvolatile memory or an interrupt occurs in the erased state. Also, it is performed to prevent the normal operation service program from being rewritten correctly.

The communication interface initial setting is performed so that the normal operation service program can be received from the communication interface connection device 6 via the communication interface 4 and the communication line 5.
In step S02, the reset vector is read. That is, a reset vector value (addresses 0xFFFFFFFC to 0xFFFFFFFF) necessary for rewriting the normal operation service program is read.

  In step S03, the reset information register is read. Reads the reset information register necessary for analyzing the activation factor of the normal operation service program rewriting program. The reset information register includes information on whether or not a reset has occurred and information on the cause of the reset.

In step S04, it is determined whether the reset vector value is an erasure value and the cause of reset of the reset information register is due to reset.
Based on the read reset vector value and the reset information register value, it is analyzed how the normal operation service program rewriting program is started, and a clear pattern of the watchdog timer is derived.

If the reset vector value is an erasure value and the generation factor of the reset information register value is activated by reset, the process proceeds to step S05.
If the reset vector value is other than the erase value, or if the cause of generation of the reset information register value is other than activation by reset, the process proceeds to step S06.

In step S05, a watchdog clear pattern B is set as a watchdog clear pattern variable as a watchdog clear pattern.
In step S06, the watchdog clear pattern A is set as the watchdog clear pattern in the watchdog clear pattern variable.

Set the watchdog timer clear pattern to the watchdog clear pattern variable as described above.
In step S07 shown in FIG. 4B, invalid setting of variable information used by the normal operation service program rewriting program is performed.

The variable information to be invalidated is a reset vector write information message reception flag and a final data message reception flag.
The reset vector write information message reception flag sets no reception of reset vector write information from the communication interface connection device 6 (non-reception state).

The final data message reception flag sets the reception of the final message of the nonvolatile memory write information that can be electrically deleted from the communication interface connection device 6 (not received).
In step S08, the CPU 2 (implementing the normal operation service program rewriting program) controls the communication interface 4 and transmits a communication interface connection establishment request message to the communication interface connection device 6 via the communication line 5.

  In step S09, the CPU 2 waits for a communication interface connection establishment response message from the communication interface connection device 6. For example, in a waiting state of a communication interface connection establishment response message, it waits by loop processing.

In step S10, the watchdog timer is cleared using the watchdog clear pattern variable.
In step S11, it is determined whether or not the communication interface connection establishment response message transmitted from the communication interface connection device 6 is received.

  When the communication interface connection establishment response message is received by the normal operation service program rewriting program, the process proceeds to step S14 in FIG. 4C. If a communication interface connection establishment response message has not been received, the process proceeds to step S12.

In step S12, the communication interface connection establishment response message from the communication interface connection device 6 is determined for timeout of reception waiting time.
In the case of time-out (reception expiration), the process proceeds to step S08, and a communication interface connection establishment request message is transmitted again in step S08.

If it is not time-out (other than reception expiration), the process proceeds to step S09.
In step S13, when the communication interface connection device 6 receives the communication interface connection establishment request message transmitted in step S08 of the normal operation service program rewriting program, it generates a communication interface connection establishment response message and sends it to the CPU 2 via the communication line 5. Send to. Thereby, the connection between the CPU 2 and the communication interface connection device 6 is established.

  In step S14 of FIG. 4C, the erasing process of the electrically erasable memory block # 5 (address space 0x00E00000 to 0x00FFFFFF) including the reset vector area is started, and the process proceeds to step S15.

  The reason why the electrically erasable memory block # 5 is electrically erased first is that the reset vector is erased first, so that even if a reset occurs thereafter, the normal operation service program is rewritten by the reset vector in the erased state. This is so that the program can be restarted.

  In step S15, an electrically erasable non-volatile memory erasure completion waiting loop process is performed, the watchdog clear pattern variable is used to clear the watchdog timer, and the process proceeds to step S16.

In step S16, completion of erasure of the electrically erasable nonvolatile memory is monitored.
If the erasure is not completed, the process proceeds to step S15. If erasure is complete, the process proceeds to step S17.

  In step S17, erasure of the electrically erasable memory blocks # 0 to # 2 (address space 0x00400000 to 0x009FFFFF) serving as the normal operation service program storage area is activated, and the process proceeds to step S18.

  In step S18, an electrically erasable non-volatile memory erasure completion waiting loop process is performed. Therefore, the watchdog clear pattern variable is used to clear the watchdog timer, and the process proceeds to step S19.

In step S19, completion of erasure of the electrically erasable nonvolatile memory is monitored.
If the erasure is not completed, the process proceeds to step S18. If erasure is complete, the process proceeds to step S20 in FIG. 4D.

  In step S20 in FIG. 4D, the communication interface 4 is controlled, and a normal operation service program write information transfer request message is transmitted to the communication interface connection apparatus 6 via the communication line 5.

  In step S21, a response waiting state for the normal operation service program write information from the communication interface connection device 6 is awaited. In a response waiting state of the normal operation service program write information transfer response message, a loop process is performed and the process proceeds to step S22.

In step S22, the watchdog clear pattern variable is used to clear the watchdog timer, and the process proceeds to step S23.
In step S23, it is determined whether a normal operation service program write information transfer response message from the communication interface connection device 6 has been received. When the response message transmitted in step S25 is received, the process proceeds to step S26 in FIG. 4E. If not received, the process proceeds to step S24.

In step S24, the expiration date of reception from the communication interface connection device 6 is determined.
If the reception period of the normal operation service program write information transfer response has expired, the process proceeds to step S07 in FIG. 4B.

When the normal operation service program write information transfer response is not expired, the process proceeds to step S21.
In step S25, when the communication interface connection device 6 receives the request message transmitted by the normal operation service program write information transfer request message transmission process in step S20 of the normal operation service program rewriting program, in step S25, the normal operation service program Generate a write information transfer response message and send a message.

The normal operation service program write information transfer response message has a write address, program data, data length, and final data determination information.
The write address is write address information of an electrically erasable nonvolatile memory.

The program data is normal operation service program main body data written to an electrically erasable nonvolatile memory.
The data length is information on the length of data written to the electrically erasable nonvolatile memory.

The final data determination information is final message determination information of a normal operation service program write information transfer response message.
In step S26 of FIG. 4E, the content validity check of the response message transmitted by the normal operation service program write information transfer response message transmission process of step S25 is performed (whether the write address information is outside the electrically erasable memory block area). Such).

In step S27, it is determined whether there is an abnormality in the normal operation service program write information transfer response message.
When there is an abnormality in the response message transmitted by the normal operation service program write information transfer response message transmission process in step S25, the process proceeds to step S07 in FIG. 4B.

When there is no abnormality in the response message transmitted by the process of step S25, the process proceeds to step S28.
In step S28, it is determined whether the received telegram final data determination information is final data.

If the received message is final data information, the process proceeds to step S29. If the received message is other than the final data information, the process proceeds to step S31.
In step S29, when the final data message reception flag information is invalid, the process proceeds to step S30. When the final data message reception flag information is valid (multiple final data message reception), the process proceeds to step S07 in FIG. 4B.

In step S30, it is determined that the final data message normal reception is normal, and the final data message normal reception lag information is enabled.
In step S31, it is determined whether the normal operation service program write information transfer response message is reset vector write information.

If the received message is reset vector write information, the process proceeds to step S32. If the received message is other than reset vector write information, the process proceeds to step S34 in FIG. 4F.
In step S32, when the reset vector write information message reception flag is invalid, the process proceeds to step S33.

When the reset vector write information message reception flag information is valid (multiple reset vector write message is received), the process proceeds to step S07 in FIG. 4B.
In step S33, the reset vector write information message reception flag is set valid, and the reset vector write information is saved.

  It is determined that the final data message is normally received, the reset vector write information message reception flag is set to be valid, the reset vector write information in the message is saved, and the process proceeds to step S34 in FIG. 4F.

  In step S34, when the final data message reception flag is valid and the reset vector write information message reception flag is invalid, the final data message is received but the reset vector write information message is not received. The process proceeds to step S07 in 4B.

If the final data message reception flag is other than valid setting or the reset vector write information message reception flag is other than invalid setting, the process proceeds to step S35.
In step S35, if the final data message reception flag is invalid and the reset vector write information message reception flag is valid, the process proceeds to step S36.

If the final data message reception flag is not set to invalid or the reset vector write information message reception flag is not set to valid, the process proceeds to step S37.
In step S36, when the received message is reset vector write, the process proceeds to step S20 in FIG. 4D, which is the next message reception process, in order to rewrite the reset vector area last.

If the received telegram is other than reset vector writing, the process proceeds to step S39 in FIG. 4G for electrically erasable nonvolatile memory writing.
In step S37, when the final data message reception flag is set to valid and the reset vector write information message reception flag is set to valid, the process proceeds to step S38.

If the final data message reception flag is not valid setting or the reset vector write information message reception flag is other than valid setting, the process proceeds to step S39 in FIG. 4G.
In step S38, if the received telegram is a reset vector write, the final rewrite condition of the reset vector area is satisfied, so the write reset processing of the saved reset vector write data in step S43 in FIG. 4G to the electrically erasable memory Transition to.

If the received telegram is other than reset vector writing, the process proceeds to step S39 in FIG. 4G for electrically erasable nonvolatile memory writing.
In step S39, the message data (normal operation service program main body) is written in the electrically erasable nonvolatile memory.

  In step S40, the process is a loop process for waiting for completion of writing to the electrically erasable nonvolatile memory, so the watchdog timer is cleared using the watchdog clear pattern variable.

In step S41, completion of writing to the electrically erasable nonvolatile memory is monitored.
If writing has not been completed, the process proceeds to step S40. If the writing is completed, the process proceeds to step S42.

In step S42, if the final data message reception flag is set valid and the reset vector write information message reception flag is set valid, it is determined that the final rewrite condition of the reset vector area is satisfied, and the process proceeds to step S43. If the final data message reception flag is not valid, or if the reset vector write information message reception flag is not valid, it is determined that the final rewrite condition in the reset vector area is not satisfied, and the process proceeds to step S20 in FIG. Transition.

In step S43, when the reset vector rewrite condition is satisfied, the saved reset vector write data is written, and the process proceeds to step S44.
In step S44, the write completion wait process for the electrically erasable non-volatile memory is performed. Therefore, the watchdog clear pattern variable is used to clear the watchdog timer, and the process proceeds to step S45. The operation service program rewriting program monitors the completion of writing to the electrically erasable nonvolatile memory.

If writing has not been completed, the process proceeds to step S44. If the writing is completed, the process proceeds to step S46.
In step S46, since all message data writing has been completed, an all-write end message is transmitted to the communication interface connection device 6, and the process proceeds to step S47.

  In step S47, autonomous reset activation is performed on the on-board board 1 storing its own program, the normal operation service program for which writing has been completed is started from the reset vector, and the process is terminated.

Note that the control processing shown in the flow of the above embodiment can be realized by causing a computer to execute a program in which an instruction for performing the control processing is described.
If this program is stored in a storage medium such as a CD-ROM, control processing can be realized by installing the program in a computer (a programmable arithmetic processing device such as a CPU, FPGA, or CPLD). . Further, this program may be downloaded to a computer via a communication network.

  The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

It is a figure which shows the hardware constitutions which operate | move in the Example in this invention. It is a figure which shows the example of the memory map of the non-volatile memory which can be erased electrically. It is a flowchart which shows the hardware operation | movement from reset generation to a program start. It is a flowchart which shows normal operation service program rewriting program operation | movement of the Example in this invention. It is a flowchart which shows normal operation service program rewriting program operation | movement of the Example in this invention. It is a flowchart which shows normal operation service program rewriting program operation | movement of the Example in this invention. It is a flowchart which shows normal operation service program rewriting program operation | movement of the Example in this invention. It is a flowchart which shows normal operation service program rewriting program operation | movement of the Example in this invention. It is a flowchart which shows normal operation service program rewriting program operation | movement of the Example in this invention. It is a flowchart which shows normal operation service program rewriting program operation | movement of the Example in this invention.

Explanation of symbols

1 On-board board 2 CPU
3 Flash memory 4 Communication interface 5 Communication line 6 Communication interface connection device

Claims (5)

A program rewriting method including reset vector erasing of a system including a CPU and an electrically erasable nonvolatile memory,
When a reset occurs, determine whether the value of the reset vector mounted in the electrically erasable nonvolatile memory is electrically erased,
When the reset vector is erased, a program for rewriting a service program, which is a program executed during normal operation, is arranged from the address indicated by the reset vector in the erased state implemented in an area that cannot be erased during operation.
A method of rewriting a program when erasing a reset vector. A program for rewriting the service program executed during normal operation is:
Erasing the electrically erasable nonvolatile memory block having the reset vector and the service program;
2. The reset vector erasing program rewriting method according to claim 1, wherein the reset vector is written after the service program is written. When a reset occurs, if the reset vector value is recognized to be other than an electrically erased value, the first watchdog clear pattern is selected as the watchdog timer clear pattern,
3. The second watchdog clear pattern is selected as a watchdog timer clear pattern when the reset vector value is recognized as an electrically erased value when a reset occurs. Program rewrite method at the time of reset vector erase described. The service program rewrite program is:
Performing read confirmation of the reset vector value, and if the reset vector value is recognized to be other than an electrically erased value, clear the watchdog timer based on the first watchdog clear pattern,
If the reset vector value is recognized as an electrically erased value, the watchdog timer is cleared based on the second watchdog clear pattern;
The method of rewriting a program at the time of reset vector erasing according to claim 3.   2. The service program rewrite according to claim 1, wherein when the reset vector is in an erased state and a reset occurs during rewriting of the service program, the service program rewrite program can be activated and the service program is rewritten. To rewrite the program when the reset vector is erased.

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