JP2009069922A - Coverage measurement method, computer-readable recording medium and data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To contribute to reduction of a development period of a semiconductor integrated circuit by reducing a coverage measurement time. <P>SOLUTION: In this coverage measurement method, a coverage is calculated about a test pattern by use of a high level abstraction model source code 1 of a circuit module using a high-abstraction-degree model having a definition of an input signal of a logic circuit and a definition of arithmetic operation to the input signal to the logic circuit described by a hardware description language of an RTL (register transfer level), and having a description form wherein a timing definition by a clock signal is omitted (S5). The high level abstraction model source code simplified as compared to the description by the RTL can be created without waiting for completion of actual logic of the RTL, in other words, in parallel with creation of the actual logic of the RTL. By using the high level abstraction model source code early created, the coverage is measured without waiting for the completion of the actual logic of the RTL. A simulation processing time using the high level abstraction model source code is shorter than a simulation time using the actual logic of the RTL. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for measuring the coverage of a test pattern used in logic simulation.

  In the design of a semiconductor integrated circuit, for example, a logic integrated circuit such as a microcomputer, it is desirable that all functions of the verification target logic are executed when the function verification test pattern is executed. In order to confirm the completeness of the functions to be executed, conventionally, a coverage indicating which function or which description is executed by what percentage of the whole has been used as an index. For example, it is measured how much the test pattern used in the logic simulation covers RTL (register transfer level) source code of the circuit to be verified.

  In Patent Document 1, two types of properties are input to the simulator: a property that expresses a test pattern necessary and sufficient for functional verification ascertained by the designer, and a test pattern created by the verifier. Describes how to check whether it meets the requirements.

  However, in this technique, it is essential to input properties without omission, and it is also necessary to verify the validity of the properties. Therefore, even if this coverage measurement method is adopted, it cannot contribute to shortening the development period from the creation of the RTL source code to the completion of the creation of the test pattern.

JP 2004-70457 A

  According to the study by the present inventor, since the conventional coverage measurement method as well as the technique of the above-mentioned Patent Document 1 is based on the premise that a logic simulation is performed using a real logic based on RTL as a verification target model, It was clarified that it would not be possible to start creating test patterns without waiting for completion, and that it would take time to perform logic simulation for coverage acquisition. As described above, since simulation based on real logic is assumed, it takes time to obtain coverage during large-scale development, which causes a problem that the development period of the semiconductor integrated circuit is prolonged.

  An object of the present invention is to reduce the coverage measurement time and contribute to shortening the development period of a semiconductor integrated circuit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the coverage measurement method has a description form in which a logic circuit described in the RTL hardware description language has a definition of an input signal and a calculation operation for the input signal, and a timing definition by a clock signal is omitted. The coverage for the test pattern is calculated using the high abstraction model source code of the circuit module using the high abstraction model having

  Accordingly, without waiting for the completion of the RTL real logic, in other words, in parallel with the creation of the RTL real logic, it is possible to create a high abstraction model source code that is simpler than the description in the RTL. It becomes possible to proceed with the creation and verification of the test pattern in parallel with the creation of the RTL real logic. By using a high abstraction model source code that can be created quickly, coverage can be measured without waiting for completion of the real logic of the RTL. Moreover, the simulation processing time using the high abstraction model source code is shorter than the simulation time using the real logic of RTL.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the coverage measurement time can be shortened, which can contribute to shortening the development period of the semiconductor integrated circuit.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings that are referred to with parentheses in the outline description of the representative embodiment merely exemplify what is included in the concept of the component to which the reference numeral is attached.

  [1] A coverage measurement method has a definition of an input signal for a logic circuit described in an RTL hardware description language (HDL) and a definition of an arithmetic operation for the input signal, and uses a clock signal. The high abstraction model source code of the circuit module using the high abstraction model having the description form in which the timing definition is omitted is input to the compiling computer device, and the monitor information for coverage measurement is input to the input high abstraction model source code. To generate an executable file. A test pattern is input to a simulation computer device to execute the execution file, and coverage information is accumulated sequentially during execution. Based on the accumulated coverage information, the coverage for the test pattern is calculated by the coverage generation computer device. As described above, it is possible to proceed with the creation and verification of test patterns in parallel with the creation of the real logic of RTL, and the coverage measurement time can be shortened, thereby shortening the development period of the semiconductor integrated circuit. Can contribute.

  [2] A coverage measurement method according to another aspect executes a first process to a fourth process using a computer device. The first process has a description form in which a logic circuit described in the RTL hardware description language has a definition of an input signal and a calculation operation for the input signal, and a timing definition by a clock signal is omitted. A high abstraction model source code of a circuit module using the high abstraction model is generated. The second process inputs the generated high abstraction model source code, inserts monitor information for coverage measurement into the input high abstraction model source code, and generates an execution file. In the third process, a test pattern is input to execute the execution file, and coverage information is sequentially accumulated during the execution. The fourth process calculates the coverage for the test pattern based on the accumulated coverage information.

  [3] In the coverage measurement method according to item 2, the high abstraction model source code is described in C language.

  [4] The computer-readable recording medium includes a compiler, a simulator, and a coverage measurement tool that can be read and executed by the computer device. The compiler has a description form in which a logic circuit described in an RTL hardware description language has a definition of an input signal and a definition of an arithmetic operation for the input signal, and a timing form by which a timing definition by a clock signal is omitted. A high abstraction model source code of a circuit module using an abstraction model is input, and monitor information for coverage measurement is inserted into the input high abstraction model source code to generate an executable file. The simulator performs control to input a test pattern, execute the execution file, and sequentially accumulate coverage information during execution. The coverage measurement tool performs control to calculate coverage for a test pattern based on the accumulated coverage information. When the computer device reads and executes the compiler, simulator, and coverage measurement tool from the recording medium, the coverage measurement method can be easily performed.

  [5] The data processing system includes computer apparatuses that execute the first to fourth processes. The first processing has a description form in which a logic circuit described in the RTL hardware description language has a definition of an input signal and a calculation operation for the input signal, and a timing definition by a clock signal is omitted. A high abstraction model source code of a circuit module using the high abstraction model is generated. The second process inputs the generated high abstraction model source code, inserts monitor information for coverage measurement into the input high abstraction model source code, and generates an execution file. In the third process, a test pattern is input to execute the execution file, and coverage information is sequentially accumulated during the execution. In the fourth process, the coverage for the test pattern is calculated based on the accumulated coverage information. By using this data processing system, the coverage measuring method can be easily performed.

2. Details of Embodiments Embodiments will be further described in detail.

  FIG. 1 illustrates a processing flow of the coverage measurement method. Coverage is an index of reliability evaluation for test patterns. The coverage measurement method shown in FIG. 1 provides a method for measuring coverage in a test pattern for functional verification of a semiconductor integrated circuit logically designed using an RTL hardware description language. In particular, coverage can be measured before the logical design using the RTL hardware description language is completed. Hereinafter, the method will be described in detail.

  The coverage measurement method shown in FIG. 1 includes high abstraction model source code generation processing (first processing) S1, compilation processing (second processing) S2, high abstraction level simulation processing (third processing) S3, and coverage generation. Processing (fourth processing) is roughly divided into S4.

  The high abstraction model source code generation process S1 has a definition of an input signal and a calculation operation for the input signal for a logic circuit described in the RTL hardware description language, and a timing definition by a clock signal. A high abstraction model source code 1 of a circuit module using the high abstraction model having the omitted description form is generated. For example, FIG. 2 illustrates a description of an adder circuit in the RTL hardware description language. The contents of this description are represented by a logic circuit as shown in FIG. In this description, every time the clock signal CLK changes, the input signals A and B are taken and substituted into the signals A ′ and B ′ (value propagation). Next, A ′ + B ′ is calculated and substituted for the output signal C. When simulating the operation of the RTL, a process for detecting a change in the clock signal CLK, a process for notifying the adder of an input signal when there is a change in the clock signal CLK, an arithmetic process for the adder, and an output of the adder are signaled. A total of four processes, that is, the process of substituting for C are required. In addition, it is necessary to save the signal value in the middle for waveform display. Assuming that the clock signal CLK is 400 MHz, the four processes must be executed 400 million times in order to simulate the operation of the adder for 1 second. Considering the actual product, the addition is not always necessary. For example, during the period in which subtraction processing other than addition is performed, processing of the adder is unnecessary. However, since the clock signal CLK changes, the operation of the adder is simulated every time. In addition to the adder, since there is a description that operates in synchronization with the clock signal, the amount of processing further increases.

  In the measurement of coverage, a simulation using a circuit description based on the RTL level is not performed. A high abstraction model is used instead of the RTL model. FIG. 4 illustrates a description of a high abstraction model corresponding to the adder circuit of FIG. In this description, inputs A and B are added and output. Detection of the clock signal CLK, propagation of signals from A and B to A 'and B', and storage of signals for waveform display, which are necessary in the RTL, are not performed. Further, when the operation of the adder is unnecessary, it is not simulated. Therefore, it is possible to confirm a functional part such as the calculation result of A + B. The high abstraction model cannot be used to confirm / verify information omitted in the high abstraction model.

  In the compile process S2, the generated high abstraction model source code 1 is input, and monitor information for coverage measurement is inserted into the input high abstraction model source code to generate an execution file (high abstraction simulator) 2. To do.

  In the high abstraction level simulation process S3, the test pattern 3 is input to execute the high abstraction level simulator 2, and coverage information 4 is sequentially accumulated during the execution. The coverage information is, for example, monitor information corresponding to the function name of the executed high abstraction model, and is accumulated in time series. In the high abstraction level simulation processing, the execution result 6 is accumulated at each time of the simulation time wheel, and the diversion to other evaluations is taken into consideration.

  The coverage generation process is a process for calculating coverage 5 for the test pattern based on the accumulated coverage information.

  FIG. 5 shows the difference between the logic simulation using the RTL description and the simulation process (S3) using the description based on the high abstraction model. When the coverage of a test pattern (verification pattern) is confirmed by a logic simulation using RTL description, the execution time per time is long. It is possible to acquire test pattern coverage at high speed by performing simulation using a high abstraction model, which is a high abstraction hardware model developed for pre-examination at the architecture level and software development. . As described above, since the high abstraction model does not simulate individual signal lines and unnecessary logic, it can be executed at high speed. In short, a high abstraction model different from the real logic is used to check the coverage of the real logic.

  FIG. 6 shows a schematic flow of design and development of a semiconductor integrated circuit. (A) is a processing flow in the case of generating a coverage by performing a logic simulation using real ethics that is a logic design result by RTL. It is necessary to wait for the RTL design, which is real logic, to be able to measure the coverage in the period P1 for the development and verification of the test pattern. In the case of (B) according to the processing flow of FIG. 1, without waiting for completion of the real logic of the RTL, in other words, in parallel with the creation of the real logic of the RTL, a simplified process higher than the description by the RTL. Abstraction model source code can be created. By using the high abstraction model source code that can be created early, coverage can be measured during the test pattern development and verification period P2 without waiting for completion of the real logic of the RTL. That is, it is possible to proceed with the creation and verification of the test pattern in parallel with the creation of the RTL real logic. Furthermore, the simulation processing time using the high abstraction model source code is shorter than the simulation time using the real logic of RTL. Therefore, the test pattern development and verification period P3 after completion of the RTL design can be shorter than the period P2. This is because the development of test patterns has already progressed to the point where coverage is already acquired in P2. In any case of P1, P2 and P3, the test pattern to be finally formed is the same.

  Since the simulation using the high abstraction model can be performed at high speed, coverage acquisition can be accelerated. Even in the flow using the high abstraction model, the processing of RTL description and verification is necessary as in the case of (B), but the test pattern development period can be shortened by speeding up the coverage acquisition, resulting in the development period of the semiconductor integrated circuit. Can be shortened from T1 to T2.

  In order to realize the method of FIG. 1, a computer apparatus (not shown) such as an engineering workstation may be used. The computer device executes a high abstraction model source code generation processing program and performs control for the high abstraction model source code generation processing S1. Further, the computer device executes a compile processing program and performs control for the compile processing S2. Further, the computer device executes a high abstraction level simulation processing program and performs control for the high abstraction level simulation processing S3. Further, the computer device executes a coverage generation processing program and performs control for the coverage generation processing S4.

  The high abstraction model source code generation processing program, compile processing program, high abstraction simulation processing program, and coverage generation processing program executed by the computer device can be read by a computer such as a CD-ROM, a DVD-ROM, or a nonvolatile memory card. Recorded on a simple recording medium.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the high abstraction model source code is not limited to a description using C language such as C ++. Languages such as Unix g ++ can also be used. The computer device that executes the high abstraction model source code generation processing program, the compilation processing program, the high abstraction simulation processing program, and the coverage generation processing program may be single or plural.

It is a flowchart which illustrates the process by a coverage measuring method. It is explanatory drawing which illustrates description of the addition circuit by the hardware description language of RTL by HDL. It is explanatory drawing which showed the description content of FIG. 2 with the logic circuit. FIG. 3 is an explanatory diagram illustrating a description of a high abstraction model corresponding to the adder circuit of FIG. 2. It is explanatory drawing which shows the difference between the logic simulation using the description of RTL, and the simulation process (S3) using the description by a high abstraction model. It is a time chart which shows the general | schematic flow of the design development of a semiconductor integrated circuit when the logic simulation by RTL is employ | adopted for acquisition of a coverage, and the design development of a semiconductor integrated circuit when a high abstraction simulation is employ | adopted.

Explanation of symbols

S1 High abstraction model source code generation process (first process)
S2 Compilation process (second process)
S3 High abstraction level simulation process (third process)
S4 Coverage generation processing (fourth processing)
1 High abstraction model source code 2 Executable file (high abstraction simulator)
3 Test pattern 4 Coverage information 5 Coverage 6 Execution result

Claims (5)

A high abstraction model having a description form in which a definition of an input signal and a calculation operation for the input signal are defined for a logic circuit described by a hardware description language of RTL, and a timing definition by a clock signal is omitted. The high abstraction model source code of the used circuit module is input to the compiling computer device, monitor information for coverage measurement is inserted into the input high abstraction model source code, and an execution file is generated.
Execute the execution file by inputting a test pattern into the simulation computer device, and accumulate coverage information sequentially during execution,
A coverage measurement method for calculating coverage for a test pattern by a coverage generation computer device based on the accumulated coverage information. A high abstraction model having a description form in which a definition of an input signal and a calculation operation for the input signal are defined for a logic circuit described by a hardware description language of RTL, and a timing definition by a clock signal is omitted. A first process for generating a high abstraction model source code of the used circuit module;
A second process of inputting the generated high abstraction model source code, inserting monitor information for coverage measurement into the input high abstraction model source code, and generating an execution file;
A third process for inputting a test pattern, executing the executable file, and accumulating coverage information sequentially during execution;
A coverage measurement method for executing a fourth process for calculating a coverage for a test pattern based on the accumulated coverage information using a computer device.   The coverage measurement method according to claim 2, wherein the high abstraction model source code is described in C language. Having a compiler, a simulator and a coverage measurement tool which can be read and executed by a computer device,
The compiler has a description form in which a logic circuit described in an RTL hardware description language has a definition of an input signal and a definition of an arithmetic operation for the input signal, and a timing form by which a timing definition by a clock signal is omitted. Input the high abstraction model source code of the circuit module using the abstraction model, insert the monitor information for coverage measurement into the input high abstraction model source code, and control to generate the executable file,
The simulator executes a test pattern input and executes the execution file, and performs control to sequentially accumulate coverage information during execution,
The said coverage measurement tool is a computer-readable recording medium which performs control which calculates the coverage about a test pattern based on the accumulated coverage information. A high abstraction model having a description form in which a definition of an input signal and a calculation operation for the input signal are defined for a logic circuit described by a hardware description language of RTL, and a timing definition by a clock signal is omitted. A first process for generating a high abstraction model source code of the used circuit module;
A second process of inputting the generated high abstraction model source code, inserting monitor information for coverage measurement into the input high abstraction model source code, and generating an execution file;
A third process for inputting a test pattern, executing the executable file, and accumulating coverage information sequentially during execution;
A data processing system having a computer device for executing a fourth process for calculating a coverage for a test pattern based on the accumulated coverage information.

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