JP2017146774A - Processing apparatus, logic simulator and design verification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of operation mismatching between a logic simulation result and an actual machine evaluation result by enabling the adjustment of a delta delay amount to be automatically performed.SOLUTION: A processing apparatus 1 comprises a processing section 10 for performing logic verification while defining an integrated circuit as a processing object, the integrated circuit being configured to be operated by multiple clock signals in the same cycle and in a synchronous relationship. The processing section 10 selects a clock signal with a maximum delta delay amount as a base clock signal from among the multiple clock signals. The processing section 10 then adjusts the other clock signals than the base clock signal in such a manner that delta delay amounts of the other clock signals than the base clock signal among the multiple clock signals are matched to the delta delay amount of the base clock signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a processing device, a logic simulator, and a design verification method.

  As one of logic simulator methods for simulating the operation of a verification model of an integrated circuit described in a hardware description language such as VHDL (VHSIC Hardware Description Language) or Verilog-HDL, there is an event driven method. In the event-driven method, a process that is a model of a minimum unit of parallel operation and an event that occurs by execution of the process are managed, and a process associated with the event is activated when each event occurs. VHSIC is an abbreviation for Very High Speed Intergrated Circuit. Examples of the integrated circuit include an LSI (Large Scale Integration) and an FPGA (Field Programmable Gate Array) mounted on the optical transmission apparatus.

  Here, for example, when there are a plurality of processes activated by an event at the same time, and a variable that is updated with a delay of 0 in one process and the other process wants to refer to the value before the update, an event-driven logic simulator In this processing method, a signal substitution process with a delta delay is used. In this case, by making the update process of the variable a signal substitution process with a delta delay, it is possible to always refer to the value before update in the other process within the same delta cycle. As an example to which signal substitution with delta delay is applied, there is a flip-flop (FF) or the like in register transfer level modeling in which no delay is added to an element. Further, specific examples of the signal substitution process with delta delay include non-blocking substitution with no delay designation in Verilog-HDL, write to a primitive channel such as sc_signal in SystemC, and the like.

  As described above, in the logic simulation of the verification model on the computer, there is a delta delay which is an infinitesimal delay (virtual delay on the logic simulation) in order to realize hardware parallel processing. The delay amount of the delta delay is handled as the number of executions of the signal substitution process in the logic simulation, and the delta delay is not an actual delay. “Delta delay” may be described as “δ delay”. In addition, the “delta delay amount” may be described as “delta delay amount” or “δ delay amount”.

JP 2006-11961 A JP 2006-127449 A

  In logic design, design work taking into account δ delay (measurement of δ delay amount and delay adjustment of each circuit) is performed by a designer's manual operation. For this reason, in the logic design, if the designer does not take into account the amount of δ delay (number of executions of signal substitution), between the logic simulation result and the actual hardware evaluation result (actual machine evaluation result; hardware simulation result). It may cause an operation mismatch. In other words, an erroneous operation when the designer manually adjusts the δ delay amount may cause an event (problem) that the logic simulation operates normally but does not operate normally on the actual machine.

  In one aspect, an object of the present invention is to prevent an operation mismatch between a logic simulation result and an actual machine evaluation result.

  The processing apparatus according to the present embodiment includes a processing unit that performs logic verification on an integrated circuit that operates with a plurality of clock signals that have the same cycle and are in a synchronous relationship. The processing unit selects a clock signal having the largest delta delay amount among the plurality of clock signals as a base clock signal. The processing unit adjusts a delta delay amount of a clock signal other than the base clock signal among the plurality of clock signals so as to match a delta delay amount of the base clock signal.

  It is possible to suppress the occurrence of operation mismatch between the logic simulation result and the actual machine evaluation result.

It is a block diagram which shows an example of the hardware constitutions of the processing apparatus containing the logic simulator which concerns on this embodiment. It is a block diagram which shows the function structure of (delta) delay automatic adjustment tool in the logic simulator shown in FIG. FIG. 3 is a diagram showing a detailed functional configuration of the δ delay automatic adjustment tool shown in FIG. 2. FIG. 4 is a flowchart for explaining an outline of the operation of the δ delay automatic adjustment tool shown in FIGS. 2 and 3. FIG. 4 is a timing chart for explaining the operation of the δ delay automatic adjustment tool shown in FIG. 3. It is a figure which shows an example of the verification result obtained by the (delta) delay verification part in the (delta) delay automatic adjustment tool shown in FIG. It is a block diagram which shows the example of a circuit which produces (delta) delay by signal substitution. It is a figure which shows the VHDL description of the A block and B block in the circuit example shown in FIG. 9 is a timing chart illustrating an example of an operation mismatch state between a logic simulation result and an actual machine evaluation result, which occurs in the circuit examples illustrated in FIGS. 7 and 8. It is a figure which shows the specific example of the simulation malfunction which arises by (delta) delay accompanying signal substitution. It is a flowchart explaining the general circuit design procedure which considered (delta) delay. It is a block diagram which shows the example of a complicated clock system. It is a flowchart explaining the outline | summary of the circuit design procedure at the time of applying this embodiment.

  Hereinafter, embodiments of a processing device, a logic simulator, and a design verification method disclosed in the present application will be described in detail with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude application of various modifications and techniques not explicitly described in the embodiment. That is, the present embodiment can be implemented with various modifications without departing from the spirit of the present embodiment. Each figure is not intended to include only the components shown in the figure, and may include other functions. And each embodiment can be suitably combined in the range which does not contradict a processing content.

[1] Overview of Related Technology and Technology of the Present Application As described above, in logic simulation of a verification model on a computer, a concept called δ delay is introduced in order to realize hardware parallel processing. The δ delay is an infinitely small delay, and the δ delay amount is treated as the number of executions of the signal substitution process. However, since the design work taking into account the δ delay in the logic design is executed by the designer's manual operation, if the δ delay amount is not considered by the designer, there will be an operation mismatch between the logic simulation result and the actual machine evaluation result. May occur.

  Here, an example in which operation mismatch occurs between the logic simulation result and the actual machine evaluation result will be described with reference to FIGS. In the circuit example having the A block and the B block shown in FIG. 7 defined by the VHDL description shown in FIG. 8, the data signal DATA from Logic and the clock signal sr_clkp_half divided by 2 are input to the FF of the A block. The Further, the data signal A_OUT from the FF of the A block and the clock signal CLK_HALF after the signal name conversion of the A block are input to the FF of the B block.

  At this time, in each of the FF of the A block and the signal name conversion at the A block boundary, signal substitution is executed once, and a δ delay amount 1 (described as Δ1 in the figure) is generated. Accordingly, the clock signal CLK_HALF and the data signal A_OUT from the A block are output to the B block with a delay amount Δ1 behind the clock signal sr_clkp_half in the A block. For this reason, the clock signal CLK_HALF and the data signal A_OUT change at the same time, and the operation of the B block becomes unstable. As shown in FIG. Inconsistency of the output value B_OUT) from the FFs may occur.

  A specific example of a simulation malfunction (operation mismatch between the logic simulation result and the actual machine evaluation result) caused by the δ delay accompanying signal substitution will be described with reference to FIG. As shown in FIG. 10, in the rear-stage circuit II, signal substitution is executed in the front-stage circuit I and other parts, so that a digital δ delay is separately added to each signal.

  At this time, the δ delay 2 clock signal s_sel2_CLK and the δ delay 3 data signal s_sel_FP are input to FF # 1 in the circuit II shown in FIG. That is, since the δ delay amount 3 of the data signal is larger than the δ delay amount 2 of the clock signal, the value substitution on the logic simulation is executed at the correct timing.

  On the other hand, the δ delay 2 clock signal s_sel2_CLK and the δ delay 2 data signal s_DT_IN (3: 0) are input to FF # 2 in the circuit II shown in FIG. That is, since the δ delay amount 2 of the clock signal and the δ delay amount 2 of the data signal are the same, the value substitution is not executed in the logic simulation, and a simulation malfunction occurs.

  Next, a general circuit design procedure considering the δ delay will be described with reference to the flowchart (steps S101 to S117) shown in FIG. First, HDL design is performed (step S101), an HDL description that defines a verification model of an integrated circuit to be logically designed is acquired, and circuit design (steps S102 to S107) is executed based on the HDL description.

  In circuit design, it is first determined whether or not parallel design is to be executed (step S102). When parallel design is not to be executed (NO route of step S102), logic design (step S103) is executed before clock design. (Step S104) is executed. When parallel design is executed (YES route in step S102), logic design (step S105) and clock design (step S106) are executed in parallel. When the clock design in step S104 is completed, or when both the logic design in step S105 and the clock design in step S106 are completed, the circuit design is completed (step S107). Here, the circuit design considering the δ delay is executed in the clock design of step S106.

  When the circuit design is completed, a logic simulation (software simulation; steps S108 to S110) is executed. At this time, it is first determined whether or not to execute a logic simulation (step S108). When a logic simulation is executed (YES route of step S108), a logic simulation (step S109) is executed and the logic simulation result is checked. (Step S110).

  When the logic simulation result is OK (YES route in step S110) or when the logic simulation is not executed (NO route in step S108), actual machine evaluation (hardware simulation; steps S111 to S113) is executed. At this time, it is first determined whether or not to execute hardware simulation (step S111). When hardware simulation is executed (YES route in step S111), hardware simulation (step S112) is executed and the hardware is simulated. The simulation result is checked (step S113).

  If the hardware simulation result is OK (YES route in step S113), or if the hardware simulation is not executed (NO route in step S111), the process ends. On the other hand, if the logic simulation result is not OK (NO route of step S110), or if the hardware simulation result is not OK (NO route of step S113), the investigation and correction examination process (step S114 ~) by the manual operation of the designer. S117) is executed.

  In the investigation and correction examination process, first, it is determined whether or not the reason why the logic simulation result or the actual machine evaluation result is not OK is a logic design failure (step S114). If the reason is not a logical design failure, that is, if the reason is a clock design failure (NO route of step S114), it is determined whether or not the clock design failure is a δ delay failure (step S115). If the clock design failure is a δ delay failure (YES route of step S115), a clock correction method for eliminating the δ delay failure is investigated (step S116).

  If there is a clock correction method (YES route in step S117), or if the clock design failure is not a δ delay failure (NO route in step S115), the process is clock design (step S104) or clock design (step S106). Return to. At this time, in step S106, based on the clock correction method investigated in step S116, circuit design is performed in consideration of the δ delay in order to eliminate the delta delay failure.

  On the other hand, when there is no clock correction method (NO route of step S117), or when the reason is logical design failure (YES route of step S114), the process is logical design (step S103) or logical design (step S105). Return to.

  In the general circuit design procedure taking into account the δ delay shown in FIG. 11, the clock signal connection check is the main work for the designer, and the δ delay consideration tends to be secondary. Therefore, when a problem occurs in logic simulation or hardware simulation, the problem part must be investigated, including the determination of whether the problem is a problem of the design itself or due to omission of consideration of δ delay. In addition to the reduction in work efficiency, the man-hour and cost of circuit design increase.

  In particular, as shown in FIG. 12, for example, in recent integrated circuits, a plurality of clock systems are provided in a chip, a multistage selection circuit (selector), a frequency divider (1 / n), and the like are provided. The system is becoming larger and more complex. For this reason, the degree of difficulty in circuit design taking into account the amount of δ delay has increased. Therefore, there is a possibility that an event that the designer makes an error in adjusting the δ delay amount by manual operation and that the logic simulation operates normally but does not operate normally in the actual machine frequently occurs.

  Also, as shown in FIG. 12, the internal circuit of blocks, IP (Intellectual Property core), design assets (macro), etc. that are automatically generated based on a high-level language have a black box or gray box. (Gray Box) is often the case. For this reason, it is difficult to calculate each δ delay amount, and it is necessary to conduct a survey in cooperation with the actual machine evaluation. In addition to a reduction in work efficiency in circuit design, a great amount of man-hours and costs are spent.

  Therefore, in the technique disclosed in the present application, when designing and verifying an integrated circuit (verification model) such as an LSI or FPGA having a plurality of clock signals, the following automatic adjustment function of δ delay (digital δ delay automatic adjustment roots, δ -Adjuster; see FIGS. 1 to 3 and 13).

  In other words, the δ delay automatic adjustment function includes a selection function for selecting a clock signal having the largest δ delay amount as a base clock signal among a plurality of clock signals having the same period and synchronous relationship in the integrated circuit (verification model). It is done. In the selection function, for all combinations of two clock signals among a plurality of clock signals, a δ delay amount difference between the two clock signals is calculated, and based on the δ delay amount difference calculated for all the combinations. A base clock signal is selected.

  The δ delay automatic adjustment function includes an adjustment function for adjusting the δ delay amount of a clock signal other than the base clock signal among the plurality of clock signals so as to match the δ delay amount of the base clock signal.

  Here, the δ delay amount is the number of executions of signal substitution with δ delay (δ delay processing) performed for each of the plurality of clock signals. Further, the plurality of clock signals having the same period and in a synchronous relationship are branched from the same clock source (master clock source described later).

  As described above, in the technique disclosed in the present application, the presence or absence of δ delay between a plurality of clock signals (clock systems) having the same period and synchronous relationship is measured, and the base clock signal having the maximum δ delay amount based on the measurement result. Is selected. Then, the δ delay automatic adjustment is performed so that the δ delay amount in each clock signal other than the base clock signal becomes the maximum δ delay amount. As a result, an optimal δ delay amount is inserted into the verification model of the integrated circuit.

  In other words, the technique disclosed in this application does not calculate the δ delay amount (absolute delay amount) of each clock system, but rather measures and calculates the δ delay amount difference between a plurality of clock systems having the same period and synchronous relationship. In detail, a functional configuration described later with reference to FIGS. 2 and 3 is provided.

  In the general circuit design procedure taking the δ delay shown in FIG. 11 into consideration, when any defect occurs, as described above, the investigation and correction examination process (steps S114 to S117) by the manual operation of the designer is executed. .

  On the other hand, in the technique disclosed in the present application, as shown in FIG. 13, the clock design process executed in step S120 in FIG. 13 corresponding to step S106 in FIG. 11 includes the automatic adjustment function (δ-adjuster) of δ delay. Is embedded). Therefore, in the technique disclosed in the present application, the automatic adjustment of the δ delay is executed together with the clock design process in step S120.

  Here, according to the flowchart (steps S101 to S105, S107 to S113, S120) shown in FIG. 13, an outline of a circuit design procedure when the present embodiment is applied will be briefly described. In steps S101 to S105 and S107 to S113 in FIG. 13, the same processes as steps 101 to S105 and S107 to S113 in FIG.

  In step S106 in FIG. 11, clock design is performed in consideration of the δ delay by a manual operation of the designer. On the other hand, in step S120 of FIG. 13 executed instead of step S106 of FIG. 11, as described above, automatic adjustment of the δ delay is performed together with the clock design process.

  As a result, as a result of the logic simulation or the hardware simulation, the problematic points are limited to the logic circuit, and it is not necessary to conduct an investigation considering the δ delay problem. For this reason, in the technique disclosed in the present application, the processing in steps S114 to S117 shown in FIG. 11 can be omitted. That is, in FIG. 13, when the logic simulation result is not OK (NO route of step S110) or when the hardware simulation result is not OK (NO route of step S113), the process is the logic design process (step S103 or S105). ).

  Therefore, according to the technique disclosed in the present application, it is possible to reduce 90-95% of the man-hour required for the δ delay countermeasure, and it is possible to greatly reduce the cost required for the delay countermeasure. The man-hours required for the δ delay countermeasure include, for example, man-hours spanning circuit design, logic simulation, and hardware simulation (actual machine evaluation).

[2] Hardware configuration of the processing apparatus of the present embodiment First, the hardware configuration of the processing apparatus 1 of the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram illustrating an example of a hardware configuration of a processing apparatus 1 including a logic simulator 11 according to the present embodiment. As shown in FIG. 1, the processing apparatus 1 of the present embodiment realizes a logic simulator 11 that simulates the operation of an integrated circuit (verification model) that is a logic design target. A digital δ delay automatic adjustment tool (δ-adjuster) 110 is included.

  Note that the processing device 1 may include a circuit that adjusts a clock delay (δ delay) in an integrated circuit such as an LSI or FPGA mounted on the optical transmission device, for example. At this time, the circuit may be a circuit that functions as the digital δ delay automatic adjustment tool (δ-adjuster) 110 of the present embodiment. In this case, the processing unit 10 (to be described later) in the processing device 1 performs logic verification on an integrated circuit that operates with a plurality of clock signals having the same period and in a synchronous relationship as an adjustment processing target for clock delay (δ delay). Also good.

  As shown in FIG. 1, the processing device 1 includes a processing unit 10, a storage unit 20, an input unit 30, and a display unit 40. The processing unit 10, the storage unit 20, the input unit 30, and the display unit 40 are configured to be able to communicate with each other via a bus 50.

  The processing unit 10 controls the entire processing apparatus 1. The processing unit 10 may be a single processor or a multiprocessor. The processing unit 10 includes, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), and an FPGA (Field Programmable Gate Array). Any one may be sufficient. Further, the processor 11 may be a combination of two or more types of elements of CPU, MPU, DSP, ASIC, PLD, and FPGA.

  The storage unit 20 stores various data necessary for processing by the processing unit 10. Examples of the various data may include HDL description 21, design result 22, simulation result 23, program 24, and the like. The HDL description 21 is described in HDL, and defines an integrated circuit (verification model) that is a design target (δ delay automatic adjustment target). The design result 22 is a logic design result or a clock design result obtained based on the HDL description 21. The simulation result 23 is information related to the result of the simulation executed based on the design result 22. The program 24 may include an OS (Operating System) program or an application program that is executed by the processing unit 10. The application program may include a program executed by the processing unit 10 in order to realize a function as the logic simulator 11 including the digital δ delay automatic adjustment tool 110. As the storage unit 20, a RAM (Random Access Memory) or a HDD (Hard Disk Drive) may be used, or a semiconductor storage device (SSD: Solid State Drive) such as a flash memory may be used.

  The program 24 to be executed by the processing device 1 (processing unit 10) may be recorded on a non-transitory portable recording medium such as an optical disk, a memory device, or a memory card. The program stored in the portable recording medium becomes executable after being installed in the storage unit 20 under the control of the processing unit 10, for example. The processing unit 10 can also read and execute a program directly from a portable recording medium.

  An optical disc is a portable non-temporary recording medium on which data is recorded so as to be readable by reflection of light. Examples of the optical disk include DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable) / RW (ReWritable), and the like. The memory device is a non-temporary recording medium equipped with a communication function with a device connection interface (not shown), for example, a USB (Universal Serial Bus) memory. The memory card is a card-type non-temporary recording medium that is connected to the processing unit 10 via a memory reader / writer (not shown) and is a target for writing / reading data.

  The input unit 30 is, for example, a keyboard and a mouse, and is operated by the user to give various instructions to the processing unit 10. Note that a touch panel, a tablet, a touch pad, a trackball, or the like may be used instead of the mouse.

  The display unit 40 is, for example, a display device or a liquid crystal display device using a CRT (Cathode Ray Tube), and displays and outputs the above-described HDL description 21, design result 22, and simulation result 23. In addition to the display unit 40, an output unit (not shown) that prints out the HDL description 21, the design result 22, and the simulation result 23 described above may be provided.

  With the processing apparatus 1 having the hardware configuration as described above, a function as a digital δ delay automatic adjustment tool (δ-adjuster) 110 of the present embodiment described later with reference to FIGS. 2 and 3 can be realized. .

[3] Functional Configuration of Processing Apparatus According to this Embodiment Next, a functional configuration of the processing apparatus 1 having the digital δ delay automatic adjustment tool 110 according to this embodiment will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram showing a functional configuration of the digital δ delay automatic adjustment tool 110 in the logic simulator 11 shown in FIG. 1. FIG. 3 is a diagram showing a detailed functional configuration of the digital δ delay automatic adjustment tool 110 shown in FIG. 2.

  As shown in FIG. 2, in the following embodiment, the δ delay is automatically adjusted for three clock systems (clock signals) 3A, 3B, 3C branched from the same master clock source (MCLK) 2. Will be described. The three clock systems 3A, 3B, and C may be expressed as clock systems A, B, and C or clock signals A, B, and C, or MCLK_A, MCLK_B, and MCLK_C, respectively.

  MCLK2 is a main clock source in a circuit that forms a synchronous circuit. Further, MCLK2 is branched into three MCLK_A, MCLK_B, and MCLK_C having different δ delay amounts. The three MCLK_A, MCLK_B, and MCLK_C are aggregated and connected to the digital δ delay automatic adjustment tool 110 of the present embodiment in order to automatically adjust the δ delay according to the present embodiment.

  The branched clock systems A, B, and C supply clock signals A, B, and C to a plurality of modules that perform a synchronous operation, respectively. The clock system A connected to each module is inserted in the middle of the clock systems A, B, and C by inserting logic such as a frequency divider, selector and “H (High)” / “L (Low)”. , B and C have different δ delay amounts. In the present embodiment, as described below, for all combinations of two clock signals among the three clock signals A, B, and C, a δ delay amount difference between the two clock signals is calculated. In the present embodiment, a case where δ delay amounts 8, 12, and 15 are generated in the clock systems A, B, and C, respectively, will be described. However, the values of these δ delay amounts are completely visible to the designer. Shall not.

  In the present embodiment, the processing unit 10 executes a predetermined application program included in the program 24 to thereby function as a digital δ delay automatic adjustment tool 110, that is, a δ delay measurement signal substitution unit 111, a δ delay verification unit. 112, serving as a δ delay insertion determination unit 113 and a δ delay adjustment signal substitution unit 114.

  The δ delay measurement signal substitution unit 111 and the δ delay verification unit 112 calculate a δ delay amount difference between two clock signals for all combinations of two clock signals among the plurality of clock signals A to C. It is an example of a part.

  The δ delay insertion determination unit 113 selects a clock signal having the largest δ delay amount among the plurality of clock signals A to C based on the δ delay amount difference calculated for all the combinations as a base clock signal. It is an example.

  Also, the δ delay insertion determination unit 113 should be inserted to match the δ delay amount of the clock signal other than the base clock signal among the plurality of clock signals with the δ delay amount (maximum δ delay amount) of the base clock signal. It also has a function of calculating a delay amount (δ delay insertion amount). That is, the δ delay insertion determination unit 113 acquires the difference between the maximum δ delay amount and the δ delay amount of each clock signal other than the base clock signal as the δ delay insertion amount.

  The δ delay adjustment signal substitution unit 114 inserts the δ delay insertion amount calculated for each clock signal by the δ delay insertion determination unit 113 into each clock signal. That is, the δ delay adjustment signal substitution unit 114 is an example of an adjustment unit that adjusts the δ delay amount of a clock signal other than the base clock signal to match the δ delay amount (maximum delta delay amount) of the base clock signal. .

  Although the digital δ delay automatic adjustment tool 110 is incorporated on a logic circuit, there is no concept of δ delay in physical design. For this reason, the δ delay is ignored / erased in the physical design and is not reflected or affected by the implementation of the logic circuit.

  Next, with reference to FIG. 3, the functions as the above-described δ delay measurement signal substitution unit 111, δ delay verification unit 112, δ delay insertion determination unit 113, and δ delay adjustment signal substitution unit 114 will be described in more detail. explain.

  The δ delay measurement signal substitution unit 111 includes δ delay addition units 111A, 111B, and 111C. If the comparison results of the comparator 125 described later do not match, the δ delay adders 111A, 111B, and 111C each set the δ delay amount by executing signal substitution once for the clock signals A, B, and C, respectively. Insert and add. When the clock signals A to C are first input from the outside to the δ delay adders 111A to 111C, the δ delay amount insertion processing by the δ delay adders 111A to 111C is not executed (see “Addition” in FIG. 6). (Refer to the section of “δ delay amount 0”).

  The δ delay verification unit 112 verifies the difference in the δ delay amount in the data interface between a plurality of different clock systems A to C having the same period and a synchronous relationship. Therefore, the δ delay verification unit 112 uses six types of data to measure and calculate the δ delay amount difference between the two clock signals for all combinations of the two clock signals among the plurality of clock signals A to C. Interface check units 112AB, 112BA, 112AC, 112CA, 112BC, and 112CB are included.

  The data interface check unit 112AB performs a data interface check from the measurement side clock signal A which is one of the two clock signals A and B to the measurement side clock signal B which is the other of the two clock signals A and B (FIG. 6). A to B). That is, the data interface check unit 112AB measures and calculates a δ delay amount difference of B with respect to A, which indicates how much the measured clock signal B is delayed with respect to the measuring clock signal A.

  Similarly, the data interface check unit 112BA performs a data interface check from the measurement side clock signal B which is one of the two clock signals B and A to the measurement side clock signal A which is the other of the two clock signals B and A. (See B to A in FIG. 6). That is, the data interface check unit 112BA measures and calculates a difference in δ delay amount of A with respect to B, which indicates how much the measured clock signal A is delayed with respect to the measurement side clock signal B.

  The data interface check unit 112AC performs a data interface check from the measurement side clock signal A that is one of the two clock signals A and C to the measurement side clock signal C that is the other of the two clock signals A and C (FIG. 6). A to C). That is, the data interface check unit 112AC measures and calculates the difference in δ delay amount of C with respect to A, which indicates how much the measured clock signal C is delayed with respect to the measuring clock signal A.

  The data interface check unit 112CA performs a data interface check from the measurement-side clock signal C that is one of the two clock signals C and A to the measurement-side clock signal A that is the other of the two clock signals C and A ( (See C to A in FIG. 6). That is, the data interface check unit 112CA measures and calculates a difference in δ delay amount of A with respect to C, which indicates how much the measured clock signal A is delayed with respect to the measuring clock signal C.

  The data interface check unit 112BC performs a data interface check from the measurement side clock signal B which is one of the two clock signals B and C to the measurement side clock signal C which is the other of the two clock signals B and C ( (See B to C in FIG. 6). That is, the data interface check unit 112BC measures and calculates a difference in the δ delay amount of C with respect to B, which indicates how much the measured clock signal C is delayed with respect to the measuring clock signal B.

  The data interface check unit 112CB performs a data interface check from the measurement-side clock signal C that is one of the two clock signals C and B to the measurement-side clock signal B that is the other of the two clock signals C and B ( (See C to B in FIG. 6). That is, the data interface check unit 112CB measures and calculates a δ delay amount difference of B with respect to C, which indicates how much the measured clock signal B is delayed with respect to the measuring clock signal C.

  Each of the data interface check units 112AB, 112BA, 112AC, 112CA, 112BC, and 112CB includes a frequency divider 121, a real time delay adding unit 122, a first FF 123, a second FF 124, a comparator 125, and a third FF 126. Although the detailed configuration of the data interface check unit 112AB will be described here, the other data interface check units 112BA, 112AC, 112CA, 112BC, and 112CB are configured in the same manner as the data interface check unit 112AB.

  The data interface check unit 112AB generates a verification pattern by an internal PPG (frequency divider 121 described later), and prepares two virtual data interfaces of a data path to which a transport delay is added and a through path. Validate path consistency. PPG is an abbreviation for Pulse Pattern Generator. If the two data passing through the two paths do not match, the difference between the δ delay amounts of the two clock systems A and B is the cause of the mismatch, so the δ delay addition of the δ delay amount measurement signal substitution unit 111 is performed. Feedback is performed on the part 111A. Accordingly, signal substitution with δ delay is performed once for the measurement side clock signal A (PPG clock), and the number of signal substitution executions (δ delay amount) is incremented by one. The data interface check unit 112AB repeatedly performs the above processing until the two data passing through the two paths match each other, thereby obtaining a verification result as described later with reference to FIG. 6, for example. Can do.

  The frequency divider (PPG) 121 divides the measurement-side clock signal A by two. The measurement-side clock signal A divided by two by the frequency divider 121 is branched into two as shown by reference numerals (a) and (c) in FIG. In FIG. 3, the path through which the signal (a) passes corresponds to the data path, and the path through which the signal (b) passes corresponds to the through path.

  The real-time delay adding unit 122 inserts an arbitrary real-time delay amount (here, for example, 1 ps (picosecond)) into one of the two branched measurement-side clock signals A, that is, the signal (a) passing through the data path. Give. Here, the reason why the 1 ps real-time delay (transport delay) is inserted is to shift the first FF 123 on the data path without being affected by the δ delay amount of the clock signal B to be measured. Then, the signal (a) given the real time delay by the real time delay giving unit 122 is a signal passing through the through path (see the output (d) of the FF 124) as the correct value (see the output (b) of the FF 123). To be compared.

  The first FF 123 receives the signal (a) generated from the measurement-side clock signal A and provided with a real-time delay of 1 ps as data, and the measurement-side clock signal B as a clock. Along with this, the first FF 123 outputs the signal (a) that has passed through the data path as the correct value (b) at the timing of the measured clock signal B.

  The second FF 124 receives the signal (c) generated from the measurement-side clock signal A and not given a real time delay as data, and the measurement-side clock signal B as a clock. Accordingly, the second FF 124 outputs the signal (c) that has passed through the through path as the signal (d) at the timing of the clock signal B to be measured.

  The comparator 125 receives and compares the output (b) from the first FF 123 and the output (d) from the second FF 124. The comparator 125 outputs, for example, “0” indicating NG when the output (b) and the output (d) do not match, while when the output (b) and the output (d) match, for example, Outputs “1” indicating OK.

  The third FF 126 receives the output from the comparator 125 as data and the measured side clock signal B as a clock. Accordingly, the third FF 126 outputs the comparison result by the comparator 125 to the δ delay measurement signal substitution unit 111 and the δ delay insertion determination unit 113 as the verification result (e) at the timing of the measured clock signal B. .

  Then, the δ delay insertion determination unit 113 refers to the verification result (see FIG. 6) obtained by the δ delay verification unit 112, so that all combinations of two clock signals among the three clock signals A to C are obtained. Δ delay amount difference can be recognized. That is, for each of the six types of combinations, the number of executions of signal substitution with δ delay at the time when the two data (b) and (d) match is the δ delay amount difference between the two clock signals of the combination. Is calculated as In this manner, the difference in the δ delay amount is measured for six combinations of two clock signals among the three clock signals A to C. The δ delay insertion determination unit 113 selects the clock signal having the largest δ delay amount among the three clock signals A to C as the base clock signal based on the six types of δ delay amount differences. Furthermore, as described above, the δ delay insertion determination unit 113 acquires the difference between the maximum δ delay amount and the δ delay amount of each clock signal other than the base clock signal as the δ delay insertion amount.

  The δ delay adjustment signal substitution unit 114 includes δ delay insertion units 114A, 114B, and 114C. The δ delay insertion units 114A, 114B, and 114C insert the δ delay insertion amounts acquired by the δ delay insertion determination unit 113 into the clock signals A, B, and C, respectively. Thereby, the δ delay amount of the clock signal other than the base clock signal is adjusted to match the δ delay amount (maximum delta delay amount) of the base clock signal.

[4] Operation of the processing apparatus of the present embodiment Next, the operation of the processing apparatus 1 of the present embodiment will be described with reference to FIGS.
First, an outline of the operation of the digital δ delay automatic adjustment tool 110 shown in FIGS. 2 and 3 will be described according to the flowchart shown in FIG. 4 (steps S1 to S5).

  In the example shown in FIG. 3, three MCLK_A, MCLK_B, and MCLK_C branched from MCLK2, that is, three clock signals A to C having the same period and synchronous relation are extracted, and the δ delay is automatically adjusted according to this embodiment. Therefore, it is input to the digital δ delay automatic adjustment tool 110 (step S1).

  Thereafter, in the six types of data interface check units 112AB, 112BA, 112AC, 112CA, 112BC, and 112CB, the δ delay amount difference between the two clock signals of the six types of combinations is verified and calculated as the number of executions of signal substitution. (Step S2).

  Here, the δ delay amount difference of the clock signal A with respect to the clock signal B and the δ delay amount difference of the clock signal B with respect to the clock signal A are verified and calculated. Further, a δ delay amount difference of the clock signal A with respect to the clock signal C and a δ delay amount difference of the clock signal C with respect to the clock signal A are verified and calculated. Further, a δ delay amount difference of the clock signal B with respect to the clock signal C and a δ delay amount difference of the clock signal C with respect to the clock signal B are verified and calculated.

  In the δ delay insertion determination unit 113, the verification result (see FIG. 6) obtained by the δ delay verification unit 112 is referred to, and all combinations of two clock signals among the three clock signals A to C are referred to. The δ delay amount difference is recognized. Based on the recognized six types of δ delay amount differences, the δ delay insertion determination unit 113 selects a clock signal (base clock signal) having the maximum δ delay amount from among the three clock signals A to C (step). S3).

  When the base clock signal is selected, the δ delay insertion determination unit 113 calculates the difference between the maximum δ delay amount of the base clock signal and the δ delay amount of each clock signal other than the base clock signal as the δ delay insertion amount. Obtained (step S4). At this time, 0 is acquired as the δ delay insertion amount for the base clock signal, and an integer value of 1 or more is acquired as the δ delay insertion amount for one or two clock signals other than the base clock signal.

  The δ delay insertion amounts for the plurality of clock signals acquired in this way are notified to the corresponding δ delay insertion units 114A, 114B, and 114C, respectively. In the δ delay insertion units 114A, 114B, and 114C, the notified δ delay insertion amount is inserted into the clock signal other than the base clock signal by the signal substitution process. As a result, the δ delay amount of the clock signals other than the base clock signal is adjusted to match the δ delay amount (maximum delta delay amount) of the base clock signal, and the δ delay amount of all the clock signals becomes the maximum δ delay amount. Unified (step S5).

  Next, the operation of the digital δ delay automatic adjustment tool 110 shown in FIG. 3, that is, the processes in steps S <b> 2 to S <b> 4 of FIG. 4 will be described in more detail with reference to FIGS. 3, 5, and 6. FIG. 5 is a timing chart for explaining the operation of the digital δ delay automatic adjustment tool 110 shown in FIG. 3, particularly the operation of the data interface check unit 112AB. FIG. 6 is a diagram illustrating an example of a verification result obtained by the δ delay verification unit 112 in the digital δ delay automatic adjustment tool 110 illustrated in FIG. 3. Here, as described above, the case where the δ delay amounts 8, 12, and 15 are generated in the clock systems A, B, and C, respectively, will be described. The values of these δ delay amounts are determined by the designer. I can't see anything.

  In the timing chart shown in FIG. 5, the data interface check operation from the clock signal A to the clock signal, that is, the verification measurement operation of the delta delay amount difference of the clock signal B with respect to the clock signal A by the data interface check unit 112AB is specifically shown. It is shown. In addition, the signal which attached | subjected the code | symbol (a)-(e) in FIG. 5 respond | corresponds to signal (a)-(e) demonstrated in FIG. 3, respectively. The verification measurement operation of the δ delay amount difference of the clock signal B with respect to the clock signal A is performed according to the procedures (i) to (viii) described below.

  (I) The two clock signals A and B to be processed by the data interface check unit 112AB are divided into a measurement side clock signal A and a measurement side clock signal B.

  (Ii) The measurement-side clock signal A is divided by two by the frequency divider 121 and then branched into the data path and the through path described above.

  (Iii) A real-time delay of 1 ps seconds is inserted into the measurement-side clock signal A branched to the data path by the real-time delay adding unit 122. The signal into which the real time delay of 1 ps seconds is inserted is input as data to the first FF 123 in the subsequent stage (see the reference symbol (a) in FIGS. 3 and 5).

  (Iv) On the other hand, the measurement-side clock signal A branched to the through path is directly input as data to the second FF 124 in the subsequent stage without being given a real-time delay (see symbol (c) in FIG. 3).

  (V) By inputting the measured-side clock signal B to the FFs 123 and 124, the signals (b) and (d) (two data) are output from the FFs 123 and 124, respectively, and these signals (b) and ( and d) are compared by the comparator 125 to determine whether or not they match. The comparison result by the comparator 125 is passed through the third FF 126 and at the timing of the clock signal B to be measured, as the verification result (e) (see FIGS. 3 and 5), the δ delay measurement signal substitution unit 111 and the δ delay insertion determination Is output to the unit 113.

  (Vi) If the comparison result is coincidence (OK), the measurement of the δ delay amount difference is completed immediately. On the other hand, if the comparison result is mismatch (NG), the difference between the δ delay amounts of the two clock signals A and B is the cause of the mismatch, so that the signal substitution with δ delay is executed once for the measurement side clock signal A. Then, the number of executions of signal substitution is incremented by 1, and the amount of δ delay is increased by 1.

  (Vii) In the processes of the above steps (ii) to (vi), the two signals (b) and (d) passing through the two paths are matched until the comparison result by the comparator 125 is matched. It is repeatedly executed until.

  (Viii) The number of executions of signal substitution at the time when the comparison result by the comparator 125 matches, that is, when the two signals (b) and (d) passing through the two paths respectively match, is the clock signal. Verification calculation is performed and stored as a δ delay amount difference of the clock signal B with respect to A. Note that the counting of the number of executions of the signal substitution process by the δ delay adding unit 111A may be executed by, for example, the data interface check unit 112AB or the δ delay insertion determining unit 113.

  In the example shown in FIG. 5, in the initial procedure (v), at the timing TB when the non-measurement-side clock signal B rises, the signals (a) and (c) “when delta delay + 0” are respectively signals ( Compared as b) and (d). At this time, since the signals (b) and (d) correspond to A and B, respectively, the comparison results are inconsistent (see “in the case of delta delay + 3 or less” in (d) and (e)). Along with this, signal substitution with δ delay is executed once for the measurement-side clock signal A.

  Next, in the second procedure (v), at the timing TB when the non-measurement-side clock signal B rises, the signals (a) and (c) “if delta delay + 1” are respectively the signals (b), ( Compared as d). Also at this time, since the signals (b) and (d) correspond to A and B, respectively, the comparison results are inconsistent (see “in the case of delta delay + 3 or less” in (d) and (e)). Along with this, signal substitution with δ delay is executed once for the measurement-side clock signal A.

  Thereafter, after the fourth procedure (v) is performed in the same manner, in the fifth procedure (v), at the timing TB when the non-measurement side clock signal B rises, the “delta” of the signals (a) and (c) The signal of “in the case of delay +4” is compared as signals (b) and (d), respectively. At this time, since the signals (b) and (d) both correspond to A, the comparison results are the same (see “in the case of delta delay + 4 or more” in (d) and (e)).

  Thereby, the δ delay amount difference 4 of the clock signal B with respect to the clock signal A is obtained as a verification result by the check unit 112AB of the δ delay verification unit 112 (see X1 in FIG. 6). Similarly, a δ delay amount difference 7 of the clock signal C with respect to the clock signal A is obtained as a verification result by the check unit 112AC of the δ delay verification unit 112 (see X2 in FIG. 6). Further, the δ delay amount difference 3 of the clock signal C with respect to the clock signal B is obtained as a verification result by the check unit 112BC of the δ delay verification unit 112 (see X3 in FIG. 6).

  Note that since the clock signal A is advanced with respect to the clock signal B, the δ delay amount difference of the clock signal A with respect to the clock signal B becomes a negative value (minus difference), and the comparison results are all identical (FIG. 6). See “B to A”). Similarly, since the clock signal A is advanced with respect to the clock signal C, the δ delay amount difference of the clock signal A with respect to the clock signal C becomes a negative value (minus difference), and the comparison results are all identical (FIG. 6). See “C to A”). Further, since the clock signal B is advanced with respect to the clock signal C, the δ delay amount difference of the clock signal B with respect to the clock signal C becomes a negative value (minus difference), and all the comparison results are coincident (FIG. 6). (See “C to B”).

  Based on the verification results as shown in FIG. 6, the clock signal B is delayed by a δ delay amount 4 with respect to the clock signal A, the clock signal C is delayed by a δ delay amount 7 with respect to the clock signal A, and the clock signal C is It is recognized that the signal B is delayed by a δ delay amount 3. Accordingly, the δ delay insertion determination unit 113 has the largest δ delay amount of the clock signal C among the three clock signals A to C, and the clock signal C is selected as the base clock signal.

  Then, in the δ delay insertion determination unit 113, differences 7 and 3 between the maximum δ delay amount and the δ delay amounts of the clock signals A and B other than the base clock signal C are acquired as δ delay insertion amounts, respectively. Notification is made to the insertion sections 114A and 114B. Thereby, in the δ delay insertion units 114A and 114B, the δ delay insertion amounts 7 and 3 are inserted by performing the signal substitution processing seven times and three times for the clock signals A and B, respectively. Therefore, the δ delay amount of the clock signals A and B other than the base clock signal C is adjusted to match the δ delay amount (maximum delta delay amount) 15 of the base clock signal C, and δ of all the clock signals A to C is adjusted. The delay amount is unified to a maximum δ delay amount 15.

[5] Effects of the present embodiment According to the processing apparatus 1 of the present embodiment, by embedding the δ delay automatic adjustment virtual circuit (digital δ delay automatic adjustment tool 110), design work considering each δ delay (for each circuit) Measurement of δ delay amount and delay amount adjustment) can be automated. Therefore, it is possible to eliminate the design work (measurement of δ delay amount and delay amount adjustment of each circuit) in consideration of δ delay, which has been performed manually by a designer between a plurality of synchronous clocks. . As a result, the number of design steps in consideration of the δ delay can be reduced, and problems caused by the δ delay can be prevented.

  For example, according to the present embodiment, it is possible to reduce 90-95% of the man-hours required for the δ delay countermeasure, and it is possible to greatly reduce the cost required for the delay countermeasure. The man-hours required for the δ delay countermeasure include, for example, man-hours spanning circuit design, logic simulation, and hardware simulation (actual machine evaluation).

  In particular, since it becomes possible to automatically adjust the δ delay between a plurality of clock systems, an erroneous operation associated with a manual operation does not occur. In other words, in the HDL logic circuit design (logic design) or development for performing logic simulation, the digital δ delay automatic adjustment tool 110 is incorporated in the circuit at the logic design stage, so that the designer must consider digital δ when executing the logic simulation. The delay can be adjusted automatically. Therefore, it is possible to reliably suppress the occurrence of operation mismatch between the logic simulation result and the actual machine evaluation result.

  In addition, the absolute delay amount is not measured and calculated for a clock system passing through a circuit including a black box, a gray box, and the like, but a relative δ delay amount difference between clock systems is measured and calculated. Then, the base clock signal having the maximum δ delay amount is selected based on the δ delay amount difference, and the δ delay automatic adjustment is performed so that the δ delay amount in each clock system other than the selected base clock signal becomes the maximum δ delay amount. It is. For this reason, even if a black box or gray box circuit is included, the δ delay can be automatically adjusted based on the δ delay amount difference, which greatly improves work efficiency, man-hours and costs in circuit design. A significant reduction can be realized.

[6] Others While the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made without departing from the spirit of the present invention. It can be changed and implemented.

  In the above-described embodiment, the case where the master clock source 3 is branched into the three clock systems A, B, and C and the δ delay amounts 8, 12, and 15 are generated in each of the clock systems A, B, and C has been described. However, the present invention is not limited to these numbers and numerical values.

[7] Supplementary Notes Regarding the above embodiment, the following supplementary notes are further disclosed.

(Appendix 1)
A processing apparatus having a processing unit that performs logic verification on an integrated circuit that operates with a plurality of clock signals having the same period and synchronous relationship,
The processor is
A clock signal having the largest delta delay amount among the plurality of clock signals is selected as a base clock signal,
The processing apparatus, wherein a delta delay amount of a clock signal other than the base clock signal among the plurality of clock signals is adjusted to match a delta delay amount of the base clock signal.

(Appendix 2)
The processor is
For all combinations of two clock signals of the plurality of clock signals, calculate a delta delay amount difference between the two clock signals,
The processing apparatus according to appendix 1, wherein the base clock signal is selected based on the delta delay amount difference calculated for all the combinations.

(Appendix 3)
The processing apparatus according to appendix 2, wherein the amount of delta delay is the number of executions of signal substitution with delta delay performed for each of the plurality of clock signals.

(Appendix 4)
The processor is
The measurement-side clock signal that is one of the two clock signals is divided into two and then branched into two, and one of the two-branched measurement-side clock signals is given an arbitrary real-time delay amount to the first flip-flop. The other side of the measurement side clock signal that has been bifurcated is input as data to the second flip-flop, and the other side of the two clock signals is input to the first flip-flop and the second flip-flop. By inputting a clock signal as a clock, two data output from the first flip-flop and the second flip-flop are compared, and if the two data do not match as a result of the comparison, the measurement side A signal substitution with a delta delay for a clock signal is executed once. Repeatedly executed until data is consistent,
4. The processing apparatus according to appendix 3, wherein the number of executions of signal substitution with delta delay when the two data coincide with each other is calculated as the delta delay amount difference between the two clock signals.

(Appendix 5)
The processing device according to any one of Supplementary Note 1 to Supplementary Note 4, wherein the plurality of clock signals are branched from the same clock source.

(Appendix 6)
A logic simulator for simulating the operation of an integrated circuit subject to logic design,
A selecting unit that selects a clock signal having the largest delta delay amount as a base clock signal among a plurality of clock signals having the same period and a synchronous relationship in the integrated circuit;
A logic simulator, comprising: an adjustment unit that adjusts a delta delay amount of a clock signal other than the base clock signal among the plurality of clock signals so as to match a delta delay amount of the base clock signal.

(Appendix 7)
A calculation unit that calculates a delta delay amount difference between the two clock signals for all combinations of two clock signals of the plurality of clock signals;
The logic simulator according to appendix 6, wherein the selection unit selects the base clock signal based on the delta delay amount difference calculated for all the combinations.

(Appendix 8)
The logic simulator according to appendix 7, wherein the delta delay amount is the number of executions of signal substitution with delta delay performed for each of the plurality of clock signals.

(Appendix 9)
The calculation unit includes:
The measurement-side clock signal that is one of the two clock signals is divided into two and then branched into two, and one of the two-branched measurement-side clock signals is given an arbitrary real-time delay amount to the first flip-flop. The other side of the measurement side clock signal that has been bifurcated is input as data to the second flip-flop, and the other side of the two clock signals is input to the first flip-flop and the second flip-flop. By inputting a clock signal as a clock, two data output from the first flip-flop and the second flip-flop are compared, and if the two data do not match as a result of the comparison, the measurement side A signal substitution with a delta delay for the clock signal is performed once, and the processing is performed as a result of the comparison. Repeatedly executed until data is consistent,
9. The logic simulator according to appendix 8, wherein the number of executions of signal substitution with delta delay when the two data coincide is calculated as the delta delay amount difference between the two clock signals.

(Appendix 10)
The logic simulator according to any one of appendix 6 to appendix 9, wherein the plurality of clock signals are branched from the same clock source.

(Appendix 11)
An integrated circuit design verification method comprising:
In the integrated circuit, a clock signal having the largest delta delay amount is selected as a base clock signal among a plurality of clock signals having the same period and synchronous relationship,
A design verification method, wherein a delta delay amount of a clock signal other than the base clock signal among the plurality of clock signals is adjusted to match a delta delay amount of the base clock signal.

(Appendix 12)
For all combinations of two clock signals of the plurality of clock signals, calculate a delta delay amount difference between the two clock signals,
12. The design verification method according to appendix 11, wherein the base clock signal is selected based on the delta delay amount difference calculated for all the combinations.

(Appendix 13)
13. The design verification method according to appendix 12, wherein the delta delay amount is the number of executions of signal substitution with delta delay performed for each of the plurality of clock signals.

(Appendix 14)
The measurement-side clock signal that is one of the two clock signals is divided into two and then branched into two, and one of the two-branched measurement-side clock signals is given an arbitrary real-time delay amount to the first flip-flop. The other side of the measurement side clock signal that has been bifurcated is input as data to the second flip-flop, and the other side of the two clock signals is input to the first flip-flop and the second flip-flop. By inputting a clock signal as a clock, two data output from the first flip-flop and the second flip-flop are compared, and if the two data do not match as a result of the comparison, the measurement side A signal substitution with a delta delay for the clock signal is performed once, and the processing is performed as a result of the comparison. Repeatedly executed until data is consistent,
14. The design verification method according to appendix 13, wherein the number of executions of signal substitution with delta delay when the two data match is calculated as the delta delay amount difference between the two clock signals.

(Appendix 15)
The design verification method according to any one of appendix 11 to appendix 14, wherein the plurality of clock signals are branched from the same clock source.

1 Processing Unit 2 Master Clock Source (MCLK)
3A Clock system A (MCLK_A)
3B Clock system B (MCLK_B)
3C Clock system C (MCLK_C)
10 Processing Unit 11 Logic Simulator 110 Digital δ Delay Automatic Adjustment Tool (δ-adjuster)
111 δ delay measurement signal substitution unit (calculation unit)
111A, 111B, 111C δ delay addition unit 112 δ delay verification unit (calculation unit)
112AB, 112BA, 112AC, 112CA, 112BC, 112CB Data interface check unit 113 δ delay insertion determination unit (selection unit)
114 δ delay adjustment signal substitution unit (adjustment unit)
114A, 114B, 114C δ delay insertion unit 121 frequency divider (PPG)
122 real time delay giving unit 123 first flip-flop (first FF)
124 second flip-flop (second FF)
125 Comparator 126 Third Flip-Flop (3rd FF)
20 storage unit 21 HDL description 22 design result 23 simulation result 24 program 30 input unit 40 display unit 50 bus

Claims (7)

A processing apparatus having a processing unit that performs logic verification on an integrated circuit that operates with a plurality of clock signals having the same period and synchronous relationship,
The processor is
A clock signal having the largest delta delay amount among the plurality of clock signals is selected as a base clock signal,
The processing apparatus, wherein a delta delay amount of a clock signal other than the base clock signal among the plurality of clock signals is adjusted to match a delta delay amount of the base clock signal. The processor is
For all combinations of two clock signals of the plurality of clock signals, calculate a delta delay amount difference between the two clock signals,
The processing apparatus according to claim 1, wherein the base clock signal is selected based on the delta delay amount difference calculated for all the combinations.   The processing apparatus according to claim 2, wherein the delta delay amount is the number of executions of signal substitution with delta delay performed for each of the plurality of clock signals. The processor is
The measurement-side clock signal that is one of the two clock signals is divided into two and then branched into two, and one of the two-branched measurement-side clock signals is given an arbitrary real-time delay amount to the first flip-flop. The other side of the measurement side clock signal that has been bifurcated is input as data to the second flip-flop, and the other side of the two clock signals is input to the first flip-flop and the second flip-flop. By inputting a clock signal as a clock, two data output from the first flip-flop and the second flip-flop are compared, and if the two data do not match as a result of the comparison, the measurement side A signal substitution with a delta delay for the clock signal is performed once, and the processing is performed as a result of the comparison. Repeatedly run until the data matches,
The processing device according to claim 3, wherein the number of executions of signal substitution with delta delay when the two data coincide with each other is calculated as the delta delay amount difference between the two clock signals. .   5. The processing device according to claim 1, wherein the plurality of clock signals are branched from the same clock source. 6. A logic simulator for simulating the operation of an integrated circuit subject to logic design,
A selecting unit that selects a clock signal having the largest delta delay amount as a base clock signal among a plurality of clock signals having the same period and a synchronous relationship in the integrated circuit;
A logic simulator, comprising: an adjustment unit that adjusts a delta delay amount of a clock signal other than the base clock signal among the plurality of clock signals so as to match a delta delay amount of the base clock signal. An integrated circuit design verification method comprising:
In the integrated circuit, a clock signal having the largest delta delay amount is selected as a base clock signal among a plurality of clock signals having the same period and synchronous relationship,
A design verification method, wherein a delta delay amount of a clock signal other than the base clock signal among the plurality of clock signals is adjusted to match a delta delay amount of the base clock signal.

Images