JP2009069660A - Display drive and display driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display drive and a display driving method capable of automatically creating a suitable timing signal corresponding to a horizontal length by the small number of registers. <P>SOLUTION: The number of clock signals corresponding to the length of one horizontal period is counted by a counting part 231. A comparison operation part 232 compares a count value counted by the counting part 231 with a storage value in a storage part 233 in each one scanning period and stores a larger value in the storage part 233. In each one vertical period, a substitution part 234 holds the storage value of the storage part 233 in a holding part 235. Various timing signals are created by a gate output shift clock creation circuit 236, a gate output on/off timing creation circuit 237 and a source output on/off timing creation circuit 237 by using the holding value of the holding part 235. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display driving apparatus and a display driving method for driving a display pixel by generating a timing signal related to driving of a display pixel in an active matrix display device.

  Conventionally, as one of methods for generating various timing signals related to driving of display pixels in an active matrix display device, an external setting terminal is provided in the display driving device, and an on-state of a signal input via the external setting terminal is turned on. There is a method of creating various timing signals according to the / off timing. When creating timing signals in response to signals from such external setting terminals, external setting terminals corresponding to the number of timing signals to be created are required, so the size of the LSI constituting the display drive device can be increased. Easy to invite.

Therefore, as a technique for avoiding such an increase in the number of terminals, on / off timing information of various timing signals is held in a register, and various timing signals are created based on the information of the registers. A technique has been proposed. Further, in Patent Document 1, in order to easily change the register setting to cope with a large number of driving modes of the display driving device, individual register setting values are held in advance for each driving mode, They can be set according to the drive mode.
JP 2005-70232 A

  Here, in the method of Patent Document 1, since a register corresponding to the number of drive modes is required, a large number of registers may be required depending on the number of drive modes. In addition, the timing signal is generated based on a specific register setting value even when the rising edge of the horizontal synchronization signal changes irregularly. For example, it is generated for the length of one horizontal period. If the timing signal is too long, the display may become impossible.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a display driving device and a display driving method capable of automatically generating an appropriate timing signal corresponding to the length in the horizontal direction with a small number of registers. And

  In order to achieve the above object, the display driving apparatus according to the first aspect of the present invention is arranged in a matrix near each intersection of a plurality of scanning lines arranged in the row direction and a plurality of signal lines arranged in the column direction. A display driving device for driving a plurality of display pixels to which a display signal voltage based on display data is applied, and a count unit that receives a clock signal and counts the number of the input clock signals; and the count unit And a storage unit for storing the number of clock signals counted in step 1, and the number of clock signals counted in the storage unit and the number of clock signals stored in the storage unit each time at least one horizontal synchronization signal is received. And a comparison operation unit that updates the number of clock signals stored in the storage unit based on a result of the comparison, and receives at least one vertical synchronization signal. Each time, the display unit sequentially selects the display pixels in the next vertical period based on the number of the clock signals stored in the storage unit and the number of the clock signals stored in the storage unit. And a generation unit that generates a timing signal for generating a signal for applying the display signal voltage to the display pixel in the selected state and a signal for setting the state.

  In order to achieve the above object, the display driving apparatus according to the second aspect of the present invention is provided near each intersection of a plurality of scanning lines arranged in the row direction and a plurality of signal lines arranged in the column direction. In a display driving device for driving a plurality of display pixels to which a display signal voltage based on display data is applied arranged in a matrix, a clock signal is input, and a counting unit that counts the number of input clock signals, A storage unit for storing the number of clock signals counted by the counting unit, and a clock signal stored in the storage unit and the number of clock signals counted by the counting unit each time at least one horizontal synchronization signal is received And a comparison operation unit that updates the number of clock signals stored in the storage unit based on the result of the comparison, and is stored in the storage unit A holding unit for holding the number of clock signals, a signal for sequentially selecting the display pixels in the next horizontal period based on the number of the clock signals held in the holding unit, and the selection state. And a generation unit that generates a timing signal for generating a signal for applying the display signal voltage to the display pixel.

  In order to achieve the above object, the display driving method according to the third aspect of the present invention is provided near each intersection of a plurality of scanning lines arranged in the row direction and a plurality of signal lines arranged in the column direction. A clock signal corresponding to the length of each horizontal period included in at least one vertical period in a display driving method for driving a plurality of display pixels arranged in a matrix and to which a display signal voltage based on display data is applied For holding the minimum value of the compared number of clock signals and sequentially setting the display pixels in the next vertical period based on the held minimum value of the number of clock signals. A timing signal for creating a signal and a signal for applying the display signal voltage to the selected display pixel is created.

  In order to achieve the above object, the display driving method according to the fourth aspect of the present invention is provided near each intersection of a plurality of scanning lines arranged in the row direction and a plurality of signal lines arranged in the column direction. In a display driving method for driving a plurality of display pixels arranged in a matrix and to which a display signal voltage based on display data is applied, the number of clock signals corresponding to the length of the previous horizontal period and the current horizontal Compare the number of clock signals corresponding to the length of the period, hold the smaller one of the compared clock signals, and in the next horizontal period based on the held number of clock signals Generating a signal for sequentially setting the display pixels in a selected state and a timing signal for generating a signal for applying the display signal voltage to the display pixels in the selected state; To.

  According to the present invention, it is possible to provide a display driving apparatus and a display driving method capable of automatically generating an appropriate timing signal corresponding to the length in the horizontal direction with a small number of registers.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a first embodiment of the present invention will be described. FIG. 1 is an overall configuration diagram of a liquid crystal display device as an example of a display device including a display driving device according to a first embodiment of the present invention. The liquid crystal display device shown in FIG. 1 includes a display panel 1, a display drive LSI 2, and a flexible printed circuit board (FPC) 3.

  The display panel 1 has a configuration in which display pixels 1c for displaying an image are arranged in a matrix in the vicinity of an intersection of a gate line (scanning line) 1a and a source line (signal line) 1b arranged orthogonal to each other. Has been. In the display pixel 1c, liquid crystal is filled between a thin film transistor (TFT) connected to the gate line 1a and the source line 1b, a pixel electrode connected to the TFT, and a common electrode disposed facing the pixel electrode. And a storage capacitor connected in parallel to the liquid crystal capacitor. In such a configuration, when a display signal voltage is applied between the pixel electrode and the common electrode via the source line 1b, the liquid crystal filled between the pixel electrode and the common electrode according to the display signal voltage. As a result, the light transmittance in the liquid crystal layer changes. At this time, image display is performed by irradiating light from the back surface of the display pixel or the like.

  The display driving LSI 2 drives the gate external output signal Gn (n = 1, 2, 3,...) For driving the gate line 1a of the display panel 1 and the source line 1b of the display panel 1 in accordance with the input signal from the FPC 3. Source external output signals Sn (n = 1, 2, 3,...) Are generated and output. Here, while the gate external output signal Gn is at the high level, the display pixel 1c connected to the corresponding gate line 1a is selected. The source external output signal Sn is a display signal voltage that is generated based on display data input through the FPC 3 and applied to the liquid crystal capacitance of the display pixel 1c that has been selected. Details of the display drive LSI 2 will be described later.

  The FPC 3 is a substrate on which wiring for inputting various input signals such as display data for displaying an image, a synchronization signal at the time of image display, and a clock signal to the display driving LSI 2 is mounted.

  Hereinafter, details of the display drive LSI 2 will be described. FIG. 2 is a diagram showing an internal configuration of the display drive LSI 2. The display drive LSI 2 shown in FIG. 2 includes a gate block 21, a source block 22, and a timing generator block 23.

  The gate block 21 generates a gate external output signal Gn according to the gate internal signals (gate output shift clock signal GPCK, gate output on / off timing signal GRES, etc.) output from the timing generator block 23, and sends it to the gate line 1a. Supply sequentially. Here, the gate output shift clock signal GPCK is a signal for setting the shift timing of the gate external output signal Gn. The gate output on / off timing signal GRES is a signal for setting the on period of the gate external output signal Gn.

  The source block 22 generates a source external output signal Sn based on a source internal signal (source output on / off timing signal STB, etc.) output from the timing generator block 23 and display data input via the FPC 3. Supply to the corresponding source line 1b. Here, the source output on / off timing signal STB is a signal for setting the display data capture timing.

  The timing generator block 23 generates various timing signals such as a gate output clock signal GPCK based on input signals (vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, clock signal CLK) input via the FPC 3. Here, image display for one screen of the display panel 1 is performed in one vertical period (a period from the rise of the vertical synchronization signal VSYNC to the next rise). As shown in FIG. 3, one vertical period is composed of a plurality of horizontal periods (periods from the rising edge of the horizontal synchronizing signal HSYNC to the next rising edge), and image display for one row of the display panel 1 in each horizontal period. Is done. Further, one horizontal period is composed of a plurality of clock periods, and image display is performed for each pixel in accordance with the clock signal CLK.

  Next, the timing generator block 23 will be further described. FIG. 4 is a block diagram showing an internal configuration of the timing generator block 23 in the first embodiment. As shown in FIG. 4, the timing generator block 23 includes a count unit 231, a comparison operation unit 232, a storage unit 233, an assignment unit 234, a holding unit 235, a gate output shift clock generation circuit 236, and a gate output. An on / off timing generation circuit 237 and a source output on / off timing generation circuit 238 are provided.

  The count unit 231 counts the number of clock signals CLK input in one horizontal period. That is, the count unit 231 counts up every time one clock signal CLK is input via the FPC 3, and resets the count value every time the horizontal synchronization signal HSYNC is input.

  The comparison operation unit 232 compares the stored value of the storage unit 233 and the counter value of the count unit 231 each time the horizontal synchronization signal HSYNC rises, and updates the value of the storage unit 233 with one of the smaller values.

  The storage unit 233 stores a counter value for one horizontal period. Here, due to the operation of the comparison operation unit 232, the storage unit 233 always stores the minimum value of the number of clocks in one horizontal period. The assigning unit 234 assigns the stored value of the storage unit 233 to the holding unit 235 every time it receives the vertical synchronization signal VSYNC. The holding unit 235 holds the value substituted by the substitution unit 234.

  The gate output shift clock generation circuit 236 generates the gate output shift clock signal GPCK using the value held in the holding unit 235 and outputs the gate output shift clock signal GPCK to the gate block 21. The gate output on / off timing creation circuit 237 creates the gate output on / off timing signal GRES using the value held in the holding unit 235 and outputs the gate output on / off timing signal GRES to the gate block 21. The source output on / off timing creation circuit 238 creates the source output on / off timing signal STB using the value held in the holding unit 235 and outputs the source output on / off timing signal STB to the source block 22.

  FIG. 5 is a flowchart showing processing within one horizontal period of the timing generator block 23 according to the first embodiment. In FIG. 5, it is first determined whether or not the horizontal synchronization signal HSYNC is input to the timing generator block 23 (step S1). If it is determined in step S1 that the horizontal synchronization signal HSYNC is not input, the process proceeds to step S5. On the other hand, when the horizontal synchronization signal HSYNC is input in the determination of step S1, the comparison operation unit 232 compares the counter value of the count unit 231 with the stored value of the storage unit 233, and the counter value of the count unit 231 is It is determined whether the value is smaller than the stored value of the storage unit 233 (step S2). If it is determined in step S2 that the counter value is smaller than the stored value, the stored value in the storage unit 233 is updated to the counter value in the count unit 231 (step S3). On the other hand, if it is determined in step S2 that the counter value is greater than or equal to the stored value, the process in step S3 is skipped.

  After step S2 or step S3, the counter value of the counting unit 231 is reset (step S4). Thereafter, it is determined whether the clock signal CLK is input to the count unit 231 (step S5). If the clock signal CLK is input to the counting unit 231 in the determination in step S5, the count value in the counting unit 231 is counted up (step S6). Thereafter, the processing in FIG. 5 ends and the processing returns to processing in one vertical period described later. On the other hand, if it is determined in step S5 that the clock signal CLK is not input to the counting unit 231, the process in step S6 is skipped, and then the process in FIG. Return to.

  By the processing as shown in FIG. 5, the number of clocks from the rising edge of HSYNC to the next rising edge, that is, one horizontal period is counted in the counting unit 231 as shown in FIG. Then, every time one horizontal period ends, the counter value of the count unit 231 and the stored value of the storage unit 233 are compared, and the smaller one is stored in the storage unit 233.

  FIG. 6 is a flowchart showing processing within one vertical period of the timing generator block 23 in the first embodiment. In FIG. 6, it is first determined whether or not the vertical synchronization signal VSYNC is input to the timing generator block 23 (step S11). If it is determined in step S11 that the vertical synchronization signal VSYNC is not input, the process proceeds to step S14. On the other hand, when the vertical synchronization signal VSYNC is input in the determination in step S11, the stored value in the storage unit 233 is substituted into the holding unit 235 by the substitution unit 234 (step S12). Thereafter, the counter value of the count unit 231 and the stored value of the storage unit 233 are reset (step S13).

  After step S11 or step S13, processing within one horizontal period shown in FIG. 5 is executed (step S14). After the process within one horizontal period is completed, the process returns to step S11.

  By the processing in one vertical period described in FIG. 6, the holding unit 235 automatically holds the minimum value of the number of clocks in one horizontal period in the previous vertical period. In the present embodiment, various timing signals are created based on the number of clocks.

  Hereinafter, as an example of timing signal generation, a method for generating the gate output shift clock signal GPCK and the gate output on / off timing signal GRES, which are timing signals related to driving of the gate line 1a of the display panel 1, will be described. FIG. 8 is a waveform diagram for explaining a method of creating the gate output shift clock signal GPCK and the gate output on / off timing signal GRES. In the following description, as an example, it is assumed that the holding unit 235 is configured by an 8-bit register.

  First, the gate output shift clock generation circuit 236 sets the gate output shift clock signal GPCK to a high level (on) after waiting for a fixed timing after the rising of the horizontal synchronization signal HSYNC is detected. Further, the gate output shift clock generation circuit 236 waits for the number of clocks obtained by dividing the number of clocks held in the holding unit 235 by 8 after the rising of the horizontal synchronization signal HSYNC is detected, and waits for the gate output shift clock signal GPCK. Is set to a low level (off). By such an operation, the gate output shift clock signal GPCK as shown in FIG. 9 is output from the gate output shift clock generation circuit 236 in synchronization with the horizontal synchronization signal HSYNC.

  In addition, the gate output on / off timing generation circuit 237 calculates the fixed timing at which the gate output shift clock signal GPCK is turned on after the rising of the horizontal synchronization signal HSYNC is detected + the number of clocks held in the holding unit 235. After waiting for the number of clocks divided by 32, the gate output on / off timing signal GRES is set to the high level (on). Further, the gate output on / off timing generation circuit 237 waits for a fixed timing at which the gate output shift clock signal GPCK is turned on + a fixed timing after the rising of the horizontal synchronization signal HSYNC is detected, and then waits for the gate output on / off. The timing signal GRES is set to a low level (off). By such an operation, a gate output on / off timing signal GRES as shown in FIG. 9 is output from the gate output on / off timing generation circuit 237 in synchronization with the horizontal synchronization signal HSYNC.

  Here, the numerical values for determining the on / off timing of the gate output shift clock signal GPCK and the gate output on / off timing signal GRES as shown in FIG. 9 are examples, and are appropriately determined depending on the specifications of the display driving LSI 2 and the like. It can be changed.

  The gate block 21 outputs the gate external output signal Gn based on the timing signal created as shown in FIGS. That is, the gate block 21 turns on the gate external output signal Gn of the corresponding gate line 1a only while the gate output on / off timing signal GRES is on. At this time, the display pixel 1c connected to the corresponding gate line 1a is selected. Each time the gate block 21 receives the gate output shift clock signal GPCK input in synchronization with the horizontal synchronization signal HSYNC, the gate block 21 shifts the gate external output signal Gn turned on line by line. As a result, the display pixels 1c in the selected state are shifted one row at a time, and one row of image display is performed every horizontal period.

  As described above, according to the first embodiment, the holding unit 235 always holds the minimum value of the number of clocks in the horizontal period in the previous vertical period by the processing in FIGS. 5 and 6. Accordingly, the gate output shift clock signal GPCK and the gate output on / off timing signal GRES can always be set based on the minimum value of the number of clocks in the horizontal period in the previous vertical period, so that one horizontal period within one vertical period. Even when the length of the signal is changed irregularly, it is possible to generate a timing signal having an appropriate length in consideration of the change in the next vertical period.

  Even in a special drive mode in which the clock signal CLK and the horizontal synchronization signal HSYNC are thinned out, only a value set in the holding unit 235 is provided with a timing signal having an appropriate length for each drive mode. Therefore, it is possible to cope with a large number of driving modes with a small number of registers.

  Here, in the above-described example, only the generation method of the timing signal related to the driving of the gate line 1a of the display panel 1 is described. However, the method of the present embodiment is not limited to this, and the source line of the display panel 1 is used. The timing signal (source output on / off timing signal STB, etc.) relating to the driving of 1b, the polarity switching timing signal of the counter electrode or display signal voltage necessary for AC driving of the display pixel 1c, the liquid crystal shown in FIG. The present invention can also be applied to creation of various timing signals such as timing signals necessary for operating the display device in the energy saving mode.

  Further, in the processing of FIGS. 5 and 6, the comparison is performed within one vertical period, but the comparison may be performed within two or more vertical periods. In this way, by performing comparison in horizontal periods within a plurality of vertical periods, the number of refreshes of the holding unit 235 can be reduced. Thereby, stabilization of the operation of the display drive LSI 2 is expected.

  Further, in the processing of FIGS. 5 and 6, the minimum value of the horizontal period within one vertical period is held in the holding unit 235. However, depending on the driving mode of the display drive LSI 2, 2 is set within one vertical period. You may make it hold | maintain the value equivalent to the above several. That is, depending on the drive mode of the display drive LSI 2, there is a case where the clock signal is largely thinned out during the horizontal period corresponding to the non-display period, and in such a drive mode, various values are used using the minimum value. Rather than creating a timing signal, it may be possible to display more appropriately by creating various timing signals using the second smallest value or a plurality of larger values.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. 5 and 6 in the first embodiment described above, the holding unit 235 is refreshed every vertical period. On the other hand, the second embodiment is an example in which the holding unit 235 is refreshed every horizontal period. Note that the second embodiment is different only in that the horizontal synchronization signal HSYNC is input to the substitution unit 234 in FIG.

  FIG. 10 is a flowchart showing the processing in one horizontal period of the timing generator block 23 in the second embodiment of the present invention.

  In FIG. 10, it is first determined whether or not the horizontal synchronization signal HSYNC is input to the timing generator block 23 (step S21). If it is determined in step S21 that the horizontal synchronization signal HSYNC is not input, the process proceeds to step S27. On the other hand, when the horizontal synchronization signal HSYNC is input in the determination of step S21, the comparison operation unit 232 compares the counter value of the count unit 231 with the stored value of the storage unit 233, and the counter value of the count unit 231 is It is determined whether the value is smaller than the stored value of the storage unit 233 (step S22). If it is determined in step S22 that the counter value is smaller than the stored value, the stored value in the storage unit 233 is updated to the counter value in the count unit 231 (step S23). Thereafter, the stored value in the storage unit 233 is substituted into the holding unit 235 by the substitution unit 234 (step S24). Then, the process proceeds to step S26. On the other hand, if it is determined in step S22 that the counter value is equal to or greater than the stored value, the stored value in the storage unit 233 is not updated and is directly substituted into the holding unit 235 (step S25). Then, the process proceeds to step S26.

  After step S24 or step S25, the counter value of the counting unit 231 is reset (step S26). Thereafter, it is determined whether the clock signal CLK is input to the count unit 231 (step S27). If the clock signal CLK is input to the counting unit 231 in the determination in step S27, the count value in the counting unit 231 is counted up (step S28). Thereafter, the process returns to step S21. On the other hand, if it is determined in step S27 that the clock signal CLK is not input to the counting unit 231, the process in step S28 is skipped, and then the process returns to step S21.

  By the processing as shown in FIG. 10, the holding value of the holding unit 235 is refreshed every horizontal period. Such a second embodiment can minimize waste even when there is a large difference in the length of the horizontal period within one vertical period. Further, unlike the first embodiment, the second embodiment has an effect that the design is easy because the resetting of the count unit 231 and the storage unit 233 by the vertical synchronization signal is unnecessary.

  Here, in the second embodiment, the comparison is performed between two horizontal periods. However, the comparison may be performed within four horizontal periods, or may be performed within more horizontal periods.

  Although the present invention has been described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications and applications are naturally possible within the scope of the gist of the present invention.

  Further, the above-described embodiments include various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some configuration requirements are deleted from all the configuration requirements shown in the embodiment, the above-described problem can be solved, and this configuration requirement is deleted when the above-described effects can be obtained. The configuration can also be extracted as an invention.

1 is an overall configuration diagram of a liquid crystal display device as an example of a display device including a display driving device according to a first embodiment of the present invention. It is a figure which shows the internal structure of a display drive LSI. FIG. 5 is a waveform diagram showing the relationship among a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. It is a block diagram which shows the internal structure of the timing generator block in 1st Embodiment. It is the flowchart which showed the process in 1 horizontal period of the timing generator block in 1st Embodiment. 6 is a flowchart showing processing within one vertical period of the timing generator block in the first embodiment. It is the figure shown about the count of the length of 1 horizontal period. It is a wave form diagram for demonstrating the production method of the gate output shift clock signal GPCK and the gate output on / off timing signal GRES. It is a wave form diagram for showing operation of a gate block. It is the flowchart which showed the process in 1 horizontal period of the timing generator block in the 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display panel, 2 ... Display drive LSI, 3 ... Flexible printed circuit board (FPC), 21 ... Gate block, 22 ... Source block, 23 ... Timing generator block, 231 ... Count part, 232 ... Comparison calculating part, 233 ... Memory | storage 234 ... Substituting unit 235 ... Holding unit 236 ... Gate output shift clock generating circuit 237 ... Gate output on / off timing generating circuit 238 ... Source output on / off timing generating circuit

Claims (8)

Display that drives a plurality of display pixels to which a display signal voltage based on display data is applied arranged in a matrix near each intersection of a plurality of scanning lines arranged in a row direction and a plurality of signal lines arranged in a column direction In the drive device,
A clock signal is input, and a count unit that counts the number of input clock signals;
A storage unit for storing the number of clock signals counted by the counting unit;
Each time at least one horizontal synchronization signal is received, the number of clock signals counted by the counting unit is compared with the number of clock signals stored in the storage unit, and the storage unit is based on the comparison result. A comparison operation unit for updating the number of clock signals stored in
A holding unit that holds the number of the clock signals stored in the storage unit every time at least one vertical synchronization signal is received;
A signal for sequentially selecting the display pixels in the next vertical period based on the number of the clock signals held in the holding unit, and for applying the display signal voltage to the display pixels in the selected state A creation unit for creating a timing signal for creating a signal of
A display driving device comprising:   The comparison operation unit updates the number of clock signals stored in the storage unit by the smaller of the number of clock signals counted by the counting unit and the number of clock signals stored in the storage unit. The display driving apparatus according to claim 1.   The comparison operation unit compares the number of clock signals counted by the counting unit with the number of clock signals stored in the storage unit every time a plurality of horizontal synchronization signals are received. Item 4. The display driving device according to Item 1.   The display driving apparatus according to claim 1, wherein the holding unit holds the number of the clock signals stored in the storage unit every time a plurality of vertical synchronization signals are received. Display that drives a plurality of display pixels to which a display signal voltage based on display data is applied arranged in a matrix near each intersection of a plurality of scanning lines arranged in a row direction and a plurality of signal lines arranged in a column direction In the drive device,
A clock signal is input, and a count unit that counts the number of input clock signals;
A storage unit for storing the number of clock signals counted by the counting unit;
Each time at least one horizontal synchronization signal is received, the number of clock signals counted by the counting unit is compared with the number of clock signals stored in the storage unit, and the storage unit is based on the comparison result. A comparison operation unit for updating the number of clock signals stored in
A holding unit for holding the number of the clock signals stored in the storage unit;
A signal for sequentially selecting the display pixels in the next horizontal period based on the number of the clock signals held in the holding unit, and for applying the display signal voltage to the display pixels in the selected state A creation unit for creating a timing signal for creating a signal of
A display driving device comprising:   The comparison operation unit compares the number of clock signals counted by the counting unit with the number of clock signals stored in the storage unit every time a plurality of horizontal synchronization signals are received. Item 6. The display driving device according to Item 5. Driving a plurality of display pixels to which a display signal voltage based on display data is applied in the vicinity of the intersections of a plurality of scanning lines arranged in a row direction and a plurality of signal lines arranged in a column direction In the display driving method of
Comparing the number of clock signals corresponding to the length of each horizontal period contained within at least one vertical period;
Holding the minimum number of clock signals compared,
A signal for sequentially selecting the display pixels in a next vertical period based on a minimum value of the number of the held clock signals, and a voltage for applying the display signal voltage to the display pixels in the selected state. Create a timing signal to create the signal,
A display driving method characterized by the above. Driving a plurality of display pixels to which a display signal voltage based on display data is applied in the vicinity of the intersections of a plurality of scanning lines arranged in a row direction and a plurality of signal lines arranged in a column direction In the display driving method of
Comparing the number of clock signals corresponding to the length of the previous horizontal period with the number of clock signals corresponding to the length of the current horizontal period;
Keep the smaller of the number of clock signals compared,
Based on the number of the held clock signals, a signal for sequentially selecting the display pixels in a next horizontal period and a signal for applying the display signal voltage to the selected display pixels are generated. Create a timing signal to
A display driving method characterized by the above.

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