JP2009065032A - Thin film transistor and manufacturing method of display device having thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor having excellent electrical characteristics, and high reliability, and a display device having it. <P>SOLUTION: A gate insulating film is formed on a gate electrode, a microcrystal semiconductor film containing a metallic element is formed on the gate insulating film, and thereby crystallinity on the interface between the gate insulating film and the microcrystal semiconductor film containing the metallic element is raised. The microcrystal semiconductor film containing the metallic element of which crystallinity on the interface between itself and the gate insulating film is raised is used as a channel forming region to form this thin film transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a method for manufacturing a thin film transistor and a method for manufacturing a display device using a thin film transistor at least in a pixel portion.

In recent years, a technique for forming a thin film transistor using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.

As a switching element of an image display device, a thin film transistor using an amorphous semiconductor film, a thin film transistor using a polycrystalline semiconductor film, or the like is used. As a method for forming a polycrystalline semiconductor film, a technique is known in which a pulsed excimer laser beam is processed into a linear shape by an optical system, and is crystallized by irradiating the amorphous silicon film while scanning the linear beam. It has been.

As a switching element of an image display device, a thin film transistor using a microcrystalline semiconductor film is used (Patent Documents 1 and 2).
JP-A-4-242724 JP 2005-49832 A

A thin film transistor using a polycrystalline semiconductor film has a mobility that is two orders of magnitude higher than a thin film transistor using an amorphous semiconductor film, and a pixel portion of a semiconductor display device and its peripheral driver circuit can be formed over the same substrate. Has the advantage. However, compared to the case where an amorphous semiconductor film is used, the process is complicated for crystallization of the semiconductor film, so that there is a problem that the yield is reduced and the cost is increased accordingly.

In addition, in an inverted staggered thin film transistor using a microcrystalline semiconductor film, there is a problem in that the crystallinity in the interface region between the gate insulating film and the microcrystalline semiconductor film is low and the electrical characteristics of the thin film transistor are poor.

  In view of the above problems, an object of the present invention is to propose a thin film transistor with excellent electrical characteristics and high reliability and a method for manufacturing a display device having the thin film transistor.

A gate insulating film is formed over the gate electrode, and a microcrystalline semiconductor film containing a metal element is formed over the gate insulating film, so that crystallinity at the interface between the gate insulating film and the microcrystalline semiconductor film containing the metal element is increased. Next, a thin film transistor is formed using a microcrystalline semiconductor film containing a metal element with improved crystallinity at the interface with the gate insulating film as a channel formation region.

Further, a thin film transistor is formed by forming a buffer layer over a microcrystalline semiconductor film containing a metal element with improved crystallinity and forming a source region and a drain region, and a source wiring and a drain wiring over the buffer layer. .

In addition, a display device is manufactured by forming a pixel electrode connected to the thin film transistor.

Silane gas and hydrogen gas and / or rare gas on the gate insulating film by a plasma CVD apparatus using an electrode containing titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, platinum, etc. A microcrystalline semiconductor film containing a metal element with improved crystallinity at the interface with the gate insulating film can be formed by forming a microcrystalline semiconductor film with the use of.

The gate is formed by plasma CVD using a gas containing a metal element such as titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, platinum, silane gas, hydrogen gas, and / or rare gas. By forming a microcrystalline semiconductor film over the insulating film, a microcrystalline semiconductor film containing a metal element with improved crystallinity at the interface with the gate insulating film can be formed.

After applying a liquid containing a metal element such as titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, platinum or the like onto the gate insulating film, silane gas and hydrogen gas and / or rare gas are applied. A microcrystalline semiconductor film containing a metal element with improved crystallinity at the interface with the gate insulating film can be formed by using the plasma CVD method to form the microcrystalline semiconductor film.

After forming a thin film containing a metal element such as titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, platinum on the gate insulating film, silane gas and hydrogen gas and / or rare gas A microcrystalline semiconductor film containing a metal element with improved crystallinity at the interface with the gate insulating film can be formed by forming a microcrystalline semiconductor film using a plasma CVD method.

In addition, a thin film transistor (TFT) is manufactured using a microcrystalline semiconductor film containing a metal element, and a display device is manufactured using the thin film transistor in a pixel portion and further in a driver circuit. A thin film transistor using a microcrystalline semiconductor film has a mobility of 1 to ²⁰ cm ² / V · sec, which is 2 to 20 times that of a thin film transistor using an amorphous semiconductor film. A part or all of the above can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

  The display device includes a light emitting device and a liquid crystal display device. The light emitting device includes a light emitting element, and the liquid crystal display device includes a liquid crystal element. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes organic EL (electroluminescence) and inorganic EL.

  The display device includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel. Furthermore, the present invention relates to an element substrate corresponding to one mode before the display element is completed in the process of manufacturing the display device, and the element substrate includes a unit for supplying current to the display element. Prepare for. Specifically, the element substrate may be in a state where only the pixel electrode of the display element is formed, or after the conductive film to be the pixel electrode is formed, the pixel electrode is formed by etching. The previous state may be used, and all forms are applicable.

Note that a display device in this specification means an image display device, a light-emitting device, or a light source (including a lighting device). Also, a connector, for example, a module with a FPC (Flexible printed circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package), a module with a printed wiring board at the end of a TAB tape or TCP, or a display It is assumed that the display device includes all modules in which an IC (integrated circuit) is directly mounted on the element by a COG (Chip On Glass) method.

According to the present invention, a highly reliable thin film transistor with excellent electrical characteristics and a display device including the thin film transistor can be manufactured.

By forming the channel formation region using a microcrystalline semiconductor film containing a metal element, variation in threshold voltage is suppressed, field-effect mobility is improved, and a subthreshold coefficient (S value) is also reduced. Thus, high performance of the thin film transistor can be achieved. As a result, the drive frequency of the display device can be increased, and it is possible to sufficiently cope with an increase in panel size and an increase in pixel density.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In the structure of the present invention described below, the same reference numerals are used in common in different drawings. In addition, arrangement | positioning of each apparatus in the production system shown by the following embodiment shows an example, and if it is arrangement | positioning which has the same effect, it should not be limitedly interpreted to what is illustrated.

(Embodiment 1)
In this embodiment, a manufacturing process of a thin film transistor will be described with reference to FIGS. 1, 2, 5, 6, 8, 10, and 11 are cross-sectional views illustrating a manufacturing process of a thin film transistor, and FIGS. 7 and 12 are top views of a connection region of a thin film transistor and a pixel electrode in one pixel. .

A thin film transistor including a microcrystalline semiconductor film containing a metal element is more suitable for use in a driver circuit because the n-type has higher mobility than the p-type. In order to reduce the number of steps, it is desirable that all thin film transistors formed over the same substrate have the same polarity. Here, description is made using an n-channel thin film transistor.

  As shown in FIG. 1A, a gate electrode 51 is formed over a substrate 50, and gate insulating films 52 a and 52 b are formed over the gate electrode 51.

The substrate 50 is a heat-resistant material that can withstand the processing temperature in this manufacturing process, in addition to a non-alkali glass substrate manufactured by a fusion method or a float method, such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass, or a ceramic substrate. A plastic substrate or the like having the above can be used. Alternatively, a substrate in which an insulating film is provided on the surface of a metal substrate such as a stainless alloy may be used.

The gate electrode 51 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, or the like is applied. A preferred example of the gate electrode 301 and the capacitor electrode 302 is formed of aluminum or a stacked structure of aluminum and a barrier metal. As the barrier metal, a refractory metal such as titanium, molybdenum, or chromium is used. The barrier metal is preferably provided to prevent hillocks and oxidation of aluminum. Here, a molybdenum film is formed as a conductive film over the substrate 50 by a sputtering method, and the conductive film formed over the substrate 50 is etched using a mask pattern formed using a first photomask to form a gate electrode. Form.

The gate electrode 51 is formed with a thickness of 50 nm to 300 nm. By setting the thickness of the gate electrode 51 to 50 nm or more and 100 nm or less, it is possible to prevent disconnection of a semiconductor film or a wiring to be formed later. In addition, by setting the thickness of the gate electrode 51 to 150 nm or more and 300 nm or less, the resistance of the gate electrode 51 can be reduced, and the area can be increased.

  Note that since a semiconductor film or a wiring is formed over the gate electrode 51, it is desirable that the end portion be tapered so as to prevent disconnection. Although not shown, a wiring connected to the gate electrode can be formed at the same time in this step.

Each of the gate insulating films 52a and 52b can be formed using a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film by a CVD method, a sputtering method, or the like. Here, a mode in which a silicon nitride film or a silicon nitride oxide film is formed as the gate insulating film 52a and a silicon oxide film or a silicon oxynitride film is formed and stacked as the gate insulating film 52b is shown. Note that the gate insulating film is not formed in two layers, and the gate insulating film can be formed using a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film.

Further, the gate insulating film is formed of three layers, a silicon nitride film or a silicon nitride oxide film is formed over the gate electrode, a silicon oxide film or a silicon oxynitride film is formed thereon, and a thickness of 1 nm is formed thereon. A silicon nitride film or a silicon nitride oxide film having a thickness of about 5 nm can be formed.

As a method for forming the silicon nitride film, the silicon nitride layer can be formed on the surface of the gate insulating film 52b by nitriding the gate insulating film 52b using high-density plasma. It is also possible to obtain a silicon nitride layer containing a higher concentration of nitrogen by performing high density plasma nitridation. The high density plasma is generated by using a high frequency microwave, for example 2.45 GHz. Since high-density plasma characterized by low electron temperature has low kinetic energy of active species, it is possible to form a layer with less plasma damage and fewer defects than conventional plasma treatment. Further, since the surface roughness of the gate insulating film 52b can be reduced, carrier mobility can be increased.

By forming the gate insulating film 52a using a silicon nitride film or a silicon nitride oxide film, the adhesion between the substrate 50 and the gate insulating film 52a is increased. When a glass substrate is used as the substrate 50, impurities from the substrate 50 Can be prevented from diffusing into the microcrystalline semiconductor film, and the gate electrode 51 can be prevented from being oxidized. That is, film peeling can be prevented and electrical characteristics of a thin film transistor to be formed later can be improved. Further, it is preferable that each of the gate insulating films 52a and 52b has a thickness of 50 nm or more because reduction in coverage due to the unevenness of the gate electrode 51 can be reduced.

Here, the silicon oxynitride film has a composition that contains more oxygen than nitrogen and has a concentration range of 55 to 65 atomic%, 1 to 20 atomic%, and 25 Si. -35 atomic%, and hydrogen is contained in the range of 0.1-10 atomic%. The silicon nitride oxide film has a composition containing more nitrogen than oxygen, and the concentration ranges of oxygen are 15 to 30 atomic%, nitrogen is 20 to 35 atomic%, and Si is 25 to 25%. 35 atomic% and hydrogen are included in the range of 15 to 25 atomic%.

  Next, a microcrystalline semiconductor film 53 containing a metal element is formed over the 52b.

Here, a microcrystalline semiconductor film containing a metal element is formed over the gate insulating film 52b so that an amorphous layer is not formed at the interface with the surface of the gate insulating film 52b.

As one embodiment of a method for forming a microcrystalline semiconductor film containing a metal element, a microcrystalline semiconductor film is formed over the gate insulating film 52b after the surface of the gate insulating film 52b is exposed to plasma. At this time, a substrate on which the gate insulating film 52b is formed is provided in a plasma CVD apparatus having an electrode containing titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, platinum, or the like. Next, a voltage is applied to the electrode of the plasma CVD apparatus, and the surface of the gate insulating film 52b is subjected to plasma treatment, so that titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, platinum Are attached to the surface of the gate insulating film 52b. After that, a microcrystalline semiconductor film is formed using silane gas and hydrogen gas and / or rare gas, so that titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten attached on the gate insulating film 52b. Crystal nuclei are formed using a metal element such as cobalt, nickel, or platinum as a catalyst, and a microcrystalline semiconductor film is formed based on the crystal nuclei. As a result, an amorphous layer is not formed at the interface with the gate insulating film 52b, and a microcrystalline semiconductor film can be deposited over the gate insulating film.

Further, as another embodiment of the method for forming a microcrystalline semiconductor film containing a metal element, as a source gas, in addition to silane gas and hydrogen gas and / or rare gas, titanium, zirconium, hafnium, vanadium, niobium, tantalum, A gas containing a metal element such as chromium, molybdenum, tungsten, cobalt, nickel, or platinum is used. Typically, there are metal halide gases that are chlorides, bromides, or iodides of the above metal elements. For example, titanium chloride, titanium bromide, titanium iodide, tantalum chloride, tungsten bromide, nickel chloride, odor There are nickel chloride, cobalt chloride, cobalt bromide, chromium chloride, chromium iodide and the like. Or, there is an organometallic gas containing the above metal element, for example, nickel carbonyl, bismethylcyclopentaenyl nickel, biscyclopentagenyl nickel, methylcyclopentagenyl trimethyl platinum, tetraisopropoxy titanium, trimethyl titanium, niobium Examples include ethoxide and tantalum ethoxide.

Specifically, silicide is formed using a silane gas, a hydrogen gas and / or a rare gas, and a gas containing the above metal element. Next, a microcrystalline semiconductor film is formed using silicide as a crystal nucleus by forming a microcrystalline semiconductor film using a silane gas and a hydrogen gas and / or a rare gas. As a result, an amorphous layer is not formed at the interface with the gate insulating film 52b, and a microcrystalline semiconductor film can be deposited over the gate insulating film.

As another embodiment of a method for forming a microcrystalline semiconductor film containing a metal element, as illustrated in FIG. 2A, titanium, zirconium, hafnium, vanadium, niobium, tantalum, A layer 57 containing a metal element such as chromium, molybdenum, tungsten, cobalt, nickel, or platinum is formed. Next, a microcrystalline semiconductor film is formed using the film 57 containing a metal element as a crystal nucleus. As a result, a microcrystalline semiconductor film containing a metal element can be formed. The layer 57 containing a metal element can be formed in a thin film shape or a dot shape. The thickness of the layer 57 containing a metal element is preferably set such that silicide reacts with silane gas to form silicide and the off-state current of the thin film transistor does not flow so much. For example, the thickness is preferably 0.1 nm or more and 5 nm or less.

The film 57 containing a metal element is formed using a metal film or metal alloy film containing the metal element. In this case, a metal film or a metal alloy film can be formed by a thin film forming method such as a sputtering method, a vapor deposition method, or a CVD method. Alternatively, a solution containing any one or more of the above metal elements can be applied to the gate insulating film 52b and dried to form a metal film or a metal alloy film.

Further, as a film 57 containing a gold electrode element, a silicide layer of the above metal element (titanium silicide, zirconium silicide, hafnium silicide, vanadium silicide, niobium silicide, tantalum silicide, chromium silicide, molybdenum silicide, cobalt silicide, nickel silicide, platinum silicide) Etc.). In this case, a metal layer or a metal alloy layer and a semiconductor layer are stacked by a thin film formation method such as a sputtering method, a vapor deposition method, or a CVD method, and the stacked layer is subjected to heat treatment or laser beam irradiation, thereby forming a metal element. A silicide layer can be formed. As a stacked structure at this time, a semiconductor layer is formed after a metal layer or a metal alloy layer is formed over the gate insulating film. Alternatively, after a semiconductor layer is formed over the gate insulating film, a metal layer or a metal alloy layer is formed.

Alternatively, a solution containing any one or more of the above metal elements is applied over the gate insulating film 52b and dried to form a metal film or a metal alloy film, and then a semiconductor film is formed, and the semiconductor film is subjected to heat treatment or A metal element silicide film is formed by laser beam treatment. Alternatively, after a semiconductor film is formed over the gate insulating film 52b, a solution containing any one of the above metal elements is applied over the semiconductor layer and dried, the semiconductor film is subjected to heat treatment or laser beam treatment to form a silicide of the metal element. A film is formed.

Note that as the semiconductor film used for forming the silicide film, an amorphous semiconductor film or a microcrystalline semiconductor film can be formed. In addition, the thickness of the semiconductor film at this time may be thin as long as it reacts with the metal film or the metal alloy film to form silicide, and may be, for example, about 0.1 to 5 nm.

A microcrystalline semiconductor film containing a metal element includes a state in which the metal element remains at the interface with the gate insulating film, a state in which the metal element is distributed on the surface of the microcrystalline semiconductor film, and a metal element in the film. A state of being dispersed.

The concentration of the metal element contained in the microcrystalline semiconductor film containing the metal element is set so that carriers do not move through the microcrystalline semiconductor film when a thin film transistor to be formed later is off, that is, a concentration at which current does not flow through the thin film transistor. . For example, it is less than 1 × 10 ¹⁸ / cm ³ , preferably less than 1 × 10 ¹⁸ / cm ³ .

The microcrystalline semiconductor film here is a film including a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). This semiconductor is a semiconductor having a third state which is stable in terms of free energy, and is a crystalline one having a short-range order and having a lattice strain, and has a columnar or needle shape with a particle size of 0.5 to 20 nm. Crystals grow in the normal direction with respect to the substrate surface. In addition, a microcrystalline semiconductor and a non-single-crystal semiconductor are mixed. Microcrystalline silicon which is a typical example of a microcrystalline semiconductor has its Raman spectrum shifted to a lower frequency side than 520.5 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520.5 cm ⁻¹ representing single crystal silicon and 480 cm ⁻¹ representing amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability can be improved and a good microcrystalline semiconductor film can be obtained. A description of such a microcrystalline semiconductor film is disclosed in, for example, US Pat. No. 4,409,134.

The microcrystalline semiconductor film 53 containing a metal element is formed to be 1 nm to 200 nm thick, preferably 1 nm to 100 nm, preferably 1 nm to 50 nm. The microcrystalline semiconductor film 53 containing a metal element functions as a channel formation region of a thin film transistor to be formed later. By setting the thickness of the microcrystalline semiconductor film 53 containing a metal element to 1 nm to 50 nm, a thin film transistor to be formed later is a fully depleted type.

Here, a plasma CVD apparatus for forming a microcrystalline semiconductor film containing a metal element and a formation method using the same are described below.

FIG. 3 shows a configuration example of a plasma CVD apparatus. The reaction chamber 400 is formed of a rigid material such as aluminum or stainless steel, and is configured so that the inside can be evacuated. The reaction chamber 400 is provided with a first electrode 401 and a second electrode 402.

High-frequency power supply means 403 is connected to the first electrode 401, and the second electrode 402 is configured to be provided with a ground potential so that a substrate can be placed thereon. The first electrode 401 is insulated from the reaction chamber 400 by an insulating material 416 so that high-frequency power does not leak. In FIG. 3, the first electrode 401 and the second electrode 402 have a capacitively coupled (parallel plate) configuration, but glow discharge plasma is generated inside the reaction chamber 400 by applying high-frequency power. Other configurations such as an inductive coupling type can be applied as long as they can be generated.

The high frequency power supply means 403 includes a high frequency power supply 404 and a matching unit 406. A band pass filter may be provided on the output side of the matching unit 406 so that high frequency power does not flow.

The high frequency power supplied from the high frequency power supply 404 is generally applied with a high frequency of 10 m or more as a wavelength, and a frequency of 3 MHz to 30 MHz, typically 13.56 MHz, which is an HF band, is applied. Further, a high frequency with a wavelength of less than 10 m that is a frequency in the VHF band is applied, and a high frequency power of 30 MHz to 300 MHz may be applied.

The first electrode 101 is also connected to the gas supply means 408. The gas supply means 408 includes a cylinder 410 filled with a reaction gas, a pressure adjustment valve 411, a stop valve 412, a mass flow controller 413, and the like. In the reaction chamber 400, the surface facing the substrate of the first electrode 401 is processed into a shower plate shape, and a large number of pores are provided. The reaction gas supplied to the first electrode 401 is supplied into the reaction chamber 400 from this pore through the hollow structure inside.

The exhaust means 409 connected to the reaction chamber 400 includes vacuum exhaust and a function of controlling the inside of the reaction chamber 400 to a predetermined pressure when a reaction gas is flowed. The configuration of the exhaust unit 409 includes a butterfly valve 417, a conductance valve 418, a turbo molecular pump 419, a dry pump 420, and the like. When the butterfly valve 417 and the conductance valve 418 are arranged in parallel, the butterfly valve 417 is closed and the conductance valve 418 is operated to control the exhaust speed of the reaction gas so that the pressure in the reaction chamber 400 is within a predetermined range. Can keep. Further, high vacuum evacuation is possible by opening the butterfly valve 417 having a large conductance.

A substrate heater 414 whose temperature is controlled by the heater controller 415 is provided on the second electrode 402. When the substrate heater 414 is provided in the second electrode 402, a heat conduction heating method is adopted, and the substrate heater 414 is configured by a sheath heater or the like. A structure that is movable so that the height of the second electrode 402 can be adjusted is included so that the distance between the first electrode 401 and the second electrode 402 can be changed as appropriate.

Next, a method for forming a microcrystalline semiconductor film containing a metal element is described below. A substrate is placed on the second electrode 402 in the reaction chamber 400, and a silane gas and a hydrogen gas and / or a rare gas are mixed to form a film by glow discharge plasma. Silane gas is diluted 10 to 2000 times with hydrogen gas and / or rare gas. Therefore, a large amount of hydrogen and / or a rare gas is required. The heating temperature of the substrate is 100 ° C to 300 ° C, preferably 120 ° C to 220 ° C. In order to inactivate the growth surface of the microcrystalline silicon film with hydrogen and promote the growth of the microcrystalline silicon, the film formation is preferably performed at 120 ° C. to 220 ° C.

As shown in this embodiment, the glow discharge plasma is generated by applying high frequency power in the HF band of 3 MHz to 30 MHz, typically 13.56 MHz, or 30 MHz to 300 MHz in the VHF band. Is called.

Here, an electrode containing titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, platinum, or the like is used as the first electrode 401 in the reaction chamber 400, and a fine element containing a metal element is used. Before forming the crystalline semiconductor film, the high-frequency power supply is turned on and the surface of the gate insulating film 52b is subjected to plasma treatment, so that titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, platinum Are attached to the surface of the gate insulating film 52b. After that, a microcrystalline semiconductor film containing a metal element is formed without forming an amorphous layer at the interface with the gate insulating film 52b by forming a microcrystalline semiconductor film using a silane gas and a hydrogen gas and / or a rare gas. Can be deposited on the gate insulating film.

Alternatively, from the cylinder 410, a silane gas, a hydrogen gas, and / or a rare gas react with a gas containing a metal element such as titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, cobalt, nickel, or platinum. By introducing into the chamber 400, turning on the high-frequency power source and generating plasma, an amorphous layer is not formed at the interface with the gate insulating film 52b, and a microcrystalline semiconductor film containing a metal element is formed over the gate insulating film. Can be deposited on.

Alternatively, after a substrate on which the layer 57 containing a metal element is formed is placed over the second electrode 402 in the reaction chamber 400, a microcrystalline semiconductor film is formed using a silane gas, a hydrogen gas, and / or a rare gas. Thus, a microcrystalline semiconductor film containing a metal element can be deposited over the gate insulating film without forming an amorphous layer at the interface with the gate insulating film 52b.

Note that SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _4, or the like can be used instead of silane. In addition, carbon hydride such as CH ₄ and C ₂ H ₆ , germanium hydride such as GeH ₄ and GeF ₄ , and germanium fluoride are mixed in a gas such as silane, and the energy bandwidth is 1.5-2. It may be adjusted to .4 eV, or 0.9 to 1.1 eV. When carbon or germanium is added to silicon, the temperature characteristics of the thin film transistor can be changed.

In addition, since the microcrystalline semiconductor film exhibits weak n-type conductivity when an impurity element for the purpose of valence electron control is not intentionally added, the microcrystalline semiconductor film includes a metal element that functions as a channel formation region of a thin film transistor. The threshold value can be controlled by adding an impurity element imparting p-type conductivity to the semiconductor film at the same time as or after the film formation. The impurity element imparting p-type is typically boron, and an impurity gas such as B ₂ H ₆ or BF ₃ may be mixed into silicon hydride at a rate of 1 ppm to 1000 ppm, preferably 1 to 100 ppm. . The boron concentration is preferably 1 × 10 ^{14 to} 6 × 10 ¹⁶ atoms / cm ³ , for example.

In addition, the oxygen concentration of the microcrystalline semiconductor film is 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and the nitrogen and carbon concentrations are 3 × 10 ¹⁸ atoms / cm ³ or less. It is preferable that By reducing the concentration of oxygen, nitrogen, and carbon in the microcrystalline semiconductor film, the microcrystalline semiconductor film can be prevented from becoming n-type.

An enlarged view of the interface between the conventional gate insulating film and the microcrystalline semiconductor film is shown in FIG. 4A, and an enlarged view of the interface between the gate insulating film and the microcrystalline semiconductor film containing the metal element of this embodiment is shown in FIG. Shown in B). In the conventional method for forming a microcrystalline semiconductor film, as shown in FIG. 4A, an amorphous layer 49 is formed in an initial deposition stage due to factors such as impurities and lattice mismatch. In a thin film transistor, carriers flow in a microcrystalline semiconductor film in the vicinity of a gate insulating film. Therefore, when an amorphous layer 49 is formed at an interface, mobility is decreased, current amount is small, and electrical characteristics of the thin film transistor are reduced. It will decline.

However, by forming the microcrystalline semiconductor film 53 containing a metal element over the gate insulating film 52b, a metal silicide that is a reaction product of the metal element and silicon is formed, and the microcrystalline semiconductor film is formed using the metal silicide as a seed. Therefore, the crystallinity in the thickness direction of the film can be improved and the crystallinity of the interface between the gate insulating film and the microcrystalline semiconductor film can be improved (see FIG. 4B).

In addition, since the microcrystalline semiconductor film 53 is formed using microcrystals, its resistance is lower than that of an amorphous semiconductor film. Therefore, in the thin film transistor using the microcrystalline semiconductor film 53, the slope of the rising portion of the curve indicating the current-voltage characteristics is steep, so that the response as a switching element is excellent and high-speed operation is possible. In addition, by using the microcrystalline semiconductor film 53 in a channel formation region of the thin film transistor, variation in threshold value of the thin film transistor can be suppressed. Therefore, a display device with little variation in electrical characteristics can be manufactured.

In addition, the microcrystalline semiconductor film 53 has higher mobility than an amorphous semiconductor film. Therefore, the area of the channel formation region, that is, the area of the thin film transistor can be reduced by using a thin film transistor in which the channel formation region is formed using the microcrystalline semiconductor film 53 for switching the display element. Therefore, the area of the thin film transistor shown per pixel is reduced, and the aperture ratio of the pixel can be increased. As a result, a display device with high resolution can be manufactured.

Further, the microcrystalline semiconductor film 53 containing a metal element may be etched to reduce the thickness of the microcrystalline semiconductor film 53 containing a metal element. When the thickness of the microcrystalline semiconductor film 53 containing a metal element is 1 nm to 50 nm, a fully depleted thin film transistor can be manufactured.

Next, as illustrated in FIG. 1B, a buffer layer 54 and a semiconductor film 55 to which an impurity imparting one conductivity type is added are formed over the microcrystalline semiconductor film 53. Next, a mask pattern 56 is formed over the semiconductor film 55 to which an impurity imparting one conductivity type is added.

The buffer layer 54 can be formed by a plasma CVD method using silane gas. Alternatively, the amorphous semiconductor film can be formed by diluting the silane gas with one or more kinds of rare gas elements selected from helium, argon, krypton, and neon. An amorphous semiconductor film containing hydrogen can be formed using hydrogen at a flow rate of 1 to 10 times, more preferably 1 to 5 times the flow rate of silane gas. Further, halogen such as fluorine, chlorine, bromine, or iodine, or nitrogen may be added to the hydrogenated semiconductor film.

The buffer layer 54 can be formed using an amorphous semiconductor as a target by sputtering with hydrogen or a rare gas to form an amorphous semiconductor film.

The buffer layer 54 is preferably formed using an amorphous semiconductor film that does not include crystal grains. For this reason, when forming by a high frequency plasma CVD method or a microwave plasma CVD method with a frequency of several tens to several hundreds of MHz, the film formation conditions are controlled so that the amorphous semiconductor film does not contain crystal grains. It is preferable to do.

The buffer layer 54 may be partially etched in a later formation process of the source region and the drain region, but it is preferable to form the buffer layer 54 with such a thickness that a part of the buffer layer 54 remains at that time. Typically, it is preferably formed with a thickness of 100 nm to 500 nm, preferably 200 nm to 300 nm. In a display device with a high applied voltage of the thin film transistor (for example, about 15 V), typically a liquid crystal display device, when the buffer layer 54 is formed thick as shown in the above range, the withstand voltage increases, and a high voltage is applied to the thin film transistor. Even if it is applied, deterioration of the thin film transistor can be avoided.

By forming an amorphous semiconductor film and further an amorphous semiconductor film containing hydrogen, nitrogen, or halogen over the surface of the microcrystalline semiconductor film 53 containing a metal element, crystal grains contained in the microcrystalline semiconductor film 53 It is possible to prevent the natural oxidation of the surface. In particular, in a region where an amorphous semiconductor is in contact with microcrystalline grains, cracks are likely to occur due to local stress. When this crack comes into contact with oxygen, the crystal grains are oxidized and silicon oxide is formed. However, by forming the buffer layer 54 on the surface of the microcrystalline semiconductor film 53 containing a metal element, oxidation of the microcrystalline grains can be prevented.

In addition, since the buffer layer 54 is formed using an amorphous semiconductor film or an amorphous semiconductor film containing hydrogen, nitrogen, or halogen, the energy gap is larger than that of the microcrystalline semiconductor film 53. In addition, the resistance is high and the mobility is as low as 1/5 to 1/10 that of the microcrystalline semiconductor film 53 containing a metal element. Therefore, in a thin film transistor to be formed later, a buffer layer formed between a source region and a drain region and a microcrystalline semiconductor film 53 containing a metal element functions as a high resistance region, and the microcrystalline semiconductor containing a metal element The film 53 functions as a channel formation region. Therefore, off current of the thin film transistor can be reduced. When the thin film transistor is used as a switching element of a display device, the contrast of the display device can be improved.

Note that after the microcrystalline semiconductor film 53 containing a metal element is formed, the buffer layer 54 is preferably formed at a temperature of 300 ° C. to 400 ° C. by a plasma CVD method. By this film formation treatment, hydrogen is supplied to the microcrystalline semiconductor film 53 containing a metal element, and an effect equivalent to that obtained by hydrogenating the microcrystalline semiconductor film 53 containing a metal element is obtained. That is, by depositing the buffer layer 54 over the microcrystalline semiconductor film 53 containing a metal element, hydrogen can be diffused into the microcrystalline semiconductor film 53 so that dangling bonds can be terminated.

The semiconductor film 55 to which an impurity imparting one conductivity type is added may be formed by adding phosphorus as a typical impurity element when an n-channel thin film transistor is formed. Impurities such as PH ₃ are added to silicon hydride. Add gas. In the case of forming a p-channel thin film transistor, boron may be added as a typical impurity element, and an impurity gas such as B ₂ H ₆ may be added to silicon hydride. The semiconductor film 55 to which an impurity imparting one conductivity type is added can be formed using a microcrystalline semiconductor film body or an amorphous semiconductor. The semiconductor film 55 to which an impurity imparting one conductivity type is added is formed with a thickness of 2 nm to 50 nm. By reducing the thickness of the semiconductor film to which an impurity imparting one conductivity type is added, throughput can be improved.

  The mask pattern 56 is formed by a photolithography technique. Here, using a second photomask, a resist applied to the semiconductor film 55 to which an impurity imparting one conductivity type is added is exposed and developed to form a mask pattern 56.

Next, the microcrystalline semiconductor film 53, the buffer layer 54, and the semiconductor film 55 to which an impurity imparting conductivity is added are etched and separated using the mask pattern 56, and as shown in FIG. A microcrystalline semiconductor film 61, a buffer layer 62, and a semiconductor film 63 to which an impurity imparting a conductivity type is added are formed. Thereafter, the mask pattern 56 is removed. Note that FIG. 1C (excluding the mask pattern 56) corresponds to a cross-sectional view taken along a line AB in FIG.

Since the side surfaces of the end portions of the microcrystalline semiconductor film 61 and the buffer layer 62 are inclined, leakage current is prevented from being generated between the source region and the drain region formed over the buffer layer 62 and the microcrystalline semiconductor film 61. Is possible. In addition, leakage current can be prevented from being generated between the wiring layer and the microcrystalline semiconductor film 61. The inclination angles of the side surfaces of the end portions of the microcrystalline semiconductor film 61 and the buffer layer 62 are 90 ° to 30 °, preferably 80 ° to 45 °. By setting such an angle, disconnection of the wiring layer due to the step shape can be prevented.

Next, as illustrated in FIG. 5A, conductive films 65a to 65c are formed over the semiconductor film 63 to which an impurity imparting conductivity is added and the gate insulating film 52b, and masks are formed over the conductive films 65a to 65c. A pattern 66 is formed. The conductive films 65a to 65c are preferably formed using a single layer or a stacked layer of aluminum or an aluminum alloy to which a heat resistance improving element such as copper, silicon, titanium, neodymium, scandium, or molybdenum or a hillock preventing element is added. In addition, a film in contact with a semiconductor film to which an impurity imparting one conductivity type is added is formed using titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, and aluminum or an aluminum alloy is formed thereover. It is good also as a laminated structure. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed. Here, a conductive film having a structure in which three layers of conductive films 65a to 65c are stacked is shown as the conductive film. A laminated conductive film using a titanium film as the films 65a and 65c and an aluminum film as the conductive film 65b is shown. The conductive films 65a to 65c are formed by a sputtering method or a vacuum evaporation method.

The mask pattern 66 can be formed in the same manner as the mask pattern 56.

Next, as illustrated in FIG. 5B, part of the conductive films 65a to 65c is etched to form a pair of wiring layers 71a to 71c (functioning as a source electrode and a drain electrode). Here, when the conductive films 65a to 65c are wet-etched using the mask pattern 66 formed by a photolithography process using a third photomask, the ends of the conductive films 65a to 65c are selectively etched. As a result, the wiring layers 71a to 71c having a smaller area than the mask pattern 66 can be formed.

Next, using the mask pattern 66, the semiconductor film 63 to which an impurity imparting one conductivity type is added is etched and separated. As a result, a pair of source and drain regions 72 as shown in FIG. 5C can be formed. Note that part of the buffer layer 62 is also etched in the etching step. A buffer layer partially etched and having a recess is referred to as a buffer layer 73. The step of forming the source region and the drain region and the concave portion of the buffer layer can be formed in the same step. By setting the depth of the concave portion of the buffer layer to 1/2 to 1/3 of the thickest region of the buffer layer, the distance between the source region and the drain region can be increased. Leakage current between the drain regions can be reduced. Thereafter, the mask pattern 66 is removed.

Note that FIG. 5C (excluding the mask pattern 66) corresponds to a cross-sectional view taken along a line AB in FIG. As shown in FIG. 7B, it can be seen that the end portions of the source region and the drain region 72 are located outside the end portion of the wiring layer 71c. Further, the end portion of the buffer layer 73 is located outside the end portions of the wiring layer 71 c and the source and drain regions 72. One of the wiring layers has a shape surrounding the other of the source region and the drain region (specifically, a U shape or a C shape). Therefore, the area of the region where carriers move can be increased, so that the amount of current can be increased and the area of the thin film transistor can be reduced. In addition, since the microcrystalline semiconductor film and the wiring layer are overlapped over the gate electrode, the influence of the unevenness of the gate electrode is small, so that coverage can be reduced and leakage current can be suppressed.

  Through the above process, a channel-etched thin film transistor 74 can be formed.

Next, as illustrated in FIG. 6A, a protective insulating film 76 is formed over the wiring layers 71a to 71c, the source and drain regions 72, the buffer layer 73, the microcrystalline semiconductor film 61, and the gate insulating film 52b. . The protective insulating film 76 can be formed in the same manner as the gate insulating films 52a and 52b. Note that the protective insulating film 76 is for preventing intrusion of contaminant impurities such as organic substances, metal substances, and water vapor floating in the air, and is preferably a dense film. In addition, by using a silicon nitride film for the protective insulating film 76, the oxygen concentration in the buffer layer 87 can be 5 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁹ atoms / cm ³ or less. The oxidation of the buffer layer 87 can be prevented.

Next, a part of the protective insulating film 76 is etched using a mask pattern formed using a fourth photomask on the protective insulating film 76 to form a contact hole, and the pixel in contact with the wiring layer 75c in the contact hole. An electrode 77 is formed. Note that FIG. 6B corresponds to a cross-sectional view taken along a line AB in FIG.

The pixel electrode 77 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, and silicon oxide. A light-transmitting conductive material such as indium tin oxide can be used.

The pixel electrode 77 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

Here, as the pixel electrode 77, an ITO film is formed by a sputtering method, and then a resist is applied on the ITO. Next, the resist is exposed and developed using a fifth photomask to form a mask pattern. Next, the pixel electrode 77 is formed by etching the ITO using the mask pattern.

Through the above steps, a thin film transistor and an element substrate that can be used for a display device can be formed.

  Next, a method for manufacturing a thin film transistor, which is different from the above mode, is described with reference to FIGS. Here, a process for manufacturing a thin film transistor using a process capable of reducing the number of photomasks from the above mode is described.

As in FIGS. 1A and 1B, a conductive film is formed over the substrate 50, a resist is applied over the conductive film, and a mask pattern is formed by a photolithography process using a first photomask. The gate electrode 51 is formed by etching a part of the conductive film using Next, as illustrated in FIG. 8A, gate insulating films 52 a and 52 b and a microcrystalline semiconductor film 53 containing a metal element are formed over the gate electrode 51 in this order. Next, a buffer layer 54, a semiconductor film 55 to which an impurity imparting one conductivity type is added, and conductive films 65a to 65c are formed in this order over the microcrystalline semiconductor film 53 containing a metal element. Next, a resist 80 is applied over the conductive film 65a.

As the resist 80, a positive resist or a negative resist can be used. Here, a positive resist is used.

Next, the resist 80 is exposed to light by irradiating the resist 80 with light using the multi-tone mask 59 as a second photomask.

Here, exposure using the multi-tone mask 59 will be described with reference to FIG.

  A multi-tone mask is a mask capable of performing three exposure levels on an exposed portion, an intermediate exposed portion, and an unexposed portion, and a plurality of (typically two types) can be obtained by one exposure and development process. It is possible to form a mask pattern having a region with a thickness of. Therefore, the number of photomasks can be reduced by using a multi-tone mask.

Typical examples of the multi-tone mask include a gray-tone mask 59a as shown in FIG. 9A and a half-tone mask 59b as shown in FIG. 9C.

As shown in FIG. 9A, the gray tone mask 59a includes a light-transmitting substrate 163, a light shielding portion 164 and a diffraction grating 165 formed thereon. In the light shielding portion 164, the amount of transmitted light is 0%. On the other hand, the diffraction grating 165 can control the amount of transmitted light by setting the interval between the light transmitting portions such as slits, dots, and meshes to be equal to or less than the resolution limit of the light used for exposure. Note that the diffraction grating 165 can use either a periodic slit, a dot, or a mesh, or an aperiodic slit, dot, or mesh.

As the substrate 163 having a light-transmitting property, a substrate having a light-transmitting property such as quartz can be used. The light shielding portion 164 and the diffraction grating 165 can be formed using a light shielding material that absorbs light such as chromium or chromium oxide.

When the gray-tone mask 59a is irradiated with exposure light, as shown in FIG. 9B, the light transmission amount 166 is 0% in the light shielding portion 164, and the light shielding portion 164 and the diffraction grating 165 are not provided. In the region, the light transmission amount 166 is 100%. The diffraction grating 165 can be adjusted in the range of 10 to 70%. The light transmission amount in the diffraction grating 165 can be adjusted by adjusting the interval and pitch of slits, dots, or meshes of the diffraction grating.

As shown in FIG. 9C, the halftone mask 59b includes a light-transmitting substrate 163, a semi-transmissive portion 167 and a light shielding portion 168 formed thereon. For the semi-transmissive portion 167, MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like can be used. The light shielding portion 168 can be formed using a light shielding material that absorbs light, such as chromium or chromium oxide.

When the halftone mask 59b is irradiated with exposure light, as shown in FIG. 9D, in the light shielding portion 168, the light transmission amount 169 is 0%, and the light shielding portion 168 and the semi-transmissive portion 167 are provided. In the absence region, the light transmission amount 169 is 100%. Moreover, in the semi-transmissive part 167, it can adjust in 10 to 70% of range. The amount of light transmitted through the semi-transmissive portion 167 can be adjusted by adjusting the material of the semi-transmissive portion 167.

By developing after exposure using a multi-tone mask, a mask pattern 81 having regions with different thicknesses can be formed as shown in FIG. 8B.

Next, the microcrystalline semiconductor film 53 containing a metal element, the buffer layer 54, the semiconductor film 55 to which an impurity imparting one conductivity type is added, and the conductive films 65a to 65c are etched and separated by the mask pattern 81. As a result, as shown in FIG. 10A, a microcrystalline semiconductor film 61 containing a metal element, a buffer layer 62, a semiconductor film 63 to which an impurity imparting one conductivity type is added, and conductive films 85a to 85c are formed. can do. Note that FIG. 10A (excluding the mask pattern 81) corresponds to a cross-sectional view taken along a line AB in FIG.

  Next, the mask pattern 81 is ashed. As a result, the resist area is reduced and the thickness is reduced. At this time, the resist in a thin region (a region overlapping with part of the gate electrode 51) is removed, and a separated mask pattern 86 can be formed as shown in FIG.

Next, using the mask pattern 86, the conductive films 85a to 85c are etched and separated. As a result, a pair of wiring layers 92a to 92c as shown in FIG. 10B can be formed. When the conductive films 89a to 89c are wet-etched using the mask pattern 86, the ends of the conductive films 89a to 89c are selectively etched. As a result, the wiring layers 92 a to 92 c having a smaller area than the mask pattern 86 can be formed.

  Next, using the mask pattern 86, the semiconductor film 63 to which an impurity imparting one conductivity type is added is etched, so that a pair of source and drain regions 88 is formed. Note that part of the buffer layer 62 is also etched in the etching step. The partially etched buffer layer is referred to as a buffer layer 87. A concave portion is formed in the buffer layer 87. The step of forming the source region and the drain region and the depression (groove) of the buffer layer can be formed in the same step. Here, a part of the buffer layer 87 is partly etched by the mask pattern 86 whose area is reduced as compared with the mask pattern 81, so that the buffer layer 87 protrudes outside the source region and the drain region 88. . Thereafter, the mask pattern 86 is removed. In addition, the end portions of the wiring layers 92a to 92c and the end portions of the source region and the drain region 88 are not coincident with each other, and the end portions of the source region and the drain region 88 are located outside the end portions of the wiring layers 92a to 92c. Is formed.

As shown in FIG. 10C, the end portions of the wiring layers 92a to 92c and the end portions of the source region and the drain region 88 are not coincident with each other. Since the distance is increased, it is possible to prevent a leakage current or a short circuit between the wiring layers. Therefore, a highly reliable thin film transistor can be manufactured.

  Through the above process, a channel-etched thin film transistor 83 can be formed. In addition, a thin film transistor can be formed using two photomasks.

Next, as illustrated in FIG. 11A, a protective insulating film 76 is formed over the wiring layers 92a to 92c, the source and drain regions 88, the buffer layer 87, the microcrystalline semiconductor film 90, and the gate insulating film 52b. . The protective insulating film 76 can be formed in the same manner as the gate insulating films 52a and 52b.

Next, a part of the protective insulating film 76 is etched using a mask pattern formed using a third photomask to form a contact hole. Next, the pixel electrode 77 in contact with the wiring layer 75c in the contact hole is formed. Here, as the pixel electrode 77, an ITO film is formed by a sputtering method, and then a resist is applied on the ITO. Next, the resist is exposed and developed using a fourth photomask to form a mask pattern. Next, the pixel electrode 77 is formed by etching the ITO using the mask pattern. Note that FIG. 11B corresponds to a cross-sectional view taken along a line AB in FIG.

Through the above, a thin film transistor and an element substrate that includes the thin film transistor and can be used for a display device can be formed.

5B or 10B, after the wiring layers 92a to 92c are formed, the mask pattern 86 is removed, and an impurity imparting one conductivity type is added using the wiring layers 92a to 92c as a mask. The semiconductor film 63 may be etched. As a result, a thin film transistor can be formed in which the wiring layers 71a to 71c and the end portions of the source region and the drain region 88 coincide. Here, after the mask pattern 86 in FIG. 5B is removed, the semiconductor film 63 to which an impurity imparting one conductivity type is added is etched using the wiring layers 92a to 92c as a mask to form a source region and a drain region. FIG. 13B shows a thin film transistor in which the end portion 89 and the end portions of the wiring layers 92a to 92c are aligned.

Through the above process, a channel-etched thin film transistor can be formed. A channel-etched thin film transistor has a small number of manufacturing steps and can reduce costs. Further, field effect mobility of 1 to ²⁰ cm ² / V · sec can be obtained by forming a channel formation region using a microcrystalline semiconductor film. Therefore, this thin film transistor can be used as an element for switching a pixel in the pixel portion and an element for forming a driving circuit on the scanning line (gate line) side.

Note that although a channel-etched thin film transistor is described in this embodiment mode, a microcrystalline semiconductor film containing a metal element can be used for a channel formation region of the channel protective thin film transistor.

According to this embodiment mode, a highly reliable thin film transistor with excellent electrical characteristics and a display substrate including the thin film transistor can be manufactured.

(Embodiment 2)
In this embodiment, a liquid crystal display device including the thin film transistor described in Embodiment 1 as one embodiment of the display device is described below. Here, a vertical alignment (VA) liquid crystal display device will be described with reference to FIGS. The VA liquid crystal display device is a type of a method for controlling the alignment of liquid crystal molecules in a liquid crystal panel. The VA liquid crystal display device is a method in which liquid crystal molecules face a vertical direction with respect to a panel surface when no voltage is applied. In the present embodiment, the pixel (pixel) is divided into several regions (sub-pixels), and each molecule is devised to tilt the molecules in different directions. This is called multi-domain or multi-domain design. In the following description, a liquid crystal display device considering multi-domain design will be described.

  14 and 15 show the pixel structure of the VA liquid crystal panel. FIG. 15 is a plan view of the substrate 600, and FIG. 14 shows a cross-sectional structure corresponding to the cutting line YZ shown in the drawing. The following description will be given with reference to both the drawings.

  In this pixel structure, one pixel has a plurality of pixel electrodes, and a thin film transistor is connected to each pixel electrode through a planarization film 622. Each thin film transistor is configured to be driven by a different gate signal. In other words, a multi-domain designed pixel has a configuration in which signals applied to individual pixel electrodes are controlled independently.

  The pixel electrode 624 is connected to the thin film transistor 628 through a wiring 618 in the contact hole 623. The pixel electrode 626 is connected to the thin film transistor 629 through a wiring 619 in a contact hole 627. The gate wiring 602 of the thin film transistor 628 and the gate wiring 603 of the thin film transistor 629 are separated so that different gate signals can be given. On the other hand, the wiring 616 functioning as a data line is used in common for the thin film transistor 628 and the thin film transistor 629. The thin film transistor 628 and the thin film transistor 629 can be manufactured using the method described in Embodiment 1.

  The pixel electrode 624 and the pixel electrode 626 have different shapes and are separated by a slit 625. A pixel electrode 626 is formed so as to surround the outside of the V-shaped pixel electrode 624. The timing of the voltage applied to the pixel electrode 624 and the pixel electrode 626 is different depending on the thin film transistor 628 and the thin film transistor 629, thereby controlling the alignment of the liquid crystal. When the gate wiring 602 and the gate wiring 603 are supplied with different gate signals, operation timings of the thin film transistor 628 and the thin film transistor 629 can be different. An alignment film 646 is formed over the pixel electrodes 624 and 626.

  A counter substrate 601 is provided with a light shielding film 632, a second coloring film 636, and a counter electrode 640. In addition, a planarization film 637 is formed between the second coloring film 636 and the counter electrode 640 to prevent alignment disorder of the liquid crystal. In addition, an alignment film 646 is formed over the counter electrode 640. FIG. 16 shows a structure on the counter substrate side. The counter electrode 640 is a common electrode between different pixels, but a slit 641 is formed. By disposing the slits 641 and the pixel electrodes 624 and the slits 625 on the pixel electrode 626 side so as to alternately engage with each other, an oblique electric field can be effectively generated to control the alignment of the liquid crystal. Thereby, the direction in which the liquid crystal is aligned can be varied depending on the location, and the viewing angle is widened.

The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 overlap with each other, so that a first liquid crystal element is formed. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 overlap with each other, so that a second liquid crystal element is formed. In addition, the multi-domain structure in which the first liquid crystal element and the second liquid crystal element are provided in one pixel.

Note that although a VA (Vertical Alignment) liquid crystal display device is shown here as the liquid crystal display device, an element substrate formed using Embodiment Mode 1 is used as an FFS liquid crystal display device or an IPS liquid crystal display. It can be used for a device, a TN liquid crystal display device, and other liquid crystal display devices.

Through the above process, a liquid crystal display device can be manufactured. Since the liquid crystal display device in this embodiment uses a thin film transistor with low off-state current, excellent electrical characteristics, and high reliability, a liquid crystal display device with high contrast and high visibility can be manufactured.

(Embodiment 3)
In this embodiment, as one embodiment of the display device, a light-emitting display device including the thin film transistor described in Embodiment 1 is described below. Here, a structure of a pixel included in the light-emitting display device is described. FIG. 17A illustrates one mode of a top view of a pixel, and FIG. 17C illustrates one mode of a cross-sectional structure of a pixel corresponding to AB in FIG. 17A.

Here, the light-emitting device is described using a light-emitting element utilizing electroluminescence. A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element. Here, Embodiment Mode 1 can be used as a manufacturing process of a thin film transistor.

  In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing the light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element. In addition, although a thin film transistor for switching for controlling input of a signal to the pixel electrode and a thin film transistor for controlling driving of the light emitting element are illustrated using a channel etch type thin film transistor, a channel protection type thin film transistor is appropriately used. be able to.

  In FIGS. 17A to 17C, the first thin film transistor 74a is a switching thin film transistor for controlling the input of a signal to the pixel electrode, and the second thin film transistor 74b is a current to the light emitting element 94. Alternatively, this corresponds to a driving thin film transistor for controlling supply of voltage.

The gate electrode of the first thin film transistor 74a is connected to the scanning line 51a, one of the source or drain is connected to the signal lines 71a to 71c, and the other of the source or drain is connected to the gate electrode 51b of the second thin film transistor 74b. One of the source and the drain of the second thin film transistor 74b is connected to the power supply lines 93a to 93c, and the other of the source and the drain is connected to the pixel electrode 79 of the display device. The capacitor element 96 includes the gate electrode, the gate insulating film, and the power supply line 93 a of the second thin film transistor 74 b, and the other of the source and the drain of the first thin film transistor 74 a is connected to the capacitor element 96.

Note that the capacitor 96 is a capacitor for holding the gate / source voltage or the gate / drain voltage (hereinafter referred to as gate voltage) of the second thin film transistor 74b when the first thin film transistor 74a is off. It is not necessary to provide it.

In this embodiment, the first thin film transistor 74a and the second thin film transistor 74b can be formed using Embodiment 1. The first thin film transistor 74a and the second thin film transistor 74b are formed using n-channel thin film transistors here, but the first thin film transistor 74a is formed using an n-channel thin film transistor and the second thin film transistor 74b is formed using a p-channel thin film transistor. It may be formed. Further, the first thin film transistor 74a and the second thin film transistor 74b may be formed using p-channel thin film transistors.

A protective insulating film 76 is formed over the first thin film transistor 74 a and the second thin film transistor 74 b, a planarizing film 78 is formed over the protective insulating film 76, and contact holes formed in the planarizing film 78 and the protective insulating film 65. The cathode 79 connected to the wiring 64c is formed. The planarizing film 78 is preferably formed using an organic resin such as acrylic, polyimide, or polyamide, or a siloxane polymer. In the contact hole, since the cathode 79 has unevenness, a partition wall 91 that covers the region and has an opening is provided. A light emitting layer 92 is formed so as to be in contact with the cathode 79 in the opening of the partition wall 91, an anode 93 is formed so as to cover the light emitting layer 92, and a protective insulating film 95 is formed so as to cover the anode 93 and the partition wall 91. .

Here, a light emitting element 94 having a top emission structure is shown as the light emitting element. Since the light-emitting element 94 having a top emission structure can emit light even on the first thin film transistor 74a and the second thin film transistor 74b, the light-emitting area can be increased. However, if the base film of the light emitting layer 92 has unevenness, the film thickness distribution is uneven in the unevenness, and the anode 93 and the cathode 79 are short-circuited, resulting in a display defect. For this reason, it is preferable to provide the planarization film 78.

  A region where the light emitting layer 92 is sandwiched between the cathode 79 and the anode 93 corresponds to the light emitting element 94. In the case of the pixel shown in FIG. 17A, light emitted from the light emitting element 94 is emitted to the anode 93 side as indicated by a white arrow.

A known material can be used for the cathode 79 as long as it has a small work function and reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. The light emitting layer 92 may be composed of a single layer or may be composed of a plurality of layers stacked. In the case of a plurality of layers, the cathode 79 is laminated in the order of an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer. Note that it is not necessary to provide all of these layers. The anode 93 is formed using a light-transmitting conductive material, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide. A light-transmitting conductive conductive film such as indium tin oxide containing ITO, ITO, indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used.

Here, a light emitting element having a top emission structure in which light emission is extracted from a surface opposite to the substrate is shown; however, a light emitting element having a bottom emission structure in which light emission is extracted from a surface on the substrate side, or a substrate side and a side opposite to the substrate. A light-emitting element having a dual emission structure in which light is extracted from a surface can be used as appropriate.

Although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

  Note that in this embodiment mode, an example in which a thin film transistor (driving thin film transistor) that controls driving of a light emitting element and the light emitting element are electrically connected is shown; however, current control is performed between the driving thin film transistor and the light emitting element. The thin film transistor may be connected.

Through the above process, a light-emitting display device can be manufactured. Since the light-emitting device of this embodiment uses a thin film transistor with low off-state current, excellent electrical characteristics, and high reliability, a light-emitting display device with high contrast and high visibility can be manufactured.

(Embodiment 4)
Next, a structure of a display panel which is one embodiment of the display device of the present invention is described below.

  FIG. 18 illustrates a mode of a display panel in which only the signal line driver circuit 6013 is separately formed and connected to the pixel portion 6012 formed over the substrate 6011. The pixel portion 6012 and the scan line driver circuit 6014 are formed using a thin film transistor including a microcrystalline semiconductor film containing a metal element. By forming a signal line driver circuit using a transistor with higher mobility than a thin film transistor using a microcrystalline semiconductor film containing a metal element, a signal line driver circuit that requires a higher driving frequency than a scanning line driver circuit is used. The operation can be stabilized. Note that the signal line driver circuit 6013 may be a transistor using a single crystal semiconductor, a thin film transistor using a polycrystalline semiconductor, or a transistor using SOI. The pixel portion 6012, the signal line driver circuit 6013, and the scan line driver circuit 6014 are supplied with a potential of a power source, various signals, and the like through the FPC 6015.

  Note that both the signal line driver circuit and the scan line driver circuit may be formed over the same substrate as the pixel portion.

  In the case where a driver circuit is separately formed, the substrate on which the driver circuit is formed is not necessarily bonded to the substrate on which the pixel portion is formed, and may be bonded to, for example, an FPC. FIG. 18B illustrates a mode of a display device panel in which only the signal line driver circuit 6023 is separately formed and connected to the pixel portion 6022 and the scan line driver circuit 6024 which are formed over the substrate 6021. The pixel portion 6022 and the scan line driver circuit 6024 are formed using a thin film transistor including a microcrystalline semiconductor film containing a metal element. The signal line driver circuit 6023 is connected to the pixel portion 6022 through the FPC 6025. The pixel portion 6022, the signal line driver circuit 6023, and the scan line driver circuit 6024 are supplied with power supply potential, various signals, and the like through the FPC 6025.

  Further, only part of the signal line driver circuit or part of the scan line driver circuit is formed over the same substrate as the pixel portion by using a thin film transistor using a microcrystalline semiconductor film containing a metal element, and the rest is separately formed. Thus, it may be electrically connected to the pixel portion. In FIG. 18C, an analog switch 6033a included in the signal line driver circuit is formed over the same substrate 6031 as the pixel portion 6032 and the scan line driver circuit 6034, and a shift register 6033b included in the signal line driver circuit is provided over a different substrate. The form of the display device panel formed and bonded is shown. The pixel portion 6032 and the scan line driver circuit 6034 are formed using a thin film transistor using a microcrystalline semiconductor film containing a metal element. A shift register 6033 b included in the signal line driver circuit is connected to the pixel portion 6032 through the FPC 6035. A potential of a power source, various signals, and the like are supplied to the pixel portion 6032, the signal line driver circuit, and the scan line driver circuit 6034 through the FPC 6035, respectively.

  As shown in FIG. 18, in the display device of this embodiment, part or all of the driver circuit is formed using a thin film transistor including a microcrystalline semiconductor film containing a metal element over the same substrate as the pixel portion. be able to.

  Note that a method for connecting a separately formed substrate is not particularly limited, and a known COG method, wire bonding method, TAB method, or the like can be used. The connection position is not limited to the position illustrated in FIG. 18 as long as electrical connection is possible. In addition, a controller, a CPU, a memory, and the like may be separately formed and connected.

  Note that the signal line driver circuit used in the present invention includes a shift register and an analog switch. Alternatively, in addition to the shift register and the analog switch, other circuits such as a buffer, a level shifter, and a source follower may be included. The shift register and the analog switch are not necessarily provided. For example, another circuit that can select a signal line such as a decoder circuit may be used instead of the shift register, or a latch or the like may be used instead of the analog switch. May be.

(Embodiment 5)
The display device obtained by the present invention can be used for an active matrix display device panel. That is, the present invention can be implemented in all electronic devices in which they are incorporated in the display portion.

  Such electronic devices include cameras such as video cameras and digital cameras, head mounted displays (goggles type displays), car navigation, projectors, car stereos, personal computers, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) ) And the like. An example of these is shown in FIG.

  FIG. 19A illustrates a television device. As shown in FIG. 19A, a television device can be completed by incorporating the display panel into a housing. A main screen 2003 is formed by the display panel, and a speaker portion 2009, operation switches, and the like are provided as other accessory equipment. In this manner, a television device can be completed.

  As shown in FIG. 19A, a display panel 2002 using a display element is incorporated in a housing 2001, and the receiver 2005 starts reception of general television broadcasts and is wired or wirelessly via a modem 2004. By connecting to a communication network, information communication in one direction (from the sender to the receiver) or in both directions (between the sender and the receiver or between the receivers) can be performed. The television device can be operated by a switch incorporated in the housing or a separate remote controller 2006, and this remote controller is also provided with a display unit 2007 for displaying information to be output. Also good.

  In addition, the television device may have a configuration in which a sub screen 2008 is formed using the second display panel in addition to the main screen 2003 to display a channel, a volume, and the like. In this structure, the main screen 2003 may be formed using a liquid crystal display panel with an excellent viewing angle, and the sub screen may be formed using a light-emitting display panel that can display with low power consumption. In order to give priority to lower power consumption, the main screen 2003 may be formed using a light-emitting display panel, the sub screen may be formed using a light-emitting display panel, and the sub screen may be blinkable.

FIG. 20 is a block diagram illustrating a main configuration of the television device. In the display panel 900, a pixel portion 921 is formed. The signal line driver circuit 922 and the scan line driver circuit 923 may be mounted on the display panel 900 by a COG method.

  As other external circuit configurations, on the input side of the video signal, among the signals received by the tuner 924, the video signal amplification circuit 925 that amplifies the video signal, and the signal output therefrom is each of red, green, and blue And a control circuit 927 for converting the video signal into an input specification of the driver IC. The control circuit 927 outputs a signal to each of the scanning line side and the signal line side. In the case of digital driving, a signal dividing circuit 928 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 924, the audio signal is sent to the audio signal amplification circuit 929, and the output is supplied to the speaker 933 through the audio signal processing circuit 930. The control circuit 931 receives control information on the receiving station (reception frequency) and volume from the input unit 932 and sends a signal to the tuner 924 and the audio signal processing circuit 930.

  Of course, the present invention is not limited to a television device, but can be applied to various applications such as personal computer monitors, information display boards at railway stations and airports, and advertisement display boards on streets. can do.

By using the display device described in the above embodiment in the main screen 2003 and the sub screen 2008, mass productivity of the television device can be improved.

FIG. 19B illustrates an example of a mobile phone 2301. The cellular phone 2301 includes a display portion 2302, an operation portion 2303, and the like. In the display portion 2302, by applying the display device described in the above embodiment mode, mass productivity of the mobile phone can be improved.

  A portable computer shown in FIG. 19C includes a main body 2401, a display portion 2402, and the like. By applying the display device described in the above embodiment to the display portion 2402, the mass productivity of the computer can be improved.

FIG. 19D illustrates a table lamp, which includes a lighting unit 2501, an umbrella 2502, a variable arm 2503, a column 2504, a base 2505, and a power source 2506. It is manufactured by using the light emitting device of the present invention for the lighting portion 2501. The lighting fixture includes a ceiling-fixed lighting fixture or a wall-mounted lighting fixture. By applying the display device described in any of the above embodiments, mass productivity can be increased and an inexpensive desk lamp can be provided.

FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. It is a figure which shows the structure of the plasma CVD apparatus applicable to this invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a top view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. It is a figure explaining the multi-tone mask applicable to this invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a top view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a cross-sectional view illustrating a method for manufacturing a display device of the present invention. FIG. 11 is a cross-sectional view illustrating a display device of the present invention. FIG. 11 is a top view illustrating a display device of the present invention. FIG. 11 is a top view illustrating a display device of the present invention. 5A and 5B are a cross-sectional view and a top view illustrating a display device of the present invention. FIG. 11 is a perspective view illustrating a display panel of the present invention. FIG. 11 is a perspective view illustrating an electronic device using the display device of the invention. It is a diagram illustrating an electronic device using a display device of the present invention.

Claims (9)

Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate and the gate electrode;
Forming a microcrystalline semiconductor film containing a metal element over the gate insulating film;
Forming a buffer layer over the microcrystalline semiconductor film containing the metal element;
Forming a source region and a drain region formed of a semiconductor film to which an impurity imparting one conductivity type is added on the buffer layer;
A method for manufacturing a thin film transistor, wherein a source electrode and a drain electrode are formed over the source region and the drain region. Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate and the gate electrode;
After processing with a plasma containing a metal element over the gate insulating film, a microcrystalline semiconductor film is formed by forming a microcrystalline semiconductor film,
Forming a buffer layer over the microcrystalline semiconductor film containing the metal element;
Forming a source region and a drain region formed of a semiconductor film to which an impurity imparting one conductivity type is added on the buffer layer;
A method for manufacturing a thin film transistor, wherein a source electrode and a drain electrode are formed over the source region and the drain region. Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate and the gate electrode;
A microcrystalline semiconductor film containing a metal element is formed on the gate insulating film by a plasma CVD method using a gas containing a metal element and a silane gas,
Forming a buffer layer over the microcrystalline semiconductor film containing the metal element;
Forming a source region and a drain region formed of a semiconductor film to which an impurity imparting one conductivity type is added on the buffer layer;
A method for manufacturing a thin film transistor, wherein a source electrode and a drain electrode are formed over the source region and the drain region. Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate and the gate electrode;
After forming a layer containing a metal element over the gate insulating film, forming a microcrystalline semiconductor film, forming a microcrystalline semiconductor film containing a metal element,
Forming a buffer layer over the microcrystalline semiconductor film containing the metal element;
Forming a source region and a drain region formed of a semiconductor film to which an impurity imparting one conductivity type is added on the buffer layer;
A method for manufacturing a thin film transistor, wherein a source electrode and a drain electrode are formed over the source region and the drain region. Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate and the gate electrode;
Forming a layer containing a metal element over the gate insulating film, forming a semiconductor layer over the layer containing the metal element, and then irradiating a laser beam to form a silicide layer;
Forming a microcrystalline semiconductor film over the silicide layer to form a microcrystalline semiconductor film containing a metal element;
Forming a buffer layer over the microcrystalline semiconductor film containing the metal element;
Forming a source region and a drain region formed of a semiconductor film to which an impurity imparting one conductivity type is added on the buffer layer;
A method for manufacturing a thin film transistor, wherein a source electrode and a drain electrode are formed over the source region and the drain region. Forming a gate electrode on the substrate;
Forming a gate insulating film on the substrate and the gate electrode;
Forming a layer containing a metal element on the gate insulating film, forming a semiconductor layer on the layer containing the metal element, and then heating to form a silicide layer;
Forming a microcrystalline semiconductor film over the silicide layer to form a microcrystalline semiconductor film containing a metal element;
Forming a buffer layer over the microcrystalline semiconductor film containing the metal element;
Forming a source region and a drain region formed of a semiconductor film to which an impurity imparting one conductivity type is added on the buffer layer;
A method for manufacturing a thin film transistor, wherein a source electrode and a drain electrode are formed over the source region and the drain region. 7. The method for manufacturing a thin film transistor according to claim 4, wherein the layer containing a metal element is formed by applying a solution containing a metal element. 7. The method for manufacturing a thin film transistor according to claim 4, wherein the layer including the metal element is formed by a thin film formation method. A method for manufacturing a display device, comprising forming a pixel electrode in contact with the source electrode or the drain electrode of the thin film transistor according to claim 1.

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