JP2009060515A - Solid-state imaging device, method of driving solid-state imaging device, and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure a contrast in both light and dark regions when there are both light and dark regions existing in a mixed manner in one frame. <P>SOLUTION: A solid-state imaging device 100 includes a group of pixels 10, a vertical shift register 20, column signal lines (a) and (b) disposed for individual columns, a shift register 50 for controlling a switch, and a horizontal shift register 40 which, each time the line is selected, enables signal voltage to be read out sequentially via the column signal line selected by each switch from each pixel belonging to the selected line. When converting the intensity of incident light into signal voltage, each pixel applies a first conversion gain when the column signal line (a) is selected, and applies a second conversion gain when the column signal line (b) is selected. Each time the line is selected by the vertical shift register 20, the shift register 50 for controlling a switch enables each switch to select either of the column signal lines (a) and (b). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a driving method for a solid-state imaging device, and a camera, and more particularly to a technique for expanding a dynamic range.

In recent years, MOS-type solid-state imaging devices have been increasingly used, and are often used in in-vehicle cameras. Some in-vehicle cameras not only project front and rear and blind spots, but also perform inter-vehicle distance monitoring and white line detection using image recognition technology called sensing. In particular, a driving support system based on white line detection or the like has attracted a great deal of attention as image recognition technology improves.
In general, a MOS solid-state imaging device includes a plurality of pixels. Each pixel generates a charge according to the intensity of incident light, and a floating diffusion unit (hereinafter referred to as an “FD unit”) that stores a charge generated by the photodiode. An amplifying element that converts the charge accumulated in the FD portion into a voltage (see, for example, Patent Document 1). The in-vehicle camera reads the voltage obtained by the amplifying element of each pixel as a pixel signal, performs analog / digital conversion for each pixel signal, and obtains one frame of imaging data.
JP 2004-241498 A

In the white line detection technique, a relatively bright area in the frame is detected as a white line. Therefore, in order to detect a white line with high accuracy, it is necessary to secure a certain degree of contrast between a bright area and a dark area in the frame.
16 and 17 are diagrams illustrating output characteristics of a conventional solid-state imaging device.
The output voltage of the solid-state imaging device increases as the brightness of the subject increases and saturates at a certain value. In the situation D (bright daytime), the voltage “a” is output for the background brightness “A”, and the voltage “b” is output for the brightness “B” of the white line. Each of the output voltages “a” and “b” is converted into a digital value by an analog / digital conversion circuit in which the reference voltage Vref is a full range. In the situation D, since the gradation difference between the digital value corresponding to the output voltage “b” and the digital value corresponding to the output voltage “a” is sufficiently large, white line detection can be performed with high accuracy. On the other hand, in the situation E (in a dark tunnel), the voltage “a ′” is output for the background brightness “A ′”, and the voltage “b ′” is output for the brightness “B ′” of the white line. The When the entire imaging range is dark as in the situation E, the gradation difference between the digital value corresponding to the output voltage “b ′” and the digital value corresponding to the output voltage “a ′” is small, and the accuracy of white line detection decreases. End up.

  If the number of bits of the digital value is increased by one, the gradation difference can be doubled, but this is not preferable because the memory capacity and time required for image recognition are greatly increased. In order to accurately detect the white line even in a dark tunnel while maintaining the number of bits of the digital value, it is conceivable to increase the sensitivity of the solid-state imaging device (corresponding to the slope of the graph of the output characteristics) as in the situation F.

  In the situation F (in the dark tunnel), the voltage “a ′” is output for the brightness “A ′” of the background, and the voltage “b ′” is output for the brightness “B ′” of the white line. If the sensitivity of the solid-state imaging device is high as in the situation F, the digital value corresponding to the output voltage “b ′” and the digital value corresponding to the output voltage “a ′” are obtained even when the entire imaging range is dark. The gradation difference is large and white line detection can be performed with high accuracy.

  However, when approaching the tunnel exit as in the situation G and detecting both the inside and outside of the tunnel as in the situation H, the detection of the white line in the tunnel is accurate if the sensitivity of the solid-state imaging device remains high. This can be done, but the accuracy of white line detection outside the tunnel will be reduced. Conversely, if the sensitivity of the solid-state imaging device is lowered, white line detection outside the tunnel can be accurately performed, but the accuracy of white line detection inside the tunnel is reduced. In any case, the situation of losing sight of the white line occurs.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a solid-state imaging device capable of ensuring contrast in any area when both bright and dark areas are mixed in one frame without increasing the number of bits of a digital value. And

  A solid-state imaging device according to the present invention is provided for each pixel group including a pixel group including a plurality of pixels arranged in a matrix, a vertical shift register that sequentially selects a line of the pixel group, and a column of the pixel group. A first and second column signal line; a switch control unit that causes a switch disposed in each column of the pixel group to select one of the first and second column signal lines; and the vertical shift register. A horizontal shift register that sequentially reads out the signal voltage from each pixel belonging to the selected line through the first or second column signal line selected by each switch each time a line is selected by When the pixel converts the intensity of incident light into a signal voltage, the pixel applies the first conversion gain when the first column signal line is selected, and the second column signal line is selected. When a line is selected by the vertical shift register, the switch control unit applies a second conversion gain different from the first conversion gain. Select one of the column signal lines.

  The solid-state imaging device driving method according to the present invention includes a pixel group including a plurality of pixels arranged in a matrix, a vertical shift register that sequentially selects a line of the pixel group, and a column of the pixel group. A first and second column signal line provided; a switch control unit that causes a switch arranged for each column of the pixel group to select one of the first and second column signal lines; A horizontal shift register that sequentially reads signal voltages from each pixel belonging to the selected line through the first or second column signal line selected by each switch each time a line is selected by the vertical shift register; Each pixel applies a first conversion gain when the intensity of incident light is converted into a signal voltage and the first column signal line is selected, and the second column signal Is selected when the line is selected by the vertical shift register, the switch for driving the solid-state imaging device that applies a second conversion gain different from the first conversion gain. The control unit causes each switch to select one of the first and second column signal lines.

  The camera according to the present invention is a camera including a solid-state imaging device and a control device, and the solid-state imaging device sequentially includes a pixel group including a plurality of pixels arranged in a matrix and a line of the pixel group. The vertical shift register to be selected, the first and second column signal lines arranged for each column of the pixel group, and the switch arranged for each column of the pixel group are connected to the first and second columns. A switch control unit for selecting one of the column signal lines, and a first or second column selected by each switch from each pixel belonging to the selected line each time a line is selected by the vertical shift register A horizontal shift register that sequentially reads out the signal voltage through the signal line, and the control device is characterized by brightness of a plurality of pixel-corresponding regions included in the imaging range of the solid-state imaging device. Acquisition means for acquiring data to be performed, and each of the data acquired by the acquisition means is either a first logical value indicating darkness compared to a threshold value or a second logical value indicating lightness compared to a threshold value And a binarizing unit that binarizes each pixel, and each pixel has a first unit when the first column signal line is selected when converting the intensity of incident light into a signal voltage. A conversion gain is applied, and when the second column signal line is selected, a second conversion gain lower than the first conversion gain is applied, and the switch control unit performs line conversion by the vertical shift register. When the data obtained by the binarization means takes a first logic value, the first column signal line is selected, and when the data obtained by the binarization means takes a second logic value, the second column signal line As selected , To select one of said first and second column signal line to each switch.

  According to the above configuration, each switch is arranged for each column and is controlled every time a line is selected. Therefore, whether the pixel applies the first or second conversion gain is controlled on a pixel-by-pixel basis. Since the conversion gain is controlled in units of pixels in this way, a low conversion gain is selected in a bright area and a high conversion gain is selected in a dark area even when both bright and dark areas are mixed in one frame. Accordingly, contrast can be ensured in any region.

  The switch control unit includes a switch control shift register configured by cascading flip-flops arranged corresponding to the switches, and the switches are held in the corresponding flip-flops. One of the first and second column signal lines is selected based on a logical value of data, and the switch control shift register corresponds to each switch every time a line is selected by the vertical shift register. It is also possible to shift in a data string composed of data.

According to the above configuration, data corresponding to each switch is input serially. Therefore, the number of data input terminals can be greatly reduced as compared with the case where the data are input in parallel.
The switch control unit includes a latch group including a latch arranged corresponding to each switch, and a flip-flop arranged corresponding to each latch, which is connected in cascade. Each switch selects one of the first and second column signal lines based on the logical value of the data held in the corresponding latch, and the switch control shift register Each time a line is selected by the vertical shift register, a data string composed of data corresponding to each switch is shifted in, and each latch corresponds each time a data string is shifted in by the switch control shift register. The data held in the flip-flop may be held.

  According to the above configuration, each switch is controlled based on the logical value of the data held in the corresponding latch, so that the data string is shifted into the switch control shift register without affecting each switch. be able to. Accordingly, reading of the signal voltage of each pixel belonging to the first line by the horizontal shift register and shift-in of the data string corresponding to the second line by the switch control shift register can be performed in parallel. The time required to read out the signal voltage for the frame can be shortened.

  Each pixel is connected to a photodiode that generates charges according to the intensity of incident light, a floating diffusion that stores charges generated by the photodiodes, and a first column signal line. And an amplifying element having a second terminal connected to the second column signal line and a third terminal connected to the floating diffusion portion, and a first terminal of the amplifying element and a second terminal The third terminal may be coupled by a first capacitor, and the second terminal and the third terminal of the amplification element may be coupled by a second capacitor different from the first capacitor.

According to the above configuration, the conversion gain can be made different when the signal voltage is read from the first column signal line and when the signal voltage is read from the second column signal line. Therefore, the first and second conversion gains can be switched without complicating the structure of the pixel portion.
The switch control unit includes a switch control shift register configured by cascading flip-flops arranged corresponding to the switches, and the switches are held in the corresponding flip-flops. One of the first and second column signal lines is selected based on a logical value of data. When the first and second lines are selected in this order by the vertical shift register, the first column signal line is selected. From the completion of reading of the signal voltage of each pixel belonging to the second line to the start of reading of the signal voltage of each pixel belonging to the second line, A data string corresponding to the second line, which is composed of corresponding data, may be shifted in.

According to the above configuration, the switch control shift register shifts in the data string when the horizontal shift register is not performing a shift operation, so carelessly while the signal voltage of each pixel is being read out. A situation in which the switch is switched can be avoided.
The switch control unit includes a latch group including a latch arranged corresponding to each switch, and a flip-flop arranged corresponding to each latch, which is connected in cascade. Each switch selects one of the first and second column signal lines based on the logical value of the data held in the corresponding latch, and the first switch by the vertical shift register. When the first and second lines are selected in this order, the signal voltage of each pixel belonging to the first line is read by the horizontal shift register, and the second line by the switch control shift register corresponds to the second line. Data consisting of data corresponding to each switch in the switch control shift register so that the shift-in of the data string is performed in parallel Each of the pixels belonging to the second line from the time when both the readout of the signal voltage of each pixel belonging to the first line and the shift-in of the data string corresponding to the second line are completed. The data held in the corresponding flip-flop may be held in each latch until the reading of the pixel signal voltage is started.

  According to the above configuration, reading of the signal voltage of each pixel belonging to the first line by the horizontal shift register and shift-in of the data string corresponding to the second line by the switch control shift register are performed in parallel. It is possible to reduce the time required to read out the signal voltage for one frame.

The best mode for carrying out the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a solid-state imaging apparatus according to Embodiment 1 of the present invention.
The solid-state imaging device 100 includes a pixel group 10, a vertical shift register 20, a switch group 30, a horizontal shift register 40, a switch control shift register 50, and an output unit 60.

The pixel group 10 includes pixels PD (1, 1) to PD (X, Y). Each pixel is arranged in a matrix.
The vertical shift register 20 includes flip-flops FFv1 to FFvY arranged corresponding to the respective lines of the pixel group 10. The flip-flops FFv1 to FFvY shift in the trigger signal Vtrig in synchronization with the clock Vck. Thereby, the lines of the pixel group 10 are sequentially selected.

The switch group 30 includes switches SW <b> 1 to SWX disposed corresponding to each column of the pixel group 10. Focusing on one switch SWm, the switch SWm selects one of the column signal lines a and b arranged in the column m based on the logical value of the data held in the flip-flop FFsm.
The horizontal shift register 40 includes flip-flops FFh <b> 1 to FFhX arranged corresponding to each column of the pixel group 10. The flip-flops FFh1 to FFhX shift in the trigger signal Htrig in synchronization with the clock Hck. Thereby, the columns of the pixel group 10 are sequentially selected.

The switch control shift register 50 includes flip-flops FFs <b> 1 to FFsX disposed corresponding to each column of the pixel group 10. The flip-flops FFs1 to FFsX shift in the data string Sdata in synchronization with the clock Sck. The data string Sdata includes data corresponding to each switch.
The output unit 60 reads the signal voltage from the column selected by the horizontal shift register 40 and outputs it.

FIG. 2 is a diagram illustrating the configuration of the pixel PD (m, n).
The pixel PD (m, n) includes a photodiode PD, an FD portion, a transfer transistor Tr1, an amplification transistor Tr2, and a reset transistor Tr3. The amplification transistor Tr2 includes a first terminal connected to the column signal line a, a second terminal connected to the column signal line, and a third terminal connected to the FD unit, and the first terminal and the third terminal. Are coupled by a capacitor C3, and the second terminal and the third terminal are coupled by a capacitor C2. The capacitors C2 and C3 are different from each other. The amplification transistor Tr2 functions to convert the charge accumulated in the FD portion into a voltage. At this time, since the capacitor C2 and the capacitor C3 are different, the conversion gain for converting the charge into the voltage differs depending on which column signal line the voltage is read from.

  Specifically, if the charge fluctuation accumulated in the FD portion is ΔQpd, when the voltage is read from the column signal line b (first mode), the voltage fluctuation ΔV1 = ΔQpd / (C1 + C3) and the column signal line a When the voltage is read from (second mode), voltage fluctuation ΔV2 = ΔQpd / (C1 + C2). Therefore, for example, if the capacitance C3 is made larger than the capacitance C2, the sensitivity in the second mode can be made higher than the sensitivity in the first mode.

FIG. 3 is a diagram illustrating a configuration of the switch SWm.
The switch SWm includes a switch circuit 41 and a NAND circuit 42. The switch circuit 41 is connected to A when the signal Ssw2 is at a high level, and is connected to B when the signal Ssw2 is at a low level. When connected to A, the pixel drive signal Sdrive is input to the pixel PD through the column signal line a, and the signal voltage of the pixel PD is read out through the column signal line b. When connected to B, the pixel drive signal Sdrive is input to the pixel PD through the column signal line b, and the signal voltage of the pixel PD is read out through the column signal line a.

FIG. 4 is a diagram illustrating signal waveforms in the first mode.
In the figure, Va represents a voltage appearing on the column signal line a, VFD represents a voltage appearing on the FD portion, and Vb represents a voltage appearing on the column signal line b.
The switch SWm selects which of the column signal lines a and b the voltage is read based on the logical value of the data SDm held in the flip-flop FFsm. When the data SDm is at a low level (logical value “0”), the column signal line b is selected (first mode).

When the data SDm is at a low level, the output signal Ssw2 of the NAND circuit 42 is fixed at a high level. Therefore, the switch circuit 41 is connected to A from time t0 to time t11, the pixel drive signal Sdrive appears on the column signal line a, and a voltage corresponding to the voltage VFD of the FD portion appears on the column signal line b.
The voltage VFD of the FD section becomes the voltage Vreset when the reset transistor Tr3 is turned on from time t2 to time t3, and becomes the voltage Vreset−ΔV1 when the transfer transistor Tr1 is turned on from time t5 to time t6. . Accordingly, the voltage Vb of the column signal line b becomes the voltage Vreset−Vth from the time t2 to the time t5, and becomes the voltage Vreset−Vth−ΔV1 from the time t6 to the time t8. These differences are read as signal voltages.

FIG. 5 is a diagram showing signal waveforms in the second mode.
The switch SWm selects which of the column signal lines a and b the voltage is read based on the logical value of the data SDm held in the flip-flop FFsm. When the data SDm is at a high level (logical value is “1”), the column signal line a is selected (second mode).
When the data SDm is at a high level, the output signal Ssw2 of the NAND circuit 42 is the same as the signal Ssw1. Therefore, the switch circuit 41 is connected to B from time t0 to time t1, connected to A from time t1 to time t4, connected to B from time t4 to time t7, connected to A from time t7 to time t10, Connected to B from t10 to time t11.

  The voltage VFD of the FD section becomes the voltage Vreset when the reset transistor Tr3 is turned on from time t2 to time t3, and becomes the voltage Vreset−ΔV2 when the transfer transistor Tr1 is turned on from time t5 to time t6. . Accordingly, the voltage Va of the column signal line a becomes the voltage Vreset−Vth from the time t4 to the time t5, and becomes the voltage Vreset−Vth−ΔV2 from the time t6 to the time t7. These differences are read as signal voltages.

FIG. 6 is a diagram for explaining a method of selecting the first mode and the second mode for each pixel.
In the figure, A shows a state where a bright subject such as a light source is imaged on the solid-state imaging device 100 through a lens. Region B is a bright subject, and region C is the background. The squares in the figure correspond to the pixels of the solid-state imaging device 100.

  D in the figure shows a state in which the brightness is binarized for each pixel of the solid-state imaging device 100. All the pixels included in the region E are brighter than the threshold value, and all the pixels included in the region F are darker than the threshold value. The threshold value may be arbitrarily set based on the use of the solid-state imaging device, the shooting conditions, and the like.

In this way, the brightness is binarized, a low gain is set for pixels included in an area brighter than the threshold value, and a high gain is set for pixels included in an area darker than the threshold value. When both areas are mixed, the contrast can be ensured in either area.
Hereinafter, the operation of the solid-state imaging device will be specifically described by taking a solid-state imaging device having 3 × 3 pixels as an example.

FIG. 7 is a diagram showing a configuration of the solid-state imaging device (3 × 3 pixels) according to Embodiment 1 of the present invention. In the solid-state imaging device of FIG. 7, the pixels PD (1, 1) to PD (3, 3) are arranged in a 3 × 3 matrix.
FIG. 8 is a diagram for explaining a method of selecting the first mode and the second mode for each pixel.

  The upper diagram in FIG. 8 shows the light amount of each pixel. Here, the light amounts of the pixels PD (1, 1), PD (2, 2), and PD (3, 3) are less than the threshold (darker than the threshold), and the light amounts of the other pixels are all lower than the threshold. Assume a large number of cases. In this case, the data SD1 (1) corresponding to the pixel PD (1,1) is at a high level, and similarly, the data SD2 (2) corresponding to the pixel PD (2,2), PD (3,3), SD3 (3) is at a high level. Further, data corresponding to the other pixels (for example, data SD2 (1) corresponding to the pixel PD (2,1)) are all at the low level.

The lower diagram of FIG. 8 shows a data string Sdata composed of data corresponding to each of the pixels PD (1, 1) to PD (3, 3), and a clock Sck for shifting the data string Sdata into the switch control shift register 50. It shows.
FIG. 9 is a diagram illustrating a signal waveform when a pixel signal of one frame is read from the solid-state imaging device (3 × 3 pixels) according to the first embodiment of the present invention.

The flip-flops FFv1 to FFv3 constituting the vertical shift register 20 shift in the trigger signal Vtrig in synchronization with the clock Vck. As a result, the lines are sequentially selected from the first line to the third line.
The flip-flops FFs1 to FFs3 constituting the switch control shift register 50 shift in the data string Sdata in synchronization with the clock Sck every time a line is selected. For example, in the period S1, data SD3 (1), SD2 (1), SD1 (1) corresponding to the pixels PD (3,1), PD (2,1), and PD (1,1) in the first line, respectively. Is shifted in. In this example, when the shift-in is completed, high-level, low-level, and low-level data are held in the flip-flops FFs1, FFs2, and FFs3, respectively. The switches SW1, SW2, and SW3 select one of the column signal lines a and b based on the logical values of the data held in the flip FFs1, FFs2, and FFs3, respectively. In this example, the switch SW1 selects the column signal line a, and the switches SW2 and SW3 each select the column signal line b.

  The flip-flops FFh1 to FFh3 constituting the horizontal shift register 40 shift in the trigger signal Htrig in synchronization with the clock Hck every time a line is selected. Thereby, columns are sequentially selected from the first column to the third column. From the selected column, the pixel signal is read through the column signal line previously selected by the switch. For example, in the period H1, the pixel signal a11 is read from the first column through the column signal line a, the pixel signal b12 is read from the second column through the column signal line b, and the column signal line from the third column. The pixel signal b13 is read through b.

As described above, in the solid-state imaging device 100 according to the first embodiment, the switch control shift register 50 shifts in the data string every time a line is selected by the vertical shift register 20. Therefore, it can be controlled pixel by pixel which of the column signal lines a and b is used to read out the pixel signal.
10 and 11 are diagrams illustrating output characteristics of the solid-state imaging device according to Embodiment 1 of the present invention.

As shown in FIG. 10, the solid-state imaging device 100 reads out a pixel signal with a high gain (the slope of the graph is large) when it is darker than the threshold, and low gain (the slope of the graph is small) when brighter than the threshold. The pixel signal can be read out.
As shown in FIG. 11, in the situation A (in the dark tunnel), the voltage “a ′” is output for the brightness “A ′” of the background in the tunnel, and the brightness “B ′” of the white line in the tunnel is output. The voltage “b ′” is output. Since the pixel signal is read at a high gain at this time, the gradation difference between the digital value corresponding to the output voltage “b ′” and the digital value corresponding to the output voltage “a ′” is sufficiently large, and white line detection is performed. Can be performed with high accuracy.

  Further, when approaching the exit of the tunnel as in the situation B and detecting both the inside and outside of the tunnel as in the situation C, the white line can be accurately detected in the tunnel as in the situation A. Further, outside the tunnel, the voltage “a” is output for the brightness “A” of the background outside the tunnel, and the voltage “b” is output for the brightness “B” of the white line outside the tunnel. At this time, since the pixel signal is read with a low gain, the white line can be detected accurately without the output voltage “b” and the output voltage “a” being saturated.

FIG. 12 is a diagram showing the configuration of the camera according to Embodiment 1 of the present invention.
The camera includes a solid-state imaging device 100, a lens 110, a timing generator 120, and a signal processing circuit 130.
The timing generator 120 generates various signals (for example, a trigger signal Vtrig) for driving the solid-state imaging device 100.

  The signal processing circuit 130 includes an AFE / AD unit 131, a signal processing unit 132, a region dividing unit 133, a switching pulse generating unit 134, and a determining unit 135. The pixel signal output from the solid-state imaging device 100 is subjected to noise cancellation, analog / digital conversion, and the like by the AFE / AD unit 131, and subjected to image processing by the signal processing unit 132 and output. Further, the pixel signal is binarized by the region dividing unit 133, the switching pulse generating unit 134, and the determining unit 135, and a data string Sdata is generated. The data string Sdata may be generated based on prediction control from the previous frame, or may be generated based on the photometric result by providing a separate photometric unit. When based on predictive control from the previous frame, a time delay of one frame occurs. However, if moving object predictive control is used, a data string can be generated with almost no error. In particular, when performing constant speed running or constant acceleration running as in an automobile, it is sufficient to use existing moving object predictive control.

FIG. 13 is a diagram illustrating a configuration example of the amplification transistor Tr2.
FIG. 13A is a top view of the amplifying transistor Tr 2 and shows a state where a polysilicon gate 81 is formed on the channel 82. In this example, a difference is provided between the width Wa on the point a side and the width Wb on the point b side of the channel 82. By doing in this way, the capacity | capacitance C2 and the capacity | capacitance C3 can be varied.

  FIG. 13B is a cross-sectional view of the amplifying transistor Tr2, and shows a state in which n-type regions 84 and 85 are formed in the p-type well 83 and a polysilicon gate 81 is formed on the substrate. In this example, a difference is provided between the overlap amount La between the n-type region 85 and the polysilicon gate 81 and the overlap amount Lb between the n-type region 84 and the polysilicon gate 81. By doing in this way, the capacity | capacitance C2 and the capacity | capacitance C3 can be varied.

  FIG. 13C is a cross-sectional view of the amplification transistor Tr2, and shows a state where n-type regions 84 and 85 are formed in the p-type well 83 and a polysilicon gate 81 is formed on the substrate. In this example, a difference is provided between the impurity concentration na of the n-type region 85 and the impurity concentration nb of the n-type region 84. By doing in this way, the capacity | capacitance C2 and the capacity | capacitance C3 can be varied.

Note that the above method is merely an example, and the capacitance C2 and the capacitance C3 may be different from each other by any other method.
(Embodiment 2)
The second embodiment is different from the first embodiment in that the shift-in of the switch control shift register 50 and the shift-in of the horizontal shift register 40 are executed in parallel. Since other than that is the same as that of Embodiment 1, description is abbreviate | omitted.

FIG. 14 is a diagram showing a configuration of a solid-state imaging device (3 × 3 pixels) according to Embodiment 2 of the present invention.
Since the solid-state imaging device 100 according to the second embodiment performs the shift-in of the switch control shift register 50 and the shift-in of the horizontal shift register 40 in parallel, the configuration of the solid-state imaging device 100 according to the first embodiment. In addition, a latch group 70 is provided.

The latch group 70 includes latches Ls1 to Ls3. The latches Ls1 to Ls3 receive and hold the data held in the flip-flops FFs1 to FFs3, respectively, in synchronization with the latch signal Latch.
The switches SW1 to SW3 select one of the column signal lines a and b based on the logical values of the data held in the latches Ls1 to Ls3, respectively.

FIG. 15 is a diagram illustrating a signal waveform when a pixel signal of one frame is read from the solid-state imaging device (3 × 3 pixels) according to the second embodiment of the present invention.
In the solid-state imaging device 100 according to the second embodiment, the shift-in of the switch control shift register 50 and the shift-in of the horizontal shift register 40 are performed in parallel. For example, in the period H1 (period S2), the pixels PD (3, 2) and PD (2, 2) in the second line are being read while the pixel signals a11, b12, and b13 in the first line are being read out. , Data SD3 (2), SD2 (2), SD1 (2) respectively corresponding to PD (1,2) are shifted in. The shifted data SD3 (2), SD2 (2), and SD1 (2) are respectively held in the latches Ls1, Ls2, and Ls3 in synchronization with the rising edge of the latch signal Latch. The switches SW1, SW2, and SW3 select one of the column signal lines a and b based on the logical values of the data held in the flips Ls1, Ls2, and Ls3, respectively.

Thus, in the solid-state imaging device 100 according to the second embodiment, the shift-in of the switch control shift register 50 and the shift-in of the horizontal shift register 40 are executed in parallel. Accordingly, it is possible to reduce the time required to read out the pixel signal for one frame.
As described above, the solid-state imaging device and the camera according to the present invention have been described based on the embodiments. However, the present invention is not limited to these embodiments. For example, the following modifications can be considered.
(1) In Embodiment 2, in order to execute the shift-in of the switch control shift register 50 and the shift-in of the horizontal shift register 40 in parallel, data is held using a latch. The invention is not limited to this example. For example, it is possible to provide a function for retaining data in the switch confidence, or a function for retaining data in the pixel confidence.
(2) In the embodiment, the case of selecting one of the two types of conversion gains is illustrated, but the present invention is not limited to these. One of three or more conversion gains may be selected.
(3) In the embodiment, the conversion gain when the charge is converted into the voltage is switched, but the present invention is not limited to this. For example, an amplifier may be provided for each column signal line, and the gain of the amplifier may be switched. However, when the gain of the amplifier is increased, thermal noise, FD conversion noise, substrate noise, etc. are also amplified together. In addition, amplification noise of the amplifier itself is also generated, so that high contrast is obtained when the subject is dark. It can be a big disadvantage to get. In such a case, it is more desirable to switch the conversion gain than to switch the gain of the amplifier.
(4) In the embodiment, an example in which a pixel is configured by three transistors is given. However, the present invention is not limited to this, and an example in which the pixel is configured by four transistors may be used. In addition, a configuration in which the FD portion and the amplification transistor Tr2 are shared by a plurality of pixels may be used.
(5) Although the white line detection is described as an example in the embodiment, the present invention is not limited to this and can be used for various applications.

  The present invention can be used for a digital camera, for example.

It is a figure which shows the structure of the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of pixel PD (m, n). It is a figure which shows the structure of switch SWm. It is a figure which shows the signal waveform in 1st mode. It is a figure which shows the signal waveform in 2nd mode. It is a figure for demonstrating the method of selecting 1st mode and 2nd mode for every pixel. It is a figure which shows the structure of the solid-state imaging device (3x3 pixel) which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the method of selecting 1st mode and 2nd mode for every pixel. It is a figure which shows a signal waveform when reading the pixel signal of 1 frame from the solid-state imaging device (3x3 pixel) which concerns on Embodiment 1 of this invention. It is a figure which shows the output characteristic of the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a figure which shows the output characteristic of the solid-state imaging device which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the camera which concerns on Embodiment 1 of this invention. It is a figure which shows the structural example of amplification transistor Tr2. It is a figure which shows the structure of the solid-state imaging device (3x3 pixel) which concerns on Embodiment 2 of this invention. It is a figure which shows a signal waveform when reading the pixel signal of 1 frame from the solid-state imaging device (3x3 pixel) which concerns on Embodiment 2 of this invention. It is a figure which shows the output characteristic of the conventional solid-state imaging device. It is a figure which shows the output characteristic of the conventional solid-state imaging device.

Explanation of symbols

10 pixel group 20 vertical shift register 30 switch group 40 horizontal shift register 41 switch circuit 42 NAND circuit 50 switch control shift register 60 output unit 70 latch group 81 polysilicon gate 82 channel 83 p-type well 84 n-type region 85 n-type region DESCRIPTION OF SYMBOLS 100 Solid-state imaging device 110 Lens 120 Timing generator 130 Signal processing circuit 131 AFE / AD part 132 Signal processing part 133 Area division part 134 Switching pulse generation part 135 Determination part

Claims (8)

A pixel group including a plurality of pixels arranged in a matrix;
A vertical shift register for sequentially selecting lines of the pixel group;
First and second column signal lines arranged for each column of the pixel group;
A switch control unit that causes a switch arranged for each column of the pixel group to select one of the first and second column signal lines;
A horizontal shift register that sequentially reads out a signal voltage from each pixel belonging to the selected line through the first or second column signal line selected by each switch each time a line is selected by the vertical shift register; With
Each pixel applies a first conversion gain when the first column signal line is selected when converting the intensity of incident light into a signal voltage, and the second column signal line is selected. When the second conversion gain is different from the first conversion gain,
The switch control unit causes each switch to select one of the first and second column signal lines each time a line is selected by the vertical shift register. The switch control unit includes a switch control shift register configured by cascading flip-flops arranged corresponding to the switches,
Each switch selects one of the first and second column signal lines based on the logical value of the data held in the corresponding flip-flop,
2. The solid-state imaging device according to claim 1, wherein the switch control shift register shifts in a data string composed of data corresponding to each switch each time a line is selected by the vertical shift register. The switch control unit includes a latch group including a latch arranged corresponding to each switch, and a switch control shift register configured by cascading flip-flops arranged corresponding to each latch; Including
Each switch selects one of the first and second column signal lines based on the logical value of the data held in the corresponding latch,
The switch control shift register shifts in a data string composed of data corresponding to each switch each time a line is selected by the vertical shift register,
2. The solid-state imaging device according to claim 1, wherein each latch holds data held in a corresponding flip-flop every time a data string is shifted in by the switch control shift register. Each pixel is
A photodiode that generates charge according to the intensity of incident light;
A floating diffusion for accumulating charges generated by the photodiode;
An amplifying element having a first terminal connected to the first column signal line, a second terminal connected to the second column signal line, and a third terminal connected to the floating diffusion portion; With
The first terminal and the third terminal of the amplifying element are coupled by a first capacitor, and the second terminal and the third terminal of the amplifying element are coupled by a second capacitor different from the first capacitor. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is coupled. A pixel group including a plurality of pixels arranged in a matrix;
A vertical shift register for sequentially selecting lines of the pixel group;
First and second column signal lines arranged for each column of the pixel group;
A switch control unit that causes a switch arranged for each column of the pixel group to select one of the first and second column signal lines;
A horizontal shift register that sequentially reads out a signal voltage from each pixel belonging to the selected line through the first or second column signal line selected by each switch each time a line is selected by the vertical shift register; With
Each pixel applies a first conversion gain when the first column signal line is selected when converting the intensity of incident light into a signal voltage, and the second column signal line is selected. A driving method for driving a solid-state imaging device that applies a second conversion gain different from the first conversion gain,
Each time a line is selected by the vertical shift register, the switch control unit causes each switch to select one of the first and second column signal lines. The switch control unit includes a switch control shift register configured by cascading flip-flops arranged corresponding to the switches,
Each switch selects one of the first and second column signal lines based on the logical value of the data held in the corresponding flip-flop,
When the first and second lines are selected in this order by the vertical shift register,
In the switch control shift register between the completion of reading of the signal voltage of each pixel belonging to the first line and the start of reading of the signal voltage of each pixel belonging to the second line, The method for driving a solid-state imaging device according to claim 5, wherein a data string corresponding to the second line, which includes data corresponding to each switch, is shifted in. The switch control unit includes a latch group including a latch arranged corresponding to each switch, and a switch control shift register configured by cascading flip-flops arranged corresponding to each latch; Including
Each switch selects one of the first and second column signal lines based on the logical value of data held in the corresponding latch.
When the first and second lines are selected in this order by the vertical shift register,
The reading of the signal voltage of each pixel belonging to the first line by the horizontal shift register and the shift-in of the data string corresponding to the second line by the switch control shift register are performed in parallel. The switch control shift register shifts in a data string composed of data corresponding to each switch,
Since the signal voltage reading of each pixel belonging to the first line and the shift-in of the data string corresponding to the second line are both completed, the signal voltage of each pixel belonging to the second line The solid-state imaging device driving method according to claim 5, wherein the data held in the corresponding flip-flop is held in each latch until the reading is started. A camera comprising a solid-state imaging device and a control device,
The solid-state imaging device
A pixel group including a plurality of pixels arranged in a matrix;
A vertical shift register for sequentially selecting lines of the pixel group;
First and second column signal lines arranged for each column of the pixel group;
A switch control unit that causes a switch arranged for each column of the pixel group to select one of the first and second column signal lines;
A horizontal shift register that sequentially reads out a signal voltage from each pixel belonging to the selected line through the first or second column signal line selected by each switch each time a line is selected by the vertical shift register; With
The controller is
Acquisition means for acquiring data for specifying the brightness of each of the plurality of pixel-corresponding regions included in the imaging range of the solid-state imaging device;
Each data acquired by the acquisition means is binarized so as to be either a first logical value indicating darkness compared to a threshold value or a second logical value indicating lightness compared to a threshold value. And binarization means,
Each pixel applies a first conversion gain when the first column signal line is selected when converting the intensity of incident light into a signal voltage, and the second column signal line is selected. Apply a second conversion gain lower than the first conversion gain,
The switch control unit selects the first column signal line when the data obtained by the binarization means takes the first logic value every time a line is selected by the vertical shift register, and selects the second logic. A camera that causes each switch to select one of the first and second column signal lines so that the second column signal line is selected when taking a value.