JP2009060020A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of preventing metal wiring layers from being short-circuited with each other. <P>SOLUTION: When an interlayer insulating film 22D is made of a positive type material, a predetermined region of a part of the interlayer insulating film 22D which is opposed to metal wiring layers 23 and 24 are exposed with an exposure amount less than exposure sensitivity such that the remaining film rate of the opposed parts is 0, and then the interlayer insulating film 22D is exposed. When the interlayer insulating film 22D is made of a negative type material, the predetermined region is exposed with an exposure amount larger than the exposure sensitivity and the region of the interlayer insulating film 22D except the predetermined region is exposed with an exposure amount larger than the exposure amount larger than the exposure sensitivity. Then the entire surface including the interlayer insulating film 22D is subjected to metal oxidation processing and then subjected to ashing using oxidation reaction to remove the part (remaining film 22E) of the interlayer insulating film 22D corresponding to the predetermined region. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a multilayer wiring structure in which insulating layers and a plurality of metal wiring layers are alternately stacked on a semiconductor substrate.

  In recent years, with higher functionality and smaller size of semiconductor devices, higher density of semiconductor devices is required. In order to satisfy this requirement, a chip size package structure (CSP structure) is used, and an external electrode terminal connected to an electrode pad of the integrated circuit via a wiring layer is provided on the side of the semiconductor device where the integrated circuit is formed. A method of arranging in an area array is generally used. Since this CSP structure can increase the number of external electrode terminals as compared to a quad flat package structure (QFP structure) of the same size, it is a main structure in a high-density surface-mount type semiconductor device. .

  In the semiconductor device having the CSP structure, the number of electrode pads has been dramatically increased as the functionality has been increased. As a result, the pitch between the electrode pads becomes narrow, and it is difficult to route the wiring layers only within one plane and arrange the external electrode terminals in an area array. Therefore, recently, the wiring layer has been made multi-layered to facilitate the routing of the wiring layer.

  Hereinafter, a general method for forming a multilayer wiring structure in a semiconductor device having a CSP structure will be described with reference to FIGS.

  FIG. 24 shows a part of the upper surface configuration of the semiconductor wafer 100 (a portion surrounded by dicing streets). 25A shows a cross-sectional configuration in the direction of arrow AA of the semiconductor wafer 100 in FIG. 24, and FIG. 25B shows a cross-sectional configuration in the direction of arrow BB of the semiconductor wafer 100 in FIG. It is. 26, 28, 30, 32, 34, 36 and 38 show the top surface configuration of the chip in the manufacturing process. 27A, FIG. 29A, FIG. 31A, FIG. 33A, FIG. 35, FIG. 37, and FIG. 39 are cross-sectional configurations in the direction of arrows AA in the previous drawing, respectively. 27 (B), FIG. 29 (B), FIG. 31 (B), and FIG. 33 (B) each represent a cross-sectional configuration in the direction of arrow BB in the previous drawing. It is.

  First, a semiconductor wafer 100 for forming a multilayer wiring structure is prepared (FIGS. 24, 25A, 25B). In this semiconductor wafer 100, an interlayer insulating film 120 and a passivation layer 130 are formed in this order on the surface on the integrated circuit side of a silicon substrate 110 on which an integrated circuit (not shown) is formed on one surface. In the interlayer insulating film 120, a wiring layer and a via (both not shown) electrically connected to the integrated circuit are formed. In addition, a plurality of electrode pads 140 are formed, for example, in a line on the upper surface of the interlayer insulating film 120, and each electrode pad 140 is connected to the integrated circuit via the wiring layer and vias of the interlayer insulating film 120. Electrically connected. The passivation layer 130 has openings corresponding to the electrode pads 140, and the electrode pads 140 are exposed from the openings.

Here, the integrated circuit includes, for example, a general MOS (Metal Oxide Semiconductor) configured by element isolation, a diffusion layer, a channel, a gate, or the like, or a bipolar transistor, a diode, a capacitor, or the like. The interlayer insulating film 120 and the passivation layer 130 are made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or an insulating material having a relative dielectric constant lower than these. The wiring layers, vias, and electrode pads 140 are made of, for example, aluminum (Al) or copper (Cu).

  Next, an interlayer insulating film 200 having an opening 200A corresponding to each electrode pad 140 is formed on the semiconductor wafer 100 (FIGS. 26, 27A and 27B). Thereby, each electrode pad 140 is exposed from the opening 200A. The interlayer insulating film 200 is made of, for example, a photosensitive resin (polyimide or the like). For example, the interlayer insulating film 200 is formed by applying a photosensitive resin on the semiconductor wafer 100, pre-baking, and subsequently performing pattern exposure and development. If necessary, a discum process may be added in which the development residue (scum) is etched under oxygen plasma.

  Next, a plurality of metal wiring layers 300 extending from the surface of each electrode pad 140 to a predetermined site on the surface of the semiconductor wafer 100, and the semiconductor wafer 100 without contacting each electrode pad 140 and each metal wiring layer 300. A metal wiring layer 310 extending on the surface is formed (FIGS. 28, 29A and 29B). Here, the metal wiring layers 300 and 310 are formed by forming a wiring layer made of Cu on a base layer formed by sequentially laminating titanium (Ti) and Cu in order from the semiconductor wafer 100 side, for example, semi-additive. Formed using the method.

  In the semi-additive method, for example, Ti and Cu (underlayer) are formed on the entire surface of the semiconductor wafer 100 by sputtering, and the metal wiring layers 300 and 310 are formed thereon. After forming a plating resist having an opening in a portion, Cu (wiring layer) is formed by electrolytic plating or the like, and then the plating resist is peeled and removed. Further, using Cu (wiring layer) as a mask, Ti and It refers to a method of removing Cu (underlayer) by wet etching.

  Next, on the surface including the metal wiring layers 300 and 310, openings corresponding to the end portions 300A of the metal wiring layers 300 not facing the electrode pads 140 and both end portions of the metal wiring layers 310 are opened. An interlayer insulating film 400 having 400A is formed (FIGS. 30, 31A, and B). As a result, the end portion 300A of each metal wiring layer 300 and both end portions of the metal wiring layer 310 are exposed from the opening 400A. The interlayer insulating film 400 is made of, for example, a photosensitive resin (polyimide or the like). For example, the photosensitive resin is applied on the surface including the metal wiring layers 300 and 310, and then pre-baked, followed by pattern exposure and development. Is formed. If necessary, a discum process may be added in which the development residue (scum) is etched under oxygen plasma.

  Next, the metal wiring layer 500 extending from the surface of the end portion 300A of one metal wiring layer 300 to a predetermined portion on the surface of the interlayer insulating film 400 through a portion facing the other metal wiring layer 300; Then, a land portion 610 that is in contact with the end portion 300A of the metal wiring layer 300 that is not in contact with the metal wiring layer 500 among the plurality of metal wiring layers 300 is formed (FIGS. 32, 33A, and 33B). Here, the metal wiring layer 300 and the land portion 610 are formed by forming a wiring layer made of Cu on an underlayer formed by sequentially laminating titanium (Ti) and Cu from the semiconductor wafer 100 side, for example. It is formed using a semi-additive method.

  Next, a columnar columnar electrode 620A is formed on each land portion 610 as necessary (FIGS. 34 and 35). For example, the columnar electrode 620A is formed by forming a wiring layer made of Cu on an underlayer formed by sequentially laminating titanium (Ti) and Cu from the semiconductor wafer 100 side. For example, the columnar electrode 620A is formed using a semi-additive method. Is done.

  Next, when the columnar electrode 620A is formed, a sealing resin thicker than the columnar electrode 620A is formed on the entire surface including the columnar electrode 620A by, for example, a transfer molding method, a dispenser method, a dipping method, or a printing method. After film formation, the upper surface of the sealing resin is polished and removed. Thereby, the columnar electrode 620 with the upper surface exposed is formed, and the sealing layer 700 having the upper surface in substantially the same plane as the upper surface of the columnar electrode 620 is formed (FIGS. 36 and 37). When burrs are generated on the upper surface of the columnar electrode 620 by polishing, the burrs are removed by wet etching or the like, and further, nickel is formed on the upper surface of the columnar electrode 620 by electroless plating in order to prevent subsequent oxidation. Surface treatment such as forming a layer may be performed.

  Next, solder bumps 630 are formed on the upper surface of the columnar electrode 620 when the columnar electrode 620 is formed, and on the upper surface of the land portion 610 when the columnar electrode 620 is not formed (FIGS. 38 and 39). . For example, the solder bump 630 is reflowed after mounting a solder ball directly on the upper surface of the columnar electrode 620, or reflowed after a solder paste is applied to the upper surface of the columnar electrode 620 by a printing method or a dispenser method. It is formed by the method.

  Finally, the semiconductor wafer 100 is cut along the dicing street S (not shown). In this manner, a multilayer wiring structure in the CSP structure semiconductor device is formed.

  By the way, in the formation process of the multilayer wiring structure described above, particles generated due to some cause (for example, material, equipment, environment) adhere to the silicon substrate 100 and cause short-circuit between the metal wiring layers, or within the metal wiring layer. May cause an open defect. If the particles themselves are a conductive material, this will cause a short circuit only between the wires. Regardless of the material of the particles, the interlayer insulating film may be deformed by the adhered particles, and sometimes the film formation of the interlayer insulating film may be hindered. For example, as shown in FIGS. 40, 41 (A) and (B), when particles P adhere to the semiconductor wafer 100 for some reason in the manufacturing process, the metal wiring layer 300 is pushed up by the particles P. It can be seen that a short circuit between the metal wiring layer 300 and the metal wiring layer 500 may occur. Here, since the metal wiring layer 300 and the metal wiring layer 500 that are short-circuited due to the presence of the particles P are originally required to be insulated and separated, it can be understood that a wiring abnormality occurs due to the presence of the particles P. Thus, when a wiring abnormality occurs due to particles, the yield may be reduced.

  In addition to particles, there are cases where the upper and lower metal wiring layers are short-circuited due to defects such as pinholes and other interlayer insulation films and wiring material hillocks, leading to a decrease in yield.

  Therefore, for example, as disclosed in Patent Document 1, it is considered that the entire surface of the metal wiring layer is oxidized in advance and an oxide film is formed on the entire surface, thereby preventing a short circuit between the metal wiring layers. It is done.

  For example, as disclosed in Patent Document 2, when a metal wiring layer is exposed from an interlayer insulating film for some reason, the exposed portion is oxidized in an oxygen atmosphere, and an oxide film is formed on the exposed portion. By doing so, it is conceivable to prevent a short circuit between the metal wiring layers.

JP 2005-252162 A Japanese Patent Laid-Open No. 01-11049

  However, in the measure of Patent Document 1, after the entire surface of the metal wiring layer is oxidized to form an oxide film, a photolithography process and an oxide film etching process are newly added, and the upper layer metal wiring in the oxide film is added. It is necessary to provide an opening in the portion that contacts the layer. Here, since the photolithography process is generally expensive, when the photolithography process is added, the manufacturing cost is significantly increased. In addition, an interlayer insulating film having an opening corresponding to a portion in contact with the upper metal wiring layer is formed on a metal wiring layer whose surface is oxidized with a photosensitive resin, and then the interlayer insulating film is masked. In the case of removing the exposed portion of the oxide film by etching, it is necessary to use an etchant such as dilute sulfuric acid for removing the oxide film. The etchant may swell the interlayer insulating film or possibly peel off the interlayer insulating film. May occur, and the function as an interlayer insulating film may be impaired.

  Further, according to the measure of Patent Document 2, it is not necessary to newly add a step of providing an opening in an oxide film formed by oxidizing a metal wiring layer. However, if a part of the lower metal wiring layer penetrates the interlayer insulating film thereabove and has a protruding shape that protrudes significantly, the entire surface including the metal wiring layer on which the oxide film is formed After forming an interlayer insulating film made of silicon oxide, when a resist having an opening is provided in a portion of the interlayer insulating film that contacts the upper metal wiring layer, the metal wiring layer has a protruding shape. There is a possibility that the portion is not coated with the resist and exposed. When the protruding portion of the metal wiring layer is actually exposed from the resist, when the interlayer insulating film is etched using the resist as a mask, the interlayer insulating film made of silicon oxide and the metal The selective ratio with the oxide film formed by oxidizing the wiring layer cannot be taken sufficiently, and the oxide film formed may be etched together, which may not lead to an improvement in yield. .

  The present invention has been made in view of such problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of preventing a short circuit between metal wiring layers.

  In the method of manufacturing a semiconductor device according to the present invention, first, after forming a first insulating layer on a semiconductor substrate, a plurality of metal wiring layers independent from each other are formed on the surface of the first insulating layer, and each metal wiring layer is further formed. A photosensitive second insulating layer is formed on the surface containing the. Next, when the second insulating layer is made of a positive type material, the first exposure amount is lower than the exposure sensitivity at which the remaining film ratio of the second insulating layer facing the metal wiring layer is zero. The second insulating layer is developed after exposing a predetermined region of the facing portion. On the other hand, when the second insulating layer is made of a negative material, the predetermined region is exposed with a second exposure amount higher than the exposure sensitivity, and the second insulation is performed with a third exposure amount higher than the second exposure amount. An area of the layer excluding the predetermined area is exposed. Next, after performing a metal oxidation process on the entire surface including the second insulating layer, ashing using an oxidation reaction is performed to remove a portion corresponding to the predetermined region in the second insulating layer.

  In the method for manufacturing a semiconductor device of the present invention, when the second insulating layer is made of a positive type material, the exposure sensitivity is such that the remaining film ratio of the second insulating layer facing the metal wiring layer is zero. When the second insulating layer is developed after the predetermined region of the facing portion is exposed with a low first exposure amount, and the second insulating layer is made of a negative material, the second exposure amount higher than the exposure sensitivity. Then, the predetermined region is exposed and a region other than the predetermined region in the second insulating layer is exposed with a third exposure amount higher than the second exposure amount. Thereby, a remaining film of the second insulating film is formed in the predetermined region. Next, a metal oxidation process is performed on the entire surface including the second insulating layer. Thereby, when a part of the metal wiring layer is exposed on the surface including the second insulating layer for some reason, an oxide film is formed on the surface of the exposed part. At this time, the remaining film of the second insulating film is formed in the predetermined region, and the portion of the metal wiring layer facing the predetermined region is protected by the remaining film. The portion facing the predetermined region is not oxidized. Next, by performing ashing utilizing an oxidation reaction, a portion corresponding to the predetermined region in the second insulating layer is removed. Thus, even if an oxide film is formed on the surface of the exposed portion of the metal wiring layer in the previous step, the metal wiring layer is opposed to the predetermined region without removing the oxide film. The part can be exposed.

  According to the method for manufacturing a semiconductor device of the present invention, with respect to the entire surface including the second insulating layer in a state where the portion facing the predetermined region of the metal wiring layer is protected by the remaining film of the second insulating film. Since the portion corresponding to the predetermined region of the second insulating layer is removed by performing ashing using an oxidation reaction after the metal oxidation treatment, the surface including the second insulating layer for some reason In addition, even when a portion of the metal wiring layer excluding the portion facing the predetermined region is exposed, an oxide film is formed on the surface of the exposed portion, and the predetermined portion of the metal wiring layer is formed. A portion facing the region can be exposed. Thereby, even when a part of the metal wiring layer is exposed on the surface including the second insulating film due to particles adhering to the surface for some reason, the metal wiring layer is formed on the second insulating layer. When a metal wiring layer electrically connected to a portion facing the predetermined region is newly formed, the metal wiring layer is opposed to the predetermined region in the metal wiring layer immediately below the second insulating film. It is possible to eliminate the possibility of direct contact with a portion other than the portion. As a result, a short circuit between the metal wiring layers caused by particles can be prevented, so that the yield is improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a top surface configuration of a semiconductor device 1 having a CSP structure manufactured by a manufacturing method according to an embodiment of the present invention. 2 shows an example of a cross-sectional configuration in the direction of arrows AA of the semiconductor device 1 in FIG. 1, and FIG. 3A shows an example of a cross-sectional configuration in the direction of arrow BB of the semiconductor device 1 in FIG. 3B represents an example of a cross-sectional configuration of the semiconductor device 1 in FIG. 1, 2, 3 </ b> A, and 3 </ b> B are schematically shown and are different from actual dimensions and shapes.

  The semiconductor device 1 includes a multilayer wiring structure 20 on a semiconductor substrate 10.

  The semiconductor substrate 10 is obtained by forming an interlayer insulating film 12 and a passivation layer 13 in this order on a surface on the integrated circuit side of a silicon substrate 11 having an integrated circuit (not shown) formed on one surface. In the interlayer insulating film 12, a wiring layer and a via (both not shown) electrically connected to the integrated circuit are formed. In addition, a plurality of electrode pads 14 are formed, for example, in a line on the upper surface of the interlayer insulating film 12, and each electrode pad 14 is connected to the integrated circuit via the wiring layer and vias of the interlayer insulating film 12. Electrically connected. The passivation layer 13 is provided with openings corresponding to the electrode pads 14, and the electrode pads 14 are exposed from the openings. 1, 2, 3 </ b> A, and 3 </ b> B illustrate the case where five electrode pads 14 are provided.

Here, the integrated circuit is configured by, for example, a general MOS configured by element isolation, a diffusion layer, a channel, a gate, or the like, or a transistor such as a bipolar, a diode, a capacitor, or the like. The interlayer insulating film 12 and the passivation layer 13 are made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), or an insulating material having a relative dielectric constant lower than these. The wiring layer, via and electrode pad 14 are made of, for example, aluminum (Al) or copper (Cu).

  The multilayer wiring structure 20 is formed on the surface of the semiconductor substrate 10 on the side where the integrated circuit is formed, and includes interlayer insulating films 21 and 22, metal wiring layers 23, 24 and 25, and external electrode terminals 26. And have. The interlayer insulating films 21 and 22 and the metal wiring layers 23, 24, and 25 are formed from the semiconductor substrate 10 (passivation layer 13) side by the interlayer insulating film 21, the metal wiring layers 23 and 24, the interlayer insulating film 22, and the metal wiring layer 25. They are stacked in order.

  The interlayer insulating film 21 is formed on the surface of the semiconductor substrate 10 and has an opening 21 </ b> A corresponding to each electrode pad 14. Thereby, each electrode pad 14 is exposed from the opening 21 </ b> A on the surface of the interlayer insulating film 21.

  The interlayer insulating film 22 is formed on the surface including the metal wiring layers 23 and 24, and corresponds to end portions 23 </ b> A (described later) of the metal wiring layers 23 and both end portions of the metal wiring layers 24. An opening 22A is provided. As a result, end portions 23 </ b> A of each metal wiring layer 23 and both end portions of metal wiring layer 24 are exposed from opening 22 </ b> A on the surface of interlayer insulating film 22.

  Here, the interlayer insulating films 21 and 22 are configured to include a heat-resistant photosensitive resin such as polyimide or PBO (polybenzoxazole), for example, and may be configured only from the heat-resistant photosensitive resin. A multilayer structure in which a photosensitive resin layer is superposed on an insulating resin layer having no photosensitivity may be employed. The photosensitive resin has a positive type in which the exposed part (irradiated with ultraviolet rays) is dissolved and removed in the subsequent development process. Conversely, the exposed part is cured and the other unexposed part. There are two types of negatives that are dissolved and removed in the development process. Either type of photosensitive resin may be used for the interlayer insulating film 21, but it is preferable to use a positive photosensitive resin that can easily control the remaining film for the interlayer insulating film 22.

  The metal wiring layer 23 is formed on the surface of the electrode pad 14 and the surface of the interlayer insulating film 21, and extends from the surface of each electrode pad 14 to a predetermined portion on the surface of the interlayer insulating film 21. It is formed (FIGS. 1, 2, and 3B). Here, the end of the metal wiring layer 23 not facing the electrode pad 14 is defined as 23A. 1, 2, and 3 (B) exemplify a case where one metal wiring layer 23 is provided on each of the five electrode pads 14.

  The metal wiring layer 24 is formed on the surface of the interlayer insulating film 21, and extends on the surface of the semiconductor substrate 10 (passivation layer 13) without contacting each electrode pad 14 and each metal wiring layer 23. (FIG. 1). FIG. 1 illustrates the case where only one metal wiring layer 24 is provided.

  The metal wiring layer 25 has an end portion of at least one of the plurality of metal wiring layers 23 on the surface of 23A, the surface of one end portion of the metal wiring layer 24, and the surface of the interlayer insulating film 22. It is formed continuously and extends from the surface of the end portion 23A of the metal wiring layer 23 through the portion facing the metal wiring layer 23 to the surface of one end portion of the metal wiring layer 24. It is formed (FIG. 1, FIG. 3 (A)). 1 and 3A illustrate the case where the metal wiring layer 25 is connected to the surfaces of the end portions 23A of the two metal wiring layers 23. FIG.

  The metal wiring layers 23, 24, and 25 are, for example, plated Cu using copper sulfate, for example, on a base layer (not shown) formed by sequentially laminating titanium (Ti) and copper (Cu) from the semiconductor wafer 100 side. A wiring layer (not shown) made of is formed.

  The external electrode terminal 26 is formed on the surface of the end portion 23 </ b> A that is not opposed to the electrode pad 14 among the metal wiring layers 23 that are not connected to the metal wiring layer 25 among the plurality of metal wiring layers 23. For example, the land portion 26A, the columnar electrode portion 26B, and the bump portion 26C are sequentially stacked from the surface side of the end portion 23A.

  The land portion 26A is for connection with the end portion 23A. For example, the land portion 26A is formed on an underlayer (not shown) formed by sequentially laminating titanium (Ti) and copper (Cu) from the semiconductor wafer 100 side. For example, a wiring layer (not shown) made of plated Cu using copper sulfate is formed.

  The columnar electrode portion 26B is for making the height of the external electrode terminal 26 constant and relieving stress during mounting on the module, and is formed, for example, in the same manner as the land portion 26A.

  The bump portion 26C is for connection with an electrode pad (not shown) such as a printed circuit board, and is made of, for example, hemispherical solder.

  A sealing layer 27 is formed on the surface including the metal wiring layer 25 and the interlayer insulating film 22. The sealing layer 27 is made of, for example, an organic resin such as an epoxy resin, covers the metal wiring layer 25 and the interlayer insulating film 22, and partially covers the external electrode terminal 26 (land portion 26 </ b> A and columnar electrode portion 26 </ b> B). Covering.

  Incidentally, in the semiconductor device 1, for example, as illustrated in FIGS. 2 and 3A, particles P are mixed. The particles P are attached with dust generated by various factors in the manufacturing process. For example, the diameter of the particles P is larger than the thickness of the interlayer insulating film 22 or 24.

  In general, the manufacturing process of the semiconductor device 1 is performed in a controlled environment called “clean room” with extremely few particles. However, the malfunction of various facilities used in the process, partial contamination of the clean room environment, There are various reasons for the generation of particles, such as those caused by a person handling a wafer in a clean room.

  Therefore, although the constituent material of the particle P differs depending on the generation factor of the particle P, it is made of, for example, a conductive or insulating material.

  As illustrated in FIG. 2 and FIG. 3A, when the metal wiring layer 23 and the metal wiring layer 25 are mixed at a location where they intersect each other when viewed from the stacking direction, as illustrated in FIGS. 23 is formed in a region including the upper surface of the particle P and is pushed up by the particle P in the stacking direction.

  At this time, the top of the portion of the metal wiring layer 23 that is pushed upward in the stacking direction by the particles P is exposed from the interlayer insulating film 22, so that the upper metal wiring layer 25 and the interlayer insulating film 22 are not interposed. An insulating film 28 is provided on the surface layer of the metal wiring layer 23 exposed from the interlayer insulating film 22. As will be described later, the insulating film 28 is formed by oxidizing a portion of the metal wiring layer 23 exposed from the interlayer insulating film 22 and forms a part of the metal wiring layer 23. Therefore, the metal wiring layer 23 and the metal wiring layer 25 are insulated and separated by the insulating film 28 in the portion exposed from the interlayer insulating film 22 in the metal wiring layer 23 and are not electrically conductive.

  Next, an example of a method for forming the multilayer wiring structure 20 in the semiconductor device 1 will be described with reference to FIGS.

  FIG. 4 shows a part of the upper surface configuration of the semiconductor wafer 10A (a portion surrounded by dicing streets). The semiconductor wafer 10A cut along the dicing street corresponds to the semiconductor substrate 10. 5A shows the cross-sectional configuration of the semiconductor wafer 10A in FIG. 4 in the direction of arrows AA, and FIG. 5B shows the cross-sectional configuration of the semiconductor wafer 10A in FIG. 3 in the direction of arrows BB. It is. 6, FIG. 8, FIG. 12, FIG. 14, FIG. 16, FIG. 18, FIG. 20 and FIG. 22 show the top surface configuration of the chip in the manufacturing process. 7A, FIG. 9A, FIG. 13A, FIG. 15A, FIG. 17A, FIG. 19A, FIG. 21A, and FIG. FIG. 7B, FIG. 9B, FIG. 13B, FIG. 15B, and FIG. 17B show cross-sectional configurations in the direction of arrows AA in the previous drawing. FIG. 19B, FIG. 21B, and FIG. 23B each show a cross-sectional configuration in the direction of arrows BB in the previous drawing.

  First, a semiconductor wafer 10A for forming the multilayer wiring structure 20 is prepared (FIGS. 4, 5A, and 5B). At this time, the passivation layer 13 is exposed on the surface of the semiconductor wafer 10 </ b> A, and the electrode pad 14 </ b> A is exposed from the opening of the passivation layer 13. Further, particles P are attached on the surface of the passivation layer 13. Here, the particle P has a diameter larger than the thickness of the interlayer insulating film 22D formed in the following process, and the metal wiring layer 23 and the metal wiring layer 25 are viewed from above in the stacking direction. It shall be attached to the intersecting part.

  Next, an interlayer insulating film 21 having openings 21A corresponding to the electrode pads 14 is formed on the surface of the semiconductor wafer 10A on the integrated circuit side (FIGS. 6, 7A, and 7B). Thereby, each electrode pad 14 is exposed from the opening 21A. The interlayer insulating film 21 is formed, for example, by applying a photosensitive resin (polyimide or the like) on the semiconductor wafer 10A, pre-baking, and subsequently performing pattern exposure and development. At this time, if necessary, a discum process for etching the undeveloped residue (scum) under oxygen plasma may be added.

  Next, a plurality of metal wiring layers 23 extending from the surface of each electrode pad 14 to a predetermined portion of the surface of the interlayer insulating film 21, and the interlayer insulating film without being in contact with each electrode pad 14 and each metal wiring layer 22 And a metal wiring layer 24 extending on the surface of 21 (FIGS. 8, 9A and 9B). Here, the metal wiring layers 23 and 24 are formed using a plating technique such as a semi-additive method. Specifically, Ti and Cu (underlying layer) are formed on the entire surface of the interlayer insulating film 21 by sputtering, and openings are formed in portions where the metal wiring layers 23 and 24 are to be formed thereon. After forming a plating resist having Cu, the Cu (wiring layer) is formed by electrolytic plating, and then the plating resist is peeled and removed. Further, using Cu (wiring layer) as a mask, Ti and Cu (underlayer) ) Are removed by wet etching to form metal wiring layers 23 and 24.

  At this time, since the particle P is attached to a portion where the metal wiring layer 23 and the metal wiring layer 25 cross each other when viewed from the stacking direction, a portion of the metal wiring layer 23 formed on the particle P Are pushed upward by the particles P in the stacking direction.

  Next, after forming a heat-resistant photosensitive resin on the surface including the metal wiring layers 23 and 24, among the formed photosensitive resin, the end 23A of each metal wiring layer 23 and each metal wiring The portions corresponding to both ends of the layer 24 are exposed and developed.

At this time, when a positive type material (for example, polyimide or PBO (polybenzoxazole)) is used as the photosensitive resin, the remaining film in the portion facing the metal wiring layers 23 and 24 in the formed photosensitive resin. End portions 23A of the respective metal wiring layers 23 and both ends of the respective metal wiring layers 24 at an exposure amount (first exposure amount) lower than the exposure sensitivity (the exposure amount corresponding to _DT in FIG. 10) at which the rate becomes zero. After exposing the part corresponding to the part, the formed photosensitive resin is developed.

Further, when a negative type material is used as the photosensitive resin, the exposure sensitivity (D in FIG. 11) in which the remaining film ratio in the portion facing the metal wiring layers 23 and 24 in the formed photosensitive resin becomes zero. (Exposure amount corresponding to _T ) is exposed at a higher exposure amount (second exposure amount), and the portions corresponding to the end portions 23A of each metal wiring layer 23 and both end portions of each metal wiring layer 24 are exposed, and D _After exposing the area | region except the area | region exposed above among the photosensitive resin formed into a film with the exposure amount (3rd exposure amount) higher than _T , the formed photosensitive resin is developed.

  10 and 11 are tables showing the relationship between the exposure amount and the remaining film rate, and it can be seen from this figure that the exposure amount and the remaining film rate are relatively proportional. Therefore, in the case of the positive type, exposure is performed with an exposure amount slightly lower than the exposure sensitivity. In the case of the negative type, exposure is performed with an exposure amount slightly higher than the exposure sensitivity. It is possible to intentionally generate a residual film.

  As a result, as shown in FIGS. 12, 13A, and 13B, the photosensitive resin is applied to the portions corresponding to the end portions 23A of each metal wiring layer 23 and both end portions of each metal wiring layer 24. An interlayer insulating film 22D having a remaining film 22E is formed.

  Here, the thickness of the remaining film 22E is preferably about 0.5 to 2 μm, considering the ease of removal when the remaining film 22E is removed in a later step, and preferably 0.5 to 0.8 μm. More preferably, it is about.

  Here, the portion of the metal wiring layer 23 formed on the particle P is exposed from the interlayer insulating film 22D, and the exposed portion (exposed portion 23B) is the interlayer insulating film. Not covered (protected) by 22D. It should be noted that the metal wiring layer 23 is originally required to be entirely covered at the stage of forming the photosensitive resin, but in this case, the exposed portion 23B occurs due to the presence of the particles P. I'm stuck.

  Next, the semiconductor wafer 10A is set in an oven that can be heated to about 200 to 400 ° C., and the entire surface including the exposed portion 23B is subjected to metal oxidation treatment in an air atmosphere or an oxygen atmosphere, and the exposed portion 23B. An oxide film 28 is formed on the surface layer by thermal oxidation (FIGS. 14, 15A and 15B).

  Here, the set temperature is a temperature at which the surface layer of the exposed portion 23B is oxidized (about 200 ° C. when the exposed portion 23B is made of copper). When the exposed portion 23B made of copper is heated in an oven set at 200 ° C. for 2 hours, the thickness of the oxide film 28 can be increased to about 50 nm to 70 nm.

  The oven set temperature and heating time vary depending on the material of the exposed portion 23B and the thickness of the oxide film 28. Further, the oxide film 28 may be formed not only by a method of heating in an air atmosphere or an oxygen atmosphere but also by using another method. For example, it may be formed using a chemical (chemical solution) such as hydrogen peroxide solution, or may be formed by performing a blackening treatment for forming a cuprous oxide film (so-called blackened film). Moreover, you may form by exposing the exposed part 23B in oxygen plasma.

  Next, ashing is performed in oxygen plasma on the remaining film 22E intentionally generated by adjusting the exposure amount. As a result, the remaining film 22E is removed, an opening 22A is formed in the interlayer insulating film 22, and the metal wiring layer 23 is exposed from the opening 22A (FIGS. 16, 17A, and B). ).

  At this time, since the oxide film 28 formed in the exposed portion 23B is a non-moving body with respect to oxygen plasma and is not affected by the oxygen plasma, only the remaining film 22E can be selectively removed. .

  Here, the ashing conditions vary depending on the equipment to be used, but when a parallel plate RIE type equipment is used, applied power = 500 W, chamber internal pressure = 150 Pa, oxygen flow rate = 1000 sccm, substrate heating temperature = Under the condition of 100 ° C., an ashing rate of about 0.5 μm / min can be obtained.

  The ashing process may be performed after the subsequent interlayer insulating film 22 is cured. In such a case, since the resistance of the interlayer insulating film 22 is increased, the ashing amount is reduced to 1/3 when the ashing conditions described above are used as compared with the case of ashing before curing. The productivity becomes worse. However, as in the case where ashing is performed before curing, it is not affected by oxygen plasma, so that only the remaining film 22E can be selectively removed.

  Next, the semiconductor wafer 10 </ b> A is set in an oven, and the interlayer insulating film 22 is baked. At this time, the oven used in the above-mentioned metal oxidation treatment step can also be used. However, the main curing of polyimide or PBO is performed at a temperature of 200 to 400 ° C. in an oven in which nitrogen substitution is performed and the oxygen concentration can be controlled to 20 ppm or less. It is common to cure. In this state, the surface of the metal wiring layer 23 exposed in the opening 22A is hardly oxidized because the curing is performed in a low oxygen state. If it has been oxidized, an oxide film (not shown) on the surface of the metal wiring layer 23 exposed in the opening 22A is lightly removed by using a mixed gas of oxygen and argon. May be. However, if this removal process is performed a lot, the oxide film 28 is also removed at the same time.

  Next, the end of at least one metal wiring layer 23 among the plurality of metal wiring layers 23 is placed over the surface of 23A, the surface of one end of the metal wiring layer 24, and the surface of the interlayer insulating film 22. A wiring layer 25 is formed, and a land is formed on the surface of the end portion 23A of the plurality of metal wiring layers 23 that is not connected to the metal wiring layer 25 and that is not opposed to the electrode pad 14. A portion 26A is formed (FIGS. 18, 19A and 19B). The metal wiring layer 25 and the land portion 26 </ b> A are formed by the same method as that for the metal wiring layer 23.

  Here, the metal wiring layer 25 is electrically isolated from the metal wiring layer 23 by an insulating film 28 formed on the surface layer of the metal wiring layer 23 exposed from the interlayer insulating film 22. Not.

  Next, columnar columnar electrodes 26B are formed on each land portion 26A as necessary (FIGS. 20, 21A, and B). The columnar electrode 26B is also formed by the same method as that for the metal wiring layer 23.

  Next, when the columnar electrode 26B is formed, the sealing resin thicker than the columnar electrode 26B is formed on the entire surface including the columnar electrode 26B by, for example, a transfer molding method, a dispenser method, a dipping method, or a printing method. After film formation, the upper surface of the sealing resin is polished and removed. As a result, the columnar electrode 26B having an exposed upper surface is formed, and the sealing layer 27 having the upper surface in substantially the same plane as the upper surface of the columnar electrode 26B is formed (FIGS. 22, 23A, and B). )).

  When burrs are generated on the upper surface of the columnar electrode 26B by polishing, the burrs are removed by wet etching or the like, and further, nickel is formed on the upper surface of the columnar electrode 26B by electroless plating in order to prevent subsequent oxidation. Surface treatment such as forming a layer may be performed.

  Next, a solder bump 26C is formed on the upper surface of the columnar electrode 26B when the columnar electrode 26B is formed, and on the upper surface of the land portion 26A when the columnar electrode 26B is not formed (FIGS. 1 and 2). FIG. 3 (A)). Thereby, the external electrode terminal 26 is formed. For example, the solder bump 26C is reflowed after mounting a solder ball directly on the upper surface of the columnar electrode 26B, or reflowed after a solder paste is applied to the upper surface of the columnar electrode 26B by a printing method or a dispenser method. It is formed by the method.

  Finally, the semiconductor wafer 10A is cut along the dicing street S (not shown). In this way, the multilayer wiring structure 20 in the semiconductor device 1 having the CSP structure is formed.

  In the method of manufacturing the semiconductor device 1 according to the present embodiment, the surface including the interlayer insulating film 22 in a state where the facing portions of the metal wiring layers 23 and 24 facing a predetermined region are protected by the remaining film 22E of the interlayer insulating film 22. After performing the metal oxidation treatment on the whole, the portion corresponding to the predetermined region is removed from the interlayer insulating film 22 by performing ashing utilizing an oxidation reaction. Even when a portion of the metal wiring layers 23 and 24 excluding the portion facing the predetermined region is exposed on the surface including the exposed portion 22, an oxide film is formed on the surface of the exposed portion (exposed portion 23B). 28 can be formed, and portions of the metal wiring layers 23 and 24 facing the predetermined region can be exposed.

  Thereby, even when a part of the metal wiring layers 23 and 24 is exposed on the surface including the interlayer insulating film 22 due to the particles P adhering to the surface for some reason, When the metal wiring layer 25 electrically connected to the portion facing the predetermined region of the metal wiring layers 23 and 24 is newly formed, the metal wiring layer 25 is a metal wiring layer immediately below the interlayer insulating film 22. It is possible to eliminate the possibility of direct contact with a portion other than the portion facing the predetermined region. As a result, the short circuit between the metal wiring layers caused by the particles P can be prevented, and the yield is improved.

  Although the present invention has been described with reference to the embodiment and the modification, the present invention is not limited to the above-described embodiment and the like, and various modifications can be made.

  For example, when forming the interlayer insulating film 22D (see FIGS. 12, 13A and 13B), instead of using a heat-resistant photosensitive resin, an insulating resin having no photosensitivity may be used. Good. However, in that case, for example, the interlayer insulating film 22D can be formed as follows.

  First, an insulating resin layer having no photosensitivity is formed on the surface including the metal wiring layers 23 and 24, and then prebaked. Next, after forming a positive resist layer over the entire surface of the pre-baked insulating resin layer, portions corresponding to the end portions 23A of each metal wiring layer 23 and both end portions of each metal wiring layer 24 To expose. Next, after developing the positive resist layer using a strong alkali solution such as TMAH aqueous solution (ammonium hydroxide), for example, using the etchant used for the development, the openings of the resist layer formed by development are opened. The insulating resin layer is etched through. At this time, by finely adjusting the etching amount of the insulating resin layer, it is possible to intentionally generate a remaining film at the etched portion. As a result, as shown in FIGS. 12, 13A, and 13B, the photosensitive resin is applied to the portions corresponding to the end portions 23A of each metal wiring layer 23 and both end portions of each metal wiring layer 24. An interlayer insulating film 22D having a remaining film 22E can be formed.

It is a section lineblock diagram of a semiconductor device concerning one embodiment of the present invention. 2 is a cross-sectional configuration diagram of the semiconductor device of FIG. FIG. 2 is a cross-sectional configuration diagram of the semiconductor device of FIG. 1 in the direction of arrows BB and CC. FIG. 2 is a top view of a semiconductor wafer for explaining a method for manufacturing the semiconductor device of FIG. 1. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 5 is a top view of a semiconductor wafer for explaining a process following FIG. 4. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 7 is a top structural view of a semiconductor wafer for explaining a process following FIG. 6. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 6 is a relationship diagram between a remaining film ratio and an exposure amount in a positive type resin. FIG. 4 is a relationship diagram between a remaining film ratio and an exposure amount in a negative resin. FIG. 9 is a top structural view of a semiconductor wafer for explaining a process following FIG. 8. It is a cross-sectional block diagram of the semiconductor wafer of FIG. It is a top surface block diagram of the semiconductor wafer for demonstrating the process following FIG. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 15 is a top structural view of a semiconductor wafer for explaining a process following FIG. 14. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 17 is a top surface configuration diagram of a semiconductor wafer for describing a process following FIG. 16. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 19 is a top surface configuration diagram of a semiconductor wafer for describing a process following the process in FIG. 18. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 21 is a top structural view of a semiconductor wafer for explaining a process following FIG. 20. It is a cross-sectional block diagram of the semiconductor wafer of FIG. It is a top surface block diagram of the semiconductor wafer for demonstrating the manufacturing method of the conventional semiconductor device. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 25 is a top surface configuration diagram of a semiconductor wafer for describing a process following FIG. 24. FIG. 27 is a cross-sectional configuration diagram of the semiconductor wafer of FIG. 26. FIG. 27 is a top surface configuration diagram of a semiconductor wafer for describing a process following FIG. 26; It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 29 is a top surface configuration diagram of a semiconductor wafer for illustrating a process following the process in FIG. 28. It is a cross-sectional block diagram of the semiconductor wafer of FIG. FIG. 31 is a top surface configuration diagram of a semiconductor wafer for describing a process following the process in FIG. 30; FIG. 33 is a cross-sectional configuration diagram of the semiconductor wafer of FIG. 32. FIG. 33 is a top surface configuration diagram of a semiconductor wafer for illustrating a process following the process in FIG. 32. FIG. 35 is a cross-sectional configuration diagram of the semiconductor wafer of FIG. 34. FIG. 35 is a top structural view of a semiconductor wafer for explaining a step following FIG. 34; FIG. 37 is a cross-sectional configuration diagram of the semiconductor wafer of FIG. 36. FIG. 37 is a top structural view of a semiconductor wafer for explaining a step following FIG. 36. It is a cross-sectional block diagram of the semiconductor wafer of FIG. It is a top surface block diagram showing typically a mode that particles mixed into a semiconductor device. FIG. 41 is a cross-sectional configuration diagram of the semiconductor device of FIG. 40.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Semiconductor substrate, 10A ... Semiconductor wafer, 11 ... Silicon substrate, 12, 21, 22 ... Interlayer insulation film, 13 ... Passivation layer, 14 ... Electrode pad, 20 ... Multilayer wiring structure, 23, 24, 25 ... Metal wiring layer, 26 ... External electrode terminal, 26A ... Land part, 26B ... Columnar electrode part, 26C ... Bump part, 27 ... Sealing layer. 28: Insulating film, P: Particle.

Claims (9)

After forming the first insulating layer on the semiconductor substrate, a plurality of independent metal wiring layers are formed on the surface of the first insulating layer, and a photosensitive second layer is formed on the surface including the metal wiring layers. Forming an insulating layer;
When the second insulating layer is made of a positive-type material, the opposing surface is exposed at a first exposure amount lower than the exposure sensitivity at which the remaining film ratio of the opposing portion of the second insulating layer to the metal wiring layer is zero. The second insulating layer is developed after exposing a predetermined area of the portion, and when the second insulating layer is made of a negative material, the predetermined area is exposed with a second exposure amount higher than the exposure sensitivity. And exposing a region excluding the predetermined region of the second insulating layer with a third exposure amount higher than the second exposure amount;
Removing a portion of the second insulating layer corresponding to the predetermined region by performing ashing utilizing an oxidation reaction after performing a metal oxidation process on the entire surface including the second insulating layer; A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 1, wherein the ashing is performed using oxygen plasma. 3. The semiconductor device according to claim 1, wherein the metal oxidation treatment is performed by heating the entire surface including the second insulating layer in a state of being exposed to an atmosphere containing oxygen. 4. Production method. The method for manufacturing a semiconductor device according to claim 1, wherein the metal oxidation treatment is ashing using an oxidation reaction. The method of manufacturing a semiconductor device according to claim 4, wherein the ashing is performed using oxygen plasma. The method for manufacturing a semiconductor device according to claim 2, wherein the second insulating layer is made of a positive photosensitive resin. The method for manufacturing a semiconductor device according to claim 6, wherein the second insulating layer is made of polyimide. The method for manufacturing a semiconductor device according to claim 6, wherein the second insulating layer is made of polybenzoxazole. The method for manufacturing a semiconductor device according to claim 1, wherein the remaining film has a thickness of 0.5 μm to 2 μm.

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