JP2009054946A - Semiconductor device and its production process - Google Patents

Semiconductor device and its production process Download PDF

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JP2009054946A
JP2009054946A JP2007222659A JP2007222659A JP2009054946A JP 2009054946 A JP2009054946 A JP 2009054946A JP 2007222659 A JP2007222659 A JP 2007222659A JP 2007222659 A JP2007222659 A JP 2007222659A JP 2009054946 A JP2009054946 A JP 2009054946A
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diffusion layer
mos transistor
trench
semiconductor substrate
semiconductor device
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Yuichiro Kitajima
裕一郎 北島
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to JP2007222659A priority Critical patent/JP2009054946A/en
Priority to TW097132821A priority patent/TW200924197A/en
Priority to US12/200,122 priority patent/US20090057731A1/en
Priority to KR1020080084634A priority patent/KR20090023235A/en
Priority to CNA2008102134043A priority patent/CN101378078A/en
Publication of JP2009054946A publication Critical patent/JP2009054946A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a high drive-capability lateral MOS transistor whose gate width per unit area is increased and whose device characteristic is stable. <P>SOLUTION: In the MOS transistor, since a structure of a trench or a fin horizontally arranged in the gate length direction is formed in a stepwise manner along a gate width direction to thereby reduce a step height between the semiconductor substrate surface and the trench bottom or the fin top, even if the MOS transistor includes a deep trench or a high fin in order to increase the drive-capability per unit area, a uniform impurity concentration in a channel region, a source diffusion region, and a drain diffusion region can be made by an ion implantation method. Accordingly, there can be obtained a stable characteristic that variation in the characteristic due to a surface on which the channel is formed does not appear, and the high drive-capability lateral MOS transistor having a reduced on-resistance per unit area can be provided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は高駆動能力を有するMOSトランジスタを含む半導体装置に関する。   The present invention relates to a semiconductor device including a MOS transistor having a high driving capability.

ボルテージレギューレータ(以下VR)やスイッチングレギュレータ(以下SWR)と呼ばれる、電源電圧を制御し、一定電圧を出力するICにおいては、使用するアプリケーションにより高効率、高出力電流が要求される場合に、低ON抵抗のMOSトランジスタが必要となってくる。この場合、駆動能力の高いMOSトランジスタが必要とされるため、外付けのPower MOSを使用することにより対応することができる。しかし、電源制御回路全体としては部品点数が増えてしまい、部品増加および実装などによりコストが増大することが懸念される。   In an IC called a voltage regulator (hereinafter referred to as VR) or switching regulator (hereinafter referred to as SWR) that controls the power supply voltage and outputs a constant voltage, when high efficiency and high output current are required by the application used, A low ON resistance MOS transistor is required. In this case, since a MOS transistor having a high driving capability is required, it can be dealt with by using an external Power MOS. However, the power supply control circuit as a whole has an increased number of parts, and there is a concern that costs increase due to an increase in parts and mounting.

そこで、外付けとして使用しているPower MOSをVRやSWRの内部に取り込むことにより、コストを削減する方法が挙げられる。Power MOSをVRおよびSWRの内部に取り込むことにより、1チップ化が図れるため、前述の部品点数や実装などによって発生するコストは削減できることになる。しかし、Power MOSでは基板の深さ方向に電流を流す縦型MOS構造が主流であり、素子単体としては非常に優れた性能を有しているが、VRやSWRの内部に取り込むことは困難である。よって、Power MOSを内部に取り込む際に横型MOS構造を採用した場合、低オン抵抗とするにはトランジスタサイズを大きくする必要が出てくるので、これによりチップ面積が増大することが懸念される。   Therefore, there is a method to reduce the cost by incorporating the power MOS used as an external device into the VR or SWR. By incorporating the Power MOS into the VR and SWR, a single chip can be achieved, thereby reducing the costs caused by the number of components and mounting described above. However, Power MOS mainly uses a vertical MOS structure in which current flows in the depth direction of the substrate, and it has excellent performance as a single element, but it is difficult to incorporate it into a VR or SWR. is there. Therefore, when the lateral MOS structure is adopted when taking the Power MOS into the inside, it is necessary to increase the transistor size in order to achieve a low on-resistance, which may increase the chip area.

その対策として、チャネル部にトレンチを形成することでトランジスタのチャネル幅を増加させる方法がある(例えば特許文献１の図２を参照)。この方法によると、素子面積を同一としたまま、溝の深さに応じてチャネルの幅を大きくできるため、素子のチャネル部の抵抗を小さく、すなわち素子自体の抵抗を小さくすることができ、オン抵抗を低減することができる。また、溝を複数形成すれば、これらの溝の設置密度に応じてもチャネルの幅を大きくできるので、より効果的にオン抵抗を低減することができるようになる。   As a countermeasure, there is a method of increasing the channel width of the transistor by forming a trench in the channel portion (see, for example, FIG. 2 of Patent Document 1). According to this method, since the channel width can be increased according to the depth of the groove while keeping the element area the same, the resistance of the channel portion of the element can be reduced, that is, the resistance of the element itself can be reduced. Resistance can be reduced. In addition, if a plurality of grooves are formed, the channel width can be increased according to the installation density of these grooves, so that the on-resistance can be more effectively reduced.

また、チャネル長方向に延在する凹部と凸部を交互に有するチャネル幅方向に沿った矩形波形状又は三角波形状等の波形形状を形成し、トランジスタ領域の拡大を伴わずに駆動能力を増大させる構造が挙げられる(例えば特許文献２参照)。
特許３４０５６８１号公報 特開平５−７５１２１号公報 Also, a waveform shape such as a rectangular wave shape or a triangular wave shape is formed along the channel width direction alternately having recesses and protrusions extending in the channel length direction, and the driving capability is increased without enlarging the transistor region. A structure is mentioned (for example, refer patent document 2).
Japanese Patent No. 3405682 JP-A-5-75121

特許文献１の発明における構造においては、製造ばらつきによりウェル拡散層の濃度変動だけではなくウェル拡散層の接合深さが変動することによりトレンチ側面に形成されるチャネル長が変動するため、素子の特性がばらつきやすい構造となっている。また、トレンチ側面に形成されるチャネルにおいては、ウェルの拡散深さによって変動する構造となっており、VRやSWRの内部に取り込む場合にはデバイス設計に制限を与えることになってしまう。   In the structure of the invention of Patent Document 1, the channel length formed on the side surface of the trench varies due to the variation in the junction depth of the well diffusion layer as well as the concentration variation of the well diffusion layer due to manufacturing variations. The structure tends to vary. In addition, the channel formed on the side surface of the trench has a structure that varies depending on the diffusion depth of the well, and when it is taken into the VR or SWR, the device design is restricted.

また、半導体基板表面におけるチャネル端から高濃度ドレイン拡散層までの低濃度ドレイン拡散層までの距離とトレンチ側面のチャネル端から高濃度ドレイン拡散層までの低濃度ドレイン拡散層までの距離が異なり、トレンチ側面のチャネル端から高濃度ドレイン拡散層までの距離の方が長くなるため、抵抗成分が大きくなり、トレンチ底部での電流量は低下する。そのため、トレンチにより単位面積当りのチャネル幅を大きくした効果があまり現れない構造となっている。   In addition, the distance from the channel end on the semiconductor substrate surface to the low concentration drain diffusion layer from the high concentration drain diffusion layer and the distance from the channel end on the side surface of the trench to the low concentration drain diffusion layer are different. Since the distance from the side channel end to the high-concentration drain diffusion layer becomes longer, the resistance component increases, and the amount of current at the bottom of the trench decreases. For this reason, the effect of increasing the channel width per unit area by the trench does not appear so much.

特許文献２の発明においては、矩形波形状の段差を深くすることにより単位面積当りの駆動能力を向上させることができる。しかし、図９に示すように半導体基板１０２に形成されたトレンチが一段である場合、単位面積当りのゲート幅を増やすために、トレンチ幅ｖ、トレンチ間隔ｌを狭くし、かつトレンチ深さｗを深くすることで単位面積当りの駆動能力を向上させることができる。しかし、半導体基板１０２表面とトレンチ底部との段差が大きくなる傾向と成り、MOSトランジスタの閾値電圧を調整する際にチャネル領域にイオン注入法を用いて不純物の導入を行なった場合、段差がきついことによって、半導体基板１０１表面、トレンチ底部およびトレンチ側面に均一にイオン注入が行なわれず、チャネル領域の不純物濃度を均一に形成することが困難になる。これにより、トレンチ幅ｖ、トレンチ間隔ｌ、トレンチ深さｗに制限を課することとなり、単位面積当りの駆動能力をさらに向上させることができない構造となっている。   In the invention of Patent Document 2, the driving capability per unit area can be improved by deepening the step of the rectangular wave shape. However, when the trench formed in the semiconductor substrate 102 is one stage as shown in FIG. 9, in order to increase the gate width per unit area, the trench width v and the trench interval l are narrowed, and the trench depth w is By increasing the depth, the driving ability per unit area can be improved. However, the step between the surface of the semiconductor substrate 102 and the bottom of the trench tends to increase, and when the impurity is introduced into the channel region using the ion implantation method when adjusting the threshold voltage of the MOS transistor, the step is tight. Therefore, the ion implantation is not uniformly performed on the surface of the semiconductor substrate 101, the bottom of the trench, and the side surface of the trench, and it becomes difficult to uniformly form the impurity concentration of the channel region. As a result, restrictions are imposed on the trench width v, the trench interval l, and the trench depth w, and the driving capability per unit area cannot be further improved.

上記の課題を解決するために、本発明は以下の手段を用いた。
（１）MOSトランジスタのチャネル領域にゲート長方向に対し水平に配置するトレンチの構造をゲート幅方向に階段状に形成することを特徴とする半導体装置とした。
（２）前記階段状の構造は半導体基板表面から下に凸であることを特徴とする半導体装置とした。
（３）前記階段状の構造は半導体基板表面から上に凸であることを特徴とする半導体装置とした。
（４）前記階段状のチャネル領域は２段以上であることを特徴とする半導体装置とした。
（５）前記MOSトランジスタのソース拡散層及びドレイン拡散層の領域も階段状に形成されていることを特徴とする半導体装置とした。 In order to solve the above problems, the present invention uses the following means.
(1) A semiconductor device is characterized in that a trench structure disposed horizontally in the gate length direction in the channel region of the MOS transistor is formed stepwise in the gate width direction.
(2) The semiconductor device is characterized in that the stepped structure is convex downward from the surface of the semiconductor substrate.
(3) The semiconductor device is characterized in that the stepped structure is convex upward from the surface of the semiconductor substrate.
(4) The semiconductor device is characterized in that the stepped channel region has two or more steps.
(5) The semiconductor device is characterized in that the regions of the source diffusion layer and the drain diffusion layer of the MOS transistor are also formed stepwise.

MOSトランジスタにおいて、ゲート長方向に対し水平に配置するトレンチもしくはフィンの構造をゲート幅方向に階段状に形成することで半導体基板表面とトレンチ底部もしくはフィン頭頂部の段差が緩和されるため、単位面積当りの駆動能力を上げるために深いトレンチもしくは高いフィンを有している場合においてもイオン注入法を用いてチャネル領域、ソース拡散層およびドレイン拡散層の不純物濃度を均一に形成することができる構造と成る。これらにより、チャネルが形成される面による特性の変動が現れない安定した特性が得られ、単位面積当りのオン抵抗が低減された高駆動能力横型MOSトランジスタを提供することが可能となる。   In a MOS transistor, the step between the surface of the semiconductor substrate and the bottom of the trench or the top of the fin is reduced by forming a trench or fin structure arranged horizontally in the gate length direction in a stepwise manner in the gate width direction. A structure in which the impurity concentration of the channel region, the source diffusion layer and the drain diffusion layer can be uniformly formed by using the ion implantation method even when a deep trench or a high fin is provided in order to increase the driving capability Become. As a result, it is possible to provide a stable driving characteristic that does not cause a change in characteristics due to the surface on which the channel is formed, and a high driving capability lateral MOS transistor with reduced on-resistance per unit area.

以下、本発明による最良の形態について図面を用いて詳細に説明を行なう。   Hereinafter, the best mode according to the present invention will be described in detail with reference to the drawings.

図１から図４に本発明の第一の実施例である半導体装置を示す。図１は、本発明の第一の実施例である横型トレンチMOSトランジスタの構造を示しており、図２は図１のA-A'一点鎖線およびB-B'一点鎖線を含む平面による断面を示した図となる。   1 to 4 show a semiconductor device according to a first embodiment of the present invention. FIG. 1 shows the structure of a lateral trench MOS transistor according to a first embodiment of the present invention, and FIG. 2 shows a cross section taken along a plane including AA ′ and BB ′ dashed lines in FIG. It becomes the figure shown.

図１に示すように、P型半導体基板１０１に高濃度不純物層となるN型ドレイン拡散層２０１およびN型ソース拡散層２０２が形成されており、P型半導体基板１０１上にゲート絶縁膜３０１が形成されており、さらにゲート絶縁膜３０１上にゲート電極４０１が形成されている。即ち、P型半導体基板１０１、N型ドレイン拡散層２０１、N型ソース拡散層２０２、ゲート電極４０１がそれぞれMOSトランジスタにおけるサブストレート、ドレイン、ソース、ゲートを担い、MOSトランジスタを形成している。   As shown in FIG. 1, an N-type drain diffusion layer 201 and an N-type source diffusion layer 202 that are high-concentration impurity layers are formed on a P-type semiconductor substrate 101, and a gate insulating film 301 is formed on the P-type semiconductor substrate 101. In addition, a gate electrode 401 is formed on the gate insulating film 301. That is, the P-type semiconductor substrate 101, the N-type drain diffusion layer 201, the N-type source diffusion layer 202, and the gate electrode 401 respectively carry the substrate, drain, source, and gate in the MOS transistor, thereby forming the MOS transistor.

N型ドレイン拡散層２０１およびN型ソース拡散層２０２は、P型半導体基板１０１の表面から深い方向に溝が形成されるような下に凸となるトレンチが形成されており、そのトレンチはA-A'一点鎖線のAからA'方向に対して階段状に深くなり、次いで、階段状に浅くなるように形成されている。   In the N-type drain diffusion layer 201 and the N-type source diffusion layer 202, a trench that protrudes downward is formed so that a groove is formed in a deep direction from the surface of the P-type semiconductor substrate 101. A ′ is formed so as to deepen stepwise from the A to A ′ direction of the alternate long and short dash line, and then shallowen stepwise.

また、図２に示すように、ゲート絶縁膜３０１下のP型半導体基板１０１についてもN型ドレイン拡散層２０１及びN型ソース拡散層２０２と同様にP型半導体基板１０１の基板表面から深い方向に溝が形成されるような半導体基板表面から下に凸となるトレンチが形成されており、そのトレンチはA-A'一点鎖線のAからA'方向に対して階段状に深くなり、次いで、階段状に浅くなるように形成されている。それぞれの階段状に形成されているトレンチは、N型ドレイン拡散層２０１からゲート絶縁膜３０１下のP型半導体基板１０１、N型ソース拡散層２０２まで、ゲート長方向に対し水平に配置する連続した帯状のトレンチとなっている。   Further, as shown in FIG. 2, the P-type semiconductor substrate 101 under the gate insulating film 301 also extends deeper from the substrate surface of the P-type semiconductor substrate 101 in the same manner as the N-type drain diffusion layer 201 and the N-type source diffusion layer 202. A trench that protrudes downward from the surface of the semiconductor substrate in which a groove is formed is formed, and the trench becomes deeper in a staircase shape from the A to A ′ direction of the AA ′ dashed line, and then the staircase It is formed so as to be shallow. The respective trenches formed in a stepped shape are continuous from the N-type drain diffusion layer 201 to the P-type semiconductor substrate 101 and the N-type source diffusion layer 202 below the gate insulating film 301 and are arranged horizontally with respect to the gate length direction. It is a strip-shaped trench.

ゲート絶縁膜３０１は、直下のP型半導体基板１０１の形状に合わせて、膜厚が均一に成るように形成され、ゲート電極４０１はゲート絶縁膜３０１を覆うようにゲート絶縁膜３０１上に形成されている。   The gate insulating film 301 is formed to have a uniform film thickness in accordance with the shape of the P-type semiconductor substrate 101 immediately below, and the gate electrode 401 is formed on the gate insulating film 301 so as to cover the gate insulating film 301. ing.

上記の横型MOSトランジスタの動作を説明する。N型ドレイン拡散層２０１に正の電圧、N型ソース拡散層２０２にN型ドレイン拡散層よりも低い電圧、つまり負の電圧が印加された状態において、ゲート電極４０１に正の電圧を印加すると、ゲート酸化膜３０１直下のP型半導体基板１０１表面がN型に反転し、電子がN型ソース拡散層２０２からN型に反転したP型半導体基板１０１表面を通り、N型ドレイン拡散層２０１に流れる。   The operation of the horizontal MOS transistor will be described. When a positive voltage is applied to the gate electrode 401 in a state where a positive voltage is applied to the N-type drain diffusion layer 201 and a lower voltage than the N-type drain diffusion layer, that is, a negative voltage is applied to the N-type source diffusion layer 202, The surface of the P-type semiconductor substrate 101 immediately below the gate oxide film 301 is inverted to N-type, and electrons flow to the N-type drain diffusion layer 201 through the surface of the P-type semiconductor substrate 101 inverted from the N-type source diffusion layer 202 to N-type. .

図３は、本発明の第一の実施例である横型MOSトランジスタを示す平面図であり、図４は図３におけるC-C'一点鎖線での断面図を示している。図３は、ゲート電極４０１を介してN型ドレイン拡散層２０１とN型ソース拡散層２０２が形成されており、ゲート長方向に対し水平に配置する帯状のトレンチを有しており、図４に示すようにゲート絶縁膜３０１直下のP型半導体基板１０１にも帯状のトレンチが形成され、N型ソース拡散層２０２からN型ドレイン拡散層まで連続した帯状のトレンチとなっている。また、このトレンチはC-C'一点鎖線のCからC'方向に対して階段状に深くなり、次いで、階段状に浅くなるように形成されている。   FIG. 3 is a plan view showing a lateral MOS transistor according to the first embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along the chain line CC ′ in FIG. In FIG. 3, an N-type drain diffusion layer 201 and an N-type source diffusion layer 202 are formed via a gate electrode 401, and has a strip-like trench disposed horizontally with respect to the gate length direction. As shown, a strip-like trench is also formed in the P-type semiconductor substrate 101 immediately below the gate insulating film 301, and is a continuous trench from the N-type source diffusion layer 202 to the N-type drain diffusion layer. Further, this trench is formed so as to be stepped deep from the C to C ′ direction of the C—C ′ dot-dash line and then shallowed stepwise.

図３、図４に示すように連続的に階段状のトレンチを配置することでMOSトランジスタのゲート幅が増加するため、電流量を増加させることが可能であり、単位面積当りの電流量はトレンチ間隔ｌ、第一トレンチ幅ｍ、第二トレンチ幅ｎを狭く、第一トレンチ深さｏ、第二トレンチ深さｐを深く形成することにより増加させることが可能である。上記の例では、階段状のトレンチを２段としているが、トレンチの段差が大きい場合は、階段状のトレンチの段数をさらに増やすことで段差を緩和することが可能となる。   As shown in FIGS. 3 and 4, the gate width of the MOS transistor is increased by arranging stepped trenches continuously, so that the amount of current can be increased, and the amount of current per unit area is the trench. The distance l, the first trench width m, and the second trench width n can be narrowed and the first trench depth o and the second trench depth p can be increased. In the above example, the stepped trench has two steps. However, if the step difference of the trench is large, the step can be reduced by further increasing the number of steps of the stepped trench.

上記は、P型半導体基板をサブストレートとし、N型拡散層をソース及びドレインとしたN型チャネルMOSトランジスタを元に説明を行なってきたが、P型チャネルMOSトランジスタにも適用することが可能である。サブストレートを半導体基板内に形成されたウェルを用いたMOSトランジスタ構造においても適用可能である。また、ソース拡散層およびドレイン拡散層に低濃度のオフセット層を有したMOSトランジスタであっても、本構造は適用できる。   The above has been described based on an N-type channel MOS transistor using a P-type semiconductor substrate as a substrate and an N-type diffusion layer as a source and drain, but can also be applied to a P-type channel MOS transistor. is there. The present invention can also be applied to a MOS transistor structure using a well in which a substrate is formed in a semiconductor substrate. This structure can be applied even to a MOS transistor having a low-concentration offset layer in the source diffusion layer and the drain diffusion layer.

本発明における第一の実施例におけるMOSトランジスタにおいては、ゲート長方向に対し水平に配置する帯状のトレンチをゲート幅方向に階段状に形成することによって、半導体基板表面とトレンチ底部の段差が緩和されるため、単位面積当りの駆動能力を上げるために深いトレンチを有している場合においてもイオン注入法を用いてチャネル領域、ソース拡散層およびドレイン拡散層の不純物濃度を均一に形成することができる構造となっている。   In the MOS transistor according to the first embodiment of the present invention, the step between the semiconductor substrate surface and the bottom of the trench is alleviated by forming a strip-like trench arranged horizontally in the gate length direction in a stepwise manner in the gate width direction. Therefore, even when a deep trench is provided in order to increase the driving capability per unit area, the impurity concentration of the channel region, the source diffusion layer, and the drain diffusion layer can be uniformly formed by using the ion implantation method. It has a structure.

これらにより、VRやSWRの内部に高駆動能力を有したMOSトランジスタを取り込む場合において、トレンチにより単位面積当りのゲート幅を増加させるMOSトランジスタを用いても、チャネルが形成される面による特性の変動が現れない安定した特性が得られ、単位面積当りのオン抵抗が低減された高駆動能力横型MOSトランジスタを提供することが可能となる。   As a result, when incorporating a MOS transistor with high drive capability inside a VR or SWR, even if a MOS transistor that increases the gate width per unit area by a trench is used, fluctuations in characteristics due to the surface on which the channel is formed Thus, it is possible to provide a lateral MOS transistor having a high driving capability in which a stable characteristic that does not appear is obtained and the on-resistance per unit area is reduced.

次に、図５から図８に本発明の第二の実施例である半導体装置を示す。図５は、本発明の第二の実施例である横型MOSトランジスタの構造を示している図であり、図６は図５のD-D'一点鎖線およびE-E'一点鎖線を含む平面における断面を示した図となる。   Next, FIGS. 5 to 8 show a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a diagram showing the structure of a lateral MOS transistor according to the second embodiment of the present invention, and FIG. 6 is a plan view including a DD ′ dashed line and an EE ′ dashed line in FIG. It is the figure which showed the cross section.

図５に示すように、P型半導体基板１０１に高濃度不純物層となるN型ドレイン拡散層２０１およびN型ソース拡散層２０２が形成されており、P型半導体基板１０１上にゲート絶縁膜３０１が形成されており、さらにゲート絶縁膜３０１上にゲート電極４０１が形成されている。MOSトランジスタにおけるサブストレート、ドレイン、ソース、ゲートをそれぞれP型半導体基板１０１、N型ドレイン拡散層２０１、N型ソース拡散層２０２、ゲート電極４０１が担い、MOSトランジスタを形成した構造となっている。   As shown in FIG. 5, an N-type drain diffusion layer 201 and an N-type source diffusion layer 202 that are high-concentration impurity layers are formed on a P-type semiconductor substrate 101, and a gate insulating film 301 is formed on the P-type semiconductor substrate 101. In addition, a gate electrode 401 is formed on the gate insulating film 301. The substrate, drain, source, and gate in the MOS transistor are respectively held by the P-type semiconductor substrate 101, the N-type drain diffusion layer 201, the N-type source diffusion layer 202, and the gate electrode 401, so that the MOS transistor is formed.

N型ドレイン拡散層２０１およびN型ソース拡散層２０２は、P型半導体基板１０１の表面から高い方向に山が形成されるような上に凸となるフィンが形成されており、そのフィンはA-A'一点鎖線のAからA'方向に対して階段状に高く、階段状に低くなるように形成されている。   The N-type drain diffusion layer 201 and the N-type source diffusion layer 202 are formed with fins that protrude upward such that peaks are formed in a high direction from the surface of the P-type semiconductor substrate 101. A ′ is formed so as to be higher in a staircase shape and lower in a staircase shape from the A to A ′ direction of the alternate long and short dash line.

また、図６に示すように、ゲート絶縁膜３０１下のP型半導体基板１０１についてもN型ドレイン拡散層２０１及びN型ソース拡散層２０２と同様にP型半導体基板１０１の基板表面から高い方向に山が形成されるような半導体基板表面から上に凸となるフィンが形成されており、そのフィンはA-A'一点鎖線のAからA'方向に対して階段状に高くなり、次いで、階段状に低くなるように形成されている。それぞれの階段状に形成されているフィンは、N型ドレイン拡散層２０１からゲート絶縁膜３０１下のP型半導体基板１０１、N型ソース拡散層２０２まで、ゲート長方向に対し水平に配置する連続した帯状のフィンとなっている。   Further, as shown in FIG. 6, the P-type semiconductor substrate 101 below the gate insulating film 301 is also arranged in a higher direction from the substrate surface of the P-type semiconductor substrate 101 in the same manner as the N-type drain diffusion layer 201 and the N-type source diffusion layer 202. Fins that protrude upward from the surface of the semiconductor substrate are formed such that peaks are formed, and the fins are raised stepwise from the A-A ′ direction of the AA ′ dashed line, and then the stairs It is formed so as to be lower. Each of the fins formed in a staircase pattern is continuously arranged from the N-type drain diffusion layer 201 to the P-type semiconductor substrate 101 and the N-type source diffusion layer 202 under the gate insulating film 301 in a horizontal direction with respect to the gate length direction. It is a strip-shaped fin.

ゲート絶縁膜３０１は、直下のP型半導体基板１０１の形状に合わせて、膜厚が均一に成るように形成され、ゲート電極４０１はゲート絶縁膜３０１を覆うようにゲート絶縁膜３０１上に形成されている。   The gate insulating film 301 is formed to have a uniform film thickness in accordance with the shape of the P-type semiconductor substrate 101 immediately below, and the gate electrode 401 is formed on the gate insulating film 301 so as to cover the gate insulating film 301. ing.

上記の横型MOSトランジスタの動作を説明する。N型ドレイン拡散層２０１に正の電圧、N型ソース拡散層２０２にN型ドレイン拡散層よりも低い電圧、つまり負の電圧が印加された状態において、ゲート電極４０１に正の電圧を印加すると、ゲート酸化膜３０１直下のP型半導体基板１０１表面がN型に反転し、電子がN型ソース拡散層２０２からN型に反転したP型半導体基板１０１表面を通り、N型ドレイン拡散層２０１に流れる。   The operation of the horizontal MOS transistor will be described. When a positive voltage is applied to the gate electrode 401 in a state where a positive voltage is applied to the N-type drain diffusion layer 201 and a lower voltage than the N-type drain diffusion layer, that is, a negative voltage is applied to the N-type source diffusion layer 202, The surface of the P-type semiconductor substrate 101 immediately below the gate oxide film 301 is inverted to N-type, and electrons flow to the N-type drain diffusion layer 201 through the surface of the P-type semiconductor substrate 101 inverted from the N-type source diffusion layer 202 to N-type. .

図７は、本発明の第一の実施例である横型MOSトランジスタを示す平面図であり、図８は図７におけるF-F'一点鎖線での断面図を示している。図７は、ゲート電極４０１を介してN型ドレイン拡散層２０１とN型ソース拡散層２０２が形成されており、ゲート長方向に対し水平に配置する帯状のフィンを有しており、図８に示すようにゲート絶縁膜３０１直下のP型半導体基板１０１にも帯状のフィンが形成され、N型ソース拡散層２０２からN型ドレイン拡散層まで連続した帯状のフィンとなっている。また、このフィンはC-C'一点鎖線のCからC'方向に対して階段状に高くなり、次いで、階段状に低くなるように形成されている。   FIG. 7 is a plan view showing a lateral MOS transistor according to the first embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along the dashed line FF ′ in FIG. In FIG. 7, an N-type drain diffusion layer 201 and an N-type source diffusion layer 202 are formed via a gate electrode 401, and have strip-shaped fins arranged horizontally with respect to the gate length direction. As shown in the figure, strip-shaped fins are also formed on the P-type semiconductor substrate 101 immediately below the gate insulating film 301 to form a continuous strip-shaped fin from the N-type source diffusion layer 202 to the N-type drain diffusion layer. The fins are formed so as to be stepped in the C to C ′ direction of the C—C ′ dot-dash line and then lowered stepwise.

図７、図８に示すように連続的に階段状のフィンを配置することでMOSトランジスタのゲート幅が増加するため、電流量を増加させることが可能であり、単位面積当りの電流量は第一フィン幅ｑ、第二フィン幅ｒ、フィン間隔ｓを狭く、第一フィン高さｔ、第二フィン高さｕを高く形成することにより増加させることが可能である。上記の例では、階段状のフィンの段数を２段としているが、フィンの段差が大きい場合は、階段状のフィンの段数をさらに増やすことで段差を緩和することが可能となる。   As shown in FIGS. 7 and 8, the gate width of the MOS transistor is increased by arranging stepped fins continuously, so that the amount of current can be increased, and the amount of current per unit area is the first amount. It is possible to increase the first fin width q, the second fin width r, and the fin interval s by narrowing the first fin height t and the second fin height u. In the above example, the number of steps of the stepped fins is two. However, if the steps of the fins are large, the steps can be reduced by further increasing the number of steps of the stepped fins.

上記は、P型半導体基板をサブストレートとし、N型拡散層をソース及びドレインとしたN型チャネルMOSトランジスタを元に説明を行なってきたが、P型チャネルMOSトランジスタにも適用することが可能である。サブストレートを半導体基板内に形成されたウェルを用いたMOSトランジスタ構造においても適用可能である。また、ソース拡散層およびドレイン拡散層に低濃度のオフセット層を有したMOSトランジスタであっても、本構造は適用できる。   The above has been described based on an N-type channel MOS transistor using a P-type semiconductor substrate as a substrate and an N-type diffusion layer as a source and drain, but can also be applied to a P-type channel MOS transistor. is there. The present invention can also be applied to a MOS transistor structure using a well in which a substrate is formed in a semiconductor substrate. This structure can be applied even to a MOS transistor having a low-concentration offset layer in the source diffusion layer and the drain diffusion layer.

本発明における第二の実施例におけるMOSトランジスタにおいては、ゲート長方向に対し水平に配置する帯状のフィンをゲート幅方向に階段状に形成することによって、半導体基板表面とフィン頭頂部の段差が緩和されるため、単位面積当りの駆動能力を上げるために高いフィンを有している場合においてもイオン注入法を用いてチャネル領域、ソース拡散層およびドレイン拡散層の不純物濃度を均一に形成することができる構造となっている。   In the MOS transistor according to the second embodiment of the present invention, the step between the surface of the semiconductor substrate and the top of the fin is alleviated by forming the strip-like fins arranged horizontally with respect to the gate length direction in a step shape in the gate width direction. Therefore, even when a high fin is provided in order to increase the driving capability per unit area, the impurity concentration of the channel region, the source diffusion layer, and the drain diffusion layer can be uniformly formed using the ion implantation method. It has a structure that can be done.

これらにより、VRやSWRの内部に高駆動能力を有したMOSトランジスタを取り込む場合において、フィンにより単位面積当りのゲート幅を増加させるMOSトランジスタを用いても、チャネルが形成される面による特性の変動が現れない安定した特性が得られ、単位面積当りのオン抵抗が低減された高駆動能力横型MOSトランジスタを提供することが可能となる。   As a result, even when MOS transistors with high drive capability are incorporated inside VR or SWR, even if MOS transistors that increase the gate width per unit area with fins are used, the characteristics fluctuate due to the surface on which the channel is formed. Thus, it is possible to provide a lateral MOS transistor having a high driving capability in which a stable characteristic that does not appear is obtained and the on-resistance per unit area is reduced.

本発明による半導体装置の第一の実施例を示す斜視図The perspective view which shows the 1st Example of the semiconductor device by this invention 図１のA-A'における断面を示す斜視図The perspective view which shows the cross section in AA 'of FIG. 本発明による半導体装置の第一の実施例を示す上面図The top view which shows the 1st Example of the semiconductor device by this invention 図１のA-A'における断面図Sectional view at AA 'in FIG. 本発明による半導体装置の第二の実施例を示す斜視図The perspective view which shows the 2nd Example of the semiconductor device by this invention. 図４のD-D'における断面を示す斜視図The perspective view which shows the cross section in DD 'of FIG. 本発明による半導体装置の第二の実施例を示す上面図The top view which shows the 2nd Example of the semiconductor device by this invention 図４のD-D'における断面図Sectional view along DD 'in FIG. 従来の実施例による半導体装置を示す断面図Sectional drawing which shows the semiconductor device by the conventional Example

符号の説明Explanation of symbols

１０１ P型半導体基板
１０２ 半導体基板
２０１ N型ドレイン拡散層
２０２ N型ソース拡散層
３０１ ゲート絶縁膜
４０１ ゲート電極 101 P-type semiconductor substrate 102 Semiconductor substrate 201 N-type drain diffusion layer 202 N-type source diffusion layer 301 Gate insulating film 401 Gate electrode

Claims (6)

チャネル領域、ソース拡散層及びドレイン拡散層にチャネル方向に沿ってトレンチが配置された配置されたＭＯＳトランジスタからなる半導体装置であって、前記トレンチは深さが均一でなく、前記チャネル方向と垂直に、階段状に漸次深くなる領域と階段状に漸次浅くなる領域とを連続して有している半導体装置。   A semiconductor device comprising a MOS transistor in which a trench is disposed along a channel direction in a channel region, a source diffusion layer, and a drain diffusion layer, wherein the trench is not uniform in depth and is perpendicular to the channel direction A semiconductor device having a region that gradually increases stepwise and a region that gradually decreases stepwise. MOSトランジスタのチャネル領域にゲート長方向に対し水平に配置するトレンチの構造をゲート幅方向に階段状に形成することを特徴とする半導体装置。   A semiconductor device characterized in that a trench structure arranged horizontally in a gate length direction in a channel region of a MOS transistor is formed stepwise in a gate width direction. 前記階段状の構造は半導体基板表面から下に凸であることを特徴とする請求項２記載の半導体装置。   3. The semiconductor device according to claim 2, wherein the stepped structure is convex downward from the surface of the semiconductor substrate. 前記階段状の構造は半導体基板表面から上に凸であることを特徴とする請求項２記載の半導体装置。   3. The semiconductor device according to claim 2, wherein the stepped structure is convex upward from the surface of the semiconductor substrate. 前記階段状のチャネル領域の段数は２段以上であることを特徴とする請求項３もしくは請求項４記載の半導体装置。   5. The semiconductor device according to claim 3, wherein the number of steps of the stepped channel region is two or more. 前記MOSトランジスタのソース拡散層及びドレイン拡散層の領域も階段状に形成されていることを特徴とする請求項２乃至５のいずれか1項に記載の半導体装置。   6. The semiconductor device according to claim 2, wherein regions of the source diffusion layer and the drain diffusion layer of the MOS transistor are also formed stepwise.
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