JP2009049441A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor integrated circuit device that can suppress deterioration in characteristic of a transistor and then variation in threshold and an increase in wiring delay, and is adaptive to microfabrication. <P>SOLUTION: A first insulating film 19 which does not consist principally of nitrogen is formed to have a hollow between a first gate electrode and a second gate electrode, and treated in an oxidizing atmosphere after being formed, and a second insulating film 20 which does not consist principally of nitrogen and has a larger water content than the first insulating film 19 is formed on the first insulating film 19 to fill the hollow between the first gate electrode and second gate electrode. A third insulating film 21 which consists principally of nitrogen and has a larger hydrogen content than the first insulating film 19 is formed on the second insulating film 20, and an interlayer dielectric 22 different from the third insulating film 21 is formed on the third insulating film 21, and etched above contact-electrode formation expected places of first diffusion layers 13 and 15 among the interlayer dielectric 22 to form a contact hole. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device including a nonvolatile semiconductor memory device.

  As a nonvolatile semiconductor memory device having a two-layer gate electrode of a floating gate and a control gate, for example, a NAND type nonvolatile semiconductor memory device is known.

  The NAND type nonvolatile semiconductor memory device has a memory cell array in which a drain side select transistor STD and a source side select transistor STS are arranged at both ends of memory cell transistors MC connected in series. The select transistor STD is electrically connected to the bit line via the bit line contact electrode, and the select transistor STS is connected to the source line via the source line contact electrode.

  The bit line contact electrode and the source line contact electrode are formed by forming a contact hole in an interlayer insulating film and filling the contact hole with a conductive material. However, in the photolithography process when forming the contact hole, the contact hole may penetrate to the element isolation region. The reason is, for example, misalignment of the photomask. When the contact hole penetrates to the element isolation region, the bit line contact electrode or the source line contact electrode comes into contact with, for example, the semiconductor substrate. As a result, the leakage current increases and the device becomes defective.

  Therefore, even if misalignment occurs, a barrier insulating film made of a silicon nitride film is used as an etching stopper between the semiconductor substrate and the element isolation region and the interlayer insulating film to prevent the device from becoming defective. It has come to be formed as.

  However, the silicon nitride film serving as the barrier insulating film contains a large amount of hydrogen and easily forms charge traps. A silicon nitride film serving as a barrier insulating film is formed on the surface of the gate electrode, the semiconductor substrate, and the element isolation region after the gate electrode is formed. For this reason, in the silicon nitride film, the charge trapped in the gate electrode sidewall and the portion formed on the diffusion layer formed in the semiconductor substrate between the gate electrodes, for example, due to the influence of electrons, the memory cell transistor Characteristics may deteriorate. In order to improve the deterioration of the characteristics, Patent Document 1 discloses a technique for forming an insulating film made of a silicon oxide film or the like between the gate electrode sidewall and the diffusion layer and the silicon nitride film.

  In addition, as device miniaturization progresses, the influence of parasitic capacitance between floating gates and between control gates increases, and transistor characteristics have been affected. When the parasitic capacitance between the floating gates becomes large, the threshold voltage variation of the memory cell transistor caused by the effect of the change in the amount of charge stored in the adjacent floating gates becomes large, making it difficult to control the threshold voltage. . Further, when the parasitic capacitance between the control gates increases, the wiring delay when driving the control gates increases and the operation speed decreases.

  In order to improve these circumstances, it is effective to reduce the dielectric constant of the insulating film embedded between the floating gates and between the control gates. For this purpose, it is preferable that the floating gates and the control gates are completely filled with a material having a low dielectric constant, for example, a silicon oxide film. This technique is described in Patent Document 2.

  However, when the amount of the buried silicon oxide film increases, depending on the film quality of the silicon oxide film, the amount of charges, for example, electrons, increases, compared to the case where the silicon nitride film is buried.

In order to improve this situation, the space between the gate electrodes may be filled with a silicon oxide film having a small hydrogen content and few charge traps. However, the silicon oxide film needs to be formed at a high temperature for a long time, which increases the manufacturing cost and makes it difficult to miniaturize the element.
JP 2001-148428 A JP 2002-280463 A

  The present invention provides a method for manufacturing a semiconductor integrated circuit device that can suppress deterioration in transistor characteristics, fluctuation in threshold value, and increase in wiring delay, and that is suitable for miniaturization.

  According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, wherein a first gate electrode and a second gate electrode are formed on a semiconductor substrate, and the semiconductor is formed using the first gate electrode and the second gate electrode as a mask. Impurities are introduced into the substrate, a first diffusion layer and a second diffusion layer are formed in the semiconductor substrate, the first diffusion layer, the second diffusion layer, the first gate electrode, and the second gate electrode A first insulating film containing no nitrogen as a main component is formed on the first gate electrode and the second gate electrode so as to have a recess, and after forming the first insulating film, the first insulating film is formed in an oxidizing atmosphere. And a second insulating film that does not contain nitrogen as a main component and has a higher hydrogen content than the first insulating film is disposed between the first gate electrode and the second gate electrode. Ni is formed so as to be embedded in the recess, and nitrogen is formed on the second insulating film. A third insulating film having a main component and a hydrogen content higher than that of the first insulating film is formed, and an interlayer insulating film different from the third insulating film is formed on the third insulating film, and the interlayer insulating film is formed. Etching a portion of the film on the first diffusion layer where the contact electrode is to be formed to form a contact hole, and forming a contact electrode electrically connected to the first diffusion layer in the contact hole To do.

  According to the present invention, it is possible to provide a method for manufacturing a semiconductor integrated circuit device that can suppress deterioration in transistor characteristics, fluctuation in threshold value, and increase in wiring delay, and that is also suitable for miniaturization.

  Several embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

(First embodiment)
The first embodiment will be described below with reference to FIGS. 1 to 9, taking a NAND type nonvolatile semiconductor memory device as an example.

  FIG. 1 is a plan view showing a plane pattern example of a NAND type nonvolatile semiconductor memory device according to the first embodiment of the present invention.

  As shown in FIG. 1, each NAND cell unit includes four memory cells MC connected in series on the element region 4 divided by the element isolation region 3, and the drain side select transistor STD and the source side select transistor STS. It is a connected configuration. The memory cells MC to MC arranged in the horizontal word line direction in the figure are connected by a common control gate line (word line) 9, and the drain side selection transistors STD to STD and the source side selection transistors STS to STS are connected to each other. Are connected by a common drain-side selection gate line 12 and a source-side selection gate line 14, respectively. The drain side select transistor STD is connected to the bit line connection portion 23 of the first wiring layer via the bit line contact electrode 16 and further connected to the bit line 25 via the inter-wiring contact electrode 24. A source line 26 of a first wiring layer is connected to the source side select transistor STS via a source line contact electrode 17.

  Four memory cell transistors MC, a drain side select transistor STD, and a source side select transistor STS constitute one memory cell array, and one memory cell array is connected to another memory cell array via a bit line contact electrode 16. It is adjacent in the direction and further adjacent to another memory cell array in the bit line direction via the source line contact electrode 17.

  2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG.

  In the cross section shown in FIG. 2, four memory cells MC in one memory cell array include gates on element regions 4 formed in wells 2 provided on a semiconductor substrate (for example, a silicon substrate) 1. A memory cell gate electrode 6 is provided on the insulating film 5.

  Each of the memory cell gate electrodes 6 in this example is a stacked gate, and is formed on a floating gate electrode 7 serving as a charge storage layer, an intergate insulating film 8 formed on the floating gate electrode 7, and an intergate insulating film 8. The control gate electrode 9 and the gate mask material 10 formed on the control gate electrode 9 are provided. The control gate electrode 9 is shared with other memory cells MC to form a word line.

  The source and drain of each memory cell MC are connected in series with each other through a diffusion layer 11 provided in the element region 4.

  Further, a drain side select gate electrode (drain side select gate line) 12 is formed on the gate insulating film 5 at the right end of the four memory cells MC. A bit line contact diffusion layer 13 is formed in the element region 4 on the side opposite to the selection transistor STD of the drain side selection gate electrode 12.

  A source-side selection gate electrode (source-side selection gate line) 14 is formed on the gate insulating film 5 at the left end of the four memory cells MC. A source line contact diffusion layer 15 is formed in the element region 4 on the side opposite to the selection transistor STS of the source side selection gate electrode 14.

  The memory cell transistor MC is constituted by the memory cell gate electrode 6 and the diffusion layer 11 provided in the element region 4 at both ends thereof.

  Further, the drain side select gate electrode 12, the diffusion layer 11 provided in the element region 4 on the memory cell side, and the bit line contact diffusion layer 13 constitute a drain side select transistor STD.

  Further, the source side select gate electrode 14, the diffusion layer 11 provided in the element region 4 on the memory cell side, and the source line contact diffusion layer 15 constitute a source side select transistor STS.

  In this way, the memory cell transistors MC are connected in series without contact with each other. A drain side select transistor STD and a source side select transistor STS are connected to both ends of the memory cell transistors MC arranged in series via the diffusion layer 11.

  A bit line contact electrode 16 is connected to the bit line contact diffusion layer 13, and a source line contact electrode 17 is connected to the source line contact diffusion layer 15.

  Here, the surface of each gate electrode 6, 12, 14 is covered with a post-oxide film 18. A first insulating film 19 is provided on the post oxide film 18 and the gate insulating film 5. The first insulating film 19 does not contain nitrogen as a main component and is formed in a concave shape between the memory cell gate electrodes 6. The first insulating film 19 has a low hydrogen content and a small number of traps for charges, and a material having a lower dielectric constant than a silicon nitride film or the like is suitable. An example of the first insulating film 19 is a silicon oxide film.

  Further, a second insulating film 20 that does not contain nitrogen as a main component is provided so as to fill the inside of the recess formed by the first insulating film 19. As the second insulating film 20, a film having a smaller dielectric constant than that of a silicon nitride film or the like is suitable. An example of the second insulating film 20 is a silicon oxide film.

  Here, “embedding” does not mean that it is completely filled, but even if it contains voids such as voids and nests, its action and effect will not change, so that it also includes cavities. To do.

  Further, the first insulating film 19 has a lower hydrogen content than the second insulating film 20 and has fewer traps for charges.

  The distance between the gate electrodes is small between the memory cell gate electrodes 6 and large between the drain side selection gate electrodes 12 with the bit line contact electrode 16 interposed therebetween and between the source side selection gate electrodes 14 with the source line contact electrode 17 interposed therebetween. ing.

  A third insulating film 21 is provided on each gate electrode 6, 12, 14 and on the first insulating film 19 and the second insulating film 20 between the gate electrodes 6, 12, 14. An example of the third insulating film 21 is a silicon nitride film. The third insulating film 21 has a higher hydrogen content and more charge traps than the first insulating film 19.

  An interlayer insulating film 22 is provided on the third insulating film 21. An example of the interlayer insulating film 22 is a silicon oxide film containing boron. An example of a silicon oxide film containing boron is a BPSG film.

  A bit line contact electrode 16 and a source line contact electrode 17 are provided through the interlayer insulating film 22, the third insulating film 21, and the gate insulating film 5. The bit line contact diffusion layer 13 and the source line contact diffusion are respectively provided. Connected to layer 15.

  On the bit line contact electrode 16, a bit line connection portion 23 is provided by a first layer wiring, and a bit line 25 by a second wiring layer is further provided via an inter-wiring contact electrode 24.

  On the source line contact electrode 17, a source line 26 of a first layer wiring is provided.

  The source line 26, the bit line connecting portion 23, and the inter-wiring contact electrode 24 are covered with an inter-wiring insulating film 27, and a bit line 25 is formed thereon.

  The NAND cell according to the first embodiment is formed by four memory cell transistors MC sandwiched between select transistors STD and STS. However, the number of memory cell transistors MC is not limited to four. For example, it can be formed in an arbitrary number such as 16 or 32. Of course, the number of memory cell transistors may be less than four.

  Here, the well is P-type and the source / drain diffusion layer is N-type, but the well may be N-type and the source / drain diffusion layer may be P-type.

  In the first embodiment, the space between the floating gate electrodes 7 and the space between the control gate electrodes 9 of the adjacent memory cell gate electrodes 6 are filled with the first insulating film 19 and the second insulating film 20, and the third insulating film 21 has a structure which does not enter. Further, the first insulating film 19 and the second insulating film 20 on the side surface of the drain side select gate electrode 12 opposite to the memory cell and the side surface of the source side select gate electrode 14 opposite to the memory cell are , Formed as a side wall. This side wall can be used as a mask for ion implantation for forming a so-called LDD (lightly doped diffusion).

  Next, in the cross section shown in FIG. 3, an element isolation region 3 is provided in the well 2 on the semiconductor substrate 1, and an element region 4 separated by the element isolation region 3 is formed. A bit line contact electrode 16 is connected to the entire surface of the element region 4. A third insulating film 21 is formed on the element isolation region 3. An interlayer insulating film 22 is formed on the third insulating film 21. A bit line contact electrode 16 is formed through the interlayer insulating film 22 and the third insulating film 21. The bit line contact electrode 16 is connected to the bit line connection portion 23 and further connected to the bit line 25 via the inter-wiring contact electrode 24. The bit line connection portion 23 and the inter-wiring contact electrode 24 are covered with an inter-wiring insulating film 27.

  Here, the upper surface of the element isolation region 3 is formed at the same position as the upper surface of the element region 4, but may be formed at a position higher than the upper surface of the element region 4.

  Although STI (shallow trench isolation) is used as an element isolation method, another element isolation method such as LOCOS (local oxidation of silicon) may be used.

  According to the nonvolatile semiconductor memory device according to the first embodiment, the insulating film embedded between the memory cell gate electrodes is divided into two layers of the first insulating film 19 and the second insulating film 20, and etching is performed at the time of opening the contact hole. In this structure, a third insulating film 21 serving as a stopper is provided on the second insulating film 20. Further, the first insulating film 19 having a lower hydrogen content and less charge trapping than the second insulating film 20 and the third insulating film 21 is provided below the second insulating film 20, and the second insulating film 20, The third insulating film 21 does not exist in the vicinity of the gate insulating film 5 of the memory cell transistor MC, for example, does not contact directly. Thereby, the hydrogen contained in the second insulating film 20 and the third insulating film 21 and the charges trapped in the second insulating film 20 and the third insulating film 21 are transferred to the memory cell transistor MC. The influence on electrical characteristics can be reduced.

  Further, the memory cell gate electrodes 6 are filled with the first insulating film 19 and the second insulating film 20 having a dielectric constant smaller than that of the third insulating film 21. Thereby, the deterioration of the wiring delay in the control gate electrode 6 of the memory cell transistor MC can be reduced.

  Further, the third insulating film 21 is made of a material that can have an etching selectivity with respect to both the element isolation region 3 and the interlayer insulating film 22. Thereby, even if the width of the element region 4 is reduced, it is possible to prevent the contact holes 16 from penetrating into the element isolation region 3 and the contact electrodes 16 and 17 from contacting the well 2.

  That is, the nonvolatile semiconductor memory device according to the first embodiment improves the etching process margin for opening the contact hole, changes the threshold voltage of the transistor, lowers the breakdown voltage in the gate insulating film, and reduces the gate electrode. It is possible to prevent deterioration of electrical characteristics such as wiring delay. Therefore, according to the first embodiment, it is possible to provide a high-reliability, high-speed operation, high-yield nonvolatile semiconductor memory device, and a manufacturing method thereof.

  Hereinafter, an example of a method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIGS. 2 and 4 to 9.

  First, as shown in FIG. 4, an element region 4 separated by a well 2 and an element isolation region 3 (not shown) is formed in a semiconductor substrate 1 such as a silicon substrate. An example of the material of the element isolation region 3 is silicon oxide. Next, the gate insulating film 5 is formed on the element region 4. Next, the floating gate electrode 7, the intergate insulating film 8, the control gate electrode 9, and the gate mask material 10 are sequentially formed on the element region 4. At this time, as indicated by reference numeral 41, the inter-gate insulating film 8 is removed from a part of the region that becomes the selection gate electrode so that the floating gate electrode 7 and the control gate electrode 9 are connected. .

  The gate insulating film 5 and the floating gate electrode 7 may be formed before the element isolation region 3 is formed, and the element isolation region 3 may be formed in a self-aligned manner with respect to the floating gate electrode 7. Further, the gate insulating film 5, the floating gate electrode 7, the inter-gate insulating film 8, and the control gate electrode 9 are formed before the element isolation region 3 is formed, and the element isolation region 3 is formed as the floating gate electrode 7 and the control gate electrode. 9 may be formed in a self-aligned manner.

  Next, as shown in FIG. 5, the gate mask material 10 is etched into a gate electrode formation pattern using a photolithography method. Next, the control gate electrode 9, the intergate insulating film 8, and the floating gate electrode 7 are etched in a self-aligned manner with respect to the gate mask material 10, and the memory cell gate electrode 6, the drain side select gate electrode 12, and the source side are etched. A select gate electrode 14 is formed. Next, the memory cell gate electrode 6, the drain side selection gate electrode 12, and the source side selection gate electrode 14 are post-oxidized, and a post oxide film 18 is formed around the gate electrodes 6, 12, and 14. Thereby, the damage of the gate electrodes 6, 12 and 14 during the gate processing is recovered. Next, an impurity having a conductivity type different from that of the well 2 is ion-implanted into the element region 4 using the gate electrodes 6, 12, and 14 and the element isolation region 3 (not shown) as a mask. And 13 are obtained. The ion implantation for obtaining the diffusion layers 11 and 13 may be performed after the post-oxidation or may be performed before. Further, it may be after the formation of the first insulating film 19 performed in a later process.

  Next, as shown in FIG. 6, the first insulating film 19 is formed on the surface of the structure shown in FIG. 5, for example, on the post oxide film 18, the gate insulating film 5, and the element isolation region 3 (not shown). ) To form. At this time, the first insulating film 19 is formed with a film thickness that does not completely fill the space between the memory cell gate electrodes 6.

An example of the material of the first insulating film 19 is silicon oxide, and an example of the thickness thereof is that after the distance L2 between the memory cell gate electrodes 6 is about 70 nm, it exists on the side surface of the memory cell gate electrode 6. The thickness is about 5 nm on the oxide film 18 and about 5 nm on the gate insulating film 5. An example of the formation process is a temperature of 780 ° C. and a film formation rate of 0.1 nm / min in a SiH ₂ Cl ₂ + N ₂ O atmosphere. According to this, a silicon oxide film having a charge trap density of about 10 ¹⁸ cm ⁻³ and a hydrogen content of about 1 mol% can be obtained.

  Thus, since the first insulating film 19 is formed with a film thickness that does not completely fill the space between the memory cell gate electrodes 6, it is thinner than when the space between the memory cell gate electrodes 6 is completely buried. Can be formed. In addition, the first insulating film 19 can be formed by using a high-temperature and long-time process in which the hydrogen content is small and the charge trap amount is small. The silicon oxide film formed by such a process is called an HTO (High Temperature Oxide) film in the field of semiconductors.

Note that after the first insulating film 19 is formed, the first insulating film 19 may be processed in an oxidizing atmosphere. By treating the first insulating film 19 in an oxidizing atmosphere, for example, a small amount of hydrogen contained in the first insulating film 19 can be extracted from the first insulating film 19. For example, oxygen molecules O ₂ and hydrogen molecules H ₂ are combined to be H ₂ O and volatilized. For this reason, hydrogen in the first insulating film 19 can be further reduced. For example, this advantage is an advantage unique to the present case that cannot be obtained by the technique described in Patent Document 2, for example. This is because in Patent Document 2, the thickness of the silicon oxide film is so thick that the oxidant cannot reach the vicinity of the gate electrode or the diffusion layer.

  Next, the second insulating film 20 is formed on the first insulating film 19. The second insulating film 20 has a thickness that completely embeds between the memory cell gate electrodes 6 and does not completely embed between the drain side select gate electrodes 12 and between the source side select gate electrodes 14. Form.

An example of the material of the second insulating film 20 is silicon oxide, and an example of the thickness thereof is post-oxidation on the upper surface of the memory cell gate electrode 6 when the distance L2 between the memory cell gate electrodes 6 is about 70 nm. About 60 nm on film 18. An example of the formation process is a temperature of 700 ° C. and a deposition rate of 3 nm / min in a Si (OC ₂ H ₅ ) ₄ atmosphere. According to this, a silicon oxide film having a hydrogen content of about 5 mol% can be obtained.

Note that the second insulating film 20 of this example, that is, silicon oxide, uses Si (OC ₂ H ₅ ) ₄ , that is, TEOS (Tetrahethoxy Silane) as a source gas. A silicon oxide film formed using TEOS as a source gas is called a TEOS film in the semiconductor field.

  Next, as shown in FIG. 7, the first insulating film 19 and the second insulating film 20 remain between the memory cell gate electrodes 6, and the first insulating film 19 and the second insulating film 20 are The first insulating film 19 and the second insulating film 20 are left as side walls on the side surface of the drain side select gate electrode 12 opposite to the memory cell and on the side surface of the source side select gate electrode 14 opposite to the memory cell. Etch away. For this, anisotropic etching may be used. Further, if necessary, impurities having the same conductivity type as that of the diffusion layers 13 and 15 are then used as masks using the first insulating film 19, the second insulating film 20, and the gate electrodes 6, 12, and 14. Ions are implanted into the diffusion layers 13 and 15. Thereby, each of the select gate transistors STD and STS has a one-side LDD structure. That is, the impurity concentration under the bit line contact electrode 16 and the source line contact electrode 17 is increased to form high impurity concentration layers 13 ′ and 15 ′, and the contact resistance is decreased.

  Next, as shown in FIG. 8, the third insulating film 21 is formed on the surface of the structure shown in FIG. 7, for example, the first insulating film 19, the second insulating film 20, the gate electrodes 6, 12, 14, and the gate insulation. It is formed on the film 5 and the element isolation region 3 (not shown).

As the material of the third insulating film 21, a material that can have an etching selectivity with respect to the element isolation region 3 (not shown) and the interlayer insulating film 22 formed in a later process is selected. One example of such a material is silicon nitride, and an example of its thickness is about 20 nm on the diffusion layer 13 or 15 (high impurity concentration layer 13 ′ or 15 ′). An example of the formation process is a temperature of 780 ° C. and a film formation rate of 3 nm / min in a SiH ₂ Cl ₂ + NH ₃ atmosphere. According to this, a silicon nitride film having a hydrogen content of about 10 mol% can be obtained.

Table 1 summarizes examples of film forming conditions for the first insulating film 19, the second insulating film 20, and the third insulating film 21 in this example.

  The charge trap density can be quantitatively determined from the amount of shift of the flat band voltage of the capacitor.

  In addition, the hydrogen content can be evaluated by using secondary ion mass spectrometry (SIMS), or by Fourier transform infrared spectroscopy (FTIR). It can be obtained by using and evaluating the amount of Si-H bonds.

  Next, an interlayer insulating film 22 is deposited on the third insulating film 21. As the material of the interlayer insulating film 22, a material that can have an etching selectivity with respect to the third insulating film 21 is selected. One example of such a material is silicon oxide. Next, the surface of the interlayer insulating film 22 is planarized using, for example, a CMP method. Thus, the interlayer insulating film 22 is embedded between the drain side select gate electrodes 12 and between the source side select gate electrodes 14.

  Next, as shown in FIG. 9, contact holes are formed in the interlayer insulating film 22. The contact holes reach the diffusion layers 13 and 15 (high impurity concentration layers 13 ′ and 15 ′). In the etching for opening the contact hole, first, the interlayer insulating film 22 is etched using etching conditions in which the interlayer insulating film 22 is easily etched and the third insulating film 21 is difficult to etch. Next, the third insulating film 21 and the gate insulating film 5 are sequentially etched using conditions that make it easy to etch the third insulating film 21 and difficult to etch the element isolation region 3 (not shown). Thereby, the diffusion layers 13 and 15 (high impurity concentration layers 13 ′ and 15 ′) are exposed to the outside.

  Next, as shown in FIG. 2, a metal such as aluminum or tungsten or a low-resistance semiconductor is buried in the contact hole to form a bit line contact electrode 16 and a source line contact electrode 17. Thereafter, a bit line connecting portion 23 and a source line 26 are formed by forming a metal wiring layer on the interlayer insulating film 22. Further, an inter-wiring insulating film 27 is deposited, an inter-wiring contact electrode 24 is formed, and a bit line 25 is formed thereon.

  Thereafter, an upper wiring layer is formed using a generally known technique, and the nonvolatile semiconductor memory device according to the first embodiment is completed.

  The first embodiment has been described based on the structure using the wiring layer for the source line. However, as shown in FIG. 10, the source line contact electrode 17 is not formed and the diffusion layer 15 is formed on the source line. It is also possible to transform into a structure using.

  As described above, the charge trap density of each of the first insulating film 19 and the second insulating film 20 can be obtained from the shift amount of the flat band voltage of the capacitor. However, when the memory cell is too fine and it is difficult to obtain the charge trap density, it can be estimated as follows.

  The density of charge traps is thought to correlate with the hydrogen content in the film, particularly the density of hydrogen. That is, the density of hydrogen in the first insulating film 19 and the second insulating film 20 may be evaluated. As described above, the density of hydrogen can be obtained by evaluating the hydrogen concentration in the film using the SIMS method, or by evaluating the amount of Si—H bonds using the FTIR method. If the hydrogen concentration is high or the amount of Si—H bonds is large, the density of charge traps increases. Conversely, if the hydrogen concentration is low or the amount of Si—H bonds is small, the density of charge traps is low. Using this relationship, the density of charge traps can be estimated.

  Also, for example, when the memory cell structure is too fine and it is difficult to determine whether or not a plurality of layers of insulating films, for example, oxide films, are embedded between the gate electrodes only by looking at the cross-sectional SEM photograph There is. Even in such a case, when the density of hydrogen is evaluated, it can be known that a plurality of layers of insulating films are embedded between the gate electrodes. Some examples of analysis of such insulating films are described below.

  FIG. 28 is a diagram showing a hydrogen profile in a film according to the first analysis example, in which the horizontal axis represents the distance from the post-oxide film surface (Distance from surface of post-oxidation film), and the vertical axis represents the hydrogen per unit volume. The content (Hydrogen content) is shown. That is, the density of hydrogen. The in-film hydrogen profile shown in FIG. 28 is along the AA portion of the cross section shown in FIG.

  As shown in FIG. 28, the hydrogen content is low from the surface of the post-oxide film 18, that is, the vicinity of the gate electrode to a certain distance, and the hydrogen content is increased from the middle. As a result of analyzing the hydrogen content of the oxide film between the gate electrodes, if a change in the hydrogen content as shown in FIG. 28 can be recognized, it is known that a plurality of layers of oxide films are embedded between the gate electrodes. be able to.

  FIG. 29 is a diagram showing a hydrogen profile in a film according to the second analysis example, which is the same as FIG.

  The first analysis example shown in FIG. 28 is an example in which the hydrogen content was observed to change discontinuously, but the second analysis example was observed to have a continuous change in hydrogen content. This is an example. Thus, even when a continuous change in the hydrogen content is observed, it can be estimated that a plurality of layers of oxide films are embedded between the gate electrodes.

  Further, from the second analysis example shown in FIG. 29, if the hydrogen content is low in the vicinity of the gate electrode and the hydrogen content tends to increase as the distance from the gate electrode increases, an insulating film between the gate electrodes, for example, Even when the oxide film is a single layer, it can be seen that the same effect as the present embodiment can be obtained. The same applies to the fourth analysis example described later.

  FIG. 30 is a view showing a hydrogen profile in a film according to the third analysis example, and is the same view as FIG.

The difference between the third analysis example and the first analysis example is whether or not the first insulating film 19 is treated in an oxidizing atmosphere (With / Without O ₂ densify).

  As described above, when the first insulating film 19 is processed in an oxidizing atmosphere, the hydrogen content in the first insulating film 19 can be further reduced. The decrease in the hydrogen content can be seen from the fact that the hydrogen content in the first insulating film 19 tends to decrease as the distance from the surface of the post oxide film 18 increases, as shown in FIG. The hydrogen content in the first insulating film 19 treated in the oxidizing atmosphere is the smallest on the surface, and the hydrogen content increases from the surface toward the inside, but the treatment is not performed in the oxidizing atmosphere indicated by the two-dot chain line. Compared to the case, the hydrogen content is small.

  Also in the third analysis example, since the hydrogen content is increased in the second insulating film 20, it can be known that a plurality of layers of insulating films, for example, oxide films are embedded between the gate electrodes.

  FIG. 31 is a view showing a hydrogen profile in a film according to the fourth analysis example, and is the same view as FIG.

  The difference between the fourth analysis example and the second analysis example is whether or not the first insulating film 19 is treated in an oxidizing atmosphere. Also in the fourth analysis example, as in the second analysis example, it is observed that the hydrogen content continuously changes and increases rapidly in the second insulating film 20, so that a plurality of gaps are formed between the gate electrodes. It can be seen that an insulating film, for example, an oxide film is buried.

  Even when the SIMS method and the FTIR method are used, it is sometimes difficult to measure a minute region such as a memory cell because a certain amount of region is required for analysis. In this case, based on the idea that “the denser the film, the smaller the amount of Si—H bonds”, the amount of Si—H bonds may be estimated using the etching rate. For example, an estimation example of the amount of Si—H bonds is as follows.

  When the first insulating film 19 is a silicon oxide film, the first insulating film 19 has a higher film quality than the second insulating film 20 because it is formed by a process at a high temperature for a long time. One of the indexes representing the quality of the film is the film density. One of the indexes representing the film density is the etching rate. Therefore, the first insulating film 19 and the second insulating film 20 are etched simultaneously and using the same etchant. If the first insulating film 19 is a denser film than the second insulating film 20, a difference is caused in each etching rate. That is, the etching rate of the first insulating film 19 is slow, and conversely, the etching rate of the second insulating film 20 is fast. According to this example, the etching rate of the first insulating film 19 is slower than twice the etching rate of the second insulating film 20. The difference in etching rate is used to examine the density of the film.

  An etching rate test example when the first insulating film 19 and the second insulating film 20 based on this estimation example are each a silicon oxide film is shown below.

  The example shown in FIGS. 32A to 32F is an example in which an etching process is performed at room temperature using a diluted HF solution, and the cross-sectional shapes of the first insulating film 19 and the second insulating film 20 for each predetermined time t, respectively. The change with time of is schematically shown. This test example is an example in which the first insulating film 19 and the second insulating film 20 are isotropically etched using a diluted HF solution.

  As shown in FIGS. 32A to 32F, the second insulating film 20 is etched deeper than the first insulating film 19. This is because there is an etching rate difference between the first insulating film 19 and the second insulating film 20.

  The example shown in FIGS. 33A to 33F assumes anisotropic etching, and schematically shows a change in cross-sectional shape with time for each predetermined time t, similarly to FIGS. 32A to 32F. Similarly, in the case of anisotropic etching, the second insulating film 20 is etched deeper than the first insulating film 19 due to the difference in etching rate between the first insulating film 19 and the second insulating film 20. Is done.

  The cross sections of the first insulating film 19 and the second insulating film 20 shown in FIGS. 32A to 32F and FIGS. 33A to 33F respectively correspond to the cross sections shown in FIG. In addition, it is assumed that the etching rate of the first insulating film 19 is about 1/4 compared with the etching rate of the second insulating film 20, but if the etching rate is different, the etching rate is about 1/2. However, even in the case of about 1/3, the second insulating film 20 is etched deeper than the first insulating film 19 as in the above two test examples.

  Thus, it is possible to selectively remove the second insulating film 20 whose etching rate is about twice or more that of the first insulating film 20, and using this, a plurality of gate electrodes can be used between the gate electrodes. It can be assumed that an insulating film, for example, an oxide film is buried.

(Second Embodiment)
A second embodiment will be described with reference to FIG. The planar pattern of the nonvolatile semiconductor memory device according to the second embodiment is the same as that of the first embodiment. The plan view refers to FIG.

  FIG. 11 is a cross-sectional view taken along line AA in FIG.

  The second embodiment is different from the first embodiment in that the third insulating film 21 is buried up to the height of the control gate electrode 9. Since other parts are the same as those in the first embodiment, description thereof is omitted.

  As shown in FIG. 11, in the second embodiment, the third insulating film 21 is formed in the recess between the memory cell gate electrodes 6 generated by forming the second insulating film 20 thinner than the first embodiment. Embedded. At this time, the lowermost portion of the buried third insulating film 21 is positioned higher than the uppermost portion of the floating gate electrode 7.

  By reducing the thickness of the second insulating film 20 having a larger amount of charge trapping than the first insulating film 19, the second insulating film 20 is trapped on the diffusion layer 11 of the memory cell transistor MC as compared with the first embodiment. The amount of charge can be further suppressed. Therefore, deterioration of the characteristics of the memory cell transistor MC can be further prevented.

(Third embodiment)
A third embodiment will be described with reference to FIG. The planar pattern of the nonvolatile semiconductor memory device according to the third embodiment is the same as that of the first embodiment. The plan view refers to FIG.

  12 is a cross-sectional view taken along the line AA in FIG.

  According to the third embodiment, the first insulating film 19 and the second insulating film 20 are not removed by etching from the bit line contact diffusion layer 13 and the source line contact diffusion layer 15 as in the first embodiment. Different. Since other parts are the same as those in the first embodiment, description thereof is omitted.

  As shown in FIG. 12, in the third embodiment, the first insulating film 19 and the second insulating film 20 are deposited, and then the third insulating film 21 is deposited.

  As in the first and second embodiments, the first insulating film 19 and the second insulating film 20 remain between the memory cell gate electrodes 6 and also remain on the memory cell gate electrode 6. Further, the etching for removing the first insulating film 19 and the second insulating film 20 from the bit line contact diffusion layer 13 and the source line contact diffusion layer 15 is not performed. For this reason, the manufacturing cost can be reduced as compared with the first embodiment.

  In the third embodiment, as in the second embodiment, the third insulating film 21 is embedded between the memory cell gate electrodes 6 so as to be positioned higher than the uppermost portion of the floating gate electrode 7. It may be a different structure.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIG. The planar pattern of the nonvolatile semiconductor memory device according to the fourth embodiment is the same as that of the first embodiment. The plan view refers to FIG.

  FIG. 13 is a cross-sectional view taken along line AA in FIG.

  In the fourth embodiment, the first insulating film 19 and the second insulating film 20 remain between the memory cell gate electrodes 6. Further, the first insulating film 19 and the second insulating film 20 are relative to the side surface of the memory cell gate electrode 6 of the source line memory cell transistor MC that is opposite to the drain side selection gate electrode 12 and to the source line selection gate electrode 14. It remains in a side wall shape on each of the side surfaces. Further, the first insulating film 21 is embedded between the drain side select gate electrode 12 and the memory cell gate electrode 6 and between the source side select gate electrode 14 and the memory cell gate electrode 6. Different from the embodiment. Since other parts are the same as those in the first embodiment, description thereof is omitted.

  As shown in FIG. 13, in the fourth embodiment, the distance between the drain side select gate electrode 12 and the memory cell gate electrode 6 and the distance between the source side select gate electrode 14 and the memory cell gate electrode 6 are shown. The distance is larger than the distance between the memory cell gate electrodes 6, between the drain side select gate electrode 12 and the memory cell gate electrode 6, and between the source side select gate electrode 14 and the memory cell gate electrode 6. The third insulating film 21 is embedded in between.

  The distance between the drain side select gate electrode 12 and the memory cell gate electrode 6 and the distance between the source side select gate electrode 14 and the memory cell gate electrode 6 are larger than the distance between the memory cell gate electrodes 6. Since it is large, the process margin when patterning the gate electrode using the photolithography method can be improved as compared with the first embodiment. Further, the space between the memory cell gate electrodes 6 is buried, and a recess is formed between the drain side selection gate electrode 12 and the memory cell gate electrode 6 and between the source side selection gate electrode 14 and the memory cell gate electrode 6. Thus, by making the second insulating film 20 thinner than in the first embodiment, the amount of charge trapped on the diffusion layer of the memory cell transistor is suppressed more than in the first embodiment, and the characteristics of the memory cell transistor MC are reduced. Decline can be prevented.

  In FIG. 13, the third insulating film 21 includes a gate insulating film between the drain side select gate electrode 12 and the memory cell gate electrode 6 and between the source side select gate electrode 14 and the memory cell gate electrode 6. 5, the depth to which the third insulating film 21 is buried is between the drain side select gate electrode 12 and the memory cell gate electrode 6, and between the source side select gate electrode 14 and the memory cell gate electrode 6. Can be any depth between.

  In the fourth embodiment, as in the second embodiment, the third insulating film 21 is embedded between the memory cell gate electrodes 6 so as to be positioned higher than the uppermost portion of the floating gate electrode 7. It may be structured.

  Further, in the fourth embodiment, similarly to the third embodiment, the first insulating film 19 and the second insulating film 20 may be deposited and then the third insulating film 21 may be deposited.

(Fifth embodiment)
The fifth embodiment relates to an example when the present invention is implemented in a NOR type nonvolatile semiconductor memory device.

  FIG. 14 is a plan view showing a structural example of a NOR type nonvolatile semiconductor memory device according to the fifth embodiment of the present invention, and FIG. 15 is a sectional view taken along line AA in FIG.

  As shown in FIGS. 14 and 15, in the fifth embodiment, the number of memory cell transistors MC connected in series between the bit line contact electrodes 16 is two and does not include a selection transistor. However, this is different from the first embodiment. Since the form in other parts is the same as that of the first embodiment, the description is omitted.

  As shown in FIG. 14, in the fifth embodiment, the first insulating film 19 and the second insulating film 20 are embedded between the side surfaces of the memory cell gate electrode 6 on the side opposite to the bit line contact electrode 16. Yes. The source line is formed by the diffusion layer 15, and the bit line contact electrode 16 is connected to the bit line 25 made of the first wiring layer.

  In the fifth embodiment, the third insulating film 21 is buried between the memory cell gate electrodes 6 so as to be positioned higher than the uppermost portion of the floating gate electrode 7 as in the second embodiment. It may be structured.

  Further, in the fifth embodiment, similarly to the third embodiment, the first insulating film 19 and the second insulating film 20 may be deposited and then the third insulating film 21 may be deposited.

  Thus, the present invention can be applied not only to a NAND type nonvolatile semiconductor memory device but also to a NOR type nonvolatile semiconductor memory device. Of course, the present invention can also be applied to an AND type or DiNOR type nonvolatile semiconductor memory device. That is, any structure can be used as long as a plurality of transistors are connected in series and no contact electrode is provided between the gate electrodes. In particular, it is useful for a nonvolatile semiconductor memory device having a contact electrode with no margin for the element region 3, passing a tunnel current through the gate oxide film 5, and applying a strong electrical stress to the gate oxide film 5. It is.

(Sixth embodiment)
A sixth embodiment will be described with reference to FIG. The planar pattern of the nonvolatile semiconductor memory device according to the sixth embodiment is the same as that of the first embodiment. The plan view refers to FIG.

  16 is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 17 is a cross-sectional view showing the distances L1 and L2 between the gate electrodes.

  The sixth embodiment is different from the first embodiment in that the first insulating film 19 and the second insulating film 20 are embedded in the upper part in the element isolation region 3. Since the form in other parts is the same as that of the first embodiment, the description is omitted.

  As device miniaturization progresses, the process margin for etching the gate electrode decreases, and the gate electrode on the device region 4 is embedded in the device isolation region 3 when, for example, the shape shown in FIG. 2 is processed. In some cases, a part of the upper portion of the insulating film is removed by etching.

  This tendency is, for example, as the difference between the distance L1 (see FIG. 17) between the select gate electrodes 12 or 14 and the distance L2 (see FIG. 17) between the memory cell gate electrodes 6 increases. , Become noticeable. That is, due to the etching speed difference caused by the pattern density difference, the portion of the element isolation region 3 located between the select gate electrodes 12 or 14 is easily etched away. As a result, as shown in FIG. 18, a depression S is generated between the upper surface of the element isolation region 3 and the upper surface of the element region 4. If the contact hole is formed in a state where the depression S is generated and a misalignment is generated, even if the third insulating film 21 is formed, the mechanism shown in FIGS. Will occur.

  First, as shown in FIG. 19, the interlayer insulating film 22 is etched until it reaches the third insulating film 21. Etching of the interlayer insulating film 22 stops at the third insulating film 21. However, overetching is usually performed so that the etching of the interlayer insulating film 22 reaches the third insulating film 21 over the entire area of the semiconductor wafer forming the integrated circuit. For this reason, the etching of the interlayer insulating film 22 proceeds below the upper surface of the element region 4 as indicated by a broken-line circle 50 in FIG.

  Next, as shown in FIG. 20, the third insulating film 21 is etched. At this time, the third insulating film 21 formed on the side surface of the element region 4 is also etched, and the side surface of the element region 4 is exposed to the outside.

  Next, as shown in FIG. 21, the gate insulating film 5 is etched. At this time, when the gate insulating film 5 and the insulating film to be the element isolation region 3 are substantially the same type of film, and the element isolation region 3 is exposed to the outside, the upper portion thereof is also etched slightly. The exposure amount on the side surface of the element region 4 may be increased.

  Next, as shown in FIG. 22, the contact electrode 16 is formed in the contact hole. Since the side surface of the element region 4 is exposed to the outside, the contact electrode 16 contacts not only the diffusion layer 13 but also the element region 4. For this reason, the contact electrode 16 is short-circuited to the element region 4, that is, the bit line is short-circuited to the back gate of the selection transistor, and the leakage current increases. A failure occurs due to an increase in leakage current. Even when the bit line is not short-circuited to the back gate of the selection transistor, if the recess S is formed, junction leakage and a reduction in element isolation breakdown voltage occur.

  However, when the width W of the element isolation trench (see FIG. 16) is equal to or less than the distance L2 between the memory cell gate electrodes 6 (L2 ≧ W) as in the sixth embodiment, the memory cell gate When the space between the electrodes 6 is filled with the first insulating film 19 and the second insulating film 20, the etched portion of the element isolation region 3 adjacent to the contact electrode 16 or 17 is not affected by the depression S. The first insulating film 19 and the second insulating film 20 can be embedded.

  That is, as shown in FIG. 16, in the sixth embodiment, the element isolation region 3 is provided in the well 2 on the semiconductor substrate 1, and the element region 4 separated by the element isolation region 3 is formed. A bit line contact electrode 16 is connected to the entire surface of the element region 4. A first insulating film 19 is embedded in the upper portion of the element isolation region 3, and a second insulating film 20 is embedded in a concave shape formed in the element isolation region 3 in the first insulating film 19. A third insulating film 21 is formed on the first insulating film 19 and the second insulating film 20 in the element isolation region 3. An interlayer insulating film 22 is formed on the third insulating film. A bit line contact electrode 16 is formed through the interlayer insulating film 22 and the third insulating film 21. The bit line contact electrode 16 is connected to the bit line connection portion 23 and further connected to the bit line 25 via the inter-wiring contact 24. The bit line connection portion 23 and the inter-wiring contact 24 are covered with an inter-wiring insulating film 27.

  Here, the upper surfaces of the first insulating film 19 and the second insulating film 20 in the element isolation region 3 are formed at the same position as the upper surface of the element region 4, but are formed at a position higher than the upper surface of the element region 4. May be.

  According to the sixth embodiment, the third insulating film 21 can be formed flat by embedding the depression S generated in the element isolation region 3 with the first insulating film 19 and the second insulating film 20. Therefore, since it can suppress that a level | step difference generate | occur | produces in the 3rd insulating film 21, generation | occurrence | production of the defect by the mechanism shown in FIGS. 19-22 can be suppressed. Therefore, it is possible to suppress a short circuit between the bit line and the back gate of the selection transistor, or a decrease in junction leakage or element isolation withstand voltage. That is, the etching process margin for opening the contact hole can be improved.

  Further, since the space between the memory cell gate electrodes 6 is filled with the first insulating film 19 and the second insulating film 20, the threshold voltage fluctuation of the transistor, the breakdown voltage of the gate insulating film is lowered, and the wiring of the gate electrode Deterioration of electrical characteristics such as delay can be prevented.

  Next, an example of a contact electrode forming process of the semiconductor integrated circuit device according to the sixth embodiment will be described.

  23 to 27 are cross-sectional views illustrating an example of a contact electrode forming process of the semiconductor integrated circuit device according to the sixth embodiment.

  As shown in FIG. 23, an interlayer insulating film 22 is formed on the third insulating film 19. In the sixth embodiment, since the recess S is filled with the first insulating film 19 and the second insulating film 20, the surface of the third insulating film 19 is flat.

  Next, as shown in FIG. 24, the interlayer insulating film 22 is etched until it reaches the third insulating film 21. Etching of the interlayer insulating film 22 stops at the third insulating film 21. However, since the surface of the third insulating film 21 is flat, exposure of a film other than the third insulating film 21 to the bottom of the contact hole is suppressed. Therefore, the overetching shape as shown in FIG. 19 does not occur.

  Next, as shown in FIG. 25, the third insulating film 21 is etched. At this time, the surface of the gate insulating film 5 and the surface of the second insulating film 20 are exposed at the bottom of the contact hole. In addition, since the first insulating film 19 is formed along the side surface of the element region 4 and the surface of the element isolation region 3, the surface of the first insulating film 19 is also formed on the gate insulating film 5 and the second insulating film 20. Exposed from between.

  Next, as shown in FIG. 26, the gate insulating film 5 is etched. At this time, the gate insulating film 5 is substantially the same type of film as the first insulating film 19 and the second insulating film 20, and the upper portions of the first insulating film 19 and the second insulating film are also slightly etched. In some cases, the surface of the element region 4 is exposed. However, in the sixth embodiment, since the etching into the depression S does not proceed, the exposure amount of the side surface of the element region 4 is much smaller than the example shown in FIG.

  Furthermore, as described in the first embodiment, the etching rate of the first insulating film 19 is smaller than the etching rate of the second insulating film 20, that is, the first insulating film 19 is more than the second insulating film 20. If it is difficult to etch, the exposure of the side surface of the element region 4 can be suppressed by the first insulating film 19 as shown in FIG. Further, it can be considered that the film quality is good if the etching rate of the first insulating film 19 is small. That is, the insulating property of the first insulating film 19 is good.

  Therefore, even if the etching of the second insulating film 19 progresses quickly, the contact electrode 16 and the element when the contact electrode 16 is formed in the contact hole by the first insulating film 19 as shown in FIG. Defects such as a short circuit with the region 4 can be better suppressed.

  In the sixth embodiment, the description has been made focusing on the portion around the bit line contact electrode 16, but the same applies to the portion around the source line contact electrode 17.

  The semiconductor integrated circuit device according to the embodiment of the present invention further includes the following requirements.

  (1) A semiconductor integrated circuit device includes a semiconductor substrate, a first gate electrode formed on the semiconductor substrate, a second gate electrode formed on the semiconductor substrate, and one side surface of the first gate electrode. A first diffusion layer formed in the semiconductor substrate below, and a first diffusion layer formed in the semiconductor substrate between the other side surface of the first gate electrode and the lower side surface of the second gate electrode. 2 diffusion layer, a contact electrode electrically connected to the first diffusion layer, and nitrogen formed in a shape having a recess between the first gate electrode and the second gate electrode, do not contain as a main component. A first insulating film, a second insulating film containing nitrogen as a main component formed on the first insulating film, and at least a part of the first insulating film on the first diffusion layer via the second insulating film And on the first gate electrode and on the second diffusion layer A third insulating film formed on the on the serial second gate electrode, the third is formed on the insulating film, and the third insulating film comprises an interlayer insulating film composed mainly differ. The lowermost position of the third insulating film on the second diffusion layer is higher than the lowermost position of the portion in contact with the contact electrode on the first diffusion layer, and the second insulating film is A multilayer structure is formed so as to embed the depression, and includes at least the first insulating film and the second insulating film between the first gate electrode and the second gate electrode.

  (2) In the semiconductor integrated circuit device according to (1), the width of the first diffusion layer is larger than the width of the second diffusion layer.

  (3) A semiconductor integrated circuit device includes a semiconductor substrate, a memory cell transistor array provided on the semiconductor substrate and including at least one memory cell transistor having a gate electrode, and the memory cell transistor array on the semiconductor substrate. A first cell unit including a selection transistor having a gate electrode, the memory cell transistor array including at least one memory cell transistor having a gate electrode provided on the semiconductor substrate; and Any one of a second cell unit including a selection transistor having a gate electrode provided adjacent to one end of the memory cell transistor row on the semiconductor substrate, the selection transistor of the first cell unit, and the memory cell transistor The selected cell of the second cell unit A diffusion layer formed in the semiconductor substrate between any of the star and the memory cell transistor, a contact electrode electrically connected to the diffusion layer, the first cell unit, and the second cell unit A first insulating film not containing nitrogen as a main component, and a second insulating film not containing nitrogen as a main component formed on the first insulating film; The first insulating film on the first cell unit, on the second cell unit, on the diffusion layer, between the gate electrodes of the first cell unit, and between the gate electrodes of the second cell unit; A third insulating film formed via the second insulating film and an interlayer insulating film formed on the third insulating film and having a different main component from the third insulating film are provided. The lowermost position of the third insulating film between the gate electrodes is higher than the lowermost position of the portion in contact with the contact electrode on the diffusion layer, and the second insulating film fills the depression. The multilayer structure includes at least the first insulating film and the second insulating film between the gate electrodes of the first cell unit and between the gate electrodes of the second cell unit.

  (4) In the semiconductor integrated circuit device according to any one of (1) to (3), the gate electrode of the memory cell transistor is a stack gate electrode including a floating gate and a control gate, and the third insulating film The lowermost position between the stack gate electrodes is higher than the uppermost position of the control gate.

  (5) In the semiconductor integrated circuit device according to any one of (1) to (3), the gate electrode of the memory cell transistor is a stack gate electrode including a floating gate and a control gate, and the third insulating film The lowermost position of the third insulating film between the stack gate electrodes is higher than the uppermost position of the floating gate.

  (6) In the semiconductor integrated circuit device according to any one of (1) to (5), the distance between the gate electrodes in each of the first cell unit and the second cell unit is a gate of the first cell unit. It is shorter than the distance between the electrode and the gate electrode of the second cell unit.

  (7) In the semiconductor integrated circuit device according to any one of (1) to (6), along the surface of the semiconductor substrate of the one insulating film formed on a side surface of the gate electrode facing the contact electrode. The sum of the film thickness in the vertical direction and the film thickness in the direction along the semiconductor substrate surface of the two insulating films formed on the side surface facing the contact electrode is at least half of the distance between the gate electrodes. .

  (8) In the semiconductor integrated circuit device according to any one of (1) to (7), the semiconductor substrate includes an element region and an element isolation region formed along the element region and including a fourth insulating film. The first cell unit, the diffusion layer, and the second cell unit are provided in the element region, and the fourth insulating film has a recess adjacent to the diffusion layer, and the first insulation A film and the second insulating film are formed in a recess of the fourth insulating film.

  (9) In the semiconductor integrated circuit device according to (8), the width of the element isolation region in a direction perpendicular to the direction along the element region is not more than the distance between the gate electrodes. .

  (10) In the semiconductor integrated circuit device according to any one of (1) to (9), each of the first insulating film and the second insulating film has a dielectric constant smaller than that of the third insulating film.

  (11) In the semiconductor integrated circuit device according to any one of (1) to (10), the density of charge traps in the first insulating film is smaller than the density of charge traps in the second insulating film.

  (12) In the semiconductor integrated circuit device according to any one of (1) to (11), the density of hydrogen contained in the first insulating film is higher than the density of hydrogen contained in the second insulating film. small.

  (13) In the semiconductor integrated circuit device according to any one of (1) to (12), an etching rate of the first insulating film is slower than an etching rate of the second insulating film.

  (14) In the semiconductor integrated circuit device according to any one of (1) to (13), each of the first insulating film and the second insulating film is a silicon oxide film.

  (15) In the semiconductor integrated circuit device according to any one of (1) to (14), the third insulating film is a silicon nitride film.

  (16) forming a first gate electrode and a second gate electrode on a semiconductor substrate, and introducing impurities into the semiconductor substrate using the first gate electrode and the second gate electrode as a mask; A first diffusion layer and a second diffusion layer are formed in the semiconductor substrate, and nitrogen is mainly formed on the first diffusion layer, the second diffusion layer, the first gate electrode, and the second gate electrode. A first insulating film that is not used as a component is formed with a depression between the first gate electrode and the second gate electrode, and a second insulating film that does not contain nitrogen as a main component is formed on the first insulating film. Is formed so as to fill a recess between the first gate electrode and the second gate electrode, a third insulating film is formed on the second insulating film, and the third insulating film is formed on the third insulating film. An interlayer insulating film having a different main component from the third insulating film is formed, and among the interlayer insulating films, A part of a semiconductor integrated circuit device, wherein a portion of a diffusion layer where a contact electrode is to be formed is etched to form a contact hole, and a contact electrode electrically connected to the first diffusion layer is formed in the contact hole Production method.

(17) A first cell unit gate electrode group including a gate electrode of at least one first memory cell transistor and a gate electrode of a first selection transistor adjacent to the gate electrode on the semiconductor substrate, and the first cell Forming a second cell unit gate electrode group adjacent to the unit gate electrode group and including a gate electrode of at least one second memory cell transistor and a gate electrode of a second select transistor adjacent to the gate electrode; Impurities are introduced into the substrate using the first cell unit gate electrode group and the second cell unit gate electrode group as a mask, a plurality of diffusion layers are formed in the semiconductor substrate, and the plurality of diffusions are formed. On the first layer, the first cell unit gate electrode group, and the second cell unit gate electrode group, a first insulating layer containing no nitrogen as a main component is formed. Forming an edge film with a recess between each gate electrode;
On the first insulating film, a second insulating film containing no nitrogen as a main component is formed between the gate electrodes in the first cell unit gate electrode group and between the gate electrodes in the second cell unit gate electrode group. A third insulating film is formed on the second insulating film, and an interlayer insulating film having a main component different from that of the third insulating film is formed on the third insulating film. Etching a portion of the diffusion layer between the first cell unit gate electrode group and the second cell unit gate electrode group on a predetermined portion of the contact electrode of the interlayer insulating film to form a contact hole, A method of manufacturing a semiconductor integrated circuit device, wherein a contact electrode electrically connected to the first diffusion layer is formed in the contact hole.

  (18) In the method of manufacturing a semiconductor integrated circuit device according to any one of (16) and (17), after forming the first insulating film, the first insulating film is processed in an oxidizing atmosphere.

  (19) In the method for manufacturing a semiconductor integrated circuit device according to any one of (16) to (18), the film formation rate of the first insulating film is made slower than the film formation rate of the second insulating film.

  Although the present invention has been described with a plurality of embodiments, the present invention is not limited to the embodiments, and various modifications can be made without departing from the spirit of the invention.

  For example, in each embodiment, the second gap is embedded between the memory cell gate electrodes 6, between the memory cell gate electrode 6 and the drain side selection gate electrode 12, and between the memory cell gate electrode 6 and the source side selection gate electrode 14. The insulating film may have a cavity. Even if there is a cavity, as long as the upper surface of the film is closed, the third insulating film 21 is not buried from the position defined in each embodiment, so the advantage in each embodiment does not change.

  Each embodiment has described an example of a NAND type or NOR type nonvolatile semiconductor memory device, but the present invention can also be applied to a nonvolatile semiconductor memory device other than a NAND type or NOR type.

  In particular, the present invention provides a three-transistor cell nonvolatile semiconductor memory device in which one memory cell MC is connected in series between a drain side select transistor STD and a source side select transistor STS as shown in FIG. As shown in FIG. 35, the present invention can also be applied to a two-transistor cell nonvolatile semiconductor memory device in which one memory cell MC and a source side select transistor STS (or a drain side select transistor STD) are connected in series. .

  Furthermore, the present invention relates to a nonvolatile semiconductor memory device having a NAND cell and a three-transistor cell in one chip, and a nonvolatile semiconductor memory having a NAND cell and a two-transistor cell in one chip. The present invention can also be applied to a nonvolatile semiconductor memory device including a device, a NAND type cell, a 3-transistor type cell, and a 2-transistor type cell in one chip.

  Moreover, although each embodiment can be implemented independently, it can also be implemented in combination as appropriate in addition to the above.

  Each embodiment includes inventions at various stages, and inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in each embodiment.

  The embodiments have been described based on an example in which the present invention is applied to a nonvolatile semiconductor memory device. However, the present invention is not limited to the nonvolatile semiconductor memory device, and a semiconductor integrated circuit incorporating the nonvolatile semiconductor memory device. Devices such as processors, system LSIs, and the like are also within the scope of the present invention.

FIG. 1 is a plan view showing an example of a plane pattern of a NAND type nonvolatile semiconductor memory device according to the first embodiment of the present invention. 2 is a cross-sectional view taken along line AA in FIG. 3 is a cross-sectional view taken along line BB in FIG. FIG. 4 is a sectional view showing an example of the manufacturing process of the NAND type nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 5 is a sectional view showing an example of the manufacturing process of the NAND type nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a sectional view showing an example of the manufacturing process of the NAND type nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 7 is a sectional view showing an example of the manufacturing process of the NAND type nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 8 is a sectional view showing an example of the manufacturing process of the NAND type nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 9 is a sectional view showing a manufacturing process example of the NAND-type nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 10 is a cross-sectional view showing a structural example of a NAND-type nonvolatile semiconductor memory device according to a modification of the first embodiment of the present invention. FIG. 11 is a sectional view showing a structural example of a NAND type nonvolatile semiconductor memory device according to the second embodiment of the invention. FIG. 12 is a sectional view showing an example of the structure of a NAND-type nonvolatile semiconductor memory device according to the third embodiment of the invention. FIG. 13 is a sectional view showing an example of the structure of a NAND-type nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. FIG. 14 is a plan view showing a plane pattern example of a NOR type nonvolatile semiconductor memory device according to the fifth embodiment of the present invention. 15 is a cross-sectional view taken along line AA in FIG. FIG. 16 is a sectional view showing an example of the structure of the nonvolatile semiconductor memory device according to the sixth embodiment. FIG. 17 is a cross-sectional view showing distances L1 and L2. 18 is a cross-sectional view showing an example of a contact hole forming process. FIG. 19 is a sectional view showing an example of a contact hole forming process. FIG. 20 is a sectional view showing an example of a contact hole forming process. FIG. 21 is a sectional view showing an example of a contact hole forming process. FIG. 22 is a sectional view showing an example of a contact hole forming process. FIG. 23 is a cross-sectional view showing an example of a contact hole forming process of the nonvolatile semiconductor memory device according to the sixth embodiment. FIG. 24 is a sectional view showing an example of a contact hole forming process of the nonvolatile semiconductor memory device according to the sixth embodiment. FIG. 25 is a sectional view showing an example of a contact hole forming process of the nonvolatile semiconductor memory device according to the sixth embodiment. FIG. 26 is a cross-sectional view showing an example of a contact hole forming step of the nonvolatile semiconductor memory device according to the sixth embodiment. FIG. 27 is a sectional view showing an example of a contact hole forming process of the nonvolatile semiconductor memory device according to the sixth embodiment. FIG. 28 shows a hydrogen profile in the film according to the first analysis example. FIG. 29 shows a hydrogen profile in the film according to the second analysis example. FIG. 30 is a diagram showing an in-film hydrogen profile according to the third analysis example. FIG. 31 shows a hydrogen profile in the film according to the fourth analysis example. 32A to 32F are diagrams showing examples of etching rate tests. 33A to 33F are diagrams showing another etching rate test example. FIG. 34 is a sectional view showing an example of a three-transistor cell nonvolatile semiconductor memory device. FIG. 35 is a sectional view showing an example of a three-transistor cell nonvolatile semiconductor memory device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 2 ... Well, 6 ... Memory cell gate electrode, 12, 14 ... Selection gate electrode, 11, 13, 15 ... Diffusion layer, 16, 17 ... Contact electrode, 19 ... 1st insulating film, 20 ... 2nd insulating film, 21 ... third insulating film, 22 ... interlayer insulating film.

Claims (5)

Forming a first gate electrode and a second gate electrode on a semiconductor substrate;
Impurities are introduced into the semiconductor substrate using the first gate electrode and the second gate electrode as a mask, and a first diffusion layer and a second diffusion layer are formed in the semiconductor substrate,
On the first diffusion layer, the second diffusion layer, the first gate electrode, and the second gate electrode, a first insulating film that does not contain nitrogen as a main component is formed, and the first gate electrode and the second gate electrode Formed with a recess between
Processing in an oxidizing atmosphere after forming the first insulating film;
A recess between the first gate electrode and the second gate electrode is embedded on the first insulating film with a second insulating film that does not contain nitrogen as a main component and has a higher hydrogen content than the first insulating film. Formed as
Forming a third insulating film containing nitrogen as a main component and having a higher hydrogen content than the first insulating film on the second insulating film;
Forming an interlayer insulating film different from the third insulating film on the third insulating film;
Etching a portion of the interlayer insulating film on the contact electrode formation planned portion of the first diffusion layer to form a contact hole,
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a contact electrode electrically connected to the first diffusion layer in the contact hole. A column of first memory cell gate electrodes on a semiconductor substrate, a first selection gate electrode adjacent to the column of first memory cell gate electrodes, a second selection gate electrode adjacent to the first selection gate, and the second selection Forming a column of second memory cell gate electrodes adjacent to the gate electrode;
Impurities are introduced into the semiconductor substrate using the column of the first memory cell gate electrode, the column of the first select gate electrode, the second select gate electrode, and the column of the second memory cell gate electrode as a mask, and the semiconductor Forming a plurality of diffusion layers in the substrate;
A plurality of diffusion layers, a column of the first memory cell gate electrodes, a column of the first selection gate electrode, the second selection gate electrode, and a column of the second memory cell gate electrode are not mainly composed of nitrogen. 1 insulating film is formed with a recess between the gates;
Processing in an oxidizing atmosphere after forming the first insulating film;
On the first insulating film, a second insulating film not containing nitrogen as a main component and having a hydrogen content higher than that of the first insulating film is provided between the first memory cell gate electrodes and the second memory cell gate electrode. Formed so as to embed the recesses in between,
Forming a third insulating film containing nitrogen as a main component and having a higher hydrogen content than the first insulating film on the second insulating film;
Forming an interlayer insulating film different from the third insulating film on the third insulating film;
Etching the portion of the interlayer insulating film on the contact electrode formation planned portion of the diffusion layer of the first selection gate electrode and the second selection gate electrode to form a contact hole,
A method of manufacturing a semiconductor integrated circuit device, wherein a contact electrode electrically connected to the diffusion layer is formed in the contact hole. On the semiconductor substrate, a column of first memory cell gate electrodes, a first select gate electrode adjacent to the column of first memory cell gate electrodes, a second select gate electrode adjacent to the first select gate, and the second Forming a column of second memory cell gate electrodes adjacent to the select gate electrode;
Impurities are introduced into the semiconductor substrate using the column of the first memory cell gate electrode, the column of the first select gate electrode, the second select gate electrode, and the column of the second memory cell gate electrode as a mask, and the semiconductor Forming a plurality of diffusion layers in the substrate;
A plurality of diffusion layers, a column of the first memory cell gate electrodes, a column of the first selection gate electrode, the second selection gate electrode, and a column of the second memory cell gate electrode are not mainly composed of nitrogen. 1 insulating film is formed with a recess between the gates;
Processing in an oxidizing atmosphere after forming the first insulating film;
A second insulating film that does not contain nitrogen as a main component and has a higher hydrogen content than the first insulating film is disposed between the first select gate electrode and the first memory cell gate electrode on the first insulating film. And forming the recess between the second select gate electrode and the second memory cell gate electrode,
Forming a third insulating film containing nitrogen as a main component and having a higher hydrogen content than the first insulating film on the second insulating film;
Forming an interlayer insulating film different from the third insulating film on the third insulating film;
Etching the portion of the interlayer insulating film on the contact electrode formation planned portion of the diffusion layer of the first selection gate electrode and the second selection gate electrode to form a contact hole,
A method of manufacturing a semiconductor integrated circuit device, wherein a contact electrode electrically connected to the diffusion layer is formed in the contact hole. Forming an element isolation region for separating a semiconductor substrate into respective element regions;
On the semiconductor substrate, a column of first memory cell gate electrodes, a first select gate electrode adjacent to the column of first memory cell gate electrodes, a second select gate electrode adjacent to the first select gate, and the first Forming a column of second memory cell gate electrodes adjacent to the two select gate electrodes;
By making the surface of the element isolation region adjacent to the contact electrode formation planned portion lower than the surface of the element region, a first depression is formed,
Impurities are introduced into the semiconductor substrate using the column of the first memory cell gate electrode, the column of the first select gate electrode, the second select gate electrode, and the column of the second memory cell gate electrode as a mask, and the semiconductor Forming a plurality of diffusion layers in the substrate;
A plurality of diffusion layers, a column of the first memory cell gate electrodes, a column of the first selection gate electrode, the second selection gate electrode, and a column of the second memory cell gate electrode are not mainly composed of nitrogen. 1 insulating film is formed with a second recess between the gates, and also formed in the first recess,
Processing in an oxidizing atmosphere after forming the first insulating film;
On the first insulating film, a second insulating film not containing nitrogen as a main component and having a hydrogen content higher than that of the first insulating film is provided between the first memory cell gate electrodes and the second memory cell gate electrode. Forming the second depression in between, and also forming in the first depression,
Forming a third insulating film containing nitrogen as a main component and having a higher hydrogen content than the first insulating film on the second insulating film;
Forming an interlayer insulating film different from the third insulating film on the third insulating film;
Etching the portion of the interlayer insulating film on the contact electrode formation planned portion of the diffusion layer of the first selection gate electrode and the second selection gate electrode to form a contact hole,
A method of manufacturing a semiconductor integrated circuit device, wherein a contact electrode electrically connected to the diffusion layer is formed in the contact hole. Forming an element isolation region for separating a semiconductor substrate into respective element regions;
On the semiconductor substrate, a column of first memory cell gate electrodes, a first select gate electrode adjacent to the column of first memory cell gate electrodes, a second select gate electrode adjacent to the first select gate, and the first Forming a column of second memory cell gate electrodes adjacent to the two select gate electrodes;
By making the surface of the element isolation region adjacent to the contact electrode formation planned portion lower than the surface of the element region, a first depression is formed,
Impurities are introduced into the semiconductor substrate using the column of the first memory cell gate electrode, the column of the first select gate electrode, the second select gate electrode, and the column of the second memory cell gate electrode as a mask, and the semiconductor Forming a plurality of diffusion layers in the substrate;
A plurality of diffusion layers, a column of the first memory cell gate electrodes, a column of the first selection gate electrode, the second selection gate electrode, and a column of the second memory cell gate electrode are not mainly composed of nitrogen. 1 insulating film is formed with a second recess between the gates, and also formed in the first recess,
Processing in an oxidizing atmosphere after forming the first insulating film;
A second insulating film not containing nitrogen as a main component and having a higher hydrogen content than the first insulating film is formed on the first insulating film between the first select gate electrode and the first memory cell gate electrode. And so as to fill the second depression between the second selection gate electrode and the second memory cell gate electrode, and also formed in the first depression,
Forming a third insulating film containing nitrogen as a main component and having a higher hydrogen content than the first insulating film on the second insulating film;
Forming an interlayer insulating film different from the third insulating film on the third insulating film;
Etching the portion of the interlayer insulating film on the contact electrode formation planned portion of the diffusion layer of the first selection gate electrode and the second selection gate electrode to form a contact hole,
A method of manufacturing a semiconductor integrated circuit device, wherein a contact electrode electrically connected to the diffusion layer is formed in the contact hole.

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