JP2009048727A - Viterbi decoding device, viterbi decoding method, program, and computer readable recording medium recorded with program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce an error rate by performing a viterbi decoding in the consideration of the existence of a pattern of a two-dimensional modulation in a bit pattern indicating the transition of a trellis state in a viterbi decoding device for viterbi-decoding a two dimensional reproduced signal of two-dimensionally modulated page data. <P>SOLUTION: The viterbi decoding device 21 is provided with a two-dimensional viterbi decoding circuit 5 which performs viterbi-decodings by calculating path metric based on transition of a trellis state about a plurality of rows including decoding object rows in a two-dimensional reproduced signal of page data being two-dimensionally modulated. The two-dimensional viterbi decoding circuit 5 performs the viterbi decoding by removing the transition of the trellis state based on a bit pattern indicating transition of the trellis state about a plurality of rows including the decoding object row and a two-dimensional modulation pattern. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a Viterbi decoding apparatus, a Viterbi decoding method, a program, and a computer-readable recording medium on which a program is recorded, which Viterbi decodes a two-dimensional signal such as a hologram memory reproduction signal.

  In recent years, a hologram memory that records and reproduces information two-dimensionally, that is, as page data using holography, is attracting attention as a next-generation high-density recording / reproducing system.

  The outline of the hologram memory system will be described with reference to FIG. FIG. 16 is a diagram schematically showing an outline of the hologram memory system. As shown in FIG. 16, in this system, when recording information data, it should be recorded using a spatial light modulator 60 (for example, a liquid crystal panel or DMD (Digital Micromirror Device)) composed of a plurality of pixels. The recording signal light is spatially modulated based on the information data, and a two-dimensional interference fringe is generated by causing the recording signal light passing through the lens 61 and the coherent recording reference light to interfere with each other. The image is recorded on the hologram medium 62 as two-dimensional information.

  Here, as the hologram medium 62, there are a rewritable medium using an inorganic photorefractive crystal typified by lithium niobate and a write-once medium using a photopolymer which is an organic polymer material.

  On the other hand, when reproducing the information data by reading the recorded interference fringes from the hologram medium 62, the reflection generated by irradiating the hologram medium 62 with the reproduction reference light at the same incident angle as the recording reference light. Light or transmitted light is received by a light receiving element 64 (for example, a CCD or CMOS sensor) having a plurality of pixels through a lens 63 to generate a reproduction signal, and the original information data is reproduced using the generated reproduction signal. To do.

  Note that the two-dimensional reproduction signal obtained as described above can be regarded as indicating a two-dimensional waveform of the signal. In addition, the reproduction signal arranged along a certain direction among the two-dimensional reproduction signals can be regarded as indicating a one-dimensional waveform of the signal. In this way, the reproduced signal is regarded as a waveform and may be referred to as a “reproduced waveform signal”.

  As described above, since reproduction is performed in units of two-dimensional page data in the above system, it is possible to significantly improve the reproduction speed as compared with a conventional optical disk that performs reproduction in one dimension.

(Decision feedback Viterbi decoding)
By the way, in the hologram memory system, various noises may be mixed in the recording process and the reproducing process (in particular, noises are often generated due to inhomogeneity of the recording medium). As a result, the SN ratio (signal-to-noise power ratio) decreases. In addition, there is an influence of a reproduction signal from an adjacent pixel, that is, an inter-pixel interference, which may prevent the original signal from being reproduced accurately.

  Therefore, conventionally, methods for accurately reproducing information by reducing the influence of noise and inter-pixel interference have been studied. In particular, a technique for Viterbi decoding of a reproduction signal output from a light receiving element has been studied. Patent Document 1 discloses a decision feedback viterbi algorithm, which is one method of viterbi decoding.

(Difference detection method)
On the other hand, in a conventional hologram memory system, a detection method called a difference detection method is disclosed (see Patent Document 2).

  The difference detection method is used when decoding a two-dimensional reproduction signal of page data two-dimensionally modulated using a modulation method called a constant weight code. Typical constant weight codes include a 1: 2 differential code in which the modulation block is composed of two pixels and a 2: 4 code in which the modulation block is 2 × 2, that is, four pixels.

(2: 4 code)
The 2: 4 code will be described with reference to FIG. In the case of the 2: 4 code shown in FIG. 17, only one of the four pixels is “1” and the remaining three pixels are “0”. Therefore, there are four types of such modulation blocks as shown in FIG. That is, [1, 0; 0, 0], [0, 1; 0, 0], [0, 0; 1, 0] and [0, 0; 0, 1] ([k, l; m, n] means a matrix in which row vectors [k, l] and [m, n] are arranged in the column direction (hereinafter, the matrix is also expressed in accordance with this notation). Then, 2 bits of information bits (2 square, that is, 4 types) are modulated and converted into a modulation block of 4 pixels, which is called a 2: 4 code. In FIG. 17, the 2-bit information bit “00” is set to [1, 0; 0, 0], the 2-bit information bit “01” is set to [0, 1; 0, 0], and the 2-bit information bit “ 10 ”is converted into [0,0; 1,0], and the two information bits“ 11 ”are converted into [0,0; 0,1].

In the difference code, a logical value “1” is a bright pixel (a corresponding pixel on the light receiving element is a bright point), and a logical value “0” is a dark pixel (a corresponding pixel on the light receiving element is a dark point). To be recorded on the hologram medium. In the difference detection method, the pixel having the highest luminance among the four pixels of the reproduction signal of each modulation block, that is, the pixel having the highest reproduction signal level is determined as “1”, and the other pixels are determined as “0”. The decoding bit is determined by.
US Pat. No. 5,740,184 (issued on April 14, 1998) JP 9-197947 A (publication date: July 31, 1997)

  As described above, in the hologram memory system, different methods, namely, a Viterbi decoding method and a difference detection method have been proposed. Since the difference detection method is based on page data modulated with a constant weight code, when standardizing the hologram memory, it is necessary to define a predetermined constant weight code as the page data modulation method. When the Viterbi decoding method is adopted in a reproducing apparatus for a hologram memory medium based on such a standard, the feature of the constant weight code cannot be taken into consideration as in the difference detection method, so that the decoding error rate is sufficiently reduced. There was a problem that it was not possible.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide bits having a low error rate using a Viterbi decoding method for page data modulated by a predetermined modulation method such as a constant weight code. An object is to realize a Viterbi decoding device capable of decoding, a Viterbi decoding method, a program, and a computer-readable recording medium recording the program.

  In order to solve the above problems, a Viterbi decoding device according to the present invention is a Viterbi decoding device that Viterbi-decodes a two-dimensional reproduction signal of two-dimensionally modulated page data, wherein a decoding target row in the two-dimensional reproduction signal is determined. Viterbi decoding means for performing Viterbi decoding by calculating a path metric using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition based on a transition of a trellis state for a plurality of rows including And the Viterbi decoding means removes the trellis state transition and removes the trellis state transition based on the bit pattern representing the trellis state transition for the plurality of rows including the decoding target row and the two-dimensional modulation pattern. It is characterized by decoding.

  The Viterbi decoding method according to the present invention is a Viterbi decoding method for Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data, wherein a trellis for a plurality of rows including a decoding target row in the two-dimensional reproduction signal. Including the Viterbi decoding step of performing Viterbi decoding by calculating a path metric based on a state transition and using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition, The step is characterized in that, based on the bit pattern representing the trellis state transition and the two-dimensional modulation pattern, the trellis state transition is removed and Viterbi decoding is performed.

  According to the above configuration, when Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data, a bit pattern representing a trellis state transition for a plurality of rows including the decoding target row, and the two-dimensional modulation Based on the pattern, the transition can be removed.

  Therefore, when Viterbi decoding is performed, branches (transitions) in the trellis diagram are reduced, so that the probability of selecting an error path is reduced.

  Therefore, in Viterbi decoding, there is an effect that bit decoding with a low error rate can be realized.

  Furthermore, the Viterbi decoding apparatus according to the present invention determines whether or not a bit pattern representing a transition of a trellis state for a plurality of rows including the decoding target row includes the entire two-dimensional modulation block in the above configuration. Block boundary determination means, and two-dimensional modulation pattern detection means for determining that the entire two-dimensional modulation block does not match any of the two-dimensional modulation patterns, wherein the block boundary determination means includes the trellis state. And the two-dimensional modulation pattern detection means determines that the entire two-dimensional modulation block is the same as any of the two-dimensional modulation patterns. When it is determined that they do not match, the Viterbi decoding unit may remove the transition and perform Viterbi decoding.

  According to the above configuration, when the bit pattern includes the entire two-dimensional modulation block and the entire two-dimensional modulation block does not match any of the two-dimensional modulation patterns, the bit pattern is represented by the bit pattern. The transitions that are present can be removed.

  Therefore, since it is determined that the portion specified as the two-dimensional modulation block in the bit pattern does not match any of the two-dimensional modulation patterns, efficient determination can be performed.

  Therefore, when performing Viterbi decoding, the branch (transition) removal process in the trellis diagram can be efficiently executed.

  Furthermore, the Viterbi decoding device according to the present invention includes the decoding target row based on the modulation method of the two-dimensional modulation and the row position and the column position in the page data of the decoding target bit in the above configuration. When it is known in advance that a bit pattern representing a trellis state transition for a plurality of rows does not exist as the two-dimensional modulation pattern, the Viterbi decoding unit may remove the transition in advance and perform Viterbi decoding.

  According to the above configuration, trellis state transitions for a plurality of rows including the decoding target row are represented using the modulation scheme of the two-dimensional modulation and the decoding target row position and column position in the page data. Whether or not a bit pattern exists as the two-dimensional modulation pattern can be recognized and the transition can be removed in advance.

  Therefore, it is not necessary to determine whether the bit pattern representing the transition of the trellis state for a plurality of rows including the decoding target row includes the entire two-dimensional modulation block.

  Therefore, when performing Viterbi decoding, it is possible to perform bit decoding processing with a low error rate with a simple circuit configuration.

  Furthermore, in order to solve the above-described problem, a Viterbi decoding device according to the present invention is a Viterbi decoding device that performs Viterbi decoding of a two-dimensional reproduction signal of two-dimensionally modulated page data, the decoding target in the two-dimensional reproduction signal Viterbi that performs Viterbi decoding by calculating a path metric using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition based on a transition of a trellis state for a plurality of rows including a row Decoding means, and decoding bit output means for outputting a decoded bit obtained as a result of Viterbi decoding the row immediately preceding the decoding target row by the Viterbi decoding means, wherein the Viterbi decoding means includes a plurality of decoding target rows. Bit pattern obtained by combining the row consisting of the above decoded bits into a matrix representing the trellis state transition for the row If, based on the pattern of the two-dimensional modulation, it is characterized by Viterbi decoding by removing the transition of the trellis states.

  The Viterbi decoding method according to the present invention is a Viterbi decoding method for Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data, wherein a trellis for a plurality of rows including a decoding target row in the two-dimensional reproduction signal. A Viterbi decoding step for performing Viterbi decoding by calculating a path metric using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric based on the state transition, and the Viterbi decoding step And a decoded bit output step for outputting a decoded bit obtained as a result of Viterbi decoding the row immediately preceding the decoding target row, and in the Viterbi decoding step, transition of a trellis state for a plurality of rows including the decoding target row A bit pattern obtained by combining a row of the decoded bits with a matrix representing Based on the dimensions modulation pattern is characterized by the Viterbi decoding by removing the transition of the trellis states.

  According to the above configuration, when Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data, a matrix representing trellis state transitions for a plurality of rows including a decoding target row in the two-dimensional reproduction signal is The transition can be removed based on a bit pattern obtained by combining decoded bits corresponding to a row immediately before the decoding target row and the two-dimensional modulation pattern.

  Therefore, even if the decoding target row in the two-dimensional reproduction signal is an even row, by using a row composed of decoding bits corresponding to the row immediately before the decoding target row, a plurality of rows including the decoding target row can be obtained. Paths consisting of trellis state transitions can be removed. Therefore, when Viterbi decoding is performed, more branches (transitions) in the trellis diagram can be removed, so that the probability of selecting an error path is further reduced.

  Therefore, in Viterbi decoding, there is an effect that bit decoding with a lower error rate can be realized.

  Furthermore, the Viterbi decoding device according to the present invention, in the above-described configuration, has a bit pattern obtained by combining a row composed of the decoded bits with a matrix representing a trellis state transition for a plurality of rows including the decoding target row. Block boundary determination means for determining whether or not the entire two-dimensional modulation block is included, and two-dimensional modulation pattern detection for determining that the entire two-dimensional modulation block does not match any of the two-dimensional modulation patterns And the block boundary determination unit determines that the bit pattern obtained by the combination includes the entire block of the two-dimensional modulation, and the two-dimensional modulation pattern detection unit detects the two-dimensional modulation pattern. If it is determined that the entire modulation block does not match any of the two-dimensional modulation patterns, the Viterbi decoding means removes the transition. It may be configured to Viterbi decoding.

  According to the above configuration, when the bit pattern obtained by the combination includes the entire two-dimensional modulation block and the entire two-dimensional modulation block does not match any of the two-dimensional modulation patterns, Transitions represented by bit patterns can be removed.

  Therefore, since it is determined that the portion specified as the two-dimensional modulation block in the bit pattern obtained by the above combination does not match any of the two-dimensional modulation patterns, an efficient determination can be performed.

  Therefore, when performing Viterbi decoding, the branch (transition) removal process in the trellis diagram can be efficiently executed.

  Furthermore, the Viterbi decoding device according to the present invention, in the configuration described above, is based on the modulation method of the two-dimensional modulation, the row position and the column position in the page data of the decoding target bit, and the decoding bit. When it is known in advance that the bit pattern obtained by combining the row of the decoded bits does not include the two-dimensional modulation pattern in the matrix representing the transition of the trellis state for a plurality of rows including the row, the Viterbi decoding means However, the above transition may be removed in advance and Viterbi decoding may be performed.

  According to the above configuration, the trellis state of a plurality of rows including the decoding target row is determined using the modulation method of the two-dimensional modulation, the row position and column position of the decoding target in the page data, and the decoding bit. It is possible to recognize in advance whether or not a bit pattern obtained by combining the row of the decoded bits with the matrix representing the transition exists as the two-dimensional modulation pattern, and to remove the transition in advance.

  Therefore, a process for determining that the bit pattern obtained by combining the row composed of the decoded bits into the matrix representing the transition of the trellis state for a plurality of rows including the decoding target row includes the entire two-dimensional modulation block Is no longer necessary.

  Therefore, when performing Viterbi decoding, it is possible to perform bit decoding processing with a low error rate with a simple circuit configuration.

  Furthermore, the Viterbi decoding apparatus according to the present invention, in the above-described configuration, further includes synchronization pattern detection means for detecting the synchronization pattern from the two-dimensional reproduction signal, wherein the page data includes a synchronization pattern. The block boundary determination means recognizes the position of the bit pattern based on the size of the block of the two-dimensional modulation and the bit position in the page data of the synchronization pattern detected by the synchronization pattern detection means, and the bit pattern is 2 It may be configured to determine whether or not the entire block of dimension modulation is included.

  According to said structure, the position of the said bit pattern can be recognized based on the bit position in the page data of the synchronous pattern contained in the said page data, and the said bit pattern contains the whole block of two-dimensional modulation? It can be determined whether or not.

  Therefore, the position of the bit pattern can be easily recognized, and a process for determining that the bit pattern includes the entire two-dimensional modulation block can be easily performed.

  Therefore, when performing Viterbi decoding, the above determination can be realized by a simple process, whereby the branch (transition) removal process in the trellis diagram can be performed and bit decoding with a low error rate can be realized. .

  Furthermore, the Viterbi decoding apparatus according to the present invention, in the above-described configuration, further includes synchronization pattern detection means for detecting the synchronization pattern from the two-dimensional reproduction signal, wherein the page data includes a synchronization pattern. The row position and the column position of the decoding target bit may be determined based on the bit position in the page data of the synchronization pattern detected by the synchronization pattern detection unit.

  According to said structure, the row position and column position of the said decoding object bit can be determined based on the bit position in the page data of the synchronous pattern contained in the said page data.

  Therefore, it is possible to easily recognize the position of the bit pattern, and based on the position of the bit pattern, it can be easily understood whether the bit pattern does not include the entire block of two-dimensional modulation.

  Therefore, when Viterbi decoding is performed, the branch (transition) removal process in the trellis diagram can be performed with a simple circuit configuration, and bit decoding with a low error rate can be realized.

  Furthermore, the Viterbi decoding apparatus according to the present invention is configured such that, in the above-described configuration, the synchronization pattern is identifiable with any one of two values adjacent to each other in the row direction or the column direction in the page data. It is good also as the structure arranged.

  According to the above configuration, the synchronization pattern is arranged in such a manner that any one of the two values is adjacent to each other in the row direction or the column direction so as to be identifiable in the page data.

  Thus, for example, the synchronization pattern is composed of 2 × 2, that is, a logical value “1” of 4 pixels, and is arranged at the upper left corner of the page data.

  Therefore, by detecting the synchronization pattern from the page data, it is possible to obtain the shape and size of the synchronization pattern.

  The Viterbi decoding device may be realized by a computer. In this case, a Viterbi decoding device control program for realizing the Viterbi decoding device by a computer by causing the computer to operate as the above-described means, and A computer-readable recording medium on which is recorded also falls within the scope of the present invention.

  As described above, the Viterbi decoding device according to the present invention is a Viterbi decoding device that Viterbi-decodes a two-dimensional reproduction signal of two-dimensionally modulated page data, and includes a plurality of rows including decoding target rows in the two-dimensional reproduction signal. Viterbi decoding means for performing Viterbi decoding by calculating a path metric using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition based on the transition of the trellis state for The Viterbi decoding means removes the trellis state transition and performs Viterbi decoding based on the bit pattern representing the trellis state transition for a plurality of rows including the decoding target row and the two-dimensional modulation pattern.

  The Viterbi decoding method according to the present invention is a Viterbi decoding method for Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data, wherein a trellis for a plurality of rows including a decoding target row in the two-dimensional reproduction signal. Including the Viterbi decoding step of performing Viterbi decoding by calculating a path metric based on a state transition and using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition, In step, the trellis state transition is removed and Viterbi decoding is performed based on the bit pattern representing the trellis state transition and the two-dimensional modulation pattern.

  Therefore, when Viterbi decoding is performed, branches (transitions) in the trellis diagram are reduced, so that the probability of selecting an error path is reduced.

  Therefore, in Viterbi decoding, there is an effect that bit decoding with a low error rate can be realized.

[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.

  A hologram memory reproduction system 20 including a Viterbi decoding device 21 according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a hologram memory reproducing system 20 including a Viterbi decoding device 21 according to the present embodiment.

  As shown in FIG. 1, the hologram memory reproduction system 20 includes a hologram memory reproduction device 1, a buffer memory 2, and a Viterbi decoding device 21. The Viterbi decoding device 21 includes a two-dimensional waveform equalization circuit 3, a synchronization pattern detection circuit 4 (synchronization pattern detection means), a two-dimensional Viterbi decoding circuit 5 (Viterbi decoding means), and a decoded bit row output circuit 6 (decoded bit output). Means), a decoding bit register 7, an assumed waveform level setting circuit 8, a block boundary determination circuit 9 (block boundary determination means), and a modulation rule determination circuit 10 (two-dimensional modulation pattern detection means).

  As will be described later, the Viterbi decoding device 21 is preferably configured to include the two-dimensional waveform equalization circuit 3 from the viewpoint of error rate, but the two-dimensional waveform equalization circuit from the viewpoint of suppressing an increase in circuit scale. 3 may be omitted.

(Hologram memory playback device 1)
The hologram memory reproducing apparatus 1 corresponds to the structure on the reproducing side in the hologram memory system described with reference to FIG. That is, reflected light or transmitted light (coherent light) generated by irradiating a reproduction reference light to a hologram medium (not shown) in which information is recorded as interference fringes is received through a lens and having a plurality of pixels. It is a device that receives a light by an element (for example, a CCD or CMOS sensor) and generates a reproduction signal. Note that the playback signal may be regarded as a waveform and referred to as a “playback waveform signal”.

  Here, the page data 50 recorded on a hologram medium (not shown) in the hologram memory reproducing apparatus 1 will be described with reference to FIG. FIG. 2 is a diagram schematically showing a format of page data 50 recorded on a hologram medium (not shown) in the hologram memory reproducing apparatus 1.

  On a hologram medium (not shown), page data 50 in the format shown in FIG. 2 is recorded. As shown in FIG. 2, the page data 50 is composed of one synchronization pattern 51 and a plurality of modulation blocks 52. When the two-dimensional modulation is 2: 4 code, the synchronization pattern 51 is composed of 2 × 2, that is, a logical value “1” of 4 pixels, and is usually arranged at the upper left corner of the page data 50. However, the position where the synchronization pattern 51 is arranged is not limited to the upper left corner of the page data 50.

  The logical value “1” is recorded on the hologram medium in correspondence with the bright pixel, and the logical value “0” is recorded on the dark pixel. The synchronization pattern 51 is not limited to being composed of a logical value “1” of 4 pixels.

  In the modulation block 52, information bits such as user data are two-dimensionally modulated by a 2: 4 code. Note that, as described with reference to FIG. 17, the 2: 4 code is used to modulate 2 information bits and convert them to a 4-pixel modulation block. The two-dimensional modulation for the modulation block 52 is not limited to the constant weight code of 2: 4 code.

(Buffer memory 2)
The buffer memory 2 is a storage device that stores the reproduction signal generated by the hologram memory reproduction device 1 in units of page data. As described with reference to FIG. 16, the reproduction signal in units of page data stored in the buffer memory 2 is a two-dimensional reproduction signal affected by the influence of reproduction signals from adjacent pixels, that is, the influence of inter-pixel interference. It has become.

(Two-dimensional waveform equalization circuit 3)
The two-dimensional waveform equalization circuit 3 assumes the reproduced waveform signal by performing two-dimensional waveform equalization on the reproduced waveform signal generated by the hologram memory reproducing device 1 and stored in the buffer memory 2. The waveform level setting circuit 8 converts the signal into a signal x suitable for the assumed signal. The configuration of the two-dimensional waveform equalization circuit 3 and the processing content of the waveform equalization are conventional techniques that are generally known, and thus detailed description thereof will be omitted.

(Synchronization pattern detection circuit 4)
The synchronization pattern detection circuit 4 is a circuit that detects the synchronization pattern 51 from the signal that has been waveform-equalized by the two-dimensional waveform equalization circuit 3.

  Here, when the synchronization pattern 51 is a total of 2 × 2, that is, a 4-bit pattern in which the logical value “1” is adjacent to each other by 2 bits in the row direction and the column direction, the reproduction signal of the synchronization pattern 51 is four times the size. Can be regarded as a bright pixel. In this case, even in a high-density system assuming that Viterbi decoding is performed, the synchronization pattern detection circuit 4 can be realized not by Viterbi decoding but by a threshold detection method with a simple circuit configuration. The threshold detection method is a method of decoding to “1” if the reproduction signal level of each pixel is greater than a predetermined threshold, and to “0” if it is smaller.

  Thus, the synchronization pattern 51 is preferably a pattern configured such that a plurality of logical values “1” are adjacent to each other in the row direction or the column direction and are identifiable.

(Two-dimensional Viterbi decoding circuit 5)
The two-dimensional Viterbi decoding circuit 5 is based on the signal x that has been waveform-equalized by the two-dimensional waveform equalization circuit 3 and the assumed waveform level w calculated by the assumed waveform level setting circuit 8. This is a circuit that performs decision feedback Viterbi decoding using the sum of squared errors of the equalized signal x as a branch metric of a trellis transition. At this time, a predetermined trellis transition is prohibited (removed). Specific processing contents for prohibiting (removing) a predetermined trellis transition will be described later.

(Decision feedback Viterbi decoding)
Here, the decision feedback Viterbi decoding executed by the two-dimensional Viterbi decoding circuit 5 will be described below. In the determination feedback Viterbi decoding method, the reproduction signal is Viterbi-decoded along the horizontal direction (that is, the row direction) of the page data. Then, the process of determining the decoded bit for each row is performed while shifting the vertical direction (that is, the column direction) for each row. At that time, the previous decoding result (feedback row) is used for Viterbi decoding of the next row.

  The outline of the decision feedback Viterbi decoding method will be described with reference to FIGS. FIG. 3 is a diagram showing an impulse response of inter-pixel interference in the decision feedback Viterbi decoding method. FIG. 4 is a trellis diagram in the decision feedback Viterbi decoding method. The trellis diagram is a state transition diagram corresponding to the Viterbi decoding process.

  As shown in FIG. 3, when the inter-pixel interference is expressed as a two-dimensional impulse response h represented by a 3 × 3 matrix, the trellis state is defined as a 2 × 2 matrix. The trellis diagram in this case is expressed as shown in FIG.

  The “two-dimensional impulse response” means an output signal that is output from the linear system when a unit impulse signal is input to the linear system. Here, the unit impulse signal means a two-dimensional bit matrix in which (a) the signal level of only 1 bit is 1, and (b) the signal levels of other bits are all 0.

  In the two-dimensional impulse response h shown in FIG. 3, the signal level is generated not only in the central pixel but also in the neighboring adjacent pixels. That is, the occurrence of inter-pixel interference is assumed.

  The trellis state is expressed as [k, l; m, n]. Here, since k, l, m, and n are all 1-bit values (that is, 0 or 1), there are 2 4, that is, 16 types of trellis states. As shown in FIG. 4, there are four branches (transitions) from one trellis state to the next trellis state for each trellis state. Similarly, there are four branches input to each trellis state for each trellis state.

  The assumed waveform level assumed by each branch is determined by a 3 × 3 matrix in which a feedback row is combined with a 2 × 3 matrix in which two trellis states connected to the branch are combined.

  For example, a level assumed by a branch from [0, 0; 0, 1] to [0, 1; 1, 0] (an assumed signal value assumed for a trellis state transition) will be described as an example. The level assumed by this branch is determined by the matrix [1, 1, 0; 0, 0, 1; 0, 1, 0], assuming that the feedback row one level above is [1, 1, 0]. Is done. Specifically, a value “0.31” obtained by performing a two-dimensional convolution operation on the two-dimensional impulse response h and the matrix [1, 1, 0; 0, 0, 1; 0, 1, 0] This is the assumed waveform level of this branch.

  The decision feedback Viterbi decoding process is performed in the row direction from left to right in the page data. If the waveform obtained by scanning the reproduction signal in the row direction is a reproduction signal waveform, the square error between the level of the reproduction signal waveform and the assumed waveform level of each branch is used as a branch metric, and the path leading to each trellis state Is the path metric. Then, the path with the smallest path metric among the four paths input to each trellis state is left as a surviving path. The path metric is an error of the input signal with respect to the ideal signal of the path.

  Then, the above processing is performed for each trellis state and repeated in the row direction. As a result, the surviving paths converge to one when going back (leftward) by a predetermined time. Therefore, this survival path is determined as the correct answer path. The predetermined time is called a path memory length.

  The above process is in principle the same as the conventional one-dimensional Viterbi decoding method. Therefore, further detailed description is omitted.

  However, correct path handling is different from one-dimensional Viterbi decoding. That is, in the case of one dimension, the correct path corresponds to the bit sequence itself, but in the case of two dimensions, the correct path is a matrix. Therefore, in the two-dimensional case, the correct answer path corresponds to a plurality of bit rows. In the above example, there are two bit rows.

  Of these two bit rows, the second row does not consider the influence from the third and subsequent bit rows. That is, since the influence of inter-pixel interference is only partially considered, the reliability is poor. On the other hand, for the first row, all the waveform interference from the top, bottom, left and right is taken into consideration and Viterbi decoded. Therefore, only the first line is output as a decoded bit.

  One bit row is obtained by Viterbi decoding in the row direction. Therefore, in order to decode the entire page data, this process is repeated while shifting one column at a time in the column direction (downward). As a result, the entire two-dimensional reproduction signal is decoded.

  Here, the concept of decision feedback is introduced. Judgment feedback is a method of reflecting the decoding result of the row immediately above the current decoding target row as a feedback row to Viterbi decoding of the next row. Specifically, it is as described above. That is, the decoding result of the next row is used for the process of determining the assumed waveform level of the branch of the next row. Thereby, the decoding result is reflected.

  The procedure for decision feedback will be described in more detail below. When reproduction is performed based on the reproduction waveform signal received in the uppermost row of the light receiving elements 64, it can be considered that the amount of received light in the upper row of the uppermost row is zero. Therefore, when information is reproduced based on the reproduction waveform signal from the top row, all feedback rows are set to zero.

  Next, information is reproduced based on the reproduced waveform signal from the second line from the top. At this time, it is assumed that the bit row is correctly decoded in the first row (that is, the uppermost row), and this is used for decoding the second row as a feedback row.

  Furthermore, the reproduction is performed based on the reproduction waveform signal from the third row from the top. At this time, it is assumed that the bit row is correctly decoded in the second row, and this is used for decoding the third row as a feedback row.

  As described above, in the decision feedback Viterbi decoding method, it is assumed that the decoding process is accurately performed in the row (up one) immediately before the current decoding target row. Then, Viterbi decoding is performed on the reproduced waveform signal from the current row while taking into consideration the effect of the immediately preceding row (up one row) (that is, performing decision feedback in the column direction). Therefore, a Viterbi decoding process is performed in which the influence of inter-pixel interference in the column direction is further taken into consideration. Therefore, the Viterbi decoding process can be executed more accurately than the conventional one-dimensional Viterbi decoding process, that is, the Viterbi decoding process using the change in the reproduction waveform only in the row direction.

(Decoded bit row output circuit 6)
The decoded bit row output circuit 6 is a circuit that extracts and outputs a decoded bit row q corresponding to the decoding target row among the decoded bit rows included in the path that survives the decoding in the two-dimensional Viterbi decoding circuit 5. That is, only the bit in the first row that is Viterbi-decoded with all waveform interference from the top, bottom, left and right taken into account is output from the decoded bit row output circuit 6 as a decoded bit.

(Decoding bit register 7)
The decoded bit register 7 is a register that holds the decoded bit output from the decoded bit row output circuit 6.

(Assumed waveform level setting circuit 8)
The assumed waveform level setting circuit 8 calculates an assumed waveform level to be used in the two-dimensional Viterbi decoding circuit 5 using the decoded bits held in the decoding bit register 7, and two-dimensional Viterbi decoding the calculated assumed waveform level w It is a circuit that transmits to the circuit 5.

(Block boundary determination circuit 9)
The block boundary determination circuit 9 determines whether or not the bit pattern representing each transition of the trellis state corresponding to the reproduced waveform signal read from the buffer memory 2 includes the entire block of two-dimensional modulation. That is, a bit pattern representing each transition of the trellis state based on the position of the synchronization pattern 51 detected by the synchronization pattern detection circuit 4 and the row position and column position of the current decoding target bit in the two-dimensional Viterbi decoding circuit 5 Determines whether the entire block of two-dimensional modulation is included.

  At this time, the boundary of the modulation block 52 is recognized based on the bit position in the page data 50 of the synchronization pattern 51 detected by the synchronization pattern detection circuit 4. That is, as described with reference to FIG. 2, when the two-dimensional modulation is 2: 4 code, the synchronization pattern 51 includes 2 × 2, that is, the logical value “1” of 4 pixels. If the bit position in the data 50 is known, the boundary of the modulation block 52 can be recognized.

  A bit pattern representing each transition of the trellis state will be described later.

(Modulation law determination circuit 10)
When the block boundary determination circuit 9 determines that the entire block of the two-dimensional modulation is included, the modulation rule determination circuit 10 determines that the entire block of the two-dimensional modulation included in the bit pattern representing each transition of the trellis state is two-dimensional. It is determined whether or not any of the modulation patterns matches.

  Therefore, the modulation rule determination circuit 10 receives from the two-dimensional Viterbi decoding circuit 5 the modulation block included in the bit pattern representing each transition of the trellis transition related to the current decoding target bit. Then, it is determined whether the received modulation block matches any one of the two-dimensional modulation patterns.

  As described above, the two-dimensional waveform equalization circuit 3, the synchronization pattern detection circuit 4, the two-dimensional Viterbi decoding circuit 5, the decoded bit row output circuit 6, and the decoded bit register 7 included in the hologram memory reproduction system 20 are assumed. The waveform level setting circuit 8, the block boundary determination circuit 9, and the modulation rule determination circuit 10 constitute a Viterbi decoding device 21.

(Assumed response matrix)
Next, a predetermined two-dimensional impulse response matrix PR in the hologram memory reproducing apparatus 1 will be described with reference to FIG. FIG. 5 is a diagram schematically showing a predetermined two-dimensional impulse response matrix PR in the hologram memory reproducing apparatus 1.

  For example, the two-dimensional Viterbi decoding circuit 5 operates assuming the two-dimensional impulse response matrix PR shown in FIG. 5 as the partial response characteristics. Therefore, the two-dimensional impulse response matrix PR is referred to as an assumed response matrix PR. Here, from the viewpoint of optical theory, it is appropriate to define the assumed response matrix PR by the amplitude of light. The partial response characteristic is used to calculate the ideal path metric difference and is expressed as a two-dimensional impulse response.

  For the sake of simplicity of explanation, the assumed response matrix PR will be described for the case where the bit width of inter-pixel interference is “3”, but is not limited to this. For example, the assumed response matrix PR may be assumed to be close to the response characteristics of the hologram memory reproducing device 1.

  The trellis diagram expressing the operation of the two-dimensional Viterbi decoding circuit 5 is basically the same as the trellis diagram described in FIG.

  Since the bit width of the inter-pixel interference of the assumed response matrix PR is 3 and the decision feedback Viterbi decoding method is applied, the trellis state is defined as a 2 × 2 matrix (one of the decoding target rows) The top row can use a feedback row, so the row width is 3-1, ie 2). Since the matrix defining the trellis state is 2 rows and 2 columns (ie, a total of 4 bits), the number of trellis states is “2 to the 4th power”, that is, 16 ways. There are four branches.

  However, as will be described later, in the two-dimensional Viterbi decoding circuit 5, a predetermined trellis transition is prohibited (removed) according to the outputs of the block boundary determination circuit 9 and the modulation rule determination circuit 10.

(Assumed waveform level)
Next, referring to FIG. 6, as an example of the assumed waveform level of the branch (assumed signal value assumed for the transition of the trellis state), four input to the trellis state [1, 0; 0, 1] The assumed waveform level for each branch will be described. FIG. 6 is a diagram illustrating an assumed waveform level for four branches input to the trellis state [1, 0; 0, 1] as an example of an assumed waveform level of the branch.

  The assumed waveform level shown in FIG. 6 is an assumed waveform level when the feedback row corresponding to the branch is [1, 1, 0]. The assumed waveform level is obtained as follows.

  First, the bit matrix determined by the branch corresponding to the transition from the trellis state [1, 1; 0, 0] to [1, 0; 0, 1] is combined with the feedback row [1, 1, 0]. 1, 1, 0; 1, 1, 0; 0, 0, 1].

  Next, as shown in FIG. 7, a two-dimensional convolution operation between the bit matrix and the assumed response matrix PR is performed. FIG. 7 is a diagram illustrating an expression for performing a two-dimensional convolution operation for obtaining an assumed waveform level. The value “7” at the center of the matrix obtained as a result of the calculation is an assumed value corresponding to the light amplitude assumed in the transition of the trellis state.

  Since the signal detected by the CCD or CMOS sensor is a signal corresponding to the light intensity, considering the relationship between the light amplitude and the intensity, that is, the square of the amplitude is the intensity, A value “49” obtained by squaring the obtained value “7” corresponds to the light intensity.

  Therefore, if this value “49” is used as the assumed waveform level, a more accurate assumed waveform level can be set.

  The assumed waveform levels of all branches can be obtained in the same manner as described above. That is, assuming that the feedback row is [f1, f2, f3], an assumed waveform of a branch corresponding to a transition from [p, q; s, t] to [q, r; t, u] in the trellis state. The level w is obtained as a value obtained by squaring the value of the center of the matrix obtained by the two-dimensional convolution operation of [f1, f2, f3; p, q, r; s, t, u] and the assumed response matrix PR. Can do.

  As can be seen from the above description, the assumed waveform level of the branch varies depending on the value of the feedback line. Therefore, the assumed waveform level setting circuit 8 calculates the assumed waveform level w of each branch based on the feedback row [f1, f2, f3].

  The assumed waveform level setting circuit 8 may be configured to perform the calculation as shown in the above example every time according to the feedback row [f1, f2, f3] output from the decoding bit register 7, A configuration may be employed in which an assumed waveform level calculated in advance is stored in a memory such as a lookup table, and a corresponding value is read from the memory according to a feedback row.

  When the branch corresponding to the transition from [p, q; s, t] to [q, r; t, u] in the trellis state survives, 2 bits [q; t] are determined as decoded bits. The However, only the bit q in the first row that is Viterbi-decoded with all waveform interference from the top, bottom, left and right taken into account is output from the decoded bit row output circuit 6 as a decoded bit.

(Flow of playback operation)
Next, the flow of the reproduction operation by the hologram memory reproduction system 20 will be described with reference to FIG. FIG. 8 is a flowchart showing the flow of the reproducing operation by the hologram memory reproducing system 20.

  First, the hologram memory reproducing apparatus 1 applies reflected light or transmitted light (coherent light) generated by irradiating a reproduction reference light to a hologram medium on which information is recorded as interference fringes, and passes a plurality of pixels through a lens. Light is received by a light receiving element (for example, a CCD or CMOS sensor) and a two-dimensional reproduction waveform signal is output. Then, the output two-dimensional reproduced waveform signal is stored in the buffer memory 2 (step S1). Here, it is assumed that page data 50 of 102 × 102 bits is recorded on the hologram medium as described with reference to FIG.

  Next, the synchronization pattern detection circuit 4 detects the synchronization pattern 51 from the signal obtained by waveform equalization with respect to the reproduced waveform signal read from the buffer memory 2 by the two-dimensional waveform equalization circuit 3, and the detected synchronization pattern 51 The pixel position is determined based on the bit position in the page data 50, the row position i is set to “1”, and the column position j is set to “1” (step S2).

  Next, Viterbi decoding in the row direction is started from the first column (step S3). That is, the two-dimensional waveform equalization circuit 3 reads the reproduction waveform signal corresponding to the i-th row and j-th column from the buffer memory 2 and reproduces the reproduction waveform signal x obtained by performing two-dimensional waveform equalization on the reproduction waveform signal. Is input to the two-dimensional Viterbi decoding circuit 5 (step S4).

  Note that the two-dimensional waveform equalization circuit 3 performs a two-dimensional waveform equalization process so that the reproduced waveform signal approaches the response matrix PR described with reference to FIG. 5. By this process, the reproduced waveform signal is directly subjected to Viterbi decoding. It is possible to realize decoding with a lower error rate than that of the configuration. Therefore, it is desirable that the two-dimensional waveform equalization circuit 3 is provided in the hologram memory reproduction system 20 from the viewpoint of reducing the error rate, but the two-dimensional waveform equalization circuit 3 is omitted from the viewpoint of suppressing an increase in circuit scale. It is good also as a structure.

Next, the two-dimensional Viterbi decoding circuit 5 executes two-dimensional Viterbi decoding in the row direction based on the trellis diagram. That is, the sum (x−w) ² of the square error between the input reproduction waveform signal x of the recording bit in the i-th row and j-th column and the assumed waveform level w corresponding thereto is obtained as a branch metric. Further, the surviving path is determined based on the branch metric accumulated until reaching each trellis state, that is, the path metric (step S5).

  Here, in step S5, when the decoding target row i is an odd row, the transition of the trellis state to be prohibited (removed) in the trellis diagram is determined by the block boundary determination circuit 9 and the modulation rule determination circuit 10. . Details of this determination process will be described later.

  Next, when the path memory length of the two-dimensional Viterbi decoding circuit 5 is L, whether or not the j-th column that is the current decoding target exceeds the L-th column (that is, the value of j is greater than the value of L Or whether the value of j is equal to or less than the value of L) (step S6). When the j-th column exceeds the L-th column (that is, the value of j is larger than the value of L) (YES in step S6), the decoded bit row output circuit 6 makes the (j− L) Of the two rows [b1; b2] in the trellis state of the column, only the bit b1 in the first row is extracted and output as a decoded bit row (step S7).

  This decoded bit row is the decoded result itself, but is also stored in the decoded bit register 7 at the same time (step S8).

  Note that if the j-th column does not exceed the L-th column (that is, the value of j is equal to or less than the value of L) (NO in step S6), the processes in steps S7 and S8 are not performed.

  Next, the target column is shifted by one column (step S9), and it is determined whether or not the target column after the shift exceeds the (100 + L) th column (that is, whether (100 + L) column decoding has been completed). (Step S10). The above (100 + L) is a value obtained by adding “L”, which is a path memory length, to “100”, which is the number of columns of page data.

  If the target column after the shift exceeds the (100 + L) column (NO in step S10), the target row is shifted by one row (step S11), and the target row after the shift is the page data It is determined whether or not 100 rows that are rows (that is, whether or not decoding for 100 rows has been completed) (step S12).

  On the other hand, when the shifted target column does not exceed the (100 + L) column (YES in step S10), the processes in steps S4 to S9 are repeated.

  In step S12, if the number of target lines after the shift exceeds 100 lines, which are page data lines (NO in step S12), the process ends.

  On the other hand, in step S12, when the shifted target row does not exceed 100 rows that are page data rows (YES in step S12), the processing from steps S3 to S11 is repeated. At this time, since the decoded bit row on the first row is stored in the decoded bit register 7, this is used as the feedback row for Viterbi decoding of the next row.

  With the above operation, a decoding result bit map is finally obtained as page data.

(Removal of trellis transition)
Next, the operation in which the two-dimensional Viterbi decoding circuit 5 prohibits (removes) a predetermined trellis transition according to the outputs of the block boundary determination circuit 9 and the modulation rule determination circuit 10 in step S5 will be described in detail below. .

  The page data 50 is encoded with a 2: 4 code, and forms a modulation block at 2 × 2, that is, every four pixels. Therefore, when the decoding target row i is an odd row, the trellis state and the modulation block have the same boundary in the column direction.

  Here, an example of determining whether or not the entire modulation block matches any of the 2: 4 code patterns will be described with reference to FIG. FIG. 9 shows a bit pattern representing a transition from the trellis state [p, q; s, t] at column position j to the trellis state [q, r; t, u] at column position (j + 1) in the trellis diagram. FIG.

  As shown in FIG. 9, in the trellis diagram, a bit represents a transition from a trellis state [p, q; s, t] at column position j to a trellis state [q, r; t, u] at column position (j + 1). The pattern is [p, q, r; s, t, u].

  Based on the bit position of the synchronization pattern 51 detected by the synchronization pattern detection circuit 4 and the position of the decoding target bit (that is, the decoding target row i and the decoding target column j), When it is determined that the modulation block [p, q; s, t] illustrated in FIG. 2 is included, the modulation rule determination circuit 10 sets the modulation block [p, q; s, t] as a pattern of 2: 4 code. It is determined whether or not it matches any of the four types of existing patterns.

  Here, as described in FIG. 17, the pattern of 2: 4 code is [1, 0; 0, 0], [0, 1; 0, 0], [0, 0; 1, 0] and There are four types [0, 0; 0, 1].

  Therefore, for example, when the value of the modulation block [p, q; s, t] is [0, 0; 0, 1], it is determined that the pattern matches one of the patterns of 2: 4 code. On the other hand, when the value of the modulation block [p, q; s, t] is [1, 0; 0, 1], it is determined that it does not match any of the 2: 4 code patterns.

  Similarly, a bit pattern representing a transition from the trellis state [q, r; t, u] at the column position (j + 1) to the trellis state [r, v; u, z] at the column position (j + 2) will be described. When the block boundary determination circuit 9 determines that the bit pattern includes a modulation block [r, v; u, z] illustrated by a dotted line, the modulation rule determination circuit 10 determines the modulation block [r, v; u, z, It is determined whether or not z] matches any one of the four types of patterns that exist as the 2: 4 code pattern.

  As described above, when the modulation rule determination circuit 10 determines that the entire modulation block does not match any of the 2: 4 code patterns, the two-dimensional Viterbi decoding circuit 5 prohibits the corresponding trellis transition. That is, the corresponding branch in the trellis diagram is removed.

  The trellis diagram after the branch is removed as described above will be described with reference to FIG. FIG. 10 is a trellis diagram after the branch is removed as described above. When the trellis diagram shown in FIG. 10 is compared with the trellis diagram (FIG. 4) before the branch is removed, a large number of branches are removed. Therefore, after removing a branch as described above, the probability of selecting an error path is greatly reduced.

  Further, as can be seen from the above description, the prohibited (removed) transition varies depending on the positional relationship between the bit pattern representing the trellis state transition and the modulation block. In the present embodiment, the block boundary determination circuit 9 determines that the bit pattern representing the trellis state transition includes the entire two-dimensional modulation block, and the modulation rule determination circuit 10 determines that the block including the bit pattern When it is determined that the pattern does not match any of the two-dimensional modulation patterns, the transition is prohibited (removed) and the result is sent to the two-dimensional Viterbi decoding circuit 5. With this configuration, even if a transition that is prohibited (removed) changes according to the positional relationship between the trellis diagram and the boundary of the modulation block, the result is reflected in the Viterbi decoding process performed by the two-dimensional Viterbi decoding circuit 5. Is possible.

  In addition, it is good also as a structure which performs Viterbi decoding in this embodiment irrespective of whether decoding object line i is an odd number line or an even number line. At this time, when the decoding target row i is an odd row, the entire two-dimensional modulation block is included in the bit pattern representing the trellis state, and as a result, trellis transition can be reduced. However, the decoding target row i is an even row. In this case, since the whole two-dimensional modulation block is not included in the bit pattern representing the trellis state, trellis transition is not reduced.

When the decoding target row i is an odd row, Viterbi decoding is executed according to the configuration in the present embodiment. When the decoding target row i is an even row, Viterbi decoding is performed according to the configuration in Embodiment 2 described later. It is good also as a structure which performs.
[Embodiment 2]
In the first embodiment, when the decoding target row i is an odd row, the entire two-dimensional modulation block is included in the bit pattern representing the trellis state, and as a result, trellis transitions can be reduced. As a result, the probability of selecting an error path can be reduced.

  However, when the decoding target row i is an even row, the entire two-dimensional modulation block is not included in the bit pattern representing the trellis state. Therefore, when the decoding target row i is an even row, the trellis transition is not reduced, and the above-described effect cannot be obtained.

  Therefore, in the present embodiment, a mode in which trellis transition can be reduced regardless of whether the decoding target row i is an odd row or an even row is described.

  An embodiment of the present invention will be described with reference to FIGS. 11 to 14 as follows. For convenience of explanation, members having the same functions as those shown in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  A hologram memory reproduction system 30 including the Viterbi decoding device 31 according to the present embodiment will be described with reference to FIG. FIG. 11 is a block diagram showing a configuration of a hologram memory reproduction system 30 including the Viterbi decoding device 31 according to the present embodiment.

  As shown in FIG. 11, the hologram memory reproduction system 30 includes substantially the same members as the hologram memory reproduction system 20 according to the first embodiment. However, the two-dimensional Viterbi decoding circuit 5 is used instead of the two-dimensional Viterbi decoding circuit 5. A decoding circuit 5A (Viterbi decoding means) is provided. Further, instead of the block boundary determination circuit 9, a block boundary determination circuit 9A (block boundary determination means) is provided. Further, in place of the modulation rule determination circuit 10, a modulation rule determination circuit 10A (two-dimensional modulation pattern detection means) is provided.

  In addition, the hologram memory reproduction system 30 is different from the hologram memory reproduction system 20 in that 1) the feedback row as the output of the decoding bit register 7 is input to the block boundary determination circuit 9A and the modulation rule determination circuit 10A. 2) The two-dimensional Viterbi decoding circuit 5A receives the input from the modulation rule determining circuit 10A and removes a predetermined trellis transition from the surviving path.

  The two-dimensional waveform equalization circuit 3, the synchronization pattern detection circuit 4, the two-dimensional Viterbi decoding circuit 5A, the decoded bit row output circuit 6, the decoded bit register 7, the assumed waveform level setting circuit 8, the block boundary determination circuit 9A, and the modulation The law determination circuit 10 </ b> A constitutes the Viterbi decoding device 31.

(Removal of trellis transition)
Next, the operation of the two-dimensional Viterbi decoding circuit 5A prohibiting (removing) a predetermined trellis transition based on the outputs of the block boundary determination circuit 9A and the modulation rule determination circuit 10A will be described in detail.

  A reproduction operation by the hologram memory reproduction system 30 will be described with reference to FIG. As shown in FIG. 12, the transition from the trellis state [p, q; s, t] at column position j to the trellis state [q, r; t, u] at column position (j + 1) and the corresponding feedback row [ A bit pattern obtained by combining d, e, f] will be described as an example. FIG. 12 shows the transition from the trellis state [p, q; s, t] at column position j to the trellis state [q, r; t, u] at column position (j + 1) and the corresponding feedback row [d, e. , F] and a bit pattern obtained by combining them.

  When the block boundary determination circuit 9A determines that the bit pattern obtained by the above combination includes the modulation block [d, e; p, q] illustrated by the dotted line, the modulation rule determination circuit 10A determines the modulation block [d , E; p, q] determines whether or not any of the four types of patterns existing as 2: 4 code patterns matches.

  Similarly, the transition from the trellis state [q, r; t, u] at column position (j + 1) to the trellis state [r, v; u, z] at column position (j + 2), and the corresponding feedback row [e, A bit pattern obtained by combining f, g] will be described. When the block boundary determination circuit 9A determines that the bit pattern obtained by the combination includes the modulation block [f, g; r, v] illustrated by the dotted line, the modulation rule determination circuit 10A determines the modulation block [f , G; r, v] is determined to match any one of the four types of patterns existing as 2: 4 code patterns.

  As described above, when the modulation rule determination circuit 10A determines that the entire modulation block does not match any of the 2: 4 code patterns, the two-dimensional Viterbi decoding circuit 5A prohibits the corresponding trellis transition. That is, the corresponding branch in the trellis diagram is removed.

  A trellis diagram after the branch is removed as described above will be described with reference to FIG. FIG. 13 is a trellis diagram after the branch is removed as described above. When the trellis diagram shown in FIG. 13 is compared with the trellis diagram (FIG. 4) before the branch is removed, many branches are removed. As a result, the probability of selecting an error path is greatly reduced.

  Further, as can be seen from the above description, not only the positional relationship between the bit pattern representing the transition of the trellis state and the modulation block 52 but also the feedback row that is the output of the decoding bit register 7 is prohibited (removed). Changes. Therefore, in the present embodiment, the block boundary determination circuit 9A determines that the bit pattern obtained by combining the feedback row and each transition of the trellis state includes the entire two-dimensional modulation block, and the modulation rule determination circuit When 10A determines that the block including the bit pattern does not match any of the two-dimensional modulation patterns, the transition is prohibited (removed) and the result is sent to the two-dimensional Viterbi decoding circuit 5A. With this configuration, even if a transition that is prohibited (removed) changes regardless of the position of the decoding target row, the result can be reflected in the Viterbi decoding process performed by the two-dimensional Viterbi decoding circuit 5.

  In the present embodiment, when the decoding target row i is an odd row (particularly when the decoding target row i is the first row), the configuration described in the first embodiment (that is, a configuration not using a feedback row). ) To perform Viterbi decoding processing.

(simulation result)
Next, with reference to FIG. 14, in order to confirm the effect of this embodiment, an experimental result in which the relationship between the reproduced signal quality and the bit error rate of the decoding result is evaluated by simulation will be described. FIG. 14 is a diagram showing a graph of experimental results in which the relationship between the reproduced signal quality and the bit error rate of the decoding result is evaluated by simulation.

  First, page data was created by applying 6: 8 modulation to the information data using randomly generated bit sequences of 0 and 1 as information data. Here, “6: 8 modulation” is a modulation method for converting 6-bit information data into a modulation block of 4 × 2, ie, 8 pixels, and 8 pixels in each modulation block are “1” and “0”. The ratio is 50% (that is, four each). A modulation method having such a characteristic that the ratio of “1” to “0” is 50% is called a balance code.

  Next, a pseudo reproduction signal is generated for the created page data using a model that simulates the reproduction characteristics of the hologram memory, and white Gaussian noise is applied to the pseudo reproduction signal as an input signal.

  The horizontal axis of the graph shown in FIG. 14 represents the S / N ratio of the reproduction signal, and the vertical axis represents the bit error rate of the decoding result. As shown in FIG. 14, in this embodiment, when compared with the difference detection method, it can be confirmed that a lower bit error rate is obtained with the same signal quality.

As described above, by performing Viterbi decoding that prohibits (removes) trellis transitions based on the characteristics of the modulation scheme as in the present embodiment, the probability of erroneous transitions is reduced, and decoding with a low error rate is performed. The effect that can be realized can be obtained.
[Embodiment 3]
In Embodiment 2, the bit pattern obtained by combining the feedback row and the matrix representing each transition of the trellis state includes the entire two-dimensional modulation block, and the block included in the bit pattern includes the two-dimensional modulation block. A configuration has been described in which a predetermined trellis transition is prohibited (removed) when none of the patterns matches. In this configuration, the modulation rule determination circuit 10A determines for each trellis state whether or not the entire two-dimensional modulation block included in the bit pattern matches any one of the two-dimensional modulation patterns.

  However, when the modulation method is determined to be a predetermined method such as 2: 4 code, it is not determined every time whether or not the entire two-dimensional modulation block included in the bit pattern matches one of the two-dimensional modulation patterns. However, based on the current row position and column position of the decoding target bit, each transition of the trellis state to be prohibited (removed) can be uniquely determined in advance. Therefore, the Viterbi decoding process can be performed in consideration of the trellis transition that is prohibited (removed) based on the current row position and column position of the decoding target bit.

  Therefore, in the present embodiment, a description will be given of a mode in which the Viterbi decoding process is performed in consideration of the trellis transition that is prohibited (removed) based on the current row position and column position of the decoding target bit and the feedback row. . This eliminates the configuration of determining the match between the two-dimensional modulation block and the two-dimensional modulation pattern, so that the determination by the modulation rule determination circuit 10A in the second embodiment is unnecessary.

  An embodiment of the present invention will be described with reference to FIG. For convenience of explanation, members having the same functions as those shown in the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted.

  A hologram memory reproduction system 40 including the Viterbi decoding device 41 according to the present embodiment will be described with reference to FIG. FIG. 15 is a block diagram showing a configuration of a hologram memory reproduction system 40 including the Viterbi decoding device 41 according to the present embodiment.

  As shown in FIG. 15, the hologram memory reproduction system 40 is configured to include substantially the same members as the hologram memory reproduction system 30 according to the second embodiment. However, the two-dimensional Viterbi decoding circuit 5A is used instead of the two-dimensional Viterbi decoding circuit 5A. A decoding circuit 5B (Viterbi decoding means) and a bit position pointer 14 are provided. The block boundary determination circuit 9A and the modulation rule determination circuit 10A are not provided.

  In addition, the hologram memory reproduction system 40 is different from the hologram memory reproduction system 30 in that 1) the feedback row that is the output of the decoding bit register 7 is input to the two-dimensional Viterbi decoding circuit 5B. And 2) The contents of the trellis transition prohibiting process by the two-dimensional Viterbi decoding circuit 5B.

  In the hologram memory reproduction system 40, the two-dimensional waveform equalization circuit 3, the synchronization pattern detection circuit 4, the two-dimensional Viterbi decoding circuit 5B, the decoded bit row output circuit 6, the decoded bit register 7, the assumed waveform level setting circuit 8, The bit position pointer 14 constitutes a Viterbi decoding device 41.

  The bit position pointer 14 indicates a bit position in the page data 50 of the reproduction signal output from the buffer memory 2 to the Viterbi decoding device 41 (that is, a row position and a column position in the page data 50 of the current decoding target bit). Is output.

  The bit position pointer 14 determines the row position and the column position of the decoding target bit based on the bit position in the page data 50 of the synchronization pattern 51 detected by the synchronization pattern detection circuit 4. Thereby, the position in the page data 50 of a decoding object bit can be output correctly.

  The two-dimensional Viterbi decoding circuit 5B performs Viterbi decoding processing based only on the row position and column position of the decoding target bit output from the bit position pointer 14 and the feedback row output from the decoding bit register 7. Here, since the modulation scheme of the page data 50 is known to be a predetermined 2: 4 code, the above feedback row is combined with a matrix representing a trellis state transition in which the specific row position and column position are the upper left corner. It can be determined in advance that the bit pattern obtained in this way does not include any of the 2: 4 code patterns. Therefore, the two-dimensional Viterbi decoding circuit 5B can be configured such that the transition of the trellis state is prohibited (removed) from the beginning in accordance with a specific row position and column position, and a feedback row.

  As described above, in the present embodiment, the prohibited transition of the trellis diagram that changes according to the bit position in the page data 50 is reflected in the Viterbi decoding with a simple circuit configuration compared to the first or second embodiment. Is possible.

  In the present embodiment, it is determined which trellis transitions are prohibited (removed) based on the feedback row and the row position and column position of the current decoding target bit. Based on only the row position and the column position of the decoding target bit, it is determined in advance which trellis transition is prohibited (removed), and the trellis transition to be removed is reflected in the Viterbi decoding circuit 5B from the beginning. Also good.

  Note that, for example, when the modulation method of the page data 50 is not determined to be a predetermined method, such as a reproducing apparatus corresponding to a plurality of different hologram memory standards, the configuration in which the determination is performed every time as in the first or second embodiment is suitable. In that case, the modulation rule used by the modulation rule determination circuit 10 of the first embodiment or the modulation rule determination circuit 10A of the second embodiment may be switched in accordance with the hologram memory standard to be reproduced.

(Additional notes)
Moreover, in the hologram memory reproduction system in each embodiment of the present invention, the Viterbi decoding method is used in which the two-dimensional Viterbi decoding is performed in the row direction and the entire two-dimensional reproduction signal is decoded by repeating this in the column direction. It is not limited to this. That is, a Viterbi decoding method may be used in which two-dimensional Viterbi decoding is performed in the column direction and this is repeated in the row direction to decode the entire two-dimensional reproduction signal.

  Further, the relationship between “upper” and “lower” and the relationship between “left” and “right” described in each embodiment of the present invention is not limited to this. That is, a configuration in which the upper and lower sides and the left and right sides are interchanged may be used.

  In addition, since the present invention imposes a restriction that prohibits the transition of Viterbi decoding, the effect can be obtained as long as Viterbi decoding is performed on a reproduction signal of page data modulated by a specific modulation method. Thus, it does not depend on the size of the trellis state matrix (that is, the number of rows and the number of columns), the modulation scheme, the number of feedback rows used for decision feedback, and the like.

  In addition to the above, the embodiment can be expressed as follows.

  [1] A Viterbi decoding apparatus according to the present invention is a Viterbi decoding apparatus that performs Viterbi decoding of a two-dimensionally reproduced page data that has been two-dimensionally modulated. Viterbi decoding means for performing Viterbi decoding on the error of the two-dimensional reproduction signal with respect to an assumed signal value assumed in the transition as a metric of the transition based on the transition, and the Viterbi decoding means represents each transition of the trellis state When the bit pattern does not exist as a two-dimensional modulation pattern, the transition may be prohibited.

  [2] Furthermore, the Viterbi decoding apparatus according to the present invention includes a block boundary determination unit that determines whether or not a bit pattern represented by each transition of a trellis state includes a block boundary of two-dimensional modulation, and the block boundary determination unit includes A modulation rule determining unit that determines whether or not the block boundary included in the bit pattern is a pattern that exists as a two-dimensional modulation pattern when it is determined that the block boundary is included, and the Viterbi decoding unit includes: When the modulation rule determining means determines that the block boundary included in the bit pattern does not exist as a two-dimensional modulation pattern, the transition may be prohibited.

  [3] Furthermore, the Viterbi decoding device according to the present invention includes a decoded bit output means for outputting a decoded bit row corresponding to a decoding target row as a decoding result among paths surviving as a result of the Viterbi decoding, and the decoded bit output Decoding bit storage means for storing the decoded bit row output by the means, wherein the block boundary determining means is a bit pattern represented by the decoded bit row stored by the decoded bit storage means and each transition of the trellis state. It may be determined whether or not includes a block boundary of two-dimensional modulation.

  [4] Further, in the Viterbi decoding apparatus according to the present invention, the page data includes a synchronization pattern for determining a block boundary of two-dimensional modulation, and detects the synchronization pattern from the two-dimensional reproduction signal. Synchronization block detection means for determining the block boundary based on the synchronization pattern detected by the synchronization pattern detection means.

  [5] Furthermore, the Viterbi decoding apparatus according to the present invention provides a reproduction signal position for outputting a row position and a column position of the two-dimensional reproduction signal, which is a target for calculating an error of trellis state transition in the Viterbi decoding means. The Viterbi decoding unit may further include an output unit, and the Viterbi decoding unit prohibits a predetermined transition determined according to the row position and the column position output by the reproduction signal position output unit.

  [6] Furthermore, the Viterbi decoding device according to the present invention includes a decoded bit output means for outputting a decoded bit row corresponding to a decoding target row among the paths surviving as a result of the Viterbi decoding, and the decoded bit output Decoding bit storage means for storing the decoded bit row output by the means, the Viterbi decoding means for decoding the row position and column position output by the reproduction signal position output means, and the decoding bit storage means A predetermined transition determined according to the bit row may be prohibited.

  [7] Further, in the Viterbi decoding apparatus according to the present invention, the page data includes a synchronization pattern for determining a two-dimensional modulation block boundary, and detects the synchronization pattern from the two-dimensional reproduction signal. And a reproduction signal position output means for specifying the output row position and column position based on the synchronization pattern detected by the synchronization pattern detection means. .

  [8] Further, in the Viterbi decoding apparatus according to the present invention, the synchronization pattern may be a pattern configured such that a plurality of bright pixels are adjacent to each other.

  [9] Further, in the Viterbi decoding apparatus according to the present invention, the two-dimensional modulation may be a constant weight encoding method.

  [10] The Viterbi decoding process according to the present invention is a Viterbi decoding method for Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data, wherein a trellis state relating to a plurality of lines including a decoding target line in the two-dimensional reproduction signal is Based on the transition, a Viterbi decoding process for Viterbi decoding the error of the two-dimensional reproduction signal with respect to an assumed signal value assumed in the transition as a metric of the transition is provided, and the Viterbi decoding process represents each transition of the trellis state When the bit pattern does not exist as a two-dimensional modulation pattern, the transition may be prohibited.

  Finally, each block of the hologram memory reproducing systems 20, 30 and 40 described in the first to third embodiments may be realized by software using a CPU (Central Processing Unit) or may be configured by hardware logic. Also good.

  When implemented by software, the Viterbi decoding device 21, the Viterbi decoding device 31, and the Viterbi decoding device 41 include a CPU that executes instructions of a control program that implements each function, a ROM (read only memory) that stores the program, A RAM (random access memory) for expanding the program, a storage device (recording medium) such as a memory for storing the program and various data, and the like are provided. The object of the present invention is the program code (execution format program, intermediate code program, source program) of the control program of the Viterbi decoding device 21, the Viterbi decoding device 31, and the Viterbi decoding device 41, which is software that implements the functions described above. Is supplied to the Viterbi decoding device 21, Viterbi decoding device 31, and Viterbi decoding device 41, and the computer (or CPU or MPU (Micro Processing Unit)) is recorded on the recording medium. This can also be achieved by reading and executing the program code.

  Examples of the recording medium include a tape system such as a magnetic tape and a cassette tape, a magnetic disk such as a floppy (registered trademark) disk / hard disk, and an optical disk such as a CD-ROM / MO / MD / DVD / CD-R. Card system such as IC card, IC card (including memory card) / optical card, or semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  In addition, the Viterbi decoding device 21, the Viterbi decoding device 31, and the Viterbi decoding device 41 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Also, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a computer data signal embedded in a carrier wave in which the program code is embodied by electronic transmission.

  Thus, in this specification, the means does not necessarily mean physical means, but includes cases where the functions of the means are realized by software. Further, the function of one means may be realized by two or more physical means, or the functions of two or more means may be realized by one physical means.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be applied to a decoding apparatus that enables decoding with a low error rate with respect to a two-dimensional signal, and is represented by a hologram memory reproducing apparatus that reproduces a two-dimensional signal, and a QR code. It can be suitably used for a two-dimensional bar code reproducing apparatus.

It is a block diagram which shows the structure of the hologram memory reproduction system containing the Viterbi decoding apparatus which concerns on embodiment of this invention. It is a figure which shows typically the format of the page data currently recorded on the hologram medium in the hologram memory reproduction | regeneration system shown in FIG. It is a figure which shows the impulse response of the interference between pixels in the decision feedback Viterbi decoding method. It is a trellis diagram in the decision feedback Viterbi decoding method. It is the figure which showed typically the predetermined | prescribed response matrix in the hologram memory reproduction | regeneration system shown in FIG. It is a figure which shows the assumed waveform level about four branches input into the trellis state [1, 0; 0, 1] in the hologram memory reproduction system shown in FIG. It is a figure which shows the type | formula which performs the two-dimensional convolution operation for calculating | requiring the assumed waveform level shown in FIG. 2 is a flowchart showing a flow of a reproducing operation by the hologram memory reproducing system shown in FIG. FIG. 7 is a diagram showing a bit pattern represented by a transition from a trellis state [p, q; s, t] at a column position j to a trellis state [q, r; t, u] at a column position (j + 1) in a trellis diagram. is there. FIG. 3 is a trellis diagram after a branch is removed by the hologram memory reproducing system shown in FIG. 1. It is a block diagram which shows the structure of the hologram memory reproduction system containing the Viterbi decoding apparatus which concerns on other embodiment of this invention. The transition from the trellis state [p, q; s, t] at column position j to the trellis state [q, r; t, u] at column position (j + 1) and the feedback row [d, e, f] It is a figure which shows the bit pattern performed. FIG. 12 is a trellis diagram after the branch is removed by the hologram memory reproducing system shown in FIG. 11. It is a figure which shows the graph of the experimental result which evaluated the relationship between reproduction signal quality and the bit error rate of a decoding result by simulation by the hologram memory reproduction system shown in FIG. It is a block diagram which shows the structure of the hologram memory reproduction system containing the Viterbi decoding apparatus which concerns on other embodiment of this invention. It is a figure which shows typically the outline | summary of the conventional hologram memory system. It is a figure explaining 2: 4 code | symbol which is one of the conventional constant weight codes | symbols.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Hologram memory reproducing device 2 Buffer memory 3 Two-dimensional waveform equalization circuit 4 Synchronization pattern detection circuit (synchronization pattern detection means)
5, 5A, 5B 2D Viterbi decoding circuit (Viterbi decoding means)
6 Decoded bit row output circuit (decoded bit output means)
7 Decoding bit register 8 Assumed waveform level setting circuit 9, 9A Block boundary determination circuit (block boundary determination means)
10, 10A modulation rule determination circuit (two-dimensional modulation pattern detection means)
14-bit position pointer 20, 30, 40 Hologram memory reproduction system 21, 31, 41 Viterbi decoding device 50 Page data 51 Synchronization pattern 52 Modulation block

Claims (13)

A Viterbi decoding device for Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data,
Based on the transition of the trellis state for a plurality of rows including the decoding target row in the two-dimensional reproduction signal, a path metric is obtained using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition. Viterbi decoding means for performing Viterbi decoding by calculating,
The Viterbi decoding means removes the trellis state transition and performs Viterbi decoding based on the bit pattern representing the transition of the trellis state for the plurality of rows including the decoding target row and the pattern of the two-dimensional modulation. A Viterbi decoding device characterized by the above. Block boundary determination means for determining whether or not a bit pattern representing a transition of a trellis state for a plurality of rows including the decoding target row includes an entire block of two-dimensional modulation;
Two-dimensional modulation pattern detection means for determining that the entire two-dimensional modulation block does not match any of the two-dimensional modulation patterns;
The block boundary determining means determines that the bit pattern representing the transition of the trellis state includes the entire block of the two-dimensional modulation; and
If the two-dimensional modulation pattern detecting means determines that the entire two-dimensional modulation block does not match any of the two-dimensional modulation patterns, the Viterbi decoding means removes the transition and performs Viterbi decoding. The Viterbi decoding device according to claim 1, characterized in that:   Based on the modulation method of the two-dimensional modulation and the row position and the column position of the decoding target bit in the page data, a bit pattern representing a trellis state transition for a plurality of rows including the decoding target row is the two-dimensional 2. The Viterbi decoding apparatus according to claim 1, wherein when it is known in advance that no modulation pattern exists, the Viterbi decoding means performs Viterbi decoding by removing the transition in advance. A Viterbi decoding device for Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data,
Based on the transition of the trellis state for a plurality of rows including the decoding target row in the two-dimensional reproduction signal, a path metric is obtained using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition. Viterbi decoding means for performing Viterbi decoding by calculating,
Decoding bit output means for outputting a decoded bit obtained as a result of Viterbi decoding the row immediately preceding the decoding target row by the Viterbi decoding means,
The Viterbi decoding means is based on a bit pattern obtained by combining a row consisting of the decoded bits with a matrix representing a trellis state transition for a plurality of rows including the decoding target row, and the two-dimensional modulation pattern. Then, a Viterbi decoding apparatus characterized in that the trellis state transition is removed and Viterbi decoding is performed. It is determined whether or not the bit pattern obtained by combining the row of the decoded bits with the matrix representing the transition of the trellis state for the plurality of rows including the decoding target row includes the entire two-dimensional modulation block. Block boundary judging means;
Two-dimensional modulation pattern detection means for determining that the entire two-dimensional modulation block does not match any of the two-dimensional modulation patterns;
The block boundary determining means determines that the bit pattern obtained by the combination includes the entire block of the two-dimensional modulation; and
If the two-dimensional modulation pattern detecting means determines that the entire two-dimensional modulation block does not match any of the two-dimensional modulation patterns, the Viterbi decoding means removes the transition and performs Viterbi decoding. The Viterbi decoding device according to claim 4, characterized in that:   Based on the modulation method of the two-dimensional modulation, the row position and the column position of the decoding target bit in the page data, and the decoding bit, a matrix representing the transition of the trellis state for a plurality of rows including the decoding target row, The Viterbi decoding means performs Viterbi decoding by removing the transition in advance when it is known in advance that the bit pattern obtained by combining the rows of the decoded bits does not include the two-dimensional modulation pattern. The Viterbi decoding device according to claim 4. The page data contains a sync pattern,
A synchronization pattern detecting means for detecting the synchronization pattern from the two-dimensional reproduction signal;
The block boundary determination means recognizes the position of the bit pattern based on the size of the block of two-dimensional modulation and the bit position in the page data of the synchronization pattern detected by the synchronization pattern detection means. 6. The Viterbi decoding apparatus according to claim 2, wherein it is determined whether or not the entire two-dimensional modulation block is included. The page data contains a sync pattern,
A synchronization pattern detecting means for detecting the synchronization pattern from the two-dimensional reproduction signal;
7. The Viterbi decoding apparatus according to claim 3, wherein a row position and a column position of the decoding target bit are determined based on a bit position in the page data of the synchronization pattern detected by the synchronization pattern detection means.   9. The synchronization pattern according to claim 7 or 8, wherein in the page data, any one of binary values is adjacently arranged in a row direction or a column direction so as to be identifiable. Viterbi decoding device. A Viterbi decoding method for Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data,
Based on the transition of the trellis state for a plurality of rows including the decoding target row in the two-dimensional reproduction signal, a path metric is obtained using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition. Including a Viterbi decoding step of calculating Viterbi decoding,
A Viterbi decoding method, wherein in the Viterbi decoding step, Viterbi decoding is performed by removing the trellis state transition based on the bit pattern representing the trellis state transition and the two-dimensional modulation pattern. A Viterbi decoding method for Viterbi decoding a two-dimensional reproduction signal of two-dimensionally modulated page data,
Based on the transition of the trellis state for a plurality of rows including the decoding target row in the two-dimensional reproduction signal, a path metric is obtained using an error of the two-dimensional reproduction signal with respect to an assumed signal value assumed for the transition as a branch metric of the transition. A Viterbi decoding step of performing Viterbi decoding by calculating,
A decoded bit output step of outputting a decoded bit obtained as a result of Viterbi decoding the row immediately preceding the decoding target row by the Viterbi decoding step,
In the Viterbi decoding step, a bit pattern obtained by combining a row composed of the decoded bits with a matrix representing a trellis state transition for a plurality of rows including the decoding target row, and a two-dimensional modulation pattern A Viterbi decoding method characterized in that, based on the trellis state transition, the Viterbi decoding is performed.   A program for operating the Viterbi decoding device according to any one of claims 1 to 9, wherein the program causes a computer to function as each of the above means.   A computer-readable recording medium on which the program according to claim 12 is recorded.

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