JP2009047749A - Image processing circuit, display device, and printer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To restrict deterioration of image quality generated when arranging, in juxtaposition, figure images on an image region including intermediate gradation. <P>SOLUTION: A memory H stores hatching pattern data. A multiplier MUO multiplies a pixel value included in input image data including an intermediate gradation value and a pixel value of each position of the hatching pattern data of the memory H at every corresponding position respectively. A subtractor SU outputs a pixel value subtracting a pixel value of each position included in input image data from the maximum pixel value. A multiplier MU1 multiplies a pixel value of each position of background color information expressing background color of images based on input image data, and a pixel value output from the subtractor SU at every corresponding position respectively. An adder AD adds a multiplied result of the multiplier MU0 and a multiplied result of the multiplier MU1 at every corresponding position respectively to be output as output image data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for arranging a plurality of graphic images side by side in an image area.

In the field of image processing, a technique called hatching processing is known. The hatching processing is processing that performs so-called shading or patterning by regularly arranging a plurality of graphic images in an image area such as a character, a table, or a graphic. For example, Patent Document 1 discloses a technique for rapidly developing a hatching pattern in a frame memory using a BiTBLT (bit boundary, block transfer) circuit that repeatedly transfers a block pattern for hatching drawing within a specified area. ing.
JP 05-210381 A

  By the way, as one of image processing techniques, an image smoothing technique called anti-aliasing is widely known. For example, when this anti-aliasing process is performed on an image in which a character represented by white and black pixels is drawn, the outline of the character can be supplemented with a gray color of intermediate gradation. As a result, it is possible to make the stepped jaggedness called jaggy generated in the contour portion drawn obliquely into a smooth curve.

  In some cases, the above-described hatching processing is further performed on the image subjected to such anti-aliasing processing. For example, assuming that the hatching process is performed on an input image including such an intermediate gradation by the technique described in Patent Document 1, the intermediate gradation part is regarded as a non-drawing area and the hatching process is performed. Either the process is not performed, or the process is regarded as a drawing area and the hatching process is performed. As a result, the intermediate gradation portion of the input image is unnaturally raised, which causes a problem that the image quality deteriorates.

In this way, in particular, when the area where the contour portion of the image is an intermediate gradation is hatched, such as a character image subjected to anti-aliasing processing, the contour of the image is not drawn neatly, and the image There is a problem that the beauty and visibility of the product are impaired.
The present invention has been made in view of such a background, and an object of the present invention is to provide a mechanism for suppressing deterioration in image quality that occurs when a graphic image is arranged in an image area including an intermediate gradation. is there.

In order to solve the above problems, the present invention provides a storage means for storing the positions and pixel values of pixels constituting a plurality of graphic images arranged side by side, and a pixel at each position stored in the storage means. A first multiplying unit that multiplies the input image data by a corresponding value for each position, and a pixel value included in the input image data in which the pixel value at each position is represented in multiple values including 0. Subtraction value output means for outputting a pixel value obtained by subtracting the pixel value at each position included from the maximum pixel value in the input image data, and an image based on the pixel value at each position included in the input image data or the input image data Second multiplying means for multiplying the pixel value of each position included in the background image data as the background of the image and the pixel value output from the subtraction value output means for each corresponding position, and the first Multiplication means And multiplication result, a multiplication result of the second multiplication means, respectively added to each corresponding said position, provides an image processing circuit, characterized by an adding means for outputting as output image data.
As a result, it is possible to suppress deterioration in image quality that occurs when graphic images are arranged side by side in an image area including an intermediate gradation.

In a preferred aspect of the present invention, the storage means includes first storage means for storing the position of each pixel constituting the plurality of graphic images, and color information representing the color of the graphic image. Second storage means for storing the pixel value of each pixel constituting the pixel, and the color information stored in the second storage means for the pixel at each position stored in the first storage means You may provide the color information output means output as a value.
Thereby, it is possible to arrange the graphic images of the colors based on the color information stored in the second storage unit side by side with respect to the image area including the intermediate gradation.

In a preferred aspect of the present invention, the second storage unit stores a plurality of types of color information, and the color information output unit stores each pixel constituting the same type of graphic image among the plurality of graphic images. Alternatively, any one of a plurality of types of color information stored in the second storage unit may be output.
As a result, graphic images of the same type and color based on the same color information can be arranged side by side in the image area including the intermediate gradation.

In a preferred aspect of the present invention, either a pixel value at each position included in the input image data or a pixel value at each position included in background image data representing the background of the image of the input image data is designated. You may provide a designation | designated means and a supply means which supplies the pixel value designated by the said designation | designated means to a said 2nd multiplication means.
As a result, the output image data represents either the pixel value at each position included in the input image data or the pixel value at each position included in the background image data representing the background of the image of the input image data. Can be specified as the pixel value of the background area.

In a preferred aspect of the present invention, either the third storage means for storing predetermined background color information or the fourth storage means for storing image information output to the display means or printing means is designated. And a supply unit that reads information stored in the storage unit designated by the designation unit as a pixel value included in the background image data and supplies the pixel value to the second multiplication unit. Good.
Thus, the output image data is stored in either the third storage unit that stores predetermined background color information or the fourth storage unit in which the image information output to the display unit or the printing unit is expanded. It can be designated as the storage means of the supply source of the pixel value of the background area in the output image to be represented.

According to another aspect of the present invention, there is provided a display device comprising: the image processing circuit according to any one of the above; and display means for displaying an image based on output image data output from the adding means. .
As a result, it is possible to suppress deterioration in image quality that occurs when graphic images are arranged and arranged in an image area including an intermediate gradation, and it is possible to display an image obtained as a result.

According to another aspect of the present invention, there is provided a printing apparatus comprising: the image processing circuit according to any one of the above; and a printing unit that performs printing based on output image data output from the adding unit.
As a result, it is possible to suppress degradation in image quality that occurs when graphic images are arranged and arranged in an image area including an intermediate gradation, and it is possible to print the resulting image.

[Embodiment]
In the embodiment described below, the process of arranging a plurality of graphic images side by side in a certain image area is referred to as “hatching”. The plurality of graphic images arranged at this time may all be the same graphic image, may be similar graphic images, or may be different graphic images. For example, it is possible to perform hatching called “hatching” by repeatedly arranging line segment images all extending in the same direction at equal intervals. Further, hatching called “shading” can be performed by repeatedly arranging line segment images extending in two directions at equal intervals. Furthermore, there are hatching in which heart-shaped and clover-shaped graphics are alternately arranged, and hatching in which abstract graphics having different shapes are arranged at random are also conceivable. That is, the size, shape, or number of graphic images used for hatching may be anything.

FIG. 1 is a diagram illustrating a configuration of an image display device 1 according to the present embodiment.
As shown in FIG. 1, an image display device 1 includes a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a VRAM (Video Random Access Memory) 14, Memory liquid crystal display 15, display control device 16, power supply 17, power supply control device 18, connector 19, storage control device 20, I / O 21, key 22, storage device 23, and image processing Circuit 25. The CPU 11 reads out a control program stored in the ROM 12, develops it in the RAM 13, and executes processing according to the procedure described in the control program. The key 22 is an operation means operated by the user, and includes an operation device such as a pen device or a joystick. The I / O 21 monitors the operation state of the key 22 and supplies a signal corresponding to the operation to the CPU 11 when the user operates the key 22. The power source 17 is, for example, a rechargeable battery, and the power source control device 18 performs various types of power source management such as on / off control of the power source 17 and power remaining amount monitoring.

  A portable external storage device 24 such as a removable medium is detachable from the connector 19. The external storage device 24 may be a card-type storage medium with a built-in flash memory such as an SD (Secure Digital) card, or a disk-type storage medium using a magnetic medium such as a flexible disk. Also good. The storage device 23 is a nonvolatile storage medium such as a flash memory or a hard disk, and is built in the image display device 1. The storage device 23 or the external storage device 24 stores image data representing images such as text (characters), graphics (graphics), or images (photographic images). This image data is binary data composed of a pixel value “0” representing white and a pixel value “1” representing black. The area where the pixel value “1” is arranged is an image drawing area, and the area where the pixel value “0” is arranged is a non-drawing area (background area). The storage control device 20 reads image data from the storage device 23 or the external storage device 24 in accordance with an instruction from the CPU 11 and supplies it to the image processing circuit 25.

  The image processing circuit 25 includes an anti-aliasing circuit 255 and a hatching circuit 250. The anti-aliasing circuit 255 performs an unaliasing process on the image data supplied in accordance with an instruction from the CPU 11. More specifically, the anti-aliasing circuit 255 averages the pixel values of a plurality of pixels included in the supplied image data, for example, a total of 16 pixels in the vertical direction 4 × the horizontal direction 4 to obtain one pixel. A value is calculated, and multi-valued image data including the calculated pixel value is generated. The image data generated in this way includes intermediate grayscale pixel values representing a gray color. For example, when this anti-aliasing processing is performed on image data representing a character represented by white and black pixels, the outline of the character is supplemented with a gray color of intermediate gradation. The hatching circuit 250 performs hatching on the image data supplied in accordance with an instruction from the CPU 11 and outputs the hatched image data to the VRAM 14. The VRAM 14 is a frame buffer and stores image data for one page displayed on the storage liquid crystal display 15. The memory liquid crystal display 15 is a display means using cholesteric liquid crystal, electrophoresis, or the like, and has a memory property that an image can be continuously displayed even when power supply is stopped. The image data stored in the VRAM 14 is supplied to the display control device 16 under the instruction of the CPU 11. The display control device 16 controls the memory liquid crystal display 15 to display an image based on the supplied image data.

Next, FIG. 2 is a diagram illustrating a configuration of the hatching circuit 250.
As shown in the figure, the hatching circuit 250 includes a memory H, hatching color registers R0 and R1, a background color register R2, a selector S, multipliers MU0 and MU1, a subtractor SU, and an adder AD. It has. The hatching circuit 250 includes a multi-value including intermediate gradation values obtained by the antialiasing circuit 255 performing antialiasing processing on binary image data read from the storage device 23 or the external storage device 24, for example. Value image data is input as input image data. The pixel values included in the input image data are expressed by “0” to “1” in the pixel values indicating the pixels with the lowest density to the pixels with the highest density. In the following description, the pixel value included in the input image data is referred to as “α”.

  Here, when the multi-valued image data output from the anti-aliasing circuit 255 is represented by pixel values “0” to “1”, the pixel value of the multi-valued image data is the pixel of the input image data as it is. The value “α” is input to the hatching circuit 250. Here, the pixel value “α” = “0” represents white (lowest density), the pixel value “α” = “1” represents black (highest density), and “α” satisfying 0 <α <1. , Represents gray. On the other hand, when the multi-value image data output from the anti-aliasing circuit 255 is represented by pixel values composed of integers (for example, “0” to “15”) larger than “0” to “1”, many It is necessary to convert the pixel value of the value image data into a value that falls within the range of “0” to “1”, and then input it to the hatching circuit 250 as the pixel value “α” of the input image data.

  A method for converting the pixel value of the multi-valued image data into the pixel value “α” of the input image data will be described. The conversion of the input image data into the pixel value “α” is performed by dividing each pixel value included in the multi-value image data by the maximum pixel value in the multi-value image data. For example, when the multi-value image data is expressed by 16 gradations “0” to “15” (“0” represents white and “15” represents black), “ The pixel value “0” is converted to “α” of 0 ÷ 15 = “0” obtained by dividing the pixel value “0” by the maximum pixel value of 15. Further, the pixel value “15” included in the input image data is converted into “α” of 15 ÷ 15 = “1” obtained by dividing the pixel value “15” by 15 of the maximum pixel value. Similarly, the pixel value “10” of the intermediate gradation value included in the input image data is obtained by dividing the pixel value “10” by 15 of the maximum pixel value 10 ÷ 15≈ “0.67” “α Is converted to.

  Then, the result of the hatching process performed by the hatching circuit 250 on the input image data is output as output image data. The memory H stores the position of each pixel constituting a hatching pattern (that is, a plurality of graphic images) used when performing the hatching process as hatching pattern data.

Here, FIG. 3 is a diagram schematically showing hatching pattern data for performing lattice pattern hatching.
The hatching pattern data is obtained by expressing a plurality of graphic images with binary bit values of “0” or “1”. In the figure, the pattern bit value “0” is arranged at the position of each pixel constituting the white grid, and the pattern bit value “1” is arranged at the position of each pixel constituting the black grid. The size of the entire hatching pattern is the same as the size of an image for one page secured in the VRAM 14. Each grid is composed of a plurality of pixels (for example, 16 × 16 = 256 pixels), but for the sake of simplicity of explanation, it is assumed that one grid is composed of one pixel. To do. In this case, the horizontal length of the entire hatching pattern is a length corresponding to the number of horizontal pixels M for one page of the image in the VRAM 14. The vertical length of the entire hatching pattern is a length corresponding to the vertical pixel count N for one page of the image in the VRAM 14.

  In the following description, the position coordinate of the pixel located at the upper left corner in the hatching pattern data is (0, 0), and the pixel at the position advanced i pixels downward and j pixels rightward from the pixel is the position coordinate. Let (i, j) be the pixel. Therefore, for example, a pixel at a position advanced one pixel in the right direction from a pixel at a position coordinate (0, 0) is a pixel at a position coordinate (0, 1), and a pixel at a position advanced two pixels is The pixel at the position coordinate (0, 2), and the pixel at the position advanced by 3 pixels is the pixel at the position coordinate (0, 3). Further, the pixel at the position advanced by one pixel from the pixel at the position coordinate (0, 0) is the pixel at the position coordinate (1, 0), and the pixel at the position advanced by two pixels is the position coordinate ( 2,0) pixels. Such a method of expressing the position coordinates is not limited to the hatching pattern shown in FIG. 3, but input image data (FIG. 4 to be described later) input to the hatching circuit 250 and output image data output from the hatching circuit 250. The same applies to (FIG. 8 described later).

Returning to the description of FIG.
The hatching color register R0 stores color information indicating the color of the pixel at the position of the pattern bit value “0” in the hatching pattern data. Here, for example, color information “C0” representing blue is stored. The hatching color register R1 stores color information representing the color of the pixel located at the pattern bit value “1” in the hatching pattern. Here, for example, color information “C1” representing yellow is stored. This color information originally includes information specifying the color itself and its gradation value. However, in the present embodiment, only two values are assumed as the gradation value of the color information indicating whether or not the color represented by the color information is present. Therefore, the color information “C0” alone is “blue”. At the same time, it means that the color is “present”. The color information “C1” means “yellow” and at the same time means that the color is “present”.

  The selector S receives color information “C0” stored in the hatching color register R0 and color information “C1” stored in the hatching color register R1 as input signals. Further, the selector S is sequentially input with each pattern bit value included in the hatching pattern data stored in the memory H as a selection signal in the order of the pixel position coordinates described above. The selector S selects and outputs the color information “C0” during the period in which the pattern bit value “0” is input as the selection signal, and the period in which the pattern bit value “1” is input as the selection signal. The color information “C1” is selected and output.

  The memory H described above functions as a first storage unit that stores the position of each pixel constituting the hatching pattern. The hatching color registers R0 and R1 function as second storage means for storing color information representing the color of the hatching pattern as pixel values of each pixel constituting the hatching pattern. The selector S functions as color information output means for outputting the color information stored in the hatching color registers R0 and R1 as the pixel value of the pixel at each position stored in the memory H. Eventually, the memory H, the hatching color registers R0 and R1, and the selector S cooperate to function as storage means for storing the position and pixel value of each pixel constituting the hatching pattern.

  The multiplier MU0 is a first multiplying unit that corresponds to the color information “C0” or “C1” output from the selector S and the pixel value “α” at each position included in the input image data. Multiply every pixel position and output. This “corresponding position” means that the position coordinates of the pixels shown in FIG. 3 are the same. That is, the multiplier MU0 receives “C0” or “C1” and “α” and outputs “α × C0” or “α × C1”.

  A pixel value “α” at each position included in the input image data and a value “1” are input to the subtractor SU, and “1-α” is obtained by subtracting “α” from the value “1”. Is output as “β”. Thereby, when “α” = “1”, the pixel value “1” is subtracted from the pixel value “1”, which is the maximum pixel value in the input image data, and the pixel value 1-1 = “0” is subtracted. Is output by the unit SU. When “α” = “0”, the pixel value “0” is subtracted from the pixel value “1”, which is the maximum pixel value in the input image data, and the pixel value 1-0 = “1”. It will be output by SU. Similarly, when “α” ≈ “0.67”, the pixel value “0.67” is subtracted from “1”, which is the maximum pixel value in the input image data, and 1−0.67 = “ A pixel value of “0.33” is output by the subtractor SU. That is, the subtractor SU functions as a subtraction value output unit that outputs a value obtained by subtracting the pixel value at each position included in the input image data from the maximum pixel value in the input image data. In this way, when the pixel value included in the input image data represents a high density, the subtracter SU outputs a pixel value representing a light density, and when representing a light density, A pixel value representing a dark density is output.

  The background color register R2 is a color that represents the color of a non-rendering area (that is, a background area that is the background of the image based on the input image data) when the image represented by the input image data is displayed on the storage liquid crystal display 15. Stores information. This color information represents, for example, white. The image processing circuit 25 is configured such that the image represented by the input image data is superimposed and drawn on a background area of a predetermined color. For this reason, the background color register R2 stores the color information of the background area. Hereinafter, the color information of the background area is referred to as “background color information”.

  The multiplier MU1 is a second multiplying unit that multiplies “β” output from the subtractor SU and background color information supplied from the background color register R2 for each corresponding pixel position and outputs the result. . That is, “β × background color information” is output as color information from the multiplier MU1.

  The adder AD adds “α × C0” or “α × C1” output from the multiplier MU0 and “β × background color information” output from the multiplier MU1 for each corresponding pixel position. The result of the addition is output as output image data. That is, the color information of each pixel included in the output image data is either the color information “α × C0 + β × background color information” or the color information “α × C1 + β × background color information” from the adder AD. Is output as

Next, the operation of the hatching circuit 250 will be specifically described.
FIG. 4 is a diagram illustrating an image representing the letter “N” as an example of an image represented by input image data input to the hatching circuit 250. Similar to the hatching pattern shown in FIG. 3, this image is composed of M pixels in the horizontal direction and N pixels in the vertical direction. The pixel value “α” of each pixel is “0” in the white portion in the drawing, “1” in the black portion, and “0.67” in the gray intermediate gradation portion. Regions with pixel values “α” of “1” and “0.67” are drawing regions where a character image “N” is drawn, and regions with pixel value “α” of “0” are character images. It is a non-drawing area that is not drawn. In the following description, an operation when such input image data is input to the hatching circuit 250 is illustrated.

First, operations of the selector S and the multiplier MU0 will be described with reference to FIG.
The pixel value “α” at each position included in the input image data shown in FIG. 4 is input to the hatching circuit 250 in the order of the position coordinates. For example, since the pixel value “α” of the pixel at the position coordinate (0, 0) of the input image data is “0”, the value “0” is input. Next, since the pixel value “α” of the pixel at the position coordinate (0, 1) of the input image data is also “0”, the value “0” is input. Similarly, the pixel value “α of the uppermost line of the input image data shown in FIG. 4, such as position coordinates (0, 2), (0, 3)... (0, M−1). Are sequentially input to the hatching circuit 250. When all the pixel values of one line are inputted to the hatching circuit 250, the position coordinates (1, 0), (1, 1), (1, 2),. The pixel value “α” of the pixel (1, M−1) is sequentially input to the hatching circuit 250. Here, the pixel values of the pixels of the position coordinates (1, 0), (1, 1), (1, 2), (1, 3) are “0”, “1”, “1”, “ 0.67 ". FIG. 5 illustrates a state in which these pixel values are input in order.

  In parallel with this input operation, the selector S receives the color information “C0” read from the hatching color register R0 and the color information “C1” read from the hatching color register R1 as input signals. Then, hatching pattern data read from the memory H is supplied as a selection signal. The selector S selects and outputs the color information “C0” during the period in which “0” is input as the selection signal, and selects the color information “C1” during the period in which “1” is input as the selection signal. Output. For example, when hatching pattern data as shown in FIG. 3 is stored in the memory H, the pattern bit value is “0” for the pixel at the position coordinate (1, 0) in the hatching pattern data. Output the color information “C0”. Subsequently, since the pattern bit value is “1” for the pixel at the position coordinate (1, 1) in the hatching pattern data, the selector S outputs the color information “C1”. Similarly, for the pixel at the position coordinate (1, 2) in the hatching pattern data, since the pattern bit value is “0”, the color information “C0” is output and the position coordinate (1, 3) in the hatching pattern data is output. For the pixel), since the pattern bit value is “1”, color information “C1” is output. The output color information is sequentially supplied to the multiplier MU0.

  The multiplier MU0 multiplies the pixel value “α” at each position included in the input image data by the color information “C0” or “C1” supplied from the selector S for each corresponding pixel position. “× C0” or “α × C1” is output. For example, for the pixel at the position coordinate (1, 0), since “α” is “0” and the color information is “C0”, a value of 0 × C0 = “0” is output. Subsequently, since “α” is “1” and the color information is “C1” for the pixel at the position coordinate (1, 1), 1 × C1 = “C1”, that is, the color supplied from the selector S. The information “C1” is output as it is. Similarly, for the pixel at the position coordinate (1, 2), since “α” is “1”, the color information “C0” supplied from the selector S is output. For the pixel at the position coordinate (1, 3), since “α” supplied from the selector S is “0.67” and the color information is “C1”, “0.67 × C1” is obtained. Color information representing a color obtained by multiplying the density of the color represented by the color information “C1” supplied from the selector S by 0.67 is output. As described above, as a result of multiplication by the multiplier MU0, a value of “0” is output for a pixel whose pixel value “α” of the input image data is “0”, that is, a pixel in a non-rendering region where a character image is not rendered. Is done. On the other hand, the pixel having the pixel value “α” of the input image data “1”, that is, the pixel having the highest density among the pixels in the region where the character image is drawn, has the pattern bit value at the corresponding position in the hatching pattern data. The color information is output as it is. In addition, a pixel whose pixel value “α” of the input image data is an intermediate gradation value such as “0.67”, that is, a pixel having a density other than the highest density among pixels in a region where a character image is drawn is hatched. Color information representing a color obtained by multiplying the color density represented by the color information of the pattern bit value at the corresponding position in the pattern data by the density represented by the pixel value “α” of the input image data is output. The “α × C0” or “α × C1” output from the multiplier MU0, that is, “α × hatching pattern color information” is supplied to the adder AD.

Next, operations of the subtractor SU and the multiplier MU1 will be described with reference to FIG.
The pixel value “α” at each position of the input image data is supplied to the subtracter SU in addition to the multiplier MU0 described above. The subtracter SU receives this “α” and “1”, and outputs “1-α” obtained by subtracting “α” from “1” as “β”. For example, for the pixel at the position coordinate (1, 0), since α is “0”, a value of 1-0 = “1” is output as “β”. Subsequently, for the pixel at the position coordinate (1, 1), since α is “1”, a value of 1-1 = “0” is output as “β”. Similarly, for the pixel at position coordinates (1, 2), since α is “1”, a value of 1-1 = “0” is output as “β”. For the pixel (1, 3), since α is “0.67”, a value of 1−0.67 = “0.33” is output as “β”. “Β” output from the subtractor Su is supplied to the multiplier MU1.

  The multiplier MU1 is supplied with “β” from the subtracter SU and background color information from the background color register R2. The multiplier MU1 outputs “β × background color information” obtained by multiplying the “β” and the background color information for each corresponding pixel position. That is, for the pixel whose pixel value “α” of the input image data is “0”, that is, the pixel in the non-rendering area where the character image is not drawn, “β” becomes “1”. Color information is output as is. On the other hand, for the pixel having the pixel value “α” of the input image data “1”, that is, the pixel of the highest density among the pixels in the drawing area of the character image, “β” is “0”. Will output a value of “0”. In addition, regarding a pixel having a pixel value “α” of the input image data having an intermediate gradation value such as “0.67”, that is, a pixel having a density other than the highest density among pixels in a region where a character image is drawn, “ β ”is a pixel value obtained by subtracting the pixel value“ α ”of the input image data from the maximum pixel value, and the multiplier MU1 multiplies the color density represented by the background color information by the density represented by the pixel value“ β ”. Color information representing the selected color is output. For example, for the pixel at the position coordinate (1, 0), β supplied from the subtractor SU is “1”, so the background color information supplied from the background color register R2 is output as it is. Subsequently, for the pixels at the position coordinates (1, 1) and (1, 2), since β supplied from the subtracter SU is “0”, a value of “0” is output. For the pixel at the position coordinate (1, 3), since β supplied from the subtracter SU is “0.33”, a value “0.33 × background color information” is output. The “β × background color information” output from the multiplier MU1 is supplied to the adder AD.

Subsequently, the operation of the adder AD will be described with reference to FIG.
The adder AD adds “α × hatching pattern color information” supplied from the multiplier MU 0 and “β × background color information” supplied from the multiplier MU 1 for each corresponding pixel position. The value of “× hatching pattern color information + β × background color information” is output. For example, for the pixel at the position coordinate (1, 0), the value of “α × hatching pattern color information” supplied from the multiplier MU0 is “0”, and “β × background color” supplied from the multiplier MU1. Since the value of “information” is “background color information”, “background color information” is output. Subsequently, for the pixel at the position coordinate (1, 1), the value of “α × hatching pattern color information” supplied from the multiplier MU0 is “C1”, and “β × supplied from the multiplier MU1. Since the value of “background color information” is “0”, the color information “C1” of the hatching pattern is output. Similarly, for the pixel at the position coordinate (1, 2), the value of “α × hatching pattern color information” is “C0”, and the value of “β × background color information” is “0”. The hatch pattern color information “C0” is output. For the pixel at the position coordinate (1, 3), the value of “α × hatching pattern color information” is “0.67 × C1”, and the value of “β × background color information” is “0.33”. Since “× background color information”, “0.67 × C1 + 0.33 × background color information” is output. This represents a color obtained by combining the color obtained by multiplying the yellow density indicated by the hatch pattern color information “C1” by 0.67 and the color obtained by multiplying the white density indicated by the background color information by 0.33.

  That is, in the adder AD, the color information of the pixels in the drawing area in the input image as shown in FIG. 4 is replaced with the color information of the hatching pattern, while the color information of the pixels in the non-drawing area is changed to the background color information. These are replaced and output as output image data. Furthermore, the color information of the pixels of the intermediate gradation among the pixels of the drawing area in the input image is replaced with color information obtained by combining the color information of the hatching pattern and the background color information according to the density of the pixel. The output image data output from the adder AD is temporarily stored in the VRAM 14, then interpreted by the display control device 16 and displayed as an image on the storage liquid crystal display 15.

Here, FIG. 8 is a diagram showing an output image displayed on the memory-type liquid crystal display 15 based on the output image data.
As shown in the figure, this output image is similar to the input image data shown in FIG. 4, the drawing area where the character image representing the character “N” is drawn, and the non-drawing where the character image is not drawn. And is composed of areas. However, the drawing area of the character image has a blue and yellow lattice pattern corresponding to the hatching pattern shown in FIG. 3, and the non-drawing area of the character image is not hatched, and the background color information The white background image represented by. Further, in the halftone portion in which the pixel value is the middle tone value in the image area of the character image, the blue or yellow image corresponding to the hatching pattern and the white background image represented by the background color information are intermediate between them. The synthesized image is synthesized according to the density of each pixel in the gradation portion. For example, the color of the pixel at the position coordinate (1, 0) is white as the background color, the color of the pixel at the position coordinate (1, 1) is yellow represented by the color information “C1” of the hatching pattern, The color of the pixel at the coordinates (1, 2) is blue represented by the color information “C0” of the hatching pattern. The color of the pixel at the position coordinates (1, 3) is a color obtained by combining 67% of yellow represented by the color information “C1” of the hatching pattern and 33% of white of the background color, that is, hatching adapted to the background color. The color of the pattern.

  According to the embodiment described above, even if the processing for arranging the graphic images side by side is performed on the image area of the input image including the intermediate gradation, the intermediate gradation portion is not unnaturally raised. be able to. That is, it is possible to suppress the image quality deterioration associated with the hatching process. In addition, only by using a circuit with a relatively simple configuration including a register, a selector, a multiplier, an adder, and a subtracter, it is possible to perform hatching only on a drawing area such as a character in an input image, and an area to be hatched This eliminates the need to specify each position coordinate or memory address. Further, the desired color can be hatched by simply storing the desired color in the hatching color registers R0 and R1.

[Modification]
The above is the description of the embodiment, but the contents of this embodiment can be modified as follows. Further, the following modifications may be combined as appropriate.
(1) In the embodiment described above, hatching pattern data representing the lattice hatching pattern shown in FIG. 3 is stored in the memory H, and input image data representing the character “N” shown in FIG. 4 is input. Although the details of the hatching have been described with reference to the example, the hatching that can be performed by the hatching circuit 250 is not limited to the above example. The hatching circuit 250 can perform various hatching according to the contents of the input image and the hatching pattern by changing the contents.

(2) In the above-described embodiment, only the binary value indicating whether or not there is a color represented by the color information is assumed as the gradation value of the color information. Therefore, the color information C0 and C1 of the hatching pattern is the color information. At the same time, it meant that the color was “present”. However, when the memory liquid crystal display 15 can display the same color with three or more gradations, this color information includes information specifying the color itself and its gradation value. .

(3) In the above-described embodiment, the subtractor SU outputs subtractor SU that outputs “β” that is a value obtained by subtracting the pixel value at each position included in the input image data from the maximum pixel value in the input image data. This subtraction value output means may be realized by another configuration. In short, as long as such a value is output as “β”, this subtraction value output means may be realized by another configuration.
For example, the pixel value “α” of the multi-valued input image data is used as a selection signal. When the selection signal “0” is input, the input signal “1” is selected and output, and the selection signal “1” is input. And the input signal “0” is selected and output, and when the selection signal “0.67” is input, the input signal “0.33” is selected and output. A selector that converts the pixel value of the position into a value “β” obtained by subtracting the pixel value from the maximum pixel value in the input image data and outputs the value may be used.

(4) In the above-described embodiment, the hatching circuit 250 uses, as input image data, multivalued image data obtained by performing anti-aliasing processing on binary image data read from the storage device 23 or the external storage device 24. The case where it inputs to is illustrated.
The multivalued image data to be hatched is not limited to image data that has been multivalued through anti-aliasing. For example, the multi-value image data to be hatched may be multi-value image data originally represented by pixel values including an intermediate gradation. In this case, the anti-aliasing circuit 255 is not necessary.
For example, it is assumed that multi-valued image data representing a halftone rectangular figure is input to the hatching circuit 250 without being subjected to the unaliasing process. In this case, the graphic drawing area in the multi-value image data image is synthesized by the hatching circuit 250 in accordance with the density of the pixel value in the drawing area and the image corresponding to the hatching pattern and the background image represented by the background color information. It will be replaced with the synthesized image. In other words, the drawing area of the figure becomes an image that appears to be translucent because the image corresponding to the hatching pattern has melted into the background image. A hatching circuit 250 may be used as a circuit for realizing such processing.

(5) In the above-described embodiment, the pixel value “α” of the input image data converted from the multi-value image data is input to the hatching circuit 250, but with 16 gradations from “0” to “15”. The expressed multi-value image data may be input to the hatching circuit 250 as it is. In this case, a conversion circuit that converts the gradation value of the multi-value data into the gradation value “α” of the input image data expressed by gradation values “0” to “1” is provided as a multiplier MU0. And the pixel value “α” converted by the conversion circuit may be supplied to the multiplier MU0 and the subtractor SU.
Further, when such a conversion circuit is not provided, when the multiplier MU0 multiplies a value other than “0” by the hatching pattern color information, if the multiplication is performed as it is, the hatching pattern color information becomes an integer. Will be doubled. Therefore, the color information of the hatching pattern may be multiplied by “1 / integer value” in advance.

(6) The area other than the hatching target area is basically a background area. As image data for displaying this background area, background color information stored in the background color register R2 as in the above-described embodiment is used. Alternatively, input image data input to the hatching circuit may be used. In the latter case, the multiplier MU1 may have a circuit configuration in which input image data is supplied instead of the background color information read from the background color register R2. Thereby, the color of the background area in the output image can be made the same as the color of the background area in the input image.

Alternatively, either the background color information stored in the background color register R2 or the input image data input to the hatching circuit may be designated.
FIG. 9 is a diagram showing the hatching circuit 251 in this case. The hatching circuit 251 is further provided with a background color designation register R3 and a selector S0. The other configuration is the same as that of the hatching circuit 250 shown in FIG. The background color designation register R3 stores a selection signal for designating either the pixel value “α” at each position of the input image data or the background color information stored in the background color register R2. That is, the background color designation register R3 functions as designation means for designating either the pixel value at each position included in the input image data or the pixel value at each position included in the background color information. The selection signal stored in the background color designation register R3 may be rewritten by the CPU 11 based on the user's key 22 operation. The selector S0 receives the input image data pixel value “α” and background color information stored in the background color register R2. The selector S0 receives a selection signal stored in the background color designation register R3. The selector S0 selects and outputs the pixel value “α” of the input image data when a selection signal (“0” in this case) designating the pixel value “α” at each position of the input image data is input. On the other hand, when a selection signal (here, “1”) designating background color information stored in the background color register R2 is input, the background color information is selected and output. That is, the selector S0 functions as a supply unit that supplies the pixel value designated by the background color designation register R3 to the multiplier MU1 that is the second multiplication unit. Thereby, either the color of the non-drawing area or the background color in the input image can be designated as the color of the background area in the output image.

(7) In the above-described embodiment, the image data stored in the VRAM 14 is displayed on the memory-type liquid crystal display 15 by the display control device 16. On the other hand, image data that has been subjected to hatching processing may be used for printing. For example, the output image data output from the adder AD may be written in the RAM 13 and the output image data may be supplied to the printing unit as image data corresponding to an image to be printed on one sheet of paper. The printing unit performs printing based on the supplied image data, and forms an image represented by the image data on a sheet.

(8) In the embodiment described above, the background color information stored in the background color register R2 is supplied to the multiplier MU1 as it is. However, in addition to the background color register R2, the background color information is stored in the VRAM 14. In such a case, any background color information may be selected and supplied to the multiplier MU1.
FIG. 10 is a diagram showing a configuration of a hatching circuit 252 according to this modification. The hatching circuit 252 is further provided with a background color designation register R4 and a selector S1. The other configuration is the same as that of the hatching circuit 250 shown in FIG. The background color designation register R4 stores a selection signal for designating either the first background color information stored in the background color register R2 or the second background color information stored in the VRAM 14. ing. That is, the background color designation register R4 is either the background color register R2 that stores predetermined first background color information or the VRAM 14 that develops image information output to the storage liquid crystal display 15. It functions as a designation means for designating. The selection signal stored in the background color designation register R4 may be rewritten by the CPU 11 based on the user's key 22 operation. The selector S1 receives the first background color information stored in the background color register R2 and the second background color information stored in the VRAM 14 as input signals. The selector S1 receives a selection signal stored in the background color designation register R4. The selector S1 selects and outputs the first background color information read from the background color register R2 when a selection signal (here, “0”) designating the background color register R2 is input. On the other hand, when a selection signal (in this case, “1”) designating the VRAM 14 is input, the second background color information read from the VRAM 14 is selected and output. That is, the selector S1 reads out the storage means designated by the background color designation register R4, that is, the information stored in the background color register R2 or the VRAM 14 as the pixel value included in the background color information, and the second multiplication means. Functions as supply means for supplying to the multiplier MU1.
Further, when an image is output (displayed or printed) by the display means or the printing means, the image information of the output image is expanded in a storage means such as the RAM 13 and once stored in the RAM 13, the display means or the printing means. Supplied to. The image information of the output image stored in the RAM 13 may be used as background color information in the above embodiment. In this case, the background color designation register R4 functions as designation means for designating either the background color register R2 that stores predetermined first background color information or the RAM 13 that stores image information of an output image. To do. Then, the selector S1 reads the storage means designated by the background color designation register R4, that is, the background color information or the image information stored in the background color register R2 or the RAM 13 as the pixel value of the background color information in the above embodiment. , Functions as supply means for supplying to the multiplier MU1 as the second multiplication means. Thereby, the storage means such as the RAM 13 can be selected as the supply source of the background color information.

(9) In the embodiment described above, the hatching circuit 250 is provided in the image processing circuit 25. On the other hand, the hatching circuit 250 may be provided in another device such as the display control device 16.

(10) The hatching circuit 250 described above may be used in a personal computer device, a mobile phone, an electronic book, or the like having a display device that displays an image according to image data.

1 is a diagram illustrating a configuration of an image display device 1. FIG. 2 is a diagram illustrating a configuration of a hatching circuit 250. FIG. It is a figure which shows the hatching pattern data for performing the hatching of a lattice pattern. It is a figure which shows an example of the image which input image data represents. It is a figure explaining operation | movement of selector S and multiplier MU0. It is a figure explaining operation | movement of the subtractor SU and multiplier MU1. It is a figure explaining operation | movement of the adder AD. It is a figure which shows the output image displayed on the memory | storage liquid crystal display body. It is a figure which shows the structure of the hatching circuit 251 which concerns on a modification. It is a figure which shows the structure of the hatching circuit 252 which concerns on a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Image display apparatus, 11 ... CPU, 12 ... ROM, 13 ... RAM, 14 ... VRAM, 15 ... Memory | storage liquid crystal display body, 16 ... Display control apparatus, 17 ... Power supply, 18 ... Power supply control apparatus, 19 ... Connector, DESCRIPTION OF SYMBOLS 20 ... Storage control device, 21 ... I / O, 22 ... Key, 23 ... Storage device, 24 ... External storage device, 25 ... Image processing circuit, 250, 251, 252 ... Hatching circuit, H ... Memory, R0, R1 ... hatching color register, S, S0, S1 ... selector, MU0, MU1 ... multiplier, SU ... subtractor, AD ... adder, R2 ... background color register, R3, R4 ... background color designation register.

Claims (7)

Storage means for storing the position of each pixel constituting a plurality of graphic images arranged side by side and the pixel value thereof;
The pixel value at each position stored in the storage means is multiplied by the pixel value included in the input image data in which the pixel value at each position is represented by multiple values including 0 for each corresponding position. 1 multiplication means;
Subtraction value output means for outputting a pixel value obtained by subtracting the pixel value at each position included in the input image data from the maximum pixel value in the input image data;
A pixel value at each position included in the input image data or a pixel value at each position included in background image data serving as a background of an image based on the input image data, and a pixel value output from the subtraction value output means Second multiplying means for multiplying each corresponding position;
An addition means for adding the multiplication result of the first multiplication means and the multiplication result of the second multiplication means for each of the corresponding positions and outputting the result as output image data. Processing circuit. The storage means
First storage means for storing the position of each pixel constituting the plurality of graphic images;
Second storage means for storing color information representing the color of the graphic image as a pixel value of each pixel constituting the plurality of graphic images;
The color information output means which outputs the color information memorize | stored by the said 2nd memory | storage means as a pixel value of the pixel of each position memorize | stored by the said 1st memory | storage means is provided. The image processing circuit according to 1. The second storage means stores a plurality of types of color information,
The color information output means outputs any one of a plurality of types of color information stored by the second storage means for each pixel constituting the same type of graphic image among the plurality of graphic images. The image processing circuit according to claim 2. A designation means for designating either a pixel value at each position included in the input image data or a pixel value at each position included in background image data representing the background of the image of the input image data;
The image processing circuit according to claim 1, further comprising: a supply unit that supplies the pixel value designated by the designation unit to the second multiplication unit. A designation unit that designates either a third storage unit that stores predetermined background color information or a fourth storage unit that stores image information output to the display unit or the printing unit;
A supply unit that reads information stored in a storage unit designated by the designation unit as a pixel value included in the background image data and supplies the pixel value to the second multiplication unit. The image processing circuit according to 1. An image processing circuit according to any one of claims 1 to 5,
A display device comprising: display means for displaying an image based on output image data output from the adding means. An image processing circuit according to any one of claims 1 to 5,
And a printing unit that performs printing based on the output image data output from the adding unit.

Images