JP4661704B2 - Image processing apparatus, image forming apparatus, and program - Google Patents

Description

  The present invention relates to an image processing apparatus, an image forming apparatus, and a program.

An image processing apparatus that performs filter processing on image data generally includes a memory having a capacity corresponding to the filter size. Such a memory is called a line memory or a line buffer. For example, when the filter size is 5 × 5 (pixels), a line memory for 4 rows or 5 rows is often provided (see FIG. 13).
JP 2003-317094 A

  By the way, in the configuration as in the above-described conventional example, image data corresponding to each row is stored in each line memory. In such a configuration, it is necessary to provide more line memories as the filter size increases. In addition, when the size of the image data or the filter size is changed, a storage area that is not effectively used may be generated in the line memory.

  On the other hand, Patent Document 1 discloses an invention for obtaining a predetermined filter effect with one line memory. However, since the invention described in Patent Document 1 is applicable only to a specific filter, there is a disadvantage that the versatility is poor.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique that can be applied to various filter operations in an image processing apparatus and that can efficiently use a memory. There is.

In order to achieve the above-mentioned object, the present invention provides the gradations that are continuous in the row direction from a storage device that stores a plurality of gradation data representing a predetermined image by being arranged in the row direction and the column direction. An image processing device that performs a filter operation by performing a first process of sequentially reading data, performing the first process sequentially on each row in the column direction, and at least m−1 (m Is a storage means having at least n (n is an integer satisfying n ≧ 1) storage areas for continuously reading out the gray scale data satisfying m ≧ 2, and from the storage device An arithmetic means for executing a filter operation on the read gradation data and the gradation data stored in the storage means by a set of filter coefficients of m rows and n columns, and the gradation data of the storage means reading And control means for controlling the input of the gradation data to the arithmetic means, the control means from the first to m− of the m pieces of gradation data continuous in the column direction. writes m-1 pieces of gradation data to the first in the storage area, the m-th gray-scale data to be continuous with the (m-1) th gray-scale data is read from the storage device, in the storage area The second process of reading the stored m-1 grayscale data from the first to the m-1th and inputting these m grayscale data to the calculation means is performed for at least n columns. to provide an image processing apparatus according to claim execution to Rukoto in order in the row direction Te.

In this aspect, the storage means may be composed of a plurality of memories. For example, the storage means includes two memories (a first memory and a second memory), and the control means starts from the first to x−1 of the first to m−1 gradation data. The gradation data up to the number (x is an integer satisfying 2 <x <m−1) are written in the first memory, and the gradation data from the xth to the m−1th are stored in the second memory. After writing and inputting the m number of gradation data to the arithmetic means, the second to xth storage areas of the first memory from which the first to x−1th gradation data are read are read. -1th gradation data and xth gradation data are written, and x + 1 to m-1th gradation data are read into the storage area of the second memory where x + 1 is read. To m-1st gradation data and the input means A configuration for writing and input m-th gray-scale data may be.
The storage unit may include three or more memories. In other words, the storage means includes at least a first memory and a second memory, and the control means includes the first to x−1th (of the first to m−1th gradation data). x is an integer satisfying 2 <x <m−1) and gradation data is written in the first memory, and xth to yth (y is an integer satisfying x <y <m−1). Are written in the second memory and the m pieces of gradation data are input to the arithmetic means, and then the first to x−1th gradation data are read out. The gradation data from the 2nd to the (x-1) th and the xth gradation data are written into the storage area of the memory, and the gradation data from the xth to the yth are read out. X + 1 to yth in the storage area of the second memory And tone data, may be configured to write and y + 1 th gray-scale data.

  In the configuration including the plurality of memories described above, for example, “second to x−1th gradation data”, “x + 1 to m−1th gradation data”, etc. It does not interfere with the gradation data. Specifically, for example, when the m is “5” and the x is “3”, the control unit converts the first to 2 (x−1) -th gradation data into the first. After writing to 1 memory and writing 3 (x) th to 4 (m−1) th gradation data to the second memory, and inputting 5 (m) gradation data to the computing means. In the storage area of the first memory from which the first to 2 (x−1) th gradation data is read, the 2 (x−1) th gradation data and the 3 (x) th gradation data are stored. The gradation data is written, and the 4 (x + 1, m−1) th is stored in the storage area of the second memory from which the 3 (x) th to 4 (m−1) th gradation data is read. And the fifth gradation data input to the input means are written. In other words, in this case, “second to x−1th gradation data” is the same as “second gradation data”, and “x + 1th to m−1th gradation data” is This is the same as “4th gradation data”.

The present invention can also be provided in a form different from the form described above. For example, the present invention can be provided in the form of an image forming apparatus including the above-described image processing apparatus, and is also provided in the form of a program for realizing the functions of the above-described image processing apparatus. It is also possible. For example, in the program according to the present invention, the gradation data continuous in the row direction is sequentially ordered from a storage device that stores a plurality of gradation data representing a predetermined image by being arranged in the row direction and the column direction. The computer of the image processing apparatus that performs the filter operation by performing the first processing to be read in the above and sequentially performing the first processing on each row continuous in the column direction, Storage means having at least n (n is an integer satisfying n ≧ 1) storage areas for continuously reading out the gradation data of integers satisfying ≧ 2 and read from the storage device against gradation data and the storage means the stored gray-scale data, operating means for executing a filtering operation by a set of filter coefficients of m rows and n columns, the gradation data to the storage means The reading and writing and the input of the gradation data to the arithmetic means are controlled, and among the m number of gradation data continuous in the column direction, m-1 floors from the 1st to the m-1st. When tone data is written in the storage area , and the mth tone data continuous to the m-1st tone data is read from the storage device, the first to m-1th stored in the storage region reads the m-1 pieces of gradation data to the second process of inputting these m pieces of gradation data to the arithmetic unit, run in sequence in the row direction with respect to at least n columns Some of them are characterized by functioning as control means.

  According to the present invention, an image processing apparatus can be applied to various filter operations while efficiently using a memory.

  Embodiments of the present invention will be described below with reference to the drawings. In the embodiment described below, “gradation data” is assumed to be 8-bit (that is, 256 gradations) monochrome data representing a gradation. The “image data” is a set in which the above-described gradation data is arranged in the row direction and the column direction, and is data representing a predetermined grayscale image by gradations represented by the respective gradation data.

[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration of an image forming apparatus 100 according to the first embodiment of the present invention, and FIG. 2 is a block diagram illustrating a configuration of an image processing apparatus 200 included in the image forming apparatus 100. . As shown in FIG. 1, the image forming apparatus 100 includes an image reading unit 1, an image processing unit 2, and an image forming unit 3. The image reading unit 1 has a so-called scanner function, and optically reads a document to generate image data. The image processing unit 2 performs various image processing on the image data generated by the image reading unit 1. The image forming unit 3 has a so-called printer function, and forms an image corresponding to the image data subjected to image processing by the image processing unit 2 on a sheet-like object such as paper.

  The image processing apparatus 200 constitutes a part of the image processing unit 2. As shown in FIG. 2, the image processing apparatus 200 includes an image memory 10, an image processing unit 20, and a control unit 30, and these units are connected to each other by a bus 40. The image memory 10 stores gradation data corresponding to one page or one page divided by a predetermined band unit. As the image memory 10, for example, a DRAM (Dynamic Random Access Memory) can be used. The image processing unit 20 is configured by an adder, a shift calculator, and the like, and receives input of gradation data from the image memory 10 via the bus 40 and executes a predetermined filter calculation. The control unit 30 is an arithmetic unit including a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like, and the CPU executes a program stored in the ROM while using the RAM as a work area. Thus, the overall operation of the image processing apparatus 200 is controlled. Note that the control unit 30 may control the overall operation of the image forming apparatus 100.

  Here, the detailed configuration of the image processing unit 20 is shown in FIG. As shown in the figure, the image processing unit 20 includes a flip-flop (FF) 201, a shift computing unit 202, an OR computing unit 203, a RAM 204, a flip-flop 205, a selection switch 206, and a shift computing unit 207a. , 207b, 207c, 207d and 207e, adders 208a and 208b, flip-flop 209, adder 210, flip-flops 211a, 211b, 211c, 211d and 211e, and shift calculators 212a, 212b, 212c and 212d. And 212e, an adder 213, and a divider 214. The arrows shown in the figure represent the data flow. In the same figure, the numbers shown in the block of the shift computing unit indicate the number of bits of the shift computation in the computing unit.

  The flip-flop 201 is a storage circuit capable of holding 8-bit data. The data held in the flip-flop 201 is supplied to the shift computing unit 207e and the OR computing unit 203. The shift arithmetic unit 202 is an arithmetic circuit that performs 8-bit shift operation (bit shift) in the left direction on the 16-bit data supplied from the flip-flop 205. Note that the upper 8-bit data overflowing at this time does not affect the operation result (that is, is ignored). That is, for example, when data “1111111111111111” in binary number is supplied, the shift computing unit 202 outputs data “1111111100000000” in binary number. The OR calculator 203 is an arithmetic circuit that outputs a logical sum of the data from the flip-flop 201 or 205 and the data from the shift calculator 202. That is, for example, when the binary data “1110111100000” is supplied from the flip-flop 201 and “1111111100000000” is supplied from the flip-flop 201, the OR calculator 203 outputs data “1111111110101010” in binary.

  The RAM 204 is a memory that stores data for executing a filter operation, and corresponds to a so-called line memory. The RAM 204 temporarily holds 16-bit data per word, and the storage capacity as a whole is desirably a capacity corresponding to gradation data for four lines. As such a RAM 204, for example, an SRAM (Static RAM) can be used.

  The flip-flop 205 is a storage circuit capable of holding 32-bit data, and holds data supplied from the RAM 204. The selection switch 206 is a circuit that selectively distributes data supplied from the flip-flop 205. The selection switch 206 supplies continuous 8-bit data to the shift calculators 207a, 207b, 207c, and 207d.

  The shift calculators 207a, 207b, 207c, 207d, and 207e are arithmetic circuits that execute a shift operation of a predetermined number of bits in the left direction. The number of bits of the shift calculation in each of the shift calculators 207a, 207b, 207c, 207d, and 207e is determined according to the filter coefficient of the filter corresponding to the filter calculation realized by the image processing apparatus 200. Details will be described later. . In the present embodiment, the number of bits of the shift operation in each shift operation unit is “0” for the shift operation unit 207a, “1” for 207b, “2” for 207c, “1” for 207d, and “0” for 207e. It is. Here, the fact that the number of bits of the shift operation is “0” is the same as not performing the shift operation. In the present embodiment, for the sake of convenience of explanation, a shift calculator is also provided in a portion where the number of bits for shift calculation is “0”.

  The adder 208a is an arithmetic circuit that adds data representing the calculation results of the shift calculators 207a and 207b, and the adder 208b is an arithmetic circuit that adds data representing the calculation results of the shift calculators 207c, 207d, and 207e. is there. The flip-flop 209 is a storage circuit that holds data representing the calculation result of the adder 208b. The adder 210 is an arithmetic circuit that adds the data supplied from the adder 208 a and the data supplied from the flip-flop 209.

  The flip-flops 211a, 211b, 211c, 211d, and 211e are storage circuits that hold data supplied from the adder 210, respectively. The flip-flop 211e holds the data supplied from the adder 210, and overwrites and holds new data supplied from the adder 210. Note that the data held in the flip-flop 211e before being overwritten is supplied to the flip-flop 211d. The flip-flop 211d holds data supplied from the flip-flop 211e, and overwrites and holds new data supplied from the flip-flop 211e. The flip-flops 211c, 211b, and 211a operate in the same manner, but the flip-flop 211a does not have a subsequent flip-flop to which data is to be supplied.

  The shift calculators 212a, 212b, 212c, 212d, and 212e are arithmetic circuits that execute a shift operation of a predetermined number of bits in the left direction. The number of bits of the shift operation in each of the shift arithmetic units 212a, 212b, 212c, 212d, and 212e is equivalent to the filter operation realized by the image processing apparatus 200, similar to that of the shift arithmetic units 207a, 207b, 207c, 207d, and 207e. Although it is determined according to the filter coefficient of the filter to be performed, details will be described later. In the present embodiment, the number of bits of the shift operation in each shift calculator is “0” for the shift calculator 212a, “1” for 212b, “2” for 212c, “1” for 212d, and “0” for 212e. It is. In this case as well, the fact that the number of bits of the shift operation is “0” is the same as not executing the shift operation.

  The adder 213 is an arithmetic circuit that adds data representing the calculation results of the shift calculators 212a, 212b, 212c, 212d, and 212e. The divider 214 is an arithmetic circuit that divides the data supplied from the adder 213 by a predetermined value C. The value C in the divider 214, that is, the divisor, is a value for normalization determined according to a filter corresponding to the filter operation realized by the image processing apparatus 200, and details will be described later.

  In the following, when it is not necessary to distinguish each of the shift computing units 207a, 207b, 207c, 207d, and 207e, they are collectively referred to as “shift computing unit 207”. Similarly, the flip-flops 211a to 211e and the shift calculators 212a to 212e are collectively referred to as “flip-flop 211” and “shift calculator 212” when it is not necessary to distinguish between them.

  Of the image processing unit 20, the shift calculator 207, the adders 208a and 208b, the flip-flop 209, the adder 210, the flip-flop 211, the shift calculator 212, the adder 213, and the divider 214 are a set of filter coefficients (description). For the sake of convenience, in the following, a filter operation represented simply as “filter” will be realized. Therefore, in the following, these units are collectively referred to as “filter operation unit 50”.

The filter calculation unit 50 executes a filter calculation corresponding to the filter shown in FIG. That is, when the filter operation in the image processing unit 20 is expressed by a matrix, the matrix M is expressed by the following equation (1).

  The filter in this embodiment, that is, the matrix M has the following characteristics. That is, the numerator of the filter coefficient in the i-th row and j-th column (where i and j are integers satisfying 2 ≦ i ≦ 5 and 2 ≦ j ≦ 5, respectively) is the numerator of the filter coefficient in the first row and j-th column. And the numerator product of the filter coefficients in the i-th row and first column.

The numerator of the filter coefficient in the first row and the numerator of the filter coefficient in the first column have a predetermined correspondence relationship with the number of bits of the shift operation in the shift calculators 207a to 207e and the shift calculators 212a to 212e. Specifically, the number of bits of the shift operation in the shift calculators 207b, 207c, 207d, and 207e is the first row, first column, the second row, first column, the third row, first column, and the fourth row, respectively. The number of bits of the shift operation in the shift calculators 212a, 212b, 212c, 212d and 212e is determined by the numerator of the filter coefficient in the first column and the fifth row and the first column, respectively. Defined by the numerator of the filter coefficients in the second column, first row and third column, first row and fourth column, and first row and fifth column. Between these values, when the number of bits of each shift operation is n and the numerator of each filter coefficient is m, the relationship of the following equation (2) is established.

  That is, for example, when performing a 1-bit shift operation in the left direction, since the first power of 2 is “2”, the numerator m of the corresponding filter coefficient is “2”. This corresponds to the relationship between the numerator of the filter coefficient in the first row and the second column and the number of bits of the shift operation in the shift calculator 207b. The first row and the fourth column and the shift calculator 207d, the second row and first column and the shift calculator 212b, and the fourth row and first column and the shift calculator 212d have the same relationship. For example, when performing a 2-bit shift operation in the left direction, since the square of 2 is “4”, the numerator m of the corresponding filter coefficient is “4”. This is because of the relationship between the numerator of the filter coefficient in the first row and third column and the number of bits of the shift operation in the shift calculator 207c, and the numerator of the filter coefficient in the third row and first column and the bit of the shift operation in the shift calculator 212c. Corresponds to the number relationship.

  Note that the value C for normalization, that is, the value corresponding to the denominator of each filter coefficient, is preferably the sum of the numerators of each filter coefficient, for example. In this case, the value C in this embodiment is “100”. However, of course, the value C may be determined by other methods.

  Based on the above configuration, the image forming apparatus 100 generates image data based on the read original, performs various image processing on the generated image data, and then forms an image according to the image data. At this time, the image processing apparatus 200 executes the filter operation defined by the above equation (1) as part of the image processing. Hereinafter, an operation when the image processing apparatus 200 executes the filter calculation will be described.

  When gradation data is input from the image reading unit 1, the control unit 30 of the image processing apparatus 200 sequentially stores the data in the image memory 10. When a predetermined amount of gradation data is stored in the image memory 10, the control unit 30 reads the gradation data from the image memory 10 and writes it in the RAM 204 of the image processing unit 20. At this time, the gradation data written in the RAM 204 corresponds to four lines of image data.

  The gradation data written in the RAM 204 will be described with reference to FIGS. FIG. 5 is a diagram schematically showing the gradation data stored in the image memory 10, and FIG. 6 is a diagram schematically showing the gradation data written in the RAM 204. As shown in FIG. In these figures, for convenience of explanation, rows are represented by alphabets and columns are represented by numbers. Here, the A line corresponds to the first line, the B line corresponds to the second line, and similarly, the C line (third line), the D line (fourth line), and so on. followed by.

  As shown in FIG. 5, the gradation data is continuously stored in the row direction and the column direction in the image memory 10. The control unit 30 reads the gradation data stored in this way, and writes it in the RAM 204 so that the gradation data is arranged in the order shown in FIG. That is, the control unit 30 stores the grayscale data so that adjacent grayscale data of rows (A and B rows, C and D rows) continuous in the column direction are stored in the same word. Write. As a result, in the RAM 204, the first word has the Ath row and the first column, the Bth row and the first column, the second word has the Cth row and the first column, the Dth row and the first column, and the third word has the third word. Gradation data is written in the A row and the second column and the B row and the second column. In FIG. 6, the gradation data (8 bits) in row A and column 1 are on the upper side, and the gradation data (8 bits) in row B and column 1 are on the lower side. These are 16 bits in total and occupy the entire word.

  When the gradation data is written in this way, the controller 30 designates the address of the first word as a read address, so that the gradation data of the A-th row, first column and the B-th row, first column are continuously obtained. Can be read. Further, the control unit 30 designates the address of the second word as a read address, so that the grayscale data of the C-th row and first column and the D-th row and first column can be read out continuously. Then, the gradation data for four rows can be continuously read out by continuously performing such a reading operation.

  In the following, in order to distinguish each of the gradation data, the notation according to the position of the row and the column when stored in the image memory 10 is performed. Specifically, for example, the gradation data of the A row and the first column is “A1”, the gradation data of the B row and the second column is “B2”, and so on, corresponding to the position of each row and column. Is attached to the gradation data.

  When the gradation data is written in the RAM 204 as described above, the control unit 30 reads each gradation data so as to input the gradation data to the filter calculation unit 50. Since the filter in this embodiment has a filter size of 5 × 5 (pixels), the control unit 30 reads out the gradation data for five rows. Since four lines of the five lines of gradation data are written in the RAM 204, the control unit 30 reads out the four lines of gradation data from the RAM 204. On the other hand, since the gradation data of the fifth line following these four lines is stored in the image memory 10, the control unit 30 reads out the gradation data of the fifth line from the image memory 10. The operation performed by the control unit 30 at this time is as follows.

  FIG. 7 is a diagram schematically showing changes in the contents stored in the RAM 204. Hereinafter, the operation performed by the control unit 30 will be described with reference to FIG. First, the control unit 30 reads out the gradation data in the E-th row and the first column, that is, the gradation data E1 from the image memory 10 and stores it in the flip-flop 201. Next, the control unit 30 continuously reads the gradation data A1, B1, C1, and D1 for four rows from the first and second words of the RAM 204 and stores them in the flip-flop 205. Then, the control unit 30 reads the gradation data A1, B1, C1, D1, and E1 for five rows from the flip-flop 201 and the flip-flop 205, and inputs them to the filter calculation unit 50.

  The filter calculation unit 50 multiplies each of the corresponding gradation data by the filter coefficient shown in FIG. 4, calculates the sum, and outputs it. The data output from the filter calculation unit 50 corresponds to, for example, the calculation result of the gradation data located at the center of the filter. In the filter calculation unit 50, the process of adding the calculation results by the shift calculator 207 (that is, the preceding process) corresponds to the process of calculating the sum of the results of the gradation data (shift calculation) in units of columns. ing. In the filter calculation unit 50, the process of adding the calculation results by the shift calculator 212 (that is, the subsequent process) corresponds to the process of calculating the sum of the results of the gradation data (shift calculation) in units of rows. ing. That is, the calculation result of the gradation data of each column is added in the adder 210, the shift calculation units 212a, 212b, 212c, 212d, and 212e perform the shift operation corresponding to each row on the addition result, and the result is obtained. By adding in the adder 213, a filter operation corresponding to the filter shown in FIG. 4 is executed.

  While executing such a filter operation, the control unit 30 rewrites the RAM 204 at an appropriate timing. Each time the gradation data for 5 rows and 1 column is input to the filter calculation unit 50, the control unit 30 rewrites the storage area from which the gradation data has been read. For example, when the gradation data A1 to E1 are input to the filter calculation unit 50, the control unit 30 rewrites the data stored in the first and second words of the RAM 204. Specifically, the control unit 30 reads the gradation data A1 and B1 of the first word from the flip-flop 205, inputs them to the shift computing unit 202, and also supplies the gradation data C1 of the second word from the flip-flop 205. Is input to the OR calculator 203.

  The OR calculator 203 receives the calculation result from the shift calculator 202 and the gradation data C1. Since the shift operator 202 performs 8-bit bit shift, the result of the operation by the OR operator 203 is data in which the upper 8 bits are equivalent to the gradation data B1 and the lower 8 bits are equivalent to the gradation data C1. It becomes. Then, the control unit 30 writes this data in the first word of the RAM 204. As a result, the contents stored in the RAM 204 change from (a) to (b) in FIG. 7 before and after the writing.

  After rewriting the first word in this way, the control unit 30 rewrites the second word. Specifically, the control unit 30 reads out the second-word gradation data C1 and D1 from the flip-flop 205, inputs them to the shift computing unit 202, and reads out the gradation data E1 from the flip-flop 201. Is input to the OR calculator 203.

  Since the calculation result by the shift calculation unit 202 and the gradation data E1 are input to the OR calculator 203, the calculation result by the OR calculator 203 has the upper 8 bits equivalent to the gradation data D1, and the lower 8 Data whose bits are equivalent to the gradation data E1. Then, the control unit 30 writes this data in the second word of the RAM 204. As a result, the contents stored in the RAM 204 change from (b) to (c) in FIG. 7 before and after the writing.

  The above processing is processing corresponding to row A to row E in the first column. The control unit 30 similarly executes such processing for the second column. That is, the control unit 30 reads out the gradation data E2 from the image memory 10, reads out the gradation data A2, B2, C2, and D2 from the RAM 204, and then rewrites the third and fourth words. As a result, the contents stored in the RAM 204 change from (c) to (d) and (e) in FIG. Further, the control unit 30 similarly performs such processing for the third and subsequent columns.

  When such processing is executed for the entire RAM 204, as shown in (f) of FIG. 7, only the gradation data of the A-th line among the stored gradation data of the A-th to D-th lines is stored. Deleted. Then, the gradation data of the Eth row is stored in place of the gradation data of the Ath row. In the gradation data of the B-th row to the E-th row, the B-th row and the C-th row are stored in the same word, the D-th row and the E-th row are stored in the same word, and these words are alternately arranged. Are arranged as follows. For this reason, it is possible to execute the filter operation for the Bth to Fth rows in the same manner as for the Ath to Eth rows.

  Thus, according to the image processing apparatus 200 of the present embodiment, it is possible to have one memory (RAM 204) for inputting gradation data to the filter calculation unit 50. Further, according to the image processing apparatus 200, the control unit 30 writes and reads out the memory so that necessary gradation data is continuously read out. Can be suppressed. In addition, according to the image processing apparatus 200, since the number of memories does not depend on the filter size, even when the filter to be used is switched to a different size, the memory is efficiently used without waste. It becomes possible.

  In this image processing apparatus 200, only the filter calculation unit 50 of the image processing unit 20 changes depending on the filter to be used, and the configuration of other parts is essentially the same. is there. Therefore, it can be said that the image processing apparatus 200 of the present embodiment is applicable to various filter operations. However, when the filter sizes are different, the number of distribution destinations of the selection switch 206 changes.

[Second Embodiment]
Subsequently, a second embodiment of the present invention will be described. This embodiment is the same as the first embodiment described above except for the configuration and operation in the image processing apparatus. Therefore, in the following, the description will focus on parts that are different from the first embodiment described above. In addition, about the component similar to 1st Embodiment mentioned above, the same code | symbol is attached | subjected also in this embodiment, and the description is abbreviate | omitted suitably. In order to distinguish from the image processing apparatus 200 and the image processing unit 20 of the first embodiment described above, the image processing apparatus and the image processing unit of the present embodiment include “image processing apparatus 200a” and “image processing”, respectively. Part 20a ".

  FIG. 8 is a diagram illustrating a configuration of the image processing unit 20a. When the image processing unit 20a of this embodiment is compared with the image processing unit 20 of the first embodiment shown in FIG. 3, the image processing unit 20 has one memory (RAM 204), whereas the image processing unit 20a has a single memory (RAM 204). The main difference is that there are two memories (RAMs 204a and 204b). Accordingly, the configuration around the RAM 204 (shift arithmetic unit 202, OR arithmetic unit 203, and flip-flop 205), which is one each in the image processing unit 20, is also two each (shift arithmetic units 202a, 202b, OR calculators 203a and 203b and flip-flops 205a and 205b), and there is no portion corresponding to the selection switch 206.

  The internal configuration of the filter calculation unit 50a is substantially the same as that of the filter calculation unit 50 of the first embodiment described above, and the corresponding filter is also the same as the filter of the first embodiment described above (FIG. 4). In FIG. 8, an adder 210 a corresponds to the adders 208 a and 208 b, the flip-flop 209, and the adder 210 of the first embodiment. In the first embodiment, the flip-flop 209 is provided because the output timings of the grayscale data of the Ath and Bth rows and the grayscale data of the Cth to Eth rows do not match. Since these output timings coincide with each other, it is possible to perform addition with one adder.

  The RAMs 204a and 204b each have a storage capacity for storing gradation data for two lines. That is, the storage capacity of each of the RAMs 204a and 204b is half of the storage capacity of the RAM 204 described above. The flip-flops 205a and 205b each hold 16-bit data. That is, this is also half of the data held by the flip-flop 205.

  Subsequently, an operation in the image processing apparatus 200a will be described. First, when gradation data is input from the image reading unit 1, the control unit 30 of the image processing apparatus 200 a sequentially stores the data in the image memory 10. At this time, the gradation data is stored in the image memory 10 as shown in FIG. When a predetermined amount of gradation data is stored in the image memory 10, the control unit 30 reads the gradation data from the image memory 10 and writes it in the RAMs 204 a and 204 b of the image processing unit 20. At this time, the gradation data written in the RAMs 204a and 204b are for two rows.

  The gradation data written in the RAMs 204a and 204b will be described with reference to FIGS. FIG. 9 is a diagram schematically showing the gradation data written in the RAM 204a, and FIG. 10 is a diagram schematically showing the gradation data written in the RAM 204b. Note that the gradation data notation method is based on FIG. 6 of the first embodiment described above.

  As shown in these figures, the RAM 204a stores the gradation data of the Ath and Bth rows, and the RAM 204b stores the gradation data of the Cth and Dth rows. In the RAM 204a, the first word has the A row and the first column and the B row, the first column, the second word has the A row, the second column, the B row, the second column, and the third word has the A row. Gradation data is written in the third column and the Bth row and the third column. In the RAM 204b, the first word has the Cth row and the first column and the Dth row and the first column, the second word has the Cth row and the second column, the Dth row and the second column, and the third word has the second row. Gradation data is written in the C row and the third column and the D row and the third column.

  When the gradation data is written in the RAMs 204a and 204b in this way, the control unit 30 reads each gradation data to input the gradation data to the filter calculation unit 50a. Since the filter in this embodiment has a filter size of 5 × 5 (pixels), the control unit 30 reads out the gradation data for five rows. Since four lines of the gradation data for five lines are written in the RAMs 204a and 204b, the control unit 30 reads the gradation data for four lines from the RAMs 204a and 204b. On the other hand, since the gradation data of the fifth line following these four lines is stored in the image memory 10, the control unit 30 reads out the gradation data of the fifth line from the image memory 10. The operation performed by the control unit 30 at this time is as follows.

  FIG. 11 is a diagram schematically showing changes in the stored contents of the RAM 204a, and FIG. 12 is a diagram schematically showing changes in the stored contents of the RAM 204b. Hereinafter, operations performed by the control unit 30 will be described with reference to these drawings as appropriate. First, the control unit 30 reads out the gradation data in the E-th row and the first column, that is, the gradation data E1 from the image memory 10 and stores it in the flip-flop 201. Next, the control unit 30 reads the gradation data A1, B1, C1, and D1 for four rows from the first words of the RAMs 204a and 204b, and stores them in the flip-flops 205a and 205b. Then, the control unit 30 reads out the five rows of gradation data A1, B1, C1, D1, and E1 from the flip-flop 201 and the flip-flops 205a and 205b, and inputs them to the filter operation unit 50a. The filter calculation unit 50a multiplies each of the corresponding gradation data by the filter coefficient shown in FIG. 4, calculates the sum, and outputs it.

  While executing the filter operation, the control unit 30 rewrites the RAMs 204a and 204b at an appropriate timing. Each time the gradation data for 5 rows and 1 column is input to the filter calculation unit 50a, the control unit 30 rewrites the storage area from which the gradation data has been read. For example, when the gradation data A1 to E1 are input to the filter calculation unit 50a, the control unit 30 rewrites the data stored in the first word of the RAM 204a. Specifically, the control unit 30 reads the first word gradation data A1 and B1 from the flip-flop 205a, inputs the first word gradation data A1 and B1 to the shift computing unit 202a, and also inputs the first word gradation data C1 from the flip-flop 205b. Is input to the OR calculator 203a.

  The OR calculator 203a receives the calculation result from the shift calculator 202a and the gradation data C1. Since the shift calculator 202a performs 8-bit bit shift, the calculation result by the OR calculator 203a is data in which the upper 8 bits are equivalent to the gradation data B1, and the lower 8 bits are equivalent to the gradation data C1. It becomes. Then, the control unit 30 writes this data in the first word of the RAM 204a. As a result, the contents stored in the RAM 204a change from (a) to (b) in FIG. 11 before and after the writing.

  In parallel with the rewriting of the RAM 204a, the control unit 30 rewrites the data stored in the first word of the RAM 204b. The control unit 30 reads the gradation data C1 and D1 of the first word from the flip-flop 205b, inputs this to the shift computing unit 202b, reads the gradation data E1 of the first word from the flip-flop 201, The result is input to the OR calculator 203b.

  The OR calculator 203b receives the calculation result from the shift calculator 202b and the gradation data E1. Since the shift calculator 202b performs 8-bit bit shift, the calculation result by the OR calculator 203b is data in which the upper 8 bits are equivalent to the gradation data D1 and the lower 8 bits are equivalent to the gradation data E1. It becomes. Then, the control unit 30 writes this data in the first word of the RAM 204b. As a result, the contents stored in the RAM 204b change from (a) to (b) in FIG. 12 before and after the writing.

  After rewriting the first word in this way, the control unit 30 rewrites the second word. Specifically, the control unit 30 reads the second word gradation data A2 and B2 from the flip-flop 205a, inputs the second word gradation data A2 and B2 to the shift computing unit 202a, and reads the gradation data C2 from the flip-flop 205b. Is input to the OR calculator 203a. Here, the control unit 30 executes the same processing as when the first word of the RAM 204a is rewritten, so that the upper 8 bits are equivalent to the gradation data B2, and the lower 8 bits are equivalent to the gradation data C2. Is written in the second word of the RAM 204a. As a result, the contents stored in the RAM 204a change from (b) to (c) in FIG. 11 before and after the writing. Further, by executing the same processing for the RAM 204b, the stored contents of the RAM 204b change from (b) to (c) in FIG.

  When such processing is executed for the entire RAM 204a, the storage content of the RAM 204a is as shown in FIG. That is, the gradation data of the Ath row is deleted from the gradation data stored for the Ath and Bth rows, and the gradation data of the Cth row is stored instead. At this time, the gradation data of the B-th row stored on the lower 8 bits side of each word moves to the upper 8 bits side. Similarly, the storage content of the RAM 204b is as shown in FIG. That is, the gradation data of the C-th row is deleted from the gradation data stored for the C-th row and the D-th row, and the gradation data of the E-th row is stored instead. At this time, the gradation data in the D-th row stored in the lower 8 bits of each word moves to the upper 8 bits.

  Also by the image processing apparatus 200a of the present embodiment, substantially the same effect as that of the first embodiment described above can be obtained. According to the image processing apparatus 200a of the present embodiment, the number of memories increases to two. However, it is possible to read and write gradation data faster than the image processing apparatus 200 of the first embodiment. Become.

[Modification]
In the above, the present invention has been described by exemplifying two preferred embodiments. However, the present invention is not limited to the above-described embodiments, and can be implemented in various other modes. . In the present invention, for example, the following modifications can be applied to the above-described embodiment. These modifications can be combined as appropriate.

  The embodiment described above exemplifies a case where the image processing apparatus according to the present invention is mounted on an image forming apparatus. However, the image processing apparatus according to the present invention can output various images (display, print, etc.). It can be applied to electronic devices. The present invention can be provided not only as an image processing apparatus but also as a program for causing a computer to execute the functions of the image processing apparatus, and as a recording medium storing the program.

  Further, the types of filters applied in the present invention are not limited to those exemplified in the above-described embodiment. For example, the filter size and the filter coefficient can be changed as appropriate. According to the example of the embodiment described above, various weighted averages for neighboring pixels can be realized by changing the filter coefficient. In the embodiment described above, the numerator of the filter coefficient is limited to 2 to the nth power due to its configuration, but other filter coefficients can be obtained by combining bit shift and addition (or subtraction). You can also.

  Further, in the above-described embodiment, the configuration in which one memory corresponding to the line memory is provided (first embodiment) and the configuration in which two memories are provided (second embodiment) have been described, but three similar memories are provided. The structure provided above may be used. For example, if the filter size is 7 × 7 (pixels), the shift arithmetic unit 202a (202b), OR arithmetic unit 203a (203b), and RAM 204a (205b) of the second embodiment are added to the configuration shown in the second embodiment. ) And the flip-flop 205a (205b), and the gradation data for two rows may be supplied from the three RAMs. Alternatively, this can be realized by increasing the number of branches of the selection switch 206 in the configuration shown in the first embodiment. Thus, by appropriately changing the configuration of the above-described two embodiments, the filter size can be made larger than 5 rows, or conversely can be made smaller.

1 is a block diagram illustrating a configuration of an image forming apparatus according to an embodiment of the present invention. 1 is a block diagram illustrating a configuration of an image processing apparatus according to a first embodiment of the present invention. It is a block diagram which shows the structure of the image process part of the embodiment. It is a figure which shows the filter equivalent to the filter calculation which the image process part of the embodiment performs. It is a figure which shows typically the gradation data of the state stored in the image memory of the embodiment. It is a figure which shows typically the gradation data in the state written in RAM of the embodiment. It is a figure which shows typically the change of the memory content of RAM of the embodiment. It is a figure which shows the structure of the image process part which concerns on the 2nd Embodiment of this invention. It is a figure which shows typically the gradation data of the state written in 1st RAM of the embodiment. It is a figure which shows typically the gradation data of the state written in 2nd RAM of the embodiment. It is a figure which shows typically the change of the memory content of 1st RAM of the embodiment. It is a figure which shows typically the change of the memory content of 2nd RAM of the embodiment. It is the figure which illustrated the structure of the general line memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Image forming apparatus, 1 ... Image reading part, 2 ... Image processing part, 3 ... Image forming part, 200 ... Image processing apparatus, 10 ... Image memory, 20 ... Image processing part, 30 ... Control part, 40 ... Bus, 50: filter operation unit, 201, 205, 205a, 205b, 209, 211a, 211b, 211c, 211d, 211e ... flip-flop, 202, 202a, 202b, 207a, 207b, 207c, 207d, 207e, 212a, 212b, 212c , 212d, 212e ... shift arithmetic unit, 203, 203a, 203b ... OR arithmetic unit, 204, 204a, 204b ... RAM, 206 ... selection switch, 208a, 208b, 210, 213 ... adder, 214 ... divider

Claims (5)

A first process of sequentially reading the gradation data continuous in the row direction from a storage device that stores a plurality of gradation data representing a predetermined image by being arranged in the row direction and the column direction, An image processing apparatus that performs a filter operation by sequentially performing a first process on each row continuous in the column direction ,
Storage means having at least n (n is an integer satisfying n ≧ 1) storage areas that store at least m−1 (m is an integer satisfying m ≧ 2) so as to be continuously readable. When,
Arithmetic means for performing a filter operation by a set of filter coefficients of m rows and n columns on the gradation data read from the storage device and the gradation data stored in the storage means;
Control means for controlling reading and writing of the gradation data to the storage means and input of the gradation data to the arithmetic means;
The control means includes
Among the m pieces of gradation data continuous in the column direction, m-1 pieces of gradation data from the first to the (m-1) th are written into the storage area , and the m-1 pieces of gradation data are continuous. When the m-th gradation data to be read is read from the storage device , the m-1 gradation data from the first to the (m-1) -th stored in the storage area are read, and these m pieces of gradation data the image processing apparatus according to claim in that the second processing to be input to the arithmetic means, it runs in sequence in the row direction with respect to at least n columns. The storage means includes a first memory and a second memory,
The control means includes
Of the first to m−1th gradation data, the first to x−1th gradation data (x is an integer satisfying 2 <x <m−1) is stored in the first memory. And writing the xth to m−1th gradation data into the second memory,
After the m pieces of gradation data are input to the computing means, the first to x−1th gradation data is read out from the second memory area into the first memory storage area. The gradation data up to the th and the x-th gradation data are written, and the x + 1-th gradation data is read into the storage area of the second memory from which the x-th to m−1th gradation data is read out. 2. The image processing apparatus according to claim 1, wherein the first to m−1 gradation data and the mth gradation data input to the input unit are written. The storage means includes at least a first memory and a second memory,
The control means includes
Of the first to m−1th gradation data, the first to x−1th gradation data (x is an integer satisfying 2 <x <m−1) is stored in the first memory. And writing the gradation data from the xth to the yth (y is an integer satisfying x <y <m−1) to the second memory,
After the m pieces of gradation data are input to the computing means, the first to x−1th gradation data is read out from the second memory area into the first memory storage area. The grayscale data up to the th and the xth grayscale data are written, and the x + 1 through y are stored in the storage area of the second memory from which the xth through yth grayscale data has been read. The image processing apparatus according to claim 1, wherein the first gradation data and the y + 1th gradation data are written.   An image forming apparatus comprising the image processing apparatus according to claim 1. A first process of sequentially reading the gradation data continuous in the row direction from a storage device that stores a plurality of gradation data representing a predetermined image by being arranged in the row direction and the column direction, A computer of an image processing apparatus that performs a filter operation by sequentially performing a first process on each row continuous in the column direction ,
Storage means having at least n (n is an integer satisfying n ≧ 1) storage areas that store at least m−1 (m is an integer satisfying m ≧ 2) so as to be continuously readable. When,
Arithmetic means for performing a filter operation by a set of filter coefficients of m rows and n columns on the gradation data read from the storage device and the gradation data stored in the storage means;
Controlling reading and writing of the gradation data with respect to the storage means and input of the gradation data with respect to the arithmetic means, the first to m−1 of the m gradation data continuous in the column direction. writes m-1 pieces of gradation data to th in the storage area, the m-th gray-scale data to be continuous with the (m-1) th gray-scale data is read from the storage device, stored in the storage area The second process of reading out the m-1 grayscale data from the first to the m-1th and inputting the m grayscale data to the calculation means is performed on at least n columns. program for functioning as a control means you run in order in the row direction.

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