JP2009044547A - Image processor and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technique for shortening a processing time and saving a memory area, by performing image processing on respective blocks of predetermined size and remainder parts smaller than the predetermined size by different processing units for an image processor which divides an image into blocks of a predetermined size and performs image processings on the respective blocks. <P>SOLUTION: The image processor comprises an input unit for inputting image data from the outside; a block division unit which divides the input data into blocks of the predetermined size; a remainder decision unit which decides whether the image data can be divided into the block of the predetermined size without remainders; a first processing unit which processes remainder parts, when the remainder parts are generated; a second processing unit which processes the respective blocks of a predetermined size, and an output unit which combines and outputs the data processed by the first processing unit or second processing unit, to the outside. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image processing apparatus and an image processing method for compressing and expanding image data.

  In an image processing apparatus that converts an image into digital data (image data) and processes the image data, the image data is often compressed in order to save storage capacity and shorten the transfer time. When using the compressed image data, a process for restoring the original image data, that is, a decompression process is performed. Various types of image data compression and expansion (compression / decompression) processing methods are known. For example, methods such as MH, MR, MMR, LZW and JBIG mainly used for binary still images and JPEG mainly used for multi-value still images are known. These compression / decompression processes can be realized by hardware or software. In general, hardware processing is faster than software processing. On the other hand, software processing has a cost merit in that the CPU can be used when processing is performed by a device such as a personal computer that is inherently equipped with a CPU. Therefore, hardware processing and software processing are properly used according to the application and equipment.

  It has also been proposed to use both hardware processing and software processing separately in one device. For example, when printing is performed by rendering a page description language for printing to a printer driver or the like on the host computer, if there is a special hardware function for performing the rendering function on the host computer, the hardware function is linked. However, the following methods have been proposed as methods for efficiently performing processing. That is, when rendering the first job managed with respect to the storage device, the rendering end time of all the second jobs stored in the storage device as hardware rendering targets and the storage as the software rendering target The CPU compares the end times of all the third jobs stored in the device, and based on the compared end times, the first job stored in the storage device is changed to the second job or the third job. Registration control is performed as a job (see, for example, Patent Document 1).

  In general, it is said that the compression processing and decompression processing of image data by hardware is faster than software processing, but the hardware processing is not always faster in any case. Hardware processing and software processing have different characteristics.

  For example, when the amount of image data to be processed is small, software processing may be faster. In the case of hardware processing, usually, operating conditions must be set before (or before and after) operating the hardware. If there are many setting locations or the processing until obtaining the setting value is complicated, the processing time required for setting the operating condition cannot be ignored.

  Further, when the processing is executed by the number of prepared hardware, the next processing must wait until the hardware resources in use are available. Therefore, hardware resource management is required. A redundant number of hardware resources is not prepared due to a cost balance. On the other hand, software having a structure capable of parallel processing, such as multitasking, has a characteristic that the number of resources (processing tasks) can be increased or decreased dynamically to some extent and is flexible.

Therefore, if the processing time required for setting hardware operating conditions and acquiring resources (so-called overhead) is included, software processing becomes more advantageous in terms of speed when the amount of image data falls below a certain level. However, the extent to which software processing is advantageous is unclear because it depends on the load at the time of actual processing and the number and capacity of each resource.
JP 2003-76511 A

  2. Description of the Related Art An image processing apparatus is known that has hardware for processing image data in units of a predetermined size block, processes image data using the hardware, and attempts to speed up image processing compared to software processing. Yes. For example, in the JPEG compression method, compression processing is performed with 8 pixels × 8 pixels as one block (processing unit). Therefore, by preparing hardware for the processing unit and transferring image data to the hardware in block units, compression / decompression processing can be realized in hardware.

  However, the number of pixels in the vertical direction or the horizontal direction of the image data to be processed is not necessarily a multiple of 8 pixels, and is usually not the case. In that case, there is a surplus portion (redundant area) whose pixel width is less than 8 pixels of the processing unit at the edge of the image. The redundant area cannot be processed by hardware designed with 8 pixels × 8 pixels as a processing unit.

  Therefore, for example, before compression or decompression processing, the pixel data is added so that the pixel width of the redundant area is expanded to 8 pixels and transferred to a hardware compressor or decompressor, and the image data is added. A countermeasure is taken such that image compression or expansion processing is performed, and added pixels are deleted from the processed image (clipping processing). Here, the pixel data to be added to the redundant area needs to be added with a pixel value (for example, pixel value zero) corresponding to white if it is a white background in accordance with the background color of the image. Otherwise, favorable results will not be obtained for that processing unit.

  Note that the unit of compression / expansion processing of 8 pixels × 8 pixels is unique to the JPEG system. However, generally, when compression / decompression processing is performed by hardware, transfer in units of data of a predetermined size is performed to the compressor or decompressor. Then, a process of rounding the pixel width in the main scanning direction to a transferable unit is performed. From this viewpoint, the image data division processing according to the present invention is not limited to the JPEG format. For example, when the image processing apparatus is configured by a 64-bit width bus and one pixel transfers 8-bit image data via the bus, the data transfer is performed in a bus width of 64 bits, that is, in units of 8 pixels. If the number of pixels in one line in the main scanning direction is not a multiple of 8 pixels, pixel data is added to the end of each line, and the number of pixels in each line is set to a multiple of 8 for transfer. Alternatively, when data transfer is performed by DMA transfer, pixel data may be added to the end of each line and transferred to a compressor or decompressor so that the number of pixels in one line is a multiple of one burst. This is because image data can be easily managed by matching each line with the unit of processing.

  The data compressed / expanded in such a manner that each line is rounded to a multiple of the transfer unit is stored in a memory area temporarily secured as a transfer destination from the compressor or the expander. The line width of the transfer destination memory area is the width after the rounding process. After that, clipping processing is performed on the portion corresponding to the pixel data added to the end of each line.

  As is clear from the above description, in the apparatus that performs compression / decompression processing by hardware, when the contents are examined in detail, preparation processing for using the compression / decompression function by hardware is performed. Usually, the preparation processing, that is, resource management, operation condition setting, and clipping processing are processed by software. Those processing times cause overhead. Furthermore, the transfer destination memory area is occupied more than the capacity of the transfer source data by the amount of pixel data added.

  The inventor feels doubtful about whether it is appropriate to compress or expand the redundant area by hardware as in the conventional case, and performs a comparative study with the case of performing compression or expansion by software. It was. And it came to the application of this application.

  The present invention has been made under the circumstances as described above. In an image processing apparatus that divides an image into blocks of a predetermined size and performs image processing on each block, the block does not reach a predetermined size with each block of a predetermined size. The present invention provides a technique that makes it possible to realize a reduction in processing time and a memory area by making a processing unit that performs image processing different from that in a surplus part.

  The present invention relates to an input unit for inputting image data from the outside, a block dividing unit for dividing the input data into blocks of a predetermined size, and whether or not the image data can be divided into blocks of a predetermined size without any remainder. It is processed by a residue determination unit that determines, a first processing unit that processes a remainder part when a residue occurs, a second processing unit that processes each block of a predetermined size, and a first processing unit or a second processing unit And an output unit that outputs the combined data to the outside.

  Further, from a different point of view, the present invention is capable of dividing the input data into blocks of a predetermined size, the step of inputting image data from the outside, the step of dividing the input data into blocks of a predetermined size, and without any remainder Determining whether or not, a first processing step for processing a surplus portion when a surplus occurs, a second processing step for processing each block of a predetermined size, and a first or second processing step And a step of combining the blocks processed in step 1 and outputting them to the outside.

  An image processing apparatus according to the present invention includes a remainder determination unit that determines whether the image data can be divided into blocks of a predetermined size without a remainder, a first processing section that processes a remainder when a remainder occurs, a predetermined processing Since the second processing unit that processes each block of the size, the processing unit that performs image processing is different for each block of the predetermined size and the remainder portion that does not satisfy the predetermined size, and the processing unit according to the characteristics of each block By doing so, it is possible to reduce the processing time and save the memory area. That is, the first processing unit is configured so that data of a predetermined size can be processed in a shorter time than the second processing unit, and the second processing unit converts the surplus portion whose size varies depending on the target image data to the first processing unit. It is comprised so that it can process in parallel with a process part. The second processing unit can be flexibly adapted to various sizes, and is configured such that a cost burden for that purpose or a variation in processing time is suppressed compared to the first processing unit.

Hereinafter, preferred embodiments of the present invention will be described.
The remainder determination unit may determine whether or not each line formed by the arrangement of pixels in the main scanning direction can be divided into blocks having a predetermined number of pixels without a remainder.

  The remainder determination unit may further determine whether or not each line can be divided into a predetermined number of lines without a remainder in the sub-scanning direction orthogonal to the main scanning direction.

  The first processing unit may be an image processing unit that performs image processing on a surplus portion when the CPU executes a program.

  Furthermore, the second processing unit may be an image processing unit that performs image processing on each block by an image processing circuit.

  The first and second image processing units may perform compression processing or decompression processing on target data.

Further, the compression processing or expansion processing method may be any one of JPEG, JBIG, and TIFF.
The various preferable aspects shown here can also be combined.

  Hereinafter, the present invention will be described in more detail with reference to the drawings. In addition, the following description is an illustration in all the points, Comprising: It should not be interpreted as limiting this invention.

FIG. 1 is a block diagram showing a configuration example of an image processing apparatus according to the present invention. In FIG. 1, the image data processing unit 11 processes the image data input from the data input unit 21 and outputs the processed image data to the data output unit 23.
The image data processing unit 11 includes a CPU 17, a memory 19, a JPEG compressor 13 configured in hardware, and a JPEG decompressor 15 configured in hardware.

  The memory 19 is a RAM. When the image data processing unit 11 is powered on, the memory 19 is loaded with a control program stored in a non-volatile storage element (not shown). The image data input from the data input unit 21 is temporarily stored. That is, a transfer source data area is provided. Furthermore, the processed image data output from the JPEG compressor 13 or JPEG decompressor 15 is temporarily stored. That is, a transfer destination data area is provided. Furthermore, a work area is provided when the CPU 17 processes image data or the like.

  The CPU 17 controls the processing of the image data by executing the control program. That is, operating conditions are set for operating the JPEG compressor 13 and JPEG decompressor 15. Also, resource management of the JPEG compressor 13 and JPEG decompressor 15 is performed. Further, the CPU 17 can perform JPEG compression and JPEG decompression on the image data input from the data input unit 21 in a software manner. That is, processing as a software JPEG compressor and JPEG decompressor is possible. The CPU 17 determines the configuration of the image data input from the input unit 21. Then, when the image data is divided into processing units (blocks), it is determined whether or not there is a redundant area, and whether compression processing or expansion processing of each block is performed by the hardware compressor 13 according to the determination result. Alternatively, it is determined whether the CPU 17 performs processing in terms of software, and control is performed so that the target block is processed according to the determination result. In this embodiment, description will be made with 8 pixels × 8 pixels, which is a processing unit of JPEG compression and JPEG expansion, as a block unit. Other compression / decompression schemes (known MH, MR, MMR, etc.) are mainly blocked in units of transfer processing, but the essence of the present invention is common to both cases.

In this embodiment, the JPEG compressor 13 and the JPEG decompressor 15 are designed and provided as application specific integrated circuits (ASICs).
The data input unit 21 is an interface circuit for acquiring image data from an external unit. An example of the external unit is an image scanner that scans and reads an image of a document. In this embodiment, the data input unit 21 and an external unit are connected by a data bus, and image data is DMA-transferred from the external unit to the data input unit 21. The data input unit 21 is a circuit including a bus interface circuit and a DMA controller.

  The data output unit 31 is an interface circuit for outputting image data to an external unit. Here, the unit is usually different from the unit that provides image data to the data input unit, but may be the same unit. An example of the unit is a printing apparatus that prints an image. Another example is an auxiliary storage device that stores image data after compression processing, specifically, a hard disk drive (HDD). Note that when decompressing image data stored in the HDD, the image data from the HDD is acquired via the data input unit 21 and decompressed. In this case, the external unit that provides image data to the data input unit is the HDD. In this embodiment, the data output unit 23 and an external unit are connected by a data bus, and image data is DMA-transferred from the data output unit 23 to the external unit. The data output unit 23 is a circuit including a bus interface circuit and a DMA controller.

  Next, a processing procedure of compression / decompression processing according to the present invention will be described. Here, before explaining the details of the processing procedure according to the present invention, a procedure for processing all image data by hardware or software will be briefly described as a reference example. This will make it easier to understand the features of the processing procedure of the present invention described later.

  FIG. 8 is a block diagram showing a functional configuration of the image processing apparatus according to the present invention. As shown in FIG. 8, the image processing apparatus 1 includes an input unit 2, a remainder determination unit 3, a block division unit 4, a first processing unit 5, a second processing unit 6, and an output unit 7.

  Image data from the outside is input via the input unit 2. The block dividing unit 4 divides input data into blocks of a predetermined size. The remainder determination unit 3 determines whether or not the image data can be divided into blocks of a predetermined size without a remainder. The first processing unit 5 processes the remainder when there is a remainder in the divided data. The second processing unit 6 processes each block having a predetermined size. The data processed by the first processing unit or the second processing unit are combined on the memory 19 and output to the outside from the output unit 7 as processed image data. Note that the image processing apparatus 1 of FIG. 8 shows a block according to the present invention. Therefore, it does not exclude that the image processing apparatus 1 includes blocks not shown in FIG.

  FIG. 2 is a flowchart showing a procedure for unconditionally compressing / decompressing input image data by hardware or software as a reference example. FIG. 2A shows a procedure of hardware processing, and FIG. 2B shows a procedure of software processing. The configuration of the image processing apparatus is similar to the configuration of FIG. 1 in the case of hardware processing, and in the case of software processing, the configuration in FIG. 1 excluding the compressor 13 and the decompressor 15 may be assumed. . FIG. 3 is an explanatory diagram schematically showing a memory area used when performing the processing of FIG. FIG. 3A shows the case of hardware processing, and FIG. 3B shows the case of software processing. As will be described below, in the case of software processing, it is not necessary to secure a redundant area in the area where the processed image data is stored.

  A case of the hardware processing of FIG. 2A will be described. It is assumed that the compressor 13 or the decompressor 15 as a resource is secured at the start of the flow. Furthermore, it is assumed that a transfer source data area and a transfer destination data area are secured on the memory 19 as memory resources.

  First, the CPU 17 sets the operating condition of the compressor 13 or the decompressor 15 in the register (step S11). The setting includes designation of the memory address of the transfer source (transfer source data area 31 in FIG. 3A) and the memory address of the transfer destination (transfer destination data area 33 in FIG. 3A).

  Thereafter, compression / decompression processing is started. That is, a data transfer trigger is given from the CPU 17 or the outside, and the image data in the transfer source data area 31 is transferred to the compressor 13 or the decompressor 15. When the data is transferred, the compressor 13 or the decompressor 15 compresses or decompresses the transferred data (step S13). The data after the compression process or the expansion process is transferred to the transfer destination data area 33 and stored. The data stored in the transfer destination data area 33 includes a redundant area. This is because the compressor 13 or the decompressor 15 processes data in units of 8 pixels × 8 pixels and stores it in the transfer source data area 31.

  The CPU 17 writes the same image data as the image background in the redundant area of the image data stored in the transfer destination data area 33. This is so-called dust removal processing (step S15). That is, the dust erasing process is a software process.

  After the dust erasing process, the image data is output to the outside via the data output unit 23 (step S17).

  Next, the case of software processing in FIG. 2B will be described. Assume that a transfer source data area 31 as a memory resource and an output data area 35 for storing data after compression / decompression processing are secured on the memory at the start of the flow. In the case of software processing, since the CPU recognizes the position of each block and performs processing, it is not necessary to secure a redundant area in the output data area 35. That is, the size of the output data area 35 coincides with the transfer source data area 31. When the block is a processing target of pixels of 8 pixels × 8 pixels or less, the CPU 17 performs processing by adding the pixel to the block on the work area and storing the processed data in the output data area. Do not store any pixels.

  The CPU 17 determines various parameters to be applied to the compression / decompression process (step S21). Next, the CPU 17 performs compression or expansion processing on a block of 8 pixels × 8 pixels in the transfer source data area 31 (step S23). Then, the processed data is stored in the output data area 33. Next, the CPU 17 determines whether or not there remains a block to be processed (step S25). If there remains a block to be processed, the routine proceeds to step S23 and performs compression or expansion processing on the next block. On the other hand, when no block to be processed remains, the compression / decompression process is terminated.

  Thus, in the case of software processing, the CPU 17 performs compression / decompression processing after recognizing the position in the image data of each block to be processed. Since data is stored based on the recognition, it is not necessary to secure a redundant area in the output data area 35. Compared to hardware processing, compression / decompression processing can be performed in a memory area that is smaller than the redundant area. However, when the size of the image data is increased, processing time is required as compared with hardware processing.

  In the above, the characteristics of hardware processing and software processing have been described by reference examples. Next, the procedure of compression / decompression processing according to the present invention will be described. It is assumed that the compressor 13 or the decompressor 15 as a resource is secured at the start of processing. Further, it is assumed that a transfer source data area and an output data area are secured on the memory 19 as memory resources.

  FIG. 6 is a flowchart showing a procedure of compression / decompression processing according to the present invention. FIG. 7 is an explanatory diagram schematically showing a memory area used when performing hardware processing in the processing of FIG. In FIG. 7, a transfer source data area secured as a memory resource is denoted by reference numeral 31, and an output data area is denoted by reference numeral 41.

  In FIG. 6, upon receiving an instruction to start compression / decompression processing, the CPU 17 acquires the amount of image data to be processed (step S31), and determines whether the amount is larger than a predetermined data amount (step S31). S33). Here, the data amount may refer to a value calculated for securing the transfer source data area prior to the start of the flow.

  If the data amount of the image data is equal to or smaller than the predetermined data amount, it is determined that the compression / decompression process is performed by software (step S35). In this case, the software processing procedure is the same as that shown in FIG.

  On the other hand, when the processing capacity exceeds the predetermined amount, it is determined that the compression / decompression process is performed by hardware. Based on this assumption, the CPU 17 determines whether there is a redundant area from the size of the image data, that is, whether the number of vertical and horizontal pixels of the image data is a multiple of 8 (step S37).

  As a result of the determination, if the number of vertical and horizontal pixels is a multiple of 8 and there is no redundant area, the entire area of the image data can be divided into blocks of 8 pixels × 8 pixels. Therefore, the operating conditions of the compressor 13 or the decompressor 15 are set so that each block is subject to hardware processing (step S41). That is, the entire transfer source data area is set to be transferred to the compressor 13 or the decompressor 15. After completing the setting, the compression processing or decompression processing of each block is started (step S43). Thereafter, the routine proceeds to step S51 described later. Note that since the number of vertical and horizontal pixels is a multiple of 8, the memory capacity of the transfer destination data area 33 matches that of the transfer source data area 31.

  On the other hand, as a result of the determination, if there is a redundant area, the CPU 17 classifies the transfer source data area 31 into a basic area 37 (see FIG. 7) in which each block has 8 pixels × 8 pixels and another redundant area 39. To do. Then, the hardware process is performed for the basic area 37 and the software process is determined for the redundant area.

First, the operating conditions of the compressor 13 or the decompressor 15 are set so that each block in the basic area 37 is subject to hardware processing (step S45). That is, the entire transfer source data area is set to be transferred to the compressor 13 or the decompressor 15. After the setting is completed, compression processing or decompression processing for each block in the basic area 37 is started (step S47). As a result, the data of each block in the basic area 37 is transferred to the compressor 13 or the decompressor 15. As shown in FIG. 7, the transfer destination of the processed image data is an area 43 in the output data area 41. The area 43 corresponds to the basic area 37.
After the processing of the basic area 37 by hardware is started, the CPU 17 executes a compression process or an expansion process of the redundant area 39 (step S49). The software processing procedure for the redundant area 39 is the same as that shown in FIG. As shown in FIG. 7, the transfer destination of the processed image data is an area 45 in the output data area 41. The area 45 corresponds to the redundant area 39.
When the software processing of the redundant area 39 is completed, the CPU 17 confirms whether or not the basic area 37 hardware processing started in step S47 is completed (step S51), and waits for completion.

  When it is confirmed that both the redundant area 39 and the basic area 37 have been processed, the CPU 17 outputs the image data stored in the output data area 41 via the data output unit 23 (step S53).

  Here, the hardware processing started in step S47 in FIG. 6 and the software processing in step S49 are performed in parallel. Since it is configured in this way, it is possible to reduce the processing time of image data compared to the case where all image data is processed by hardware or the case where all image data is processed by software.

  In FIG. 7, the memory capacity of the area 45 in the output data area 41 is equal to the memory capacity of the redundant area 39. This is because the redundant area 39 is processed by software. Further, the memory capacity of the area 43 in the output data area 41 is equal to the memory capacity of the basic area 37. This is because each block of the basic area 37 is composed of 8 pixels × 8 pixels. Therefore, the memory capacity of the output data area 41 is equal to the memory capacity of the transfer source data area 31.

  Previously, it was stated that software processing would be advantageous in terms of speed when the amount of image data was below a certain level. Reference values demonstrating the tendency are explained below. However, as described above, there are various factors that affect the result, and it cannot be said that the extent to which software processing is advantageous is unclear.

  As a reference example, given an example of the overall processing time when all 1 MB image data is processed by hardware and the processing time when all software processing is performed, 350 msec is required for hardware processing and software processing is performed. In this case, 670 msec was required.

  Further, when 150 kB image data was processed by the same image processing apparatus, 30 msec was required for all hardware processing, and 22 msec was required for all software processing.

  4 and 5 are graphs showing the ratio of each step of the hardware processing of FIG. 2 (a) and each step of the software processing of FIG. 2 (b) to the total processing time in the above processing. FIG. 4 shows the results when 1 MB image data is processed, and FIG. 5 shows the results when 1 kB image data is processed.

  4A and 5A show the case of hardware processing. “Register setting” is the processing time corresponding to step S11 of FIG. 2A, “Image processing” is the processing time corresponding to steps S13 and S15 of FIG. 2A, and “Data transfer” is FIG. The processing time corresponding to step S17 of a) is shown.

  FIG. 4B and FIG. 5B show the case of software processing. “Parameter setting” indicates the processing time corresponding to step S21 in FIG. 2B, and “Image processing” indicates the processing time corresponding to steps S23 and S25 in FIG. 2B. Comparing FIG. 4 with FIG. 5, it can be seen that the proportion of the so-called overhead processing time increases as the amount of data decreases. Since the rate of change differs between software processing and hardware processing, it can be said that the processing time of software processing as a whole is shortened compared to hardware processing when the amount of data is small.

  In addition to the embodiments described above, there can be various modifications of the present invention. These modifications should not be construed as not belonging to the scope of the present invention. The present invention should include the meaning equivalent to the scope of the claims and all modifications within the scope.

It is a block diagram which shows the structural example of the image processing apparatus of this invention. As a reference example, it is a flowchart showing a procedure for unconditionally compressing / decompressing input image data by hardware or software. It is explanatory drawing which shows typically the memory area used when performing the process of FIG. 2 as a reference example. In a reference example, it is the 1st graph which shows the ratio which each step of the hardware processing of Drawing 2 (a) and each step of the software processing of Drawing 2 (b) occupy for the whole processing time. In a reference example, it is the 2nd graph which shows the ratio which each step of the hardware processing of Fig.2 (a) and each step of the software processing of FIG.2 (b) occupies for the whole processing time. It is a flowchart which shows the procedure of the compression / decompression process based on this invention. It is explanatory drawing which shows typically the memory area used when performing a hardware process in the compression / decompression process which concerns on this invention. It is a block diagram which shows the functional structure of the image processing apparatus of this invention.

Explanation of symbols

1: Image processing device 2: Input unit 3: Remainder determination unit 4: Block division unit 5: First processing unit 6: Second processing unit 7: Output unit 11: Image data processing unit 13: Compressor (hardware)
15: Stretcher (hardware)
17: CPU
19: Memory 21: Data input unit 23: Data output unit 31: Transfer source data area 33: Transfer destination data area (hardware processing)
35: Output data area (software processing)
37: Basic area 39: Redundant area 41: Output data area (application processing)
43: Basic area corresponding part 45: Redundant area corresponding part

Claims (8)

An input unit for inputting image data from the outside;
A block dividing unit that divides input data into blocks of a predetermined size;
A remainder determination unit that determines whether the image data can be divided into blocks of a predetermined size without a remainder;
A first processing unit that processes a portion of the surplus when a surplus occurs;
A second processing unit for processing each block of a predetermined size;
An image processing apparatus comprising: an output unit configured to combine and output the data processed by the first processing unit or the second processing unit to the outside.   The image processing apparatus according to claim 1, wherein the remainder determination unit determines whether or not each line composed of an array of pixels in the main scanning direction can be divided into blocks having a predetermined number of pixels without a remainder.   The image processing apparatus according to claim 2, wherein the remainder determination unit further determines whether each line can be divided into a predetermined number of lines without a remainder in the sub-scanning direction orthogonal to the main scanning direction.   The image processing apparatus according to claim 1, wherein the first processing unit is an image processing unit that performs image processing on a surplus portion when the CPU executes a program.   The image processing apparatus according to claim 1, wherein the second processing unit is an image processing unit that performs image processing on each block using an image processing circuit.   The image processing apparatus according to claim 1, wherein the first and second image processing units perform compression processing or decompression processing on target data.   The image processing apparatus according to claim 1, wherein the compression processing or decompression processing is any one of JPEG, JBIG, and LZW. A process part for inputting image data from the outside;
Dividing the input data into blocks of a predetermined size;
Determining whether the image data can be divided into blocks of a predetermined size without any remainder;
A first processing step for processing a surplus portion when a surplus occurs; and
A second processing step for processing each block of a predetermined size;
And a step of combining the blocks processed in the first or second processing step and outputting them to the outside.

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